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gerrit.onosproject.org / onos / 6230a61fb6a0f73662bdce1cd65f387ddd972a32 / . / tools / test / p4src / p4-14 / p4c-out / tofino / ecmp / mavericks / logs / mau.config.log
blob: 0e6c14991ec68db1ddc37fa9726b996e2069558c [file] [log] [blame]
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1+---------------------------------------------------------------------+
2| Log file: mau.config.log |
3| Compiler version: 5.1.0 (fca32d1) |
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]4| Created on: Wed Sep 13 00:59:40 2017 |
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]5+---------------------------------------------------------------------+
6
7Final Stage dependencies are:
8 (0, 'ingress') : match
9 (1, 'ingress') : match
10 (2, 'ingress') : match
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]11 (3, 'ingress') : concurrent
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]12 (4, 'ingress') : concurrent
13 (5, 'ingress') : concurrent
14 (6, 'ingress') : match
15 (7, 'ingress') : concurrent
16 (8, 'ingress') : concurrent
17 (9, 'ingress') : concurrent
18 (10, 'ingress') : concurrent
19 (11, 'ingress') : concurrent
20 (0, 'egress') : match
21 (1, 'egress') : concurrent
22 (2, 'egress') : concurrent
23 (3, 'egress') : concurrent
24 (4, 'egress') : concurrent
25 (5, 'egress') : concurrent
26 (6, 'egress') : match
27 (7, 'egress') : concurrent
28 (8, 'egress') : concurrent
29 (9, 'egress') : concurrent
30 (10, 'egress') : concurrent
31 (11, 'egress') : concurrent
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]32Action/Concurrent chaining in ingress consists of [3, 4, 5]
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]33Action/Concurrent chaining in ingress consists of [7, 8, 9, 10, 11]
34Action/Concurrent chaining in egress consists of [1, 2, 3, 4, 5]
35Action/Concurrent chaining in egress consists of [7, 8, 9, 10, 11]
36
37+------------------------------------------------------------------------
38| MAU Stage 0
39+------------------------------------------------------------------------
40
41+------------------------------------------------------------------------
42| Working on table _condition_0 in stage 0 ---
43+------------------------------------------------------------------------
44--> Stage Gateway Table for condition _condition_0 in stage 0
45Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
46Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
47Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
48Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
49Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
50Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]51Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x2. (old value = 0x0 OR new value = 0x2)
52Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]53Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_address to be 4.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]54Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]55Configuring match input crossbar byte 12 to come from 8-bit PHV container 4.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]56 That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]57Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10)
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]58Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2)
59Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
60Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=6][hash_bit_index=40].byte0 to be 0x2.
61Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
62Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
63Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
64Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
65Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
66Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
67Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
68Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
69Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
70Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0
71Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0
72Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
73Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
74Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
75Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
76Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
77Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff
78Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xfffffe
79Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x10
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]80Configuring rams.match.merge.gateway_next_table_lut[0][4] to be 0x1
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]81Configuring rams.match.merge.gateway_en.gateway_en to be 0x1
82Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf
83Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1
84Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_logical_select to be 0x0
85Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_inhibit_enable to be 0x1
86Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff
87Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff
88
89+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]90| Working on table process_packet_out_table__action__ in stage 0 ---
91+------------------------------------------------------------------------
92--> Action Data Table process_packet_out_table__action__ with logical_table_id 1 that is reference type is 'direct'
93
94+------------------------------------------------------------------------
95| Working on table process_packet_out_table in stage 0 ---
96+------------------------------------------------------------------------
97--> Match Table with no key process_packet_out_table with logical_table_id 1
98allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
99Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
100Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
101Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
102Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
103Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
104Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
105Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 1 (logical table id).
106Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
107Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 1 (logical table id).
108Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
109Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x40.
110Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x0.
111Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0x20.
112Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0x20.
113Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x2 (previous_value=0x0 OR new_value=0x2).
114Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x45.
115Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
116Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_instr to be 0x74412.
117Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_color to be 1.
118Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_parity to be 0.
119Micro instruction added in VLIW 2 for 16-bit position 2 for table process_packet_out_table.
120 Assembled as 0x74412 (or decimal 476178)
121 Micro Instruction deposit-field for PHV Container 130 has bit width 23
122 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
123 Field Src1 [4:0] : 0x1 (5 bits in instruction bits [8:4])
124 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
125 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
126 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
127 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
128 Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16])
129 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
130
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]131Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_instr to be 0x74d84.
132Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_color to be 1.
133Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_parity to be 0.
134Micro instruction added in VLIW 2 for 8-bit position 4 for table process_packet_out_table.
135 Assembled as 0x74d84 (or decimal 478596)
136 Micro Instruction deposit-field for PHV Container 68 has bit width 20
137 Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]138 Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4])
139 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
140 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
141 Field high_bit [2:0] : 0x1 (3 bits in instruction bits [13:11])
142 Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14])
143 Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16])
144 Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
145
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]146Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]147Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6)
148--> Stage Gateway Table for condition process_packet_out_table_always_true_condition in stage 0
149Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
150Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
151Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
152Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
153Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
154Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
155Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x2. (old value = 0x2 OR new value = 0x0)
156Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
157Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x2 OR new value = 0x0)
158Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
159Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
160Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
161Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
162Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
163Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
164Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1
165Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0
166Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
167Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
168Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
169Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff
170Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff
171Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff
172Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff
173Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8
174Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0x20
175Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10)
176Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0x20
177Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2)
178Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe
179Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1
180allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
181Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x1
182Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1
183Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2
184Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x0
185Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0
186Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x0
187Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0
188Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff
189Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff
190Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
191
192+------------------------------------------------------------------------
193| Working on table table0__action__ in stage 0 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]194+------------------------------------------------------------------------
195--> Action Data Table table0__action__ with logical_table_id 0 that is reference type is 'direct'
196Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_input_bytemask[array_half=1].action_hv_ixbar_input_bytemask to be 0x3.
197Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_ctl_halfword[slice_group=1][array_half=1].action_hv_ixbar_ctl_halfword_3to0_ctl to be 0.
198Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_ctl_halfword[slice_group=1][array_half=1].action_hv_ixbar_ctl_halfword_3to0_enable to be 1.
199Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_select to be 5.
200Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_enable to be 1.
201Configuring rams.array.switchbox.row[row=6].ctl.r_action_o_mux_select.r_action_o_sel_action_rd_r_i to be 1.
202Configuring rams.array.row[row=6].ram[col=8].unit_ram_ctl.match_ram_write_data_mux_select to be select of 7.
203Configuring rams.array.row[row=6].ram[col=8].unit_ram_ctl.match_ram_read_data_mux_select to be select of 4.
204Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_type to be 2.
205Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_vpn to be 0.
206Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_logical_table to be 0.
207Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_ingress to be 1.
208Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_action_subword_out_en to be 1.
209Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_enable to be 1.
210Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=2].ram_unitram_adr_mux_select to be 1.
211Configuring rams.array.row[row=6].actiondata_error_uram_ctl[direction=0].actiondata_error_uram_ctl to be select of 0x40. (previous value = 0x0 OR new value = 0x40)
212Action data table table0__action__ is used by match table table0.
213Configuring rams.match.adrdist.adr_dist_action_data_adr_icxbar_ctl[match_logical_table_id=0].address_distr_to_logical_rows to be 0x2000.
214
215---- Hash Distribution Units for table table0__action__ ----
216Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x2 OR new value = 0x3)
217Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]218Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_address to be 2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]219Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_lo_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]220Configuring match input crossbar byte 0 to come from 32-bit PHV container 2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]221 That PHV byte contains {ipv4.dstAddr[7:0]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]222Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_address to be 2.
223Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_lo_enable to be 1.
224Configuring match input crossbar byte 1 to come from 32-bit PHV container 2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]225 That PHV byte contains {ipv4.dstAddr[15:8]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]226Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_address to be 2.
227Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_lo_enable to be 1.
228Configuring match input crossbar byte 2 to come from 32-bit PHV container 2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]229 That PHV byte contains {ipv4.dstAddr[23:16]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]230Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_address to be 3.
231Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_lo_enable to be 1.
232Configuring match input crossbar byte 3 to come from 32-bit PHV container 3.
233 That PHV byte contains {tcp.dstPort[7:0]}.
234Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_address to be 1.
235Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_lo_enable to be 1.
236Configuring match input crossbar byte 4 to come from 32-bit PHV container 1.
237 That PHV byte contains {ipv4.srcAddr[31:24]}.
238Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=5].match_input_xbar_816b_ctl_address to be 20.
239Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=5].match_input_xbar_816b_ctl_enable to be 1.
240Configuring match input crossbar byte 5 to come from 16-bit PHV container 4.
241 That PHV byte contains {tcp.srcPort[7:0]}.
242Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=6].match_input_xbar_816b_ctl_address to be 20.
243Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=6].match_input_xbar_816b_ctl_enable to be 1.
244Configuring match input crossbar byte 6 to come from 16-bit PHV container 4.
245 That PHV byte contains {tcp.dstPort[15:8]}.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]246Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=7].match_input_xbar_32b_ctl_address to be 2.
247Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=7].match_input_xbar_32b_ctl_lo_enable to be 1.
248Configuring match input crossbar byte 7 to come from 32-bit PHV container 2.
249 That PHV byte contains {ipv4.dstAddr[31:24]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]250Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_address to be 19.
251Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_enable to be 1.
252Configuring match input crossbar byte 8 to come from 16-bit PHV container 3.
253 That PHV byte contains {ipv4.srcAddr[7:0]}.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]254Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_address to be 19.
255Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_enable to be 1.
256Configuring match input crossbar byte 9 to come from 16-bit PHV container 3.
257 That PHV byte contains {ipv4.srcAddr[15:8]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]258Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_address to be 1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]259Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]260Configuring match input crossbar byte 10 to come from 8-bit PHV container 1.
261 That PHV byte contains {tcp.srcPort[15:8]}.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]262Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_address to be 0.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]263Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_enable to be 1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]264Configuring match input crossbar byte 11 to come from 8-bit PHV container 0.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]265 That PHV byte contains {ipv4.srcAddr[23:16]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]266Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0xe. (previous value = 0x0 OR new value = 0xe)
267Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x13. (previous value = 0x10 OR new value = 0x3)
268Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x18. (previous value = 0x0 OR new value = 0x18)
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]269Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x3. (previous value = 0x2 OR new value = 0x3)
270Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]271Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0xff.
272Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte1 to be 0xaf.
273Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte0 to be 0xfe.
274Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte1 to be 0xff.
275Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte0 to be 0x7f.
276Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte1 to be 0xff.
277Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte0 to be 0xfb.
278Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte1 to be 0x1f.
279Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0xfb.
280Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte1 to be 0xbf.
281Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte0 to be 0xe7.
282Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte1 to be 0xe6.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]283Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
284Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 1. (old value = 0 OR new value = 1).
285Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 8. (old value = 0 OR new value = 8).
286Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 1. (old value = 0 OR new value = 1).
287Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x0. (old value = 0x0 OR new value = 0x0).
288Configuring rams.match.merge.mau_hash_group_mask[which_16=0].mau_hash_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
289Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=1][control_group_index=0].mau_hash_group_xbar_ctl to be 0x8 (old value = 0x0 OR new value = 0x8).
290
291+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]292| Working on table table0 in stage 0 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]293+------------------------------------------------------------------------
294--> Ternary Match Table table0 with logical_table_id 0
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]295Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1).
296Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1).
297Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1).
298Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1).
299Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1).
300Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1).
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]301Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id).
302Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
303Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id).
304Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
305Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x7.
306Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_default to be 0x0.
307Configuring rams.match.merge.mau_action_instruction_adr_per_entry_en_mux_ctl[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_per_entry_en_mux_ctl to be 0x3.
308Configuring rams.match.merge.mau_actiondata_adr_default[table_type_index=1][physical_result_bus=0].mau_actiondata_adr_default to be 0x400001.
309Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=1].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
310Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x870a080.
311Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x44.
312Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]313Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x20.
314Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data1 to be 0x10.
315Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x20.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]316Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x1.
317Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=1][result_bus_number=0].mau_immediate_data_mask to be 0x0.
318Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=1][result_bus_number=0].mau_stats_adr_mask to be 0xffffe.
319Configuring rams.match.merge.mau_stats_adr_default[table_type_index=1][result_bus_number=0].mau_stats_adr_default to be 0x80000.
320Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x3 OR new value = 0x0)
321Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x3. (old value = 0x0 OR new value = 0x3)
322Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_address to be 16.
323Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_enable to be 1.
324Configuring match input crossbar byte 133 to come from 16-bit PHV container 0.
325 That PHV byte contains version/valid
326{unused[6:0], ig_intr_md.ingress_port[8:8]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]327Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_address to be 5.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]328Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_lo_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]329Configuring match input crossbar byte 128 to come from 32-bit PHV container 5.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]330 That PHV byte contains {ethernet.srcAddr[7:0]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]331Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_address to be 5.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]332Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_lo_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]333Configuring match input crossbar byte 129 to come from 32-bit PHV container 5.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]334 That PHV byte contains {ethernet.srcAddr[15:8]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]335Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_address to be 5.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]336Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_lo_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]337Configuring match input crossbar byte 130 to come from 32-bit PHV container 5.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]338 That PHV byte contains {ethernet.srcAddr[23:16]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]339Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_address to be 5.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]340Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_lo_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]341Configuring match input crossbar byte 131 to come from 32-bit PHV container 5.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]342 That PHV byte contains {ethernet.srcAddr[31:24]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]343Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_address to be 4.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]344Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_lo_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]345Configuring match input crossbar byte 132 to come from 32-bit PHV container 4.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]346 That PHV byte contains {ethernet.dstAddr[15:8]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]347Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_address to be 4.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]348Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_lo_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]349Configuring match input crossbar byte 134 to come from 32-bit PHV container 4.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]350 That PHV byte contains {ethernet.dstAddr[31:24]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]351Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_address to be 4.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]352Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_lo_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]353Configuring match input crossbar byte 135 to come from 32-bit PHV container 4.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]354 That PHV byte contains {ethernet.dstAddr[39:32]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]355Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_address to be 22.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]356Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]357Configuring match input crossbar byte 136 to come from 16-bit PHV container 6.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]358 That PHV byte contains {ethernet.etherType[7:0]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]359Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_address to be 4.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]360Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_lo_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]361Configuring match input crossbar byte 137 to come from 32-bit PHV container 4.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]362 That PHV byte contains {ethernet.dstAddr[23:16]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]363Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_address to be 21.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]364Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]365Configuring match input crossbar byte 138 to come from 16-bit PHV container 5.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]366 That PHV byte contains {ethernet.srcAddr[47:40]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]367Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_address to be 22.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]368Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]369Configuring match input crossbar byte 139 to come from 16-bit PHV container 6.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]370 That PHV byte contains {ethernet.etherType[15:8]}.
371Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_address to be 16.
372Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_enable to be 1.
373Configuring match input crossbar byte 140 to come from 16-bit PHV container 0.
374 That PHV byte contains {ig_intr_md.ingress_port[7:0]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]375Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_address to be 21.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]376Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]377Configuring match input crossbar byte 141 to come from 16-bit PHV container 5.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]378 That PHV byte contains {ethernet.dstAddr[7:0]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]379Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 3.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]380Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]381Configuring match input crossbar byte 142 to come from 8-bit PHV container 3.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]382 That PHV byte contains {ethernet.srcAddr[39:32]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]383Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]384Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]385Configuring match input crossbar byte 143 to come from 8-bit PHV container 2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]386 That PHV byte contains {ethernet.dstAddr[47:40]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]387Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x3e. (previous value = 0xe OR new value = 0x30)
388Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x1f. (previous value = 0x13 OR new value = 0xc)
389Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x79. (previous value = 0x18 OR new value = 0x61)
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]390
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]391--> Idletime Table for match table table0 in stage 0
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]392Looking at Map RAM: Row 7 Unit 0
393Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 0.
394Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 1.
395Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].two_way_idletime_notification to be 1.
396Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].per_flow_idletime to be 1.
397Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].idletime_bitwidth to be 2 (precision = 3 bits).
398Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_type to be 4.
399Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
400FIXME: Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn_members to be 0.
401Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn to be 0.
402Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
403Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
404Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
405Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
406Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 2.
407Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
408Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
409Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
410Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_stats_meter_adr_mux_select_idlet to be 1.
411Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0.
412Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1.
413Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0.
414Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1.
415Configuring rams.map_alu.row[row=7].adrmux.idletime_cfg_rd_clear_val[map_ram_index=0].idletime_cfg_rd_clear_val to be 0x36.
416 logical table ID is 0
417Configuring rams.match.adrdist.adr_dist_idletime_adr_oxbar_ctl.[entry_index=2].adr_dist_idletime_adr_oxbar_ctl be 0x4000 (previous value = 0x0 OR new value = 0x4000)
418Note that rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_en must be programmed by run time.
419Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_offset be 0x0.
420Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_size be 0x0.
421Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_pos be 0x0.
422Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_en be 0x0.
423Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_interval be 0x7.
424Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_offset be 0x0.
425Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_size be 0x0.
426Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_pos be 0x0.
427Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_en be 0.
428Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_size be 2.
429Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_direct be 1.
430Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=2].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1)
431Configuring rams.match.merge.mau_idletime_adr_mask[table_type_index=1][result_bus_number=0].mau_idletime_adr_mask to be 0x1ffff8.
432Configuring rams.match.merge.mau_idletime_adr_default[table_type_index=1][result_bus_number=0].idletime_adr_default to be 0x100003.
433Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x4602.
434Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1.
435Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 1.
436Micro instruction added in VLIW 0 for 16-bit position 2 for table table0.
437 Assembled as 0x4602 (or decimal 17922)
438 Micro Instruction deposit-field for PHV Container 130 has bit width 23
439 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
440 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
441 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
442 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
443 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
444 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
445 Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
446 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
447
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]448Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x6 OR new value = 0x4)
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]449Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a07.
450Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_color to be 0.
451Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_parity to be 0.
452Micro instruction added in VLIW 1 for 16-bit position 7 for table table0.
453 Assembled as 0xc7a07 (or decimal 817671)
454 Micro Instruction alu_a for PHV Container 135 has bit width 23
455 Field Src2 [3:0] : 0x7 (4 bits in instruction bits [3:0])
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]456 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
457 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
458 Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
459 Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20])
460
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]461Configuring dp.imem.imem_subword16[unit_number=8][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a28.
462Configuring dp.imem.imem_subword16[unit_number=8][vliw_instruction_number=1].imem_subword16_color to be 0.
463Configuring dp.imem.imem_subword16[unit_number=8][vliw_instruction_number=1].imem_subword16_parity to be 1.
464Micro instruction added in VLIW 1 for 16-bit position 8 for table table0.
465 Assembled as 0xc7a28 (or decimal 817704)
466 Micro Instruction alu_a for PHV Container 136 has bit width 23
467 Field Src2 [3:0] : 0x8 (4 bits in instruction bits [3:0])
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]468 Field Src1 [4:0] : 0x2 (5 bits in instruction bits [8:4])
469 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
470 Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
471 Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20])
472
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]473Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_instr to be 0x4602.
474Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_color to be 1.
475Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_parity to be 1.
476Micro instruction added in VLIW 1 for 16-bit position 2 for table table0.
477 Assembled as 0x4602 (or decimal 17922)
478 Micro Instruction deposit-field for PHV Container 130 has bit width 23
479 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
480 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
481 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
482 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
483 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
484 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
485 Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
486 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
487
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]488Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_instr to be 0x594.
489Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_color to be 1.
490Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_parity to be 0.
491Micro instruction added in VLIW 1 for 8-bit position 4 for table table0.
492 Assembled as 0x594 (or decimal 1428)
493 Micro Instruction deposit-field for PHV Container 68 has bit width 20
494 Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]495 Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
496 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
497 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
498 Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11])
499 Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14])
500 Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16])
501 Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
502
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]503Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_instr to be 0x39fc01.
504Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_color to be 1.
505Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_parity to be 0.
506Micro instruction added in VLIW 1 for 16-bit position 1 for table table0.
507 Assembled as 0x39fc01 (or decimal 3800065)
508 Micro Instruction deposit-field for PHV Container 129 has bit width 23
509 Field Src2 [3:0] : 0x1 (4 bits in instruction bits [3:0])
510 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
511 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
512 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
513 Field high_bit [3:0] : 0xf (4 bits in instruction bits [14:11])
514 Field low_bit_lo [0:0] : 0x1 (1 bits in instruction bits [15:15])
515 Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16])
516 Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20])
517
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]518Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x10. (previous value = 0x10 OR new value = 0x10)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]519Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x7. (previous value = 0x6 OR new value = 0x7)
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]520Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_instr to be 0xb7d95.
521Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_color to be 0.
522Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_parity to be 1.
523Micro instruction added in VLIW 2 for 8-bit position 5 for table table0.
524 Assembled as 0xb7d95 (or decimal 753045)
525 Micro Instruction deposit-field for PHV Container 69 has bit width 20
526 Field Src2 [3:0] : 0x5 (4 bits in instruction bits [3:0])
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]527 Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
528 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
529 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
530 Field high_bit [2:0] : 0x7 (3 bits in instruction bits [13:11])
531 Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14])
532 Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16])
533 Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19])
534
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]535Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x30. (previous value = 0x10 OR new value = 0x20)
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]536Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].idletime_adr_payload_shifter_en to be 1.
537Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].stats_adr_payload_shifter_en to be 1.
538Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].actiondata_adr_payload_shifter_en to be 1.
539Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].action_instruction_adr_payload_shifter_en to be 1.
540Configuring rams.match.merge.mau_table_counter_ctl[half_index=0].mau_table_counter_ctl to be 0x2. (previous value = 0x0 OR new value = 0x2)
541dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit']
542Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data_dirtcam_mode to be 0x155.
543Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vbit_dirtcam_mode to be 0x1.
544Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data1_select to be 1.
545Configuring tcams.col[col=1].tcam_mode[row=9].tcam_chain_out_enable to be 0.
546Configuring tcams.col[col=1].tcam_mode[row=9].tcam_ingress to be 1.
547Configuring tcams.col[col=1].tcam_mode[row=9].tcam_match_output_enable to be 1.
548Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vpn to be 0.
549Configuring tcams.col[col=1].tcam_mode[row=9].tcam_logical_table to be 0.
550TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit.
551Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=0] to be 15.
552Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=1] to be 15.
553Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=2] to be 15.
554Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=3] to be 15.
555Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=4] to be 15.
556Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=5] to be 15.
557Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=6] to be 15.
558Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=7] to be 15.
559Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_select to be 0 (don't care).
560Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_enable to be 1.
561Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_select to be 2.
562Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_enable to be 1.
563dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit']
564Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data_dirtcam_mode to be 0x155.
565Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vbit_dirtcam_mode to be 0x0.
566Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data1_select to be 1.
567Configuring tcams.col[col=1].tcam_mode[row=10].tcam_chain_out_enable to be 1.
568Configuring tcams.col[col=1].tcam_mode[row=10].tcam_ingress to be 1.
569Configuring tcams.col[col=1].tcam_mode[row=10].tcam_match_output_enable to be 0.
570Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vpn to be 0.
571Configuring tcams.col[col=1].tcam_mode[row=10].tcam_logical_table to be 0.
572TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit.
573Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15.
574Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15.
575Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15.
576Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15.
577Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15.
578Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15.
579Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15.
580Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15.
581Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_select to be 3 (version on [3:2] and valid bits for [1:0]).
582Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_enable to be 1.
583Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0.
584Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1.
585Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_select to be 1.
586Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_enable to be 1.
587dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit']
588Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data_dirtcam_mode to be 0x155.
589Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vbit_dirtcam_mode to be 0x1.
590Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data1_select to be 1.
591Configuring tcams.col[col=1].tcam_mode[row=11].tcam_chain_out_enable to be 1.
592Configuring tcams.col[col=1].tcam_mode[row=11].tcam_ingress to be 1.
593Configuring tcams.col[col=1].tcam_mode[row=11].tcam_match_output_enable to be 0.
594Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vpn to be 0.
595Configuring tcams.col[col=1].tcam_mode[row=11].tcam_logical_table to be 0.
596TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit.
597Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15.
598Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15.
599Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15.
600Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15.
601Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15.
602Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15.
603Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15.
604Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15.
605Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_select to be 0 (extra byte low nibble [3:0]).
606Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_enable to be 1.
607Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0.
608Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1.
609Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_select to be 0.
610Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_enable to be 1.
611Configuring tcams.col[col=0].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x0.
612Configuring tcams.col[col=1].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x200.
613--> Ternary Indirection table for Match Table table0 with logical_table_id 0
614Configuring tcams.tcam_match_adr_shift[tcam_table_id=0] to be left shift of 1.
615Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_write_data_mux_select to be select of 7.
616Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_read_data_mux_select to be select of 7.
617Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.tind_result_bus_select to be select of 1.
618Configuring rams.map_alu.row[row=0].adrmux.ram_address_mux_ctl[column_half=0][column_index=2].ram_unitram_adr_mux_select to be 2.
619Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_type to be 6.
620Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_vpn to be 0.
621Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_logical_table to be 0.
622Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_ingress to be 1.
623Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_enable to be 1.
624Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id).
625Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_enable to be 1.
626Configuring rams.array.row[row=0].tind_ecc_error_uram_ctl[direction=0].tind_ecc_error_uram_ctl to be select of 0x1. (previous value = 0x0 OR new value = 0x1)
627Configuring rams.match.merge.tind_ram_data_size[tind_bus_number=0].tind_ram_data_size to be code 2.
628Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id).
629Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_enable to be 1.
630TODO: rams.match.merge.tind_bus_prop[tind_bus_number=0] is currently always set to 1.
631Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].tcam_piped to be 1.
632Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].enabled to be 1.
633Configuring rams.match.merge.mau_action_instruction_adr_tcam_shiftcount[physical_result_bus=0].mau_action_instruction_adr_tcam_shiftcount to be 1.
634Configuring rams.match.merge.mau_actiondata_adr_mask[table_type_index=1][physical_result_bus=0].mau_actiondata_adr_mask to be 0x3ffffc.
635Configuring rams.match.merge.mau_actiondata_adr_tcam_shiftcount[physical_result_bus=0].mau_actiondata_adr_tcam_shiftcount to be 68.
636Configuring rams.match.merge.mau_idletime_adr_tcam_shiftcount[result_bus_number=0].mau_idletime_adr_tcam_shiftcount to be 0x42.
637Configuring rams.match.merge.mau_stats_adr_tcam_shiftcount[result_bus_index=0].mau_stats_adr_tcam_shiftcount to be 0x47.
638Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_select to be 0 (logical table id).
639Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_enable to be 1.
640TODO: rams.match.merge.tcam_table_prop[tcam_table_id=0] is currently always set to 1.
641Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].tcam_piped to be 1.
642Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].enabled to be 1.
643Configuring tcams.tcam_output_table_thread[tcam_table_id=0].tcam_output_table_thread to be 1.
644TODO: tcams.tcam_piped is currently always set to True for ingress and egress.
645Configuring tcams.tcam_piped to be 3.
646Configuring cfg_regs.mau_cfg_movereg_tcam_only.mau_cfg_movereg_tcam_only to be 0x1. (previous value = 0x0 OR new value = 0x1)
647
648+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]649| Working on table table0_counter in stage 0 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]650+------------------------------------------------------------------------
651Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
652Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
653Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
654Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
655Note that unitram_vpn does not need to be programmed for synthetic two port rams.
656Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0.
657Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
658Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
659Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
660Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
661Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
662Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
663Note that unitram_vpn does not need to be programmed for synthetic two port rams.
664Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0.
665Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
666Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
667Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
668Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
669Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
670Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
671Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
672Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
673Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
674Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
675Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
676Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
677Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
678Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
679Stat table table0_counter is used by match table table0.
680Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8)
681Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
682Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
683Note that map ram vpn does not need to be configured for synthetic two port map rams.
684Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
685Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
686Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
687Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
688Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
689Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
690Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
691Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
692Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0.
693Note that map ram vpn does not need to be configured for synthetic two port map rams.
694Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
695Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
696Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
697Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
698Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
699Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
700Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
701For counter width 32 and N = 4096
702 number iterations = 32
703 b_cur = 379488672.0
704 eqn(b_cur) = 4294964039.26
705 max_counter_value = 4294967295
706Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
707Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
708Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
709Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
710Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
711Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
712Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4.
713Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1.
714Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1.
715TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0.
716Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x0.
717Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4.
718Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1.
719Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0.
720Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0.
721Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0.
722Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0.
723Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0.
724Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
725Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
726Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1.
727Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3.
728Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_direct be 1.
729Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=0].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1)
730Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_tcam be 1.
731Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x0.
732Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x7. ( previous value = 0x0 OR new value = 0x7)
733Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x1.
734+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]735Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 12.
736Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
737Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]738Configuring rams.match.merge.exact_match_delay_thread[copy_index=0].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
739Configuring rams.match.merge.exact_match_delay_thread[copy_index=1].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
740Configuring rams.match.merge.exact_match_delay_thread[copy_index=2].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]741Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 10.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]742Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]743Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]744Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
745Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
746Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
747Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]748Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x3.
749Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x2.
750Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]751Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]752Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]753Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
754Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
755Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
756Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 16.
757Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 21.
758Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
759Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
760Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
761Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
762Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
763Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
764Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
765Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
766--------------------------------------------
767Configuration for unused statistics ALUs.
768Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
769Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
770Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
771+------------------------------------------------------------------------
772Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
773Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
774Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]775Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
776Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
777Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]778Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
779Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
780Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]781Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
782Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
783Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]784Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
785Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
786Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
787Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
788Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
789Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]790Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
791Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
792Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
793Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
794Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 1.
795Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 1.
796Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
797Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
798Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
799Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
800Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
801Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
802+------------------------------------------------------------------------
803Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 19.
804Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 2.
805Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
806Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
807Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
808Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]809Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]810Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]811Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
812Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]813Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
814Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
815Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
816Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
817
818+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]819| MAU Stage 1
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]820+------------------------------------------------------------------------
821
822+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]823| Working on table ecmp_group_table__action__ in stage 1 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]824+------------------------------------------------------------------------
825--> Action Data Table ecmp_group_table__action__ with logical_table_id 0 that is reference type is 'direct'
826Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_select to be 4.
827Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_enable to be 1.
828
829+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]830| Working on table ecmp_group_table in stage 1 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]831+------------------------------------------------------------------------
832--> Hash Match Table ecmp_group_table with logical_table_id 0
833Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
834Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
835Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
836Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
837Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
838Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
839Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=14].enabled_4bit_muxctl_select to be 0 (logical table id).
840Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=14].enabled_4bit_muxctl_enable to be 1.
841Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=14].enabled_4bit_muxctl_select to be 0 (logical table id).
842Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=14].enabled_4bit_muxctl_enable to be 1.
843Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=14].mau_action_instruction_adr_mask to be 0x0.
844Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=14].mau_action_instruction_adr_default to be 0x40.
845Configuring rams.match.merge.mau_action_instruction_adr_per_entry_en_mux_ctl[table_type_index=0][physical_result_bus=14].mau_action_instruction_adr_per_entry_en_mux_ctl to be 0x0.
846Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
847Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x41.
848Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
849Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]850Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x20.
851Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x20.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]852Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x0.
853Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=0][result_bus_number=14].mau_immediate_data_mask to be 0xffff.
854Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=0][result_bus_number=14].mau_stats_adr_mask to be 0xffffe.
855Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=14].mau_stats_adr_default to be 0x80000.
856Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
857Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]858Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 24.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]859Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]860Configuring match input crossbar byte 0 to come from 16-bit PHV container 8.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]861 That PHV byte contains {ecmp_metadata.selector[7:0]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]862Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 24.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]863Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]864Configuring match input crossbar byte 1 to come from 16-bit PHV container 8.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]865 That PHV byte contains {ecmp_metadata.selector[15:8]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]866Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 23.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]867Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]868Configuring match input crossbar byte 2 to come from 16-bit PHV container 7.
Carmelo Cascone8aa05482017-09-12 13:21:59 +0200[diff] [blame]869 That PHV byte contains {ecmp_metadata.group_id[7:0]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]870Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 23.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]871Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_enable to be 1.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]872Configuring match input crossbar byte 3 to come from 16-bit PHV container 7.
Carmelo Cascone8aa05482017-09-12 13:21:59 +0200[diff] [blame]873 That PHV byte contains {ecmp_metadata.group_id[15:8]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]874Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x80. (previous value = 0x0 OR new value = 0x80)
875Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=9].match_input_xbar_din_power_ctl to be 0x1. (previous value = 0x0 OR new value = 0x1)
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]876Configuring dp.xbar_hash.hash.hash_seed[output_bit=2].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
877Configuring dp.xbar_hash.hash.hash_seed[output_bit=3].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
878Configuring dp.xbar_hash.hash.hash_seed[output_bit=5].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
879Configuring dp.xbar_hash.hash.hash_seed[output_bit=7].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
880Configuring dp.xbar_hash.hash.hash_seed[output_bit=8].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
881Configuring dp.xbar_hash.hash.hash_seed[output_bit=10].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
882Configuring dp.xbar_hash.hash.hash_seed[output_bit=11].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
883Configuring dp.xbar_hash.hash.hash_seed[output_bit=15].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
884Configuring dp.xbar_hash.hash.hash_seed[output_bit=19].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
885Configuring dp.xbar_hash.hash.hash_seed[output_bit=20].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
886Configuring dp.xbar_hash.hash.hash_seed[output_bit=21].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
887Configuring dp.xbar_hash.hash.hash_seed[output_bit=23].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
888Configuring dp.xbar_hash.hash.hash_seed[output_bit=24].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
889Configuring dp.xbar_hash.hash.hash_seed[output_bit=25].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
890Configuring dp.xbar_hash.hash.hash_seed[output_bit=26].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
891Configuring dp.xbar_hash.hash.hash_seed[output_bit=28].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
892Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
893Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
894Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x1.
895Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte1 to be 0x84.
896Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte0 to be 0xa9.
897Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte1 to be 0xbe.
898Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte0 to be 0x2.
899Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte1 to be 0xa0.
900Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=1].byte0 to be 0xd3.
901Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=1].byte1 to be 0xc0.
902Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte0 to be 0x4.
903Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte1 to be 0xd4.
904Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=2].byte0 to be 0xdc.
905Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=2].byte1 to be 0x26.
906Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte0 to be 0x8.
907Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte1 to be 0x38.
908Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=3].byte0 to be 0xd0.
909Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=3].byte1 to be 0x78.
910Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte0 to be 0x10.
911Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte1 to be 0x8.
912Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=4].byte0 to be 0xdc.
913Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=4].byte1 to be 0xf4.
914Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte0 to be 0x20.
915Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte1 to be 0x24.
916Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=5].byte0 to be 0xe.
917Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=5].byte1 to be 0x90.
918Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte0 to be 0x40.
919Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte1 to be 0xf4.
920Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=6].byte0 to be 0x3e.
921Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=6].byte1 to be 0x8e.
922Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte0 to be 0x80.
923Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte1 to be 0x8c.
924Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=7].byte0 to be 0x7d.
925Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=7].byte1 to be 0x4.
926Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=8].byte1 to be 0x79.
927Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=8].byte0 to be 0x12.
928Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=8].byte1 to be 0x40.
929Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=9].byte1 to be 0xee.
930Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=9].byte0 to be 0x30.
931Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=9].byte1 to be 0x21.
932Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=10].byte1 to be 0x7a.
933Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=10].byte0 to be 0xf0.
934Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=10].byte1 to be 0x7f.
935Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=11].byte0 to be 0x1.
936Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=11].byte1 to be 0x5c.
937Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=11].byte0 to be 0x54.
938Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=11].byte1 to be 0x14.
939Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=12].byte0 to be 0x2.
940Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=12].byte1 to be 0x94.
941Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=12].byte0 to be 0x62.
942Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=12].byte1 to be 0x63.
943Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=13].byte0 to be 0x4.
944Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=13].byte1 to be 0xb4.
945Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=13].byte0 to be 0x47.
946Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=13].byte1 to be 0x30.
947Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=14].byte0 to be 0x8.
948Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=14].byte1 to be 0xfc.
949Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=14].byte0 to be 0xa5.
950Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=14].byte1 to be 0xaa.
951Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=15].byte0 to be 0x10.
952Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=15].byte1 to be 0x48.
953Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=15].byte0 to be 0xee.
954Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=15].byte1 to be 0x84.
955Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=16].byte0 to be 0x20.
956Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=16].byte1 to be 0xb4.
957Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=16].byte0 to be 0xf1.
958Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=16].byte1 to be 0x93.
959Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=17].byte0 to be 0x40.
960Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=17].byte1 to be 0xb4.
961Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=17].byte0 to be 0xd7.
962Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=17].byte1 to be 0x19.
963Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=18].byte0 to be 0x80.
964Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=18].byte1 to be 0xec.
965Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=18].byte0 to be 0x62.
966Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=18].byte1 to be 0x13.
967Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=19].byte1 to be 0x29.
968Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=19].byte0 to be 0x12.
969Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=19].byte1 to be 0x16.
970Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=20].byte1 to be 0x45.
971Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=20].byte0 to be 0xe0.
972Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=20].byte1 to be 0xfe.
973Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=21].byte1 to be 0x6.
974Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=21].byte0 to be 0xd1.
975Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=21].byte1 to be 0x65.
976Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=22].byte0 to be 0x1.
977Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=22].byte1 to be 0x84.
978Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=22].byte0 to be 0x33.
979Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=22].byte1 to be 0xa4.
980Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=23].byte0 to be 0x2.
981Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=23].byte1 to be 0xc.
982Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=23].byte0 to be 0x7c.
983Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=23].byte1 to be 0xe.
984Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=24].byte0 to be 0x4.
985Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=24].byte1 to be 0x4c.
986Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=24].byte0 to be 0x8d.
987Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=24].byte1 to be 0x6f.
988Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=25].byte0 to be 0x8.
989Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=25].byte1 to be 0x2c.
990Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=25].byte0 to be 0xc2.
991Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=25].byte1 to be 0xf9.
992Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=26].byte0 to be 0x10.
993Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=26].byte1 to be 0xd0.
994Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=26].byte0 to be 0x17.
995Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=26].byte1 to be 0xf9.
996Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=27].byte0 to be 0x20.
997Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=27].byte1 to be 0x8.
998Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=27].byte0 to be 0x6c.
999Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=27].byte1 to be 0x32.
1000Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=28].byte0 to be 0x40.
1001Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=28].byte1 to be 0x74.
1002Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=28].byte0 to be 0xdc.
1003Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=28].byte1 to be 0xb7.
1004Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=29].byte0 to be 0x80.
1005Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=29].byte1 to be 0xf8.
1006Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=29].byte0 to be 0x5c.
1007Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=29].byte1 to be 0xa.
1008Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
1009Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x4602.
1010Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1.
1011Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 1.
1012Micro instruction added in VLIW 0 for 16-bit position 2 for table ecmp_group_table.
1013 Assembled as 0x4602 (or decimal 17922)
1014 Micro Instruction deposit-field for PHV Container 130 has bit width 23
1015 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
1016 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
1017 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
1018 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
1019 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
1020 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
1021 Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
1022 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
1023
1024Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
1025Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=14].stats_adr_payload_shifter_en to be 1.
1026Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=14].action_instruction_adr_payload_shifter_en to be 1.
1027Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=14].immediate_data_payload_shifter_en to be 1.
1028Configuring rams.match.merge.mau_table_counter_ctl[half_index=0].mau_table_counter_ctl to be 0x2. (previous value = 0x0 OR new value = 0x2)
1029--> Hash Match Way 0
1030Packed entry for hash way 0 is
1031 [0] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 0))
1032 [1] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 1))
1033 [2] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 2))
1034 [3] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 3))
1035 [4] = (field_bit=4, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 4))
1036 [5] = (field_bit=5, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 5))
1037 [6] = (field_bit=6, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 6))
1038 [7] = (field_bit=7, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 7))
1039 [8] = (field_bit=8, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 8))
1040 [9] = (field_bit=9, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 9))
1041 [10] = (field_bit=10, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 10))
1042 [11] = (field_bit=11, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 11))
1043 [12] = (field_bit=12, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 12))
1044 [13] = (field_bit=13, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 13))
1045 [14] = (field_bit=14, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 14))
1046 [15] = (field_bit=15, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 15))
Carmelo Cascone8aa05482017-09-12 13:21:59 +0200[diff] [blame]1047 [16] = (field_bit=0, hash_match_group_bit=16, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 0))
1048 [17] = (field_bit=1, hash_match_group_bit=17, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 1))
1049 [18] = (field_bit=2, hash_match_group_bit=18, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 2))
1050 [19] = (field_bit=3, hash_match_group_bit=19, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 3))
1051 [20] = (field_bit=4, hash_match_group_bit=20, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 4))
1052 [21] = (field_bit=5, hash_match_group_bit=21, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 5))
1053 [22] = (field_bit=6, hash_match_group_bit=22, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 6))
1054 [23] = (field_bit=7, hash_match_group_bit=23, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 7))
1055 [24] = (field_bit=8, hash_match_group_bit=24, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 8))
1056 [25] = (field_bit=9, hash_match_group_bit=25, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 9))
1057 [26] = (field_bit=10, hash_match_group_bit=26, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 10))
1058 [27] = (field_bit=11, hash_match_group_bit=27, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 11))
1059 [28] = (field_bit=12, hash_match_group_bit=28, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 12))
1060 [29] = (field_bit=13, hash_match_group_bit=29, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 13))
1061 [30] = (field_bit=14, hash_match_group_bit=30, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 14))
1062 [31] = (field_bit=15, hash_match_group_bit=31, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 15))
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1063 [32] = None
1064 [33] = None
1065 [34] = (field_bit=10, hash_match_group_bit=10, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 10))
1066 [35] = (field_bit=11, hash_match_group_bit=11, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 11))
1067 [36] = (field_bit=12, hash_match_group_bit=12, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 12))
1068 [37] = (field_bit=13, hash_match_group_bit=13, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 13))
1069 [38] = (field_bit=14, hash_match_group_bit=14, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 14))
1070 [39] = (field_bit=15, hash_match_group_bit=15, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 15))
1071 [40] = None
1072 [41] = None
1073 [42] = None
1074 [43] = None
1075 [44] = None
1076 [45] = None
1077 [46] = None
1078 [47] = None
1079 [48] = None
1080 [49] = None
1081 [50] = None
1082 [51] = None
1083 [52] = None
1084 [53] = None
1085 [54] = None
1086 [55] = None
1087 [56] = None
1088 [57] = None
1089 [58] = None
1090 [59] = None
1091 [60] = None
1092 [61] = None
1093 [62] = None
1094 [63] = None
1095 [64] = None
1096 [65] = None
1097 [66] = None
1098 [67] = None
1099 [68] = None
1100 [69] = None
1101 [70] = None
1102 [71] = None
1103 [72] = None
1104 [73] = None
1105 [74] = None
1106 [75] = None
1107 [76] = None
1108 [77] = None
1109 [78] = None
1110 [79] = None
1111 [80] = None
1112 [81] = None
1113 [82] = None
1114 [83] = None
1115 [84] = None
1116 [85] = None
1117 [86] = None
1118 [87] = None
1119 [88] = None
1120 [89] = None
1121 [90] = None
1122 [91] = None
1123 [92] = None
1124 [93] = None
1125 [94] = None
1126 [95] = None
1127 [96] = None
1128 [97] = None
1129 [98] = None
1130 [99] = None
1131 [100] = None
1132 [101] = None
1133 [102] = None
1134 [103] = None
1135 [104] = None
1136 [105] = None
1137 [106] = None
1138 [107] = None
1139 [108] = None
1140 [109] = None
1141 [110] = None
1142 [111] = None
1143 [112] = None
1144 [113] = None
1145 [114] = None
1146 [115] = None
1147 [116] = None
1148 [117] = None
1149 [118] = None
1150 [119] = None
1151 [120] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 0))
1152 [121] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 1))
1153 [122] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 2))
1154 [123] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 3))
1155 [124] = None
1156 [125] = None
1157 [126] = None
1158 [127] = None
1159
1160Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=0].match_mask to be 0xffff.
1161Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=1].match_mask to be 0xffffff03.
1162Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=2].match_mask to be 0xffffffff.
1163Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=3].match_mask to be 0xf0ffffff.
1164Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_ram_write_data_mux_select to be 7.
1165Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_ram_read_data_mux_select to be 7.
1166Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_result_bus_select to be 1.
1167Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_entry_enable to be 1.
1168Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_ram_logical_table to be 0x0.
1169For entry_in_ram_word 0, should have vpn 0, with lower_two_bits of 0 and upper_vpn of 0
1170for entry_in_ram_word 0, use lsbs of 0
1171Configuring rams.array.row[row=7].ram[column=2].match_ram_vpn.match_ram_vpn0 to be 0.
1172Configuring rams.array.row[row=7].ram[column=2].match_ram_vpn.match_ram_vpn_lsbs to be 0x0.
1173version valid nibbles are : [30]
1174Configuring rams.array.row[row=7].ram[column=2].match_nibble_s0q1_enable.match_nibble_s0q1_enable to be 0xbfffffff.
1175Configuring rams.array.row[row=7].ram[column=2].match_nibble_s1q0_enable.match_nibble_s1q0_enable to be 0xffffffff.
1176Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=0].mask_bytes_0_to_13 to be 0x3fe3.
1177Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=0].mask_nibbles_28_to_31 to be 0xb.
1178Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=1].mask_bytes_0_to_13 to be 0x3fff.
1179Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=1].mask_nibbles_28_to_31 to be 0xf.
1180Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=2].mask_bytes_0_to_13 to be 0x3fff.
1181Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=2].mask_nibbles_28_to_31 to be 0xf.
1182Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=3].mask_bytes_0_to_13 to be 0x3fff.
1183Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=3].mask_nibbles_28_to_31 to be 0xf.
1184Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=4].mask_bytes_0_to_13 to be 0x3fff.
1185Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=4].mask_nibbles_28_to_31 to be 0xf.
1186Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1187Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1188Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1189Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1190Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1191Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1192Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1193Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1194Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1195Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1196Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1197Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1198Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1199Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1200Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1201Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1202Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1203Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1204Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1205Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1206Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1207Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1208Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1209Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1210Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1211Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1212Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
1213Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
1214Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_thread to be 0.
1215Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=2].exactmatch_bank_enable_bank_mask to be 0x0.
1216Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=2].exactmatch_bank_enable_bank_id to be 0x0.
1217Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=2].exactmatch_bank_enable_inp_sel to be 1.
1218Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
1219Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
1220Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=2].enabled_4bit_muxctl_select to be 0.
1221Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=2].enabled_4bit_muxctl_enable to be 1.
1222Configuring rams.match.merge.mau_action_instruction_adr_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_action_instruction_adr_exact_shiftcount to be 0.
1223Configuring rams.match.merge.mau_immediate_data_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_immediate_data_exact_shiftcount to be 0.
1224Configuring rams.match.merge.mau_stats_adr_exact_shiftcount[result_bus_number = 14][entry_in_ram_word=0].mau_stats_adr_exact_shiftcount to be 0x46.
1225Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_type to be 1.
1226Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_logical_table to be 0.
1227Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_ingress to be 1.
1228Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_enable to be 1.
1229Configuring rams.array.row[row=7].emm_ecc_error_uram_ctl[direction=0].emm_ecc_error_uram_ctl to be select of 0x1. (previous value = 0x0 OR new value = 0x1)
1230In Ram Word 0:
1231 wide entry 0 occupied ram word entry 0
1232Configuring rams.match.merge.col[col_number=2].row_action_nxtable_bus_drive[row_number=7].row_action_nxtable_bus_drive to be 1.
1233Configuring rams.match.merge.col[col_number=2].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_select to be 14 (hit signal to output on).
1234Configuring rams.match.merge.col[col_number=2].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1.
1235--> Hash Match Way 1
1236Packed entry for hash way 1 is
1237 [0] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 0))
1238 [1] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 1))
1239 [2] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 2))
1240 [3] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 3))
1241 [4] = (field_bit=4, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 4))
1242 [5] = (field_bit=5, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 5))
1243 [6] = (field_bit=6, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 6))
1244 [7] = (field_bit=7, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 7))
1245 [8] = (field_bit=8, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 8))
1246 [9] = (field_bit=9, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 9))
1247 [10] = (field_bit=10, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 10))
1248 [11] = (field_bit=11, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 11))
1249 [12] = (field_bit=12, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 12))
1250 [13] = (field_bit=13, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 13))
1251 [14] = (field_bit=14, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 14))
1252 [15] = (field_bit=15, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 15))
Carmelo Cascone8aa05482017-09-12 13:21:59 +0200[diff] [blame]1253 [16] = (field_bit=0, hash_match_group_bit=16, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 0))
1254 [17] = (field_bit=1, hash_match_group_bit=17, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 1))
1255 [18] = (field_bit=2, hash_match_group_bit=18, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 2))
1256 [19] = (field_bit=3, hash_match_group_bit=19, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 3))
1257 [20] = (field_bit=4, hash_match_group_bit=20, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 4))
1258 [21] = (field_bit=5, hash_match_group_bit=21, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 5))
1259 [22] = (field_bit=6, hash_match_group_bit=22, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 6))
1260 [23] = (field_bit=7, hash_match_group_bit=23, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 7))
1261 [24] = (field_bit=8, hash_match_group_bit=24, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 8))
1262 [25] = (field_bit=9, hash_match_group_bit=25, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 9))
1263 [26] = (field_bit=10, hash_match_group_bit=26, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 10))
1264 [27] = (field_bit=11, hash_match_group_bit=27, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 11))
1265 [28] = (field_bit=12, hash_match_group_bit=28, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 12))
1266 [29] = (field_bit=13, hash_match_group_bit=29, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 13))
1267 [30] = (field_bit=14, hash_match_group_bit=30, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 14))
1268 [31] = (field_bit=15, hash_match_group_bit=31, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 15))
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1269 [32] = None
1270 [33] = None
1271 [34] = (field_bit=10, hash_match_group_bit=10, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 10))
1272 [35] = (field_bit=11, hash_match_group_bit=11, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 11))
1273 [36] = (field_bit=12, hash_match_group_bit=12, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 12))
1274 [37] = (field_bit=13, hash_match_group_bit=13, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 13))
1275 [38] = (field_bit=14, hash_match_group_bit=14, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 14))
1276 [39] = (field_bit=15, hash_match_group_bit=15, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 15))
1277 [40] = None
1278 [41] = None
1279 [42] = None
1280 [43] = None
1281 [44] = None
1282 [45] = None
1283 [46] = None
1284 [47] = None
1285 [48] = None
1286 [49] = None
1287 [50] = None
1288 [51] = None
1289 [52] = None
1290 [53] = None
1291 [54] = None
1292 [55] = None
1293 [56] = None
1294 [57] = None
1295 [58] = None
1296 [59] = None
1297 [60] = None
1298 [61] = None
1299 [62] = None
1300 [63] = None
1301 [64] = None
1302 [65] = None
1303 [66] = None
1304 [67] = None
1305 [68] = None
1306 [69] = None
1307 [70] = None
1308 [71] = None
1309 [72] = None
1310 [73] = None
1311 [74] = None
1312 [75] = None
1313 [76] = None
1314 [77] = None
1315 [78] = None
1316 [79] = None
1317 [80] = None
1318 [81] = None
1319 [82] = None
1320 [83] = None
1321 [84] = None
1322 [85] = None
1323 [86] = None
1324 [87] = None
1325 [88] = None
1326 [89] = None
1327 [90] = None
1328 [91] = None
1329 [92] = None
1330 [93] = None
1331 [94] = None
1332 [95] = None
1333 [96] = None
1334 [97] = None
1335 [98] = None
1336 [99] = None
1337 [100] = None
1338 [101] = None
1339 [102] = None
1340 [103] = None
1341 [104] = None
1342 [105] = None
1343 [106] = None
1344 [107] = None
1345 [108] = None
1346 [109] = None
1347 [110] = None
1348 [111] = None
1349 [112] = None
1350 [113] = None
1351 [114] = None
1352 [115] = None
1353 [116] = None
1354 [117] = None
1355 [118] = None
1356 [119] = None
1357 [120] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 0))
1358 [121] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 1))
1359 [122] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 2))
1360 [123] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 3))
1361 [124] = None
1362 [125] = None
1363 [126] = None
1364 [127] = None
1365
1366Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=0].match_mask to be 0xffff.
1367Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=1].match_mask to be 0xffffff03.
1368Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=2].match_mask to be 0xffffffff.
1369Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=3].match_mask to be 0xf0ffffff.
1370Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_ram_write_data_mux_select to be 7.
1371Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_ram_read_data_mux_select to be 7.
1372Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_result_bus_select to be 1.
1373Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_entry_enable to be 1.
1374Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_ram_logical_table to be 0x0.
1375For entry_in_ram_word 0, should have vpn 1, with lower_two_bits of 1 and upper_vpn of 0
1376for entry_in_ram_word 0, use lsbs of 1
1377Configuring rams.array.row[row=7].ram[column=3].match_ram_vpn.match_ram_vpn0 to be 0.
1378Configuring rams.array.row[row=7].ram[column=3].match_ram_vpn.match_ram_vpn_lsbs to be 0x1.
1379version valid nibbles are : [30]
1380Configuring rams.array.row[row=7].ram[column=3].match_nibble_s0q1_enable.match_nibble_s0q1_enable to be 0xbfffffff.
1381Configuring rams.array.row[row=7].ram[column=3].match_nibble_s1q0_enable.match_nibble_s1q0_enable to be 0xffffffff.
1382Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=0].mask_bytes_0_to_13 to be 0x3fe3.
1383Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=0].mask_nibbles_28_to_31 to be 0xb.
1384Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=1].mask_bytes_0_to_13 to be 0x3fff.
1385Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=1].mask_nibbles_28_to_31 to be 0xf.
1386Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=2].mask_bytes_0_to_13 to be 0x3fff.
1387Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=2].mask_nibbles_28_to_31 to be 0xf.
1388Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=3].mask_bytes_0_to_13 to be 0x3fff.
1389Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=3].mask_nibbles_28_to_31 to be 0xf.
1390Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=4].mask_bytes_0_to_13 to be 0x3fff.
1391Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=4].mask_nibbles_28_to_31 to be 0xf.
1392Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1393Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1394Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1395Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1396Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1397Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1398Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1399Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1400Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1401Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1402Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1403Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1404Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1405Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1406Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1407Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1408Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1409Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1410Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1411Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1412Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1413Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1414Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1415Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1416Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1417Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1418Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
1419Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
1420Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_thread to be 0.
1421Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=3].exactmatch_bank_enable_bank_mask to be 0x0.
1422Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=3].exactmatch_bank_enable_bank_id to be 0x0.
1423Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=3].exactmatch_bank_enable_inp_sel to be 1.
1424Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
1425Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
1426Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=3].enabled_4bit_muxctl_select to be 1.
1427Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=3].enabled_4bit_muxctl_enable to be 1.
1428Configuring rams.match.merge.mau_action_instruction_adr_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_action_instruction_adr_exact_shiftcount to be 0.
1429Configuring rams.match.merge.mau_immediate_data_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_immediate_data_exact_shiftcount to be 0.
1430Configuring rams.match.merge.mau_stats_adr_exact_shiftcount[result_bus_number = 14][entry_in_ram_word=0].mau_stats_adr_exact_shiftcount to be 0x46.
1431Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_type to be 1.
1432Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_logical_table to be 0.
1433Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_ingress to be 1.
1434Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_enable to be 1.
1435Configuring rams.array.row[row=7].emm_ecc_error_uram_ctl[direction=0].emm_ecc_error_uram_ctl to be select of 0x3. (previous value = 0x1 OR new value = 0x2)
1436In Ram Word 0:
1437 wide entry 0 occupied ram word entry 0
1438Configuring rams.match.merge.col[col_number=3].row_action_nxtable_bus_drive[row_number=7].row_action_nxtable_bus_drive to be 1.
1439Configuring rams.match.merge.col[col_number=3].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_select to be 14 (hit signal to output on).
1440Configuring rams.match.merge.col[col_number=3].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1.
1441--> Hash Match Way 2
1442Packed entry for hash way 2 is
1443 [0] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 0))
1444 [1] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 1))
1445 [2] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 2))
1446 [3] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 3))
1447 [4] = (field_bit=4, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 4))
1448 [5] = (field_bit=5, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 5))
1449 [6] = (field_bit=6, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 6))
1450 [7] = (field_bit=7, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 7))
1451 [8] = (field_bit=8, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 8))
1452 [9] = (field_bit=9, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 9))
1453 [10] = (field_bit=10, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 10))
1454 [11] = (field_bit=11, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 11))
1455 [12] = (field_bit=12, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 12))
1456 [13] = (field_bit=13, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 13))
1457 [14] = (field_bit=14, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 14))
1458 [15] = (field_bit=15, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 15))
Carmelo Cascone8aa05482017-09-12 13:21:59 +0200[diff] [blame]1459 [16] = (field_bit=0, hash_match_group_bit=16, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 0))
1460 [17] = (field_bit=1, hash_match_group_bit=17, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 1))
1461 [18] = (field_bit=2, hash_match_group_bit=18, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 2))
1462 [19] = (field_bit=3, hash_match_group_bit=19, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 3))
1463 [20] = (field_bit=4, hash_match_group_bit=20, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 4))
1464 [21] = (field_bit=5, hash_match_group_bit=21, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 5))
1465 [22] = (field_bit=6, hash_match_group_bit=22, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 6))
1466 [23] = (field_bit=7, hash_match_group_bit=23, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 7))
1467 [24] = (field_bit=8, hash_match_group_bit=24, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 8))
1468 [25] = (field_bit=9, hash_match_group_bit=25, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 9))
1469 [26] = (field_bit=10, hash_match_group_bit=26, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 10))
1470 [27] = (field_bit=11, hash_match_group_bit=27, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 11))
1471 [28] = (field_bit=12, hash_match_group_bit=28, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 12))
1472 [29] = (field_bit=13, hash_match_group_bit=29, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 13))
1473 [30] = (field_bit=14, hash_match_group_bit=30, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 14))
1474 [31] = (field_bit=15, hash_match_group_bit=31, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 15))
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1475 [32] = None
1476 [33] = None
1477 [34] = (field_bit=10, hash_match_group_bit=10, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 10))
1478 [35] = (field_bit=11, hash_match_group_bit=11, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 11))
1479 [36] = (field_bit=12, hash_match_group_bit=12, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 12))
1480 [37] = (field_bit=13, hash_match_group_bit=13, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 13))
1481 [38] = (field_bit=14, hash_match_group_bit=14, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 14))
1482 [39] = (field_bit=15, hash_match_group_bit=15, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 15))
1483 [40] = None
1484 [41] = None
1485 [42] = None
1486 [43] = None
1487 [44] = None
1488 [45] = None
1489 [46] = None
1490 [47] = None
1491 [48] = None
1492 [49] = None
1493 [50] = None
1494 [51] = None
1495 [52] = None
1496 [53] = None
1497 [54] = None
1498 [55] = None
1499 [56] = None
1500 [57] = None
1501 [58] = None
1502 [59] = None
1503 [60] = None
1504 [61] = None
1505 [62] = None
1506 [63] = None
1507 [64] = None
1508 [65] = None
1509 [66] = None
1510 [67] = None
1511 [68] = None
1512 [69] = None
1513 [70] = None
1514 [71] = None
1515 [72] = None
1516 [73] = None
1517 [74] = None
1518 [75] = None
1519 [76] = None
1520 [77] = None
1521 [78] = None
1522 [79] = None
1523 [80] = None
1524 [81] = None
1525 [82] = None
1526 [83] = None
1527 [84] = None
1528 [85] = None
1529 [86] = None
1530 [87] = None
1531 [88] = None
1532 [89] = None
1533 [90] = None
1534 [91] = None
1535 [92] = None
1536 [93] = None
1537 [94] = None
1538 [95] = None
1539 [96] = None
1540 [97] = None
1541 [98] = None
1542 [99] = None
1543 [100] = None
1544 [101] = None
1545 [102] = None
1546 [103] = None
1547 [104] = None
1548 [105] = None
1549 [106] = None
1550 [107] = None
1551 [108] = None
1552 [109] = None
1553 [110] = None
1554 [111] = None
1555 [112] = None
1556 [113] = None
1557 [114] = None
1558 [115] = None
1559 [116] = None
1560 [117] = None
1561 [118] = None
1562 [119] = None
1563 [120] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 0))
1564 [121] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 1))
1565 [122] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 2))
1566 [123] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 3))
1567 [124] = None
1568 [125] = None
1569 [126] = None
1570 [127] = None
1571
1572Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=0].match_mask to be 0xffff.
1573Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=1].match_mask to be 0xffffff03.
1574Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=2].match_mask to be 0xffffffff.
1575Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=3].match_mask to be 0xf0ffffff.
1576Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_ram_write_data_mux_select to be 7.
1577Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_ram_read_data_mux_select to be 7.
1578Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_result_bus_select to be 1.
1579Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_entry_enable to be 1.
1580Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_ram_logical_table to be 0x0.
1581For entry_in_ram_word 0, should have vpn 2, with lower_two_bits of 2 and upper_vpn of 0
1582for entry_in_ram_word 0, use lsbs of 2
1583Configuring rams.array.row[row=7].ram[column=4].match_ram_vpn.match_ram_vpn0 to be 0.
1584Configuring rams.array.row[row=7].ram[column=4].match_ram_vpn.match_ram_vpn_lsbs to be 0x2.
1585version valid nibbles are : [30]
1586Configuring rams.array.row[row=7].ram[column=4].match_nibble_s0q1_enable.match_nibble_s0q1_enable to be 0xbfffffff.
1587Configuring rams.array.row[row=7].ram[column=4].match_nibble_s1q0_enable.match_nibble_s1q0_enable to be 0xffffffff.
1588Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=0].mask_bytes_0_to_13 to be 0x3fe3.
1589Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=0].mask_nibbles_28_to_31 to be 0xb.
1590Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=1].mask_bytes_0_to_13 to be 0x3fff.
1591Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=1].mask_nibbles_28_to_31 to be 0xf.
1592Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=2].mask_bytes_0_to_13 to be 0x3fff.
1593Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=2].mask_nibbles_28_to_31 to be 0xf.
1594Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=3].mask_bytes_0_to_13 to be 0x3fff.
1595Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=3].mask_nibbles_28_to_31 to be 0xf.
1596Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=4].mask_bytes_0_to_13 to be 0x3fff.
1597Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=4].mask_nibbles_28_to_31 to be 0xf.
1598Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1599Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1600Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1601Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1602Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1603Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1604Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1605Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1606Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1607Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1608Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1609Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1610Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1611Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1612Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1613Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1614Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1615Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1616Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1617Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1618Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1619Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1620Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1621Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1622Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1623Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1624Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
1625Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
1626Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_thread to be 0.
1627Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=4].exactmatch_bank_enable_bank_mask to be 0x0.
1628Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=4].exactmatch_bank_enable_bank_id to be 0x0.
1629Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=4].exactmatch_bank_enable_inp_sel to be 1.
1630Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
1631Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
1632Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=4].enabled_4bit_muxctl_select to be 2.
1633Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=4].enabled_4bit_muxctl_enable to be 1.
1634Configuring rams.match.merge.mau_action_instruction_adr_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_action_instruction_adr_exact_shiftcount to be 0.
1635Configuring rams.match.merge.mau_immediate_data_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_immediate_data_exact_shiftcount to be 0.
1636Configuring rams.match.merge.mau_stats_adr_exact_shiftcount[result_bus_number = 14][entry_in_ram_word=0].mau_stats_adr_exact_shiftcount to be 0x46.
1637Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_type to be 1.
1638Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_logical_table to be 0.
1639Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_ingress to be 1.
1640Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_enable to be 1.
1641Configuring rams.array.row[row=7].emm_ecc_error_uram_ctl[direction=0].emm_ecc_error_uram_ctl to be select of 0x7. (previous value = 0x3 OR new value = 0x4)
1642In Ram Word 0:
1643 wide entry 0 occupied ram word entry 0
1644Configuring rams.match.merge.col[col_number=4].row_action_nxtable_bus_drive[row_number=7].row_action_nxtable_bus_drive to be 1.
1645Configuring rams.match.merge.col[col_number=4].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_select to be 14 (hit signal to output on).
1646Configuring rams.match.merge.col[col_number=4].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1.
1647
1648+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1649| Working on table ecmp_group_table_counter in stage 1 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1650+------------------------------------------------------------------------
1651Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
1652Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
1653Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
1654Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
1655Note that unitram_vpn does not need to be programmed for synthetic two port rams.
1656Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0.
1657Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
1658Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
1659Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
1660Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
1661Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
1662Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
1663Note that unitram_vpn does not need to be programmed for synthetic two port rams.
1664Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0.
1665Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
1666Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
1667Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
1668Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
1669Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
1670Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
1671Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
1672Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
1673Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
1674Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
1675Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
1676Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
1677Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
1678Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
1679Stat table ecmp_group_table_counter is used by match table ecmp_group_table.
1680Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8)
1681Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
1682Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
1683Note that map ram vpn does not need to be configured for synthetic two port map rams.
1684Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
1685Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
1686Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
1687Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
1688Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
1689Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
1690Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
1691Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
1692Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0.
1693Note that map ram vpn does not need to be configured for synthetic two port map rams.
1694Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
1695Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
1696Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
1697Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
1698Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
1699Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
1700Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
1701For counter width 32 and N = 4096
1702 number iterations = 32
1703 b_cur = 379488672.0
1704 eqn(b_cur) = 4294964039.26
1705 max_counter_value = 4294967295
1706Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
1707Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
1708Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
1709Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
1710Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
1711Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
1712Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4.
1713Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1.
1714Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1.
1715TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0.
1716Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x0.
1717Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4.
1718Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1.
1719Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0.
1720Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0.
1721Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0.
1722Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0.
1723Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0.
1724Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
1725Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
1726Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1.
1727Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3.
1728Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_direct be 1.
1729Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=0].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1)
1730Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x0.
1731Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x7. ( previous value = 0x0 OR new value = 0x7)
1732Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x1.
1733+------------------------------------------------------------------------
1734Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19.
1735Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
1736Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
1737Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1738Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1739Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1740Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1741Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1742Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1743Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1744Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1745Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x1.
1746Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1747Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1748Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1749Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x40.
1750Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1751Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1752Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1753Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
1754Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1755Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1756Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
1757Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1758Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1759Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1760Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1761Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1762--------------------------------------------
1763Configuration for unused statistics ALUs.
1764Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1765Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1766Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1767+------------------------------------------------------------------------
1768Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
1769Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
1770Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]1771Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
1772Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
1773Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1774Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
1775Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
1776Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]1777Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
1778Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
1779Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1780Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1781Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1782Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1783Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1784Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1785Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1786Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1787Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1788Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1789Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1790Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1791Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1792Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1793Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1794Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1795Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1796Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1797Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1798+------------------------------------------------------------------------
1799Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1800Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1801Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
1802Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
1803Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1804Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1805Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1806Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
1807Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1.
1808Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2.
1809Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1810Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1811Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1812Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1813
1814+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1815| MAU Stage 2
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1816+------------------------------------------------------------------------
1817
1818+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1819| Working on table _condition_2 in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1820+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1821--> Stage Gateway Table for condition _condition_2 in stage 2
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1822Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
1823Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
1824Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
1825Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
1826Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
1827Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
1828Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
1829Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]1830Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 18.
1831Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_enable to be 1.
1832Configuring match input crossbar byte 2 to come from 16-bit PHV container 2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1833 That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]1834Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 18.
1835Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_enable to be 1.
1836Configuring match input crossbar byte 3 to come from 16-bit PHV container 2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1837 That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
1838Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
1839Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
1840Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]1841Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=40].byte1 to be 0x1.
1842Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=41].byte0 to be 0x1.
1843Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=42].byte0 to be 0x2.
1844Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=43].byte0 to be 0x4.
1845Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=44].byte0 to be 0x8.
1846Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=45].byte0 to be 0x10.
1847Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=46].byte0 to be 0x20.
1848Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=47].byte0 to be 0x40.
1849Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=48].byte0 to be 0x80.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1850Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
1851Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
1852Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
1853Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
1854Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
1855Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
1856Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
1857Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
1858Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
1859Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0
1860Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0
1861Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
1862Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
1863Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
1864Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
1865Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
1866Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_mode to be 0x2
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]1867Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffff00
1868Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff00
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1869Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1870Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x21
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1871Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid0 to be 0x3
1872Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid1 to be 0x3
1873Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][0] to be 0xffffffff
1874Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][1] to be 0xffffffff
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]1875Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xff00ff
1876Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff00ff
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1877Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xc (previous value 0x8 OR new value 0x4)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1878Configuring rams.match.merge.gateway_next_table_lut[0][2] to be 0x21
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1879Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid0 to be 0x3
1880Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid1 to be 0x3
1881Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][0] to be 0xffffffff
1882Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][1] to be 0xffffffff
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]1883Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0x3ffff
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1884Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][1] to be 0xffff
1885Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xe (previous value 0xc OR new value 0x2)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1886Configuring rams.match.merge.gateway_next_table_lut[0][1] to be 0x21
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1887Configuring rams.match.merge.gateway_en.gateway_en to be 0x1
1888Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf
1889Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1
1890allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
1891Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x0
1892Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1
1893Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2
1894Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x1
1895Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0
1896Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x1
1897Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0
1898Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff
1899Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff
1900
1901+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1902| Working on table ingress_port_count_table__action__ in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1903+------------------------------------------------------------------------
1904--> Action Data Table ingress_port_count_table__action__ with logical_table_id 0 that is reference type is 'direct'
1905
1906+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1907| Working on table ingress_port_count_table in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1908+------------------------------------------------------------------------
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]1909--> Hash Action Table ingress_port_count_table with logical_table_id 0
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1910allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
1911Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
1912Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
1913Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
1914Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
1915Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
1916Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
1917Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id).
1918Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
1919Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id).
1920Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
1921Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x0.
1922Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x1.
1923Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0xff.
1924Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=1].mau_stats_adr_default to be 0x0.
1925Configuring rams.match.merge.mau_stats_adr_per_entry_en_mux_ctl[table_type_index=0][result_bus_number=1].mau_stats_adr_per_entry_en_mux_ctl to be 0x7.
1926Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
1927Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2000.
1928Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]1929
1930---- Hash Distribution Units for table ingress_port_count_table ----
1931Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x1)
1932Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
1933Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 16.
1934Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
1935Configuring match input crossbar byte 0 to come from 16-bit PHV container 0.
1936 That PHV byte contains {ig_intr_md.ingress_port[7:0]}.
1937Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 16.
1938Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
1939Configuring match input crossbar byte 1 to come from 16-bit PHV container 0.
1940 That PHV byte contains {unused[6:0], ig_intr_md.ingress_port[8:8]}.
1941Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x5. (previous value = 0x4 OR new value = 0x1)
1942Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x1)
1943Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
1944Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x1.
1945Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte0 to be 0x2.
1946Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte0 to be 0x4.
1947Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte0 to be 0x8.
1948Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte0 to be 0x10.
1949Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte0 to be 0x20.
1950Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte0 to be 0x40.
1951Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte0 to be 0x80.
1952Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=8].byte1 to be 0x1.
1953Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
1954Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 1. (old value = 0 OR new value = 1).
1955Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 8. (old value = 0 OR new value = 8).
1956Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 1. (old value = 0 OR new value = 1).
1957Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x1. (old value = 0x0 OR new value = 0x1).
1958Configuring rams.match.merge.mau_hash_group_mask[which_16=0].mau_hash_group_mask to be 0x3ff. (previous value = 0x0 OR new value = 0x3ff)
1959Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=3][control_group_index=0].mau_hash_group_xbar_ctl to be 0x8 (old value = 0x0 OR new value = 0x8).
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1960Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].stats_adr_payload_shifter_en to be 1.
1961Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
1962
1963+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1964| Working on table egress_port_count_table__action__ in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1965+------------------------------------------------------------------------
1966--> Action Data Table egress_port_count_table__action__ with logical_table_id 1 that is reference type is 'direct'
1967
1968+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1969| Working on table egress_port_count_table in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1970+------------------------------------------------------------------------
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]1971--> Hash Action Table egress_port_count_table with logical_table_id 1
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1972allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
1973Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
1974Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
1975Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
1976Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
1977Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
1978Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
1979Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id).
1980Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
1981Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id).
1982Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
1983Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_default to be 0x40.
1984Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x0.
1985Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0xff.
1986Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0xff.
1987Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=0].mau_stats_adr_default to be 0x80000.
1988Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2).
1989Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x40.
1990Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]1991
1992---- Hash Distribution Units for table egress_port_count_table ----
1993Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x1 OR new value = 0x2)
1994Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
1995Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_address to be 18.
1996Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_enable to be 1.
1997Configuring match input crossbar byte 8 to come from 16-bit PHV container 2.
1998 That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
1999Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_address to be 18.
2000Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_enable to be 1.
2001Configuring match input crossbar byte 9 to come from 16-bit PHV container 2.
2002 That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
2003Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x5. (previous value = 0x5 OR new value = 0x4)
2004Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=1][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2)
2005Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=1][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
2006Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0x1.
2007Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=1].byte0 to be 0x2.
2008Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=2].byte0 to be 0x4.
2009Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=3].byte0 to be 0x8.
2010Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=4].byte0 to be 0x10.
2011Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=5].byte0 to be 0x20.
2012Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=6].byte0 to be 0x40.
2013Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=7].byte0 to be 0x80.
2014Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=8].byte1 to be 0x1.
2015Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x3. (previous value = 0x1 OR new value = 0x2)
2016Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 9. (old value = 1 OR new value = 8).
2017Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 152. (old value = 8 OR new value = 144).
2018Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 65. (old value = 1 OR new value = 64).
2019Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x201. (old value = 0x1 OR new value = 0x200).
2020Configuring rams.match.merge.mau_hash_group_mask[which_16=3].mau_hash_group_mask to be 0x3ff. (previous value = 0x0 OR new value = 0x3ff)
2021Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=3][control_group_index=0].mau_hash_group_xbar_ctl to be 0xb8 (old value = 0x8 OR new value = 0xb0).
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2022--> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 2
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2023Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
2024Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
2025Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
2026Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
2027Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
2028Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2029Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x3 OR new value = 0x0)
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2030Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
2031Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x0)
2032Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2033Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x3. (previous value = 0x3 OR new value = 0x1)
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2034Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
2035Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
2036Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
2037Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
2038Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1
2039Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0
2040Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
2041Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
2042Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
2043Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff
2044Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff
2045Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff
2046Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff
2047Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8
2048Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0xff
2049Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10)
2050Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0xff
2051Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2)
2052Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe
2053Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1
2054allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
2055Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_logical_select to be 0x1
2056Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_inhibit_enable to be 0x1
2057Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x3 (previous value 0x2 OR new value 0x1)
2058Configuring rams.match.merge.gateway_payload_data[0][0][0][0].gateway_payload_data to be 0x0
2059Configuring rams.match.merge.gateway_payload_data[0][0][1][0].gateway_payload_data to be 0x0
2060Configuring rams.match.merge.gateway_payload_data[0][0][0][1].gateway_payload_data to be 0x0
2061Configuring rams.match.merge.gateway_payload_data[0][0][1][1].gateway_payload_data to be 0x0
2062Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff
2063Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff
2064Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=0].action_instruction_adr_payload_shifter_en to be 1.
2065
2066+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2067| Working on table ingress_port_counter in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2068+------------------------------------------------------------------------
2069Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
2070Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
2071Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
2072Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
2073Note that unitram_vpn does not need to be programmed for synthetic two port rams.
2074Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0.
2075Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
2076Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
2077Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
2078Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
2079Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
2080Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
2081Note that unitram_vpn does not need to be programmed for synthetic two port rams.
2082Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0.
2083Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
2084Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
2085Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
2086Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
2087Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
2088Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
2089Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
2090Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1.
2091Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
2092Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
2093Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
2094Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
2095Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
2096Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1.
2097Stat table ingress_port_counter is used by match table ingress_port_count_table.
2098Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x4. (previous value = 0x0 OR new value =0x4)
2099Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
2100Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
2101Note that map ram vpn does not need to be configured for synthetic two port map rams.
2102Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
2103Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
2104Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
2105Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
2106Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
2107Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
2108Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
2109Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
2110Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0.
2111Note that map ram vpn does not need to be configured for synthetic two port map rams.
2112Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
2113Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
2114Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
2115Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
2116Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
2117Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
2118Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
2119For counter width 32 and N = 4096
2120 number iterations = 32
2121 b_cur = 379488672.0
2122 eqn(b_cur) = 4294964039.26
2123 max_counter_value = 4294967295
2124Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
2125Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
2126Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
2127Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
2128Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
2129Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
2130Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_entries_per_word to be 4.
2131Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_process_packets to be 1.
2132Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.lrt_enable to be 1.
2133TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_alu_error_enable to be 0.
2134Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0x0.
2135Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4.
2136Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1.
2137Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0.
2138Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0.
2139Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=2].stats_lrt_fsm_sweep_size to be 0x0.
2140Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=2].stats_lrt_fsm_sweep_offset to be 0x0.
2141Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=2].stats_lrt_sweep_adr to be 0x0.
2142Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
2143Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
2144Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=2].packet_action_at_headertime be 1.
2145Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_size be 3.
2146Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_lt be 0x0.
2147Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x6. ( previous value = 0x0 OR new value = 0x6)
2148Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=2].mau_ad_stats_virt_lt be 0x1.
2149
2150+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2151| Working on table egress_port_counter in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2152+------------------------------------------------------------------------
2153Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
2154Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
2155Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
2156Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
2157Note that unitram_vpn does not need to be programmed for synthetic two port rams.
2158Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 1.
2159Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
2160Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
2161Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
2162Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
2163Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
2164Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
2165Note that unitram_vpn does not need to be programmed for synthetic two port rams.
2166Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 1.
2167Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
2168Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
2169Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
2170Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
2171Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
2172Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
2173Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
2174Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
2175Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
2176Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
2177Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
2178Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
2179Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
2180Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
2181Stat table egress_port_counter is used by match table egress_port_count_table.
2182Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=1].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8)
2183Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
2184Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 1.
2185Note that map ram vpn does not need to be configured for synthetic two port map rams.
2186Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
2187Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
2188Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
2189Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
2190Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
2191Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
2192Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
2193Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
2194Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 1.
2195Note that map ram vpn does not need to be configured for synthetic two port map rams.
2196Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
2197Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
2198Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
2199Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
2200Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
2201Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
2202Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
2203For counter width 32 and N = 4096
2204 number iterations = 32
2205 b_cur = 379488672.0
2206 eqn(b_cur) = 4294964039.26
2207 max_counter_value = 4294967295
2208Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
2209Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
2210Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
2211Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
2212Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
2213Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
2214Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4.
2215Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1.
2216Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1.
2217TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0.
2218Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x1.
2219Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_entries_per_word be 0x4.
2220Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_has_packets be 0x1.
2221Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_offset be 0x0.
2222Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_size be 0x0.
2223Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0.
2224Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0.
2225Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0.
2226Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
2227Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
2228Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1.
2229Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3.
2230Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x1.
2231Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=3].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x3e. ( previous value = 0x6 OR new value = 0x38)
2232Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x2.
2233+------------------------------------------------------------------------
2234Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19.
2235Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
2236Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
2237Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2238Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2239Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2240Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2241Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2242Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2243Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2244Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2245Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x3.
2246Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2247Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2248Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x3.
2249Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2250Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2251Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2252Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2253Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2254Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2255Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2256Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2257Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2258Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2259Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2260Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2261Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2262--------------------------------------------
2263Configuration for unused statistics ALUs.
2264Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2265Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2266+------------------------------------------------------------------------
2267Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2268Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2269Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2270Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2271Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2272Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2273Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2274Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2275Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2276Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
2277Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
2278Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2279Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2280Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2281Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2282Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2283Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2284Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2285Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2286Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2287Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2288Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2289Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2290Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2291Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2292Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2293Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2294Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2295Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2296Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2297+------------------------------------------------------------------------
2298Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2299Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2300Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
2301Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2302Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2303Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2304Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2305Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2306Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1.
2307Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2.
2308Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2309Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2310Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2311Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2312
2313+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2314| MAU Stage 3
2315+------------------------------------------------------------------------
2316+------------------------------------------------------------------------
2317Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2318Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2319Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2320Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2321Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2322Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2323Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2324Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2325Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2326Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2327Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2328Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2329Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2330Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2331Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2332Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2333Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2334Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2335Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2336Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2337Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2338Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2339Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2340Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2341Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2342Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2343Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2344Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2345--------------------------------------------
2346Configuration for unused statistics ALUs.
2347Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2348Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2349Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2350Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2351+------------------------------------------------------------------------
2352Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2353Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2354Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2355Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2356Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2357Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2358Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2359Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2360Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2361Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
2362Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
2363Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2364Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2365Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2366Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2367Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2368Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2369Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
2370Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2371Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2372Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2373Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2374Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2375Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2376Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2377Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2378Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2379Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2380Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2381Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2382+------------------------------------------------------------------------
2383Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2384Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2385Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2386Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2387Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2388Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2389Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2390Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2391Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2392Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2393Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2394Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2395Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2396Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2397
2398+------------------------------------------------------------------------
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2399| MAU Stage 4
2400+------------------------------------------------------------------------
2401+------------------------------------------------------------------------
2402Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2403Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2404Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2405Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2406Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2407Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2408Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2409Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2410Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2411Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2412Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2413Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2414Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2415Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2416Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2417Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2418Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2419Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2420Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2421Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2422Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2423Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2424Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2425Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2426Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2427Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2428Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2429Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2430--------------------------------------------
2431Configuration for unused statistics ALUs.
2432Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2433Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2434Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2435Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2436+------------------------------------------------------------------------
2437Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2438Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2439Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2440Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2441Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2442Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2443Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2444Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2445Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2446Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
2447Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
2448Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2449Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2450Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2451Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2452Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2453Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2454Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2455Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2456Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2457Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2458Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2459Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2460Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2461Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2462Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2463Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2464Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2465Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2466Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2467+------------------------------------------------------------------------
2468Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2469Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2470Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2471Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2472Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2473Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2474Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2475Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2476Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2477Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2478Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2479Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2480Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2481Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2482
2483+------------------------------------------------------------------------
2484| MAU Stage 5
2485+------------------------------------------------------------------------
2486+------------------------------------------------------------------------
2487Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2488Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2489Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2490Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2491Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2492Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2493Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2494Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2495Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2496Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2497Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2498Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2499Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2500Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2501Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2502Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2503Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2504Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2505Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2506Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
2507Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2508Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2509Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19.
2510Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2511Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2512Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2513Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2514Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2515--------------------------------------------
2516Configuration for unused statistics ALUs.
2517Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2518Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2519Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2520Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2521+------------------------------------------------------------------------
2522Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2523Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2524Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2525Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2526Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2527Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2528Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2529Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2530Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2531Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
2532Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
2533Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2534Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2535Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2536Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2537Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2538Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2539Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2540Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2541Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2542Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2543Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2544Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2545Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2546Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2547Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2548Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2549Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2550Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2551Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2552+------------------------------------------------------------------------
2553Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2554Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2555Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2556Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
2557Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2558Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2559Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2560Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0.
2561Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2562Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2563Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2564Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2565Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2566Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2567
2568+------------------------------------------------------------------------
2569| MAU Stage 6
2570+------------------------------------------------------------------------
2571+------------------------------------------------------------------------
2572Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19.
2573Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
2574Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
2575Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 19.
2576Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 9.
2577Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 3.
2578Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2579Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2580Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2581Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2582Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2583Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2584Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2585Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2586Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2587Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2588Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2589Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2590Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2591Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2592Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2593Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2594Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2595Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2596Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2597Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2598Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2599Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2600--------------------------------------------
2601Configuration for unused statistics ALUs.
2602Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2603Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2604Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2605Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2606+------------------------------------------------------------------------
2607Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2608Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2609Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2610Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2611Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2612Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2613Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2614Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2615Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2616Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
2617Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
2618Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2619Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2620Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2621Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2622Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2623Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2624Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2625Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2626Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2627Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2628Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2629Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2630Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2631Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2632Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2633Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2634Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2635Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2636Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2637+------------------------------------------------------------------------
2638Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2639Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2640Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
2641Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2642Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2643Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2644Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0.
2645Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2646Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 3.
2647Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0.
2648Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2649Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2650Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2651Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2652
2653+------------------------------------------------------------------------
2654| MAU Stage 7
2655+------------------------------------------------------------------------
2656+------------------------------------------------------------------------
2657Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2658Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2659Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2660Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2661Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2662Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2663Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2664Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2665Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2666Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2667Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2668Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2669Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2670Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2671Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2672Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2673Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2674Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2675Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2676Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2677Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2678Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2679Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2680Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2681Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2682Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2683Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2684Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2685--------------------------------------------
2686Configuration for unused statistics ALUs.
2687Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2688Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2689Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2690Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2691+------------------------------------------------------------------------
2692Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2693Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2694Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2695Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2696Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2697Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2698Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2699Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2700Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2701Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
2702Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
2703Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2704Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2705Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2706Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2707Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2708Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2709Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2710Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2711Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2712Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2713Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2714Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2715Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2716Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2717Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2718Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2719Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2720Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2721Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2722+------------------------------------------------------------------------
2723Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2724Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2725Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2726Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2727Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2728Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2729Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2730Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2731Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2732Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2733Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2734Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2735Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2736Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2737
2738+------------------------------------------------------------------------
2739| MAU Stage 8
2740+------------------------------------------------------------------------
2741+------------------------------------------------------------------------
2742Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2743Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2744Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2745Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2746Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2747Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2748Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2749Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2750Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2751Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2752Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2753Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2754Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2755Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2756Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2757Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2758Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2759Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2760Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2761Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2762Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2763Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2764Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2765Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2766Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2767Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2768Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2769Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2770--------------------------------------------
2771Configuration for unused statistics ALUs.
2772Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2773Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2774Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2775Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2776+------------------------------------------------------------------------
2777Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2778Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2779Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2780Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2781Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2782Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2783Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2784Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2785Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2786Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
2787Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
2788Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2789Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2790Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2791Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2792Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2793Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2794Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2795Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2796Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2797Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2798Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2799Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2800Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2801Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2802Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2803Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2804Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2805Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2806Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2807+------------------------------------------------------------------------
2808Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2809Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2810Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2811Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2812Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2813Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2814Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2815Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2816Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2817Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2818Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2819Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2820Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2821Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2822
2823+------------------------------------------------------------------------
2824| MAU Stage 9
2825+------------------------------------------------------------------------
2826+------------------------------------------------------------------------
2827Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2828Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2829Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2830Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2831Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2832Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2833Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2834Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2835Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2836Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2837Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2838Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2839Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2840Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2841Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2842Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2843Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2844Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2845Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2846Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2847Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2848Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2849Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2850Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2851Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2852Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2853Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2854Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2855--------------------------------------------
2856Configuration for unused statistics ALUs.
2857Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2858Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2859Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2860Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2861+------------------------------------------------------------------------
2862Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2863Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2864Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2865Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2866Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2867Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2868Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2869Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2870Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2871Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
2872Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
2873Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2874Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2875Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2876Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2877Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2878Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2879Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2880Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2881Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2882Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2883Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2884Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2885Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2886Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2887Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2888Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2889Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2890Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2891Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2892+------------------------------------------------------------------------
2893Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2894Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2895Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2896Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2897Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2898Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2899Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2900Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2901Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2902Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2903Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2904Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2905Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2906Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2907
2908+------------------------------------------------------------------------
2909| MAU Stage 10
2910+------------------------------------------------------------------------
2911+------------------------------------------------------------------------
2912Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2913Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2914Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2915Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2916Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2917Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2918Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2919Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2920Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2921Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2922Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2923Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2924Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2925Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2926Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2927Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2928Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2929Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2930Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2931Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2932Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2933Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2934Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2935Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2936Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2937Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2938Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2939Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2940--------------------------------------------
2941Configuration for unused statistics ALUs.
2942Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2943Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2944Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2945Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2946+------------------------------------------------------------------------
2947Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2948Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2949Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2950Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2951Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2952Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2953Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2954Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2955Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]2956Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
2957Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
2958Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2959Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2960Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2961Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2962Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2963Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2964Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2965Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2966Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2967Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2968Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2969Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2970Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2971Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2972Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2973Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2974Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2975Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2976Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2977+------------------------------------------------------------------------
2978Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2979Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2980Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2981Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2982Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2983Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2984Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2985Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2986Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2987Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2988Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2989Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2990Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2991Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2992
2993+------------------------------------------------------------------------
2994| MAU Stage 11
2995+------------------------------------------------------------------------
2996+------------------------------------------------------------------------
2997Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2998Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2999Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
3000Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
3001Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
3002Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
3003Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
3004Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
3005Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
3006Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
3007Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
3008Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
3009Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
3010Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
3011Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
3012Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
3013Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
3014Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
3015Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
3016Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
3017Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
3018Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
3019Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19.
3020Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
3021Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
3022Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
3023Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
3024Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
3025--------------------------------------------
3026Configuration for unused statistics ALUs.
3027Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
3028Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
3029Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
3030Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
3031+------------------------------------------------------------------------
3032Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
3033Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
3034Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]3035Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
3036Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
3037Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3038Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
3039Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
3040Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]3041Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
3042Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
3043Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]3044Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
3045Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
3046Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
3047Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
3048Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
3049Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3050Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
3051Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
3052Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
3053Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
3054Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
3055Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
3056Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
3057Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
3058Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
3059Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
3060Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
3061Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
3062+------------------------------------------------------------------------
3063Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
3064Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
3065Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
3066Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
3067Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
3068Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
3069Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
3070Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0.
3071Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
3072Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
3073Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
3074Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
3075Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
3076Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
3077
3078+------------------------------------------------------------------------
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame^]3079| Number of configuration field values set in Match-Action Stages: 2186
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3080+------------------------------------------------------------------------
3081
3082+------------------------------------------------------------------------
3083| MAU Feature Characteristics:
3084+------------------------------------------------------------------------
3085
3086
3087Features per Stage for ingress:
3088-----------------------------------------------------------------------------------------------
3089| Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency |
3090| | | | | LPF | (max words) | | to Previous |
3091-----------------------------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]3092| 0 | Yes | Yes | Yes | No | No (0) | No | match |
3093| 1 | Yes | No | Yes | No | No (0) | No | match |
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3094| 2 | Yes | No | Yes | No | No (0) | No | match |
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]3095| 3 | Yes* | No | Yes* | No | No (0) | No | concurrent |
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3096| 4 | Yes* | No | Yes* | No | No (0) | No | concurrent |
3097| 5 | Yes* | No | Yes* | No | No (0) | No | concurrent |
3098| 6 | No | No | No | No | No (0) | No | match |
3099| 7 | No | No | No | No | No (0) | No | concurrent |
3100| 8 | No | No | No | No | No (0) | No | concurrent |
3101| 9 | No | No | No | No | No (0) | No | concurrent |
3102| 10 | No | No | No | No | No (0) | No | concurrent |
3103| 11 | No | No | No | No | No (0) | No | concurrent |
3104-----------------------------------------------------------------------------------------------
3105
3106A '*' denotes that this feature was added to balance an action/concurrent chain.
3107
3108
3109Features per Stage for egress:
3110-----------------------------------------------------------------------------------------------
3111| Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency |
3112| | | | | LPF | (max words) | | to Previous |
3113-----------------------------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]3114| 0 | No | No | No | No | No (0) | No | match |
3115| 1 | No | No | No | No | No (0) | No | concurrent |
3116| 2 | No | No | No | No | No (0) | No | concurrent |
3117| 3 | No | No | No | No | No (0) | No | concurrent |
3118| 4 | No | No | No | No | No (0) | No | concurrent |
3119| 5 | No | No | No | No | No (0) | No | concurrent |
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3120| 6 | No | No | No | No | No (0) | No | match |
3121| 7 | No | No | No | No | No (0) | No | concurrent |
3122| 8 | No | No | No | No | No (0) | No | concurrent |
3123| 9 | No | No | No | No | No (0) | No | concurrent |
3124| 10 | No | No | No | No | No (0) | No | concurrent |
3125| 11 | No | No | No | No | No (0) | No | concurrent |
3126-----------------------------------------------------------------------------------------------
3127
3128A '*' denotes that this feature was added to balance an action/concurrent chain.
3129
3130+------------------------------------------------------------------------
3131| MAU Latency Characteristics:
3132+------------------------------------------------------------------------
3133
3134
3135Clock Cycles Per Stage For ingress:
3136-----------------------------------------------------------------------------------------------------
3137| Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency |
3138-----------------------------------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]3139| 0 | 22 | 13 | match | 22 |
3140| 1 | 20 | 11 | match | 20 |
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3141| 2 | 20 | 11 | match | 20 |
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]3142| 3 | 20 | 11 | concurrent | 1 |
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3143| 4 | 20 | 11 | concurrent | 1 |
3144| 5 | 20 | 11 | concurrent | 1 |
3145| 6 | 20 | 11 | match | 20 |
3146| 7 | 20 | 11 | concurrent | 1 |
3147| 8 | 20 | 11 | concurrent | 1 |
3148| 9 | 20 | 11 | concurrent | 1 |
3149| 10 | 20 | 11 | concurrent | 1 |
3150| 11 | 20 | 11 | concurrent | 1 |
3151-----------------------------------------------------------------------------------------------------
3152
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]3153Total latency for ingress: 94
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3154
3155
3156Clock Cycles Per Stage For egress:
3157-----------------------------------------------------------------------------------------------------
3158| Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency |
3159-----------------------------------------------------------------------------------------------------
3160| 0 | 20 | 11 | match | 20 |
3161| 1 | 20 | 11 | concurrent | 1 |
3162| 2 | 20 | 11 | concurrent | 1 |
3163| 3 | 20 | 11 | concurrent | 1 |
3164| 4 | 20 | 11 | concurrent | 1 |
3165| 5 | 20 | 11 | concurrent | 1 |
3166| 6 | 20 | 11 | match | 20 |
3167| 7 | 20 | 11 | concurrent | 1 |
3168| 8 | 20 | 11 | concurrent | 1 |
3169| 9 | 20 | 11 | concurrent | 1 |
3170| 10 | 20 | 11 | concurrent | 1 |
3171| 11 | 20 | 11 | concurrent | 1 |
3172-----------------------------------------------------------------------------------------------------
3173
3174Total latency for egress: 54