Workaround to counter-issue as suggested by Antonin
Manually modified via makefile context.json
Change-Id: Ibed9e0691bf1d552db28470da57955e8f3ca802a
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.config.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.config.log
index b0c43cd..0e6c149 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.config.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.config.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.config.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
Final Stage dependencies are:
@@ -50,11 +50,11 @@
Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x2. (old value = 0x0 OR new value = 0x2)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_address to be 4.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 12 to come from 8-bit PHV container 3.
+Configuring match input crossbar byte 12 to come from 8-bit PHV container 4.
That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=6][hash_bit_index=40].byte0 to be 0x2.
@@ -128,13 +128,13 @@
Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16])
Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
-Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=2].imem_subword8_instr to be 0x74d83.
-Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=2].imem_subword8_color to be 1.
-Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=2].imem_subword8_parity to be 1.
-Micro instruction added in VLIW 2 for 8-bit position 3 for table process_packet_out_table.
- Assembled as 0x74d83 (or decimal 478595)
- Micro Instruction deposit-field for PHV Container 67 has bit width 20
- Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_instr to be 0x74d84.
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_color to be 1.
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_parity to be 0.
+Micro instruction added in VLIW 2 for 8-bit position 4 for table process_packet_out_table.
+ Assembled as 0x74d84 (or decimal 478596)
+ Micro Instruction deposit-field for PHV Container 68 has bit width 20
+ Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -143,7 +143,7 @@
Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16])
Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
+Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10)
Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6)
--> Stage Gateway Table for condition process_packet_out_table_always_true_condition in stage 0
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
@@ -215,72 +215,71 @@
---- Hash Distribution Units for table table0__action__ ----
Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x2 OR new value = 0x3)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_address to be 5.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_address to be 2.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 0 to come from 32-bit PHV container 5.
- That PHV byte contains {udp.dstPort[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_address to be 5.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 1 to come from 32-bit PHV container 5.
- That PHV byte contains {udp.dstPort[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_address to be 5.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 2 to come from 32-bit PHV container 5.
- That PHV byte contains {udp.srcPort[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_address to be 5.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 3 to come from 32-bit PHV container 5.
- That PHV byte contains {udp.srcPort[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_address to be 2.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 4 to come from 32-bit PHV container 2.
+Configuring match input crossbar byte 0 to come from 32-bit PHV container 2.
That PHV byte contains {ipv4.dstAddr[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=5].match_input_xbar_32b_ctl_address to be 2.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=5].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 5 to come from 32-bit PHV container 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_address to be 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_lo_enable to be 1.
+Configuring match input crossbar byte 1 to come from 32-bit PHV container 2.
That PHV byte contains {ipv4.dstAddr[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=6].match_input_xbar_32b_ctl_address to be 2.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=6].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 6 to come from 32-bit PHV container 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_address to be 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_lo_enable to be 1.
+Configuring match input crossbar byte 2 to come from 32-bit PHV container 2.
That PHV byte contains {ipv4.dstAddr[23:16]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_lo_enable to be 1.
+Configuring match input crossbar byte 3 to come from 32-bit PHV container 3.
+ That PHV byte contains {tcp.dstPort[7:0]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_address to be 1.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_lo_enable to be 1.
+Configuring match input crossbar byte 4 to come from 32-bit PHV container 1.
+ That PHV byte contains {ipv4.srcAddr[31:24]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=5].match_input_xbar_816b_ctl_address to be 20.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=5].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 5 to come from 16-bit PHV container 4.
+ That PHV byte contains {tcp.srcPort[7:0]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=6].match_input_xbar_816b_ctl_address to be 20.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=6].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 6 to come from 16-bit PHV container 4.
+ That PHV byte contains {tcp.dstPort[15:8]}.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=7].match_input_xbar_32b_ctl_address to be 2.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=7].match_input_xbar_32b_ctl_lo_enable to be 1.
Configuring match input crossbar byte 7 to come from 32-bit PHV container 2.
That PHV byte contains {ipv4.dstAddr[31:24]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=8].match_input_xbar_32b_ctl_address to be 1.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=8].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 8 to come from 32-bit PHV container 1.
- That PHV byte contains {ipv4.srcAddr[31:24]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_address to be 19.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 8 to come from 16-bit PHV container 3.
+ That PHV byte contains {ipv4.srcAddr[7:0]}.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_address to be 19.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_enable to be 1.
Configuring match input crossbar byte 9 to come from 16-bit PHV container 3.
That PHV byte contains {ipv4.srcAddr[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_address to be 19.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_address to be 1.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 10 to come from 16-bit PHV container 3.
- That PHV byte contains {ipv4.srcAddr[7:0]}.
+Configuring match input crossbar byte 10 to come from 8-bit PHV container 1.
+ That PHV byte contains {tcp.srcPort[15:8]}.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_address to be 0.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_enable to be 1.
Configuring match input crossbar byte 11 to come from 8-bit PHV container 0.
That PHV byte contains {ipv4.srcAddr[23:16]}.
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x26. (previous value = 0x0 OR new value = 0x26)
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x9. (previous value = 0x8 OR new value = 0x1)
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
-Configuring dp.xbar_hash.hash.hash_seed[output_bit=0].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0xe. (previous value = 0x0 OR new value = 0xe)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x13. (previous value = 0x10 OR new value = 0x3)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x18. (previous value = 0x0 OR new value = 0x18)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x3. (previous value = 0x2 OR new value = 0x3)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x4.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte1 to be 0xd1.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte0 to be 0x1.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte1 to be 0xdf.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte0 to be 0x48.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte1 to be 0x1b.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte0 to be 0x4e.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte1 to be 0x5a.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0x7.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte1 to be 0x82.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte0 to be 0xf1.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte1 to be 0xfa.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0xff.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte1 to be 0xaf.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte0 to be 0xfe.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte1 to be 0xff.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte0 to be 0x7f.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte1 to be 0xff.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte0 to be 0xfb.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte1 to be 0x1f.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0xfb.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte1 to be 0xbf.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte0 to be 0xe7.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte1 to be 0xe6.
Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 1. (old value = 0 OR new value = 1).
Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 8. (old value = 0 OR new value = 8).
@@ -325,69 +324,69 @@
Configuring match input crossbar byte 133 to come from 16-bit PHV container 0.
That PHV byte contains version/valid
{unused[6:0], ig_intr_md.ingress_port[8:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_address to be 4.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_address to be 5.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 128 to come from 32-bit PHV container 4.
+Configuring match input crossbar byte 128 to come from 32-bit PHV container 5.
That PHV byte contains {ethernet.srcAddr[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_address to be 4.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_address to be 5.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 129 to come from 32-bit PHV container 4.
+Configuring match input crossbar byte 129 to come from 32-bit PHV container 5.
That PHV byte contains {ethernet.srcAddr[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_address to be 4.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_address to be 5.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 130 to come from 32-bit PHV container 4.
+Configuring match input crossbar byte 130 to come from 32-bit PHV container 5.
That PHV byte contains {ethernet.srcAddr[23:16]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_address to be 4.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_address to be 5.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 131 to come from 32-bit PHV container 4.
+Configuring match input crossbar byte 131 to come from 32-bit PHV container 5.
That PHV byte contains {ethernet.srcAddr[31:24]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_address to be 4.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 132 to come from 32-bit PHV container 3.
+Configuring match input crossbar byte 132 to come from 32-bit PHV container 4.
That PHV byte contains {ethernet.dstAddr[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_address to be 4.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 134 to come from 32-bit PHV container 3.
+Configuring match input crossbar byte 134 to come from 32-bit PHV container 4.
That PHV byte contains {ethernet.dstAddr[31:24]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_address to be 4.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 135 to come from 32-bit PHV container 3.
+Configuring match input crossbar byte 135 to come from 32-bit PHV container 4.
That PHV byte contains {ethernet.dstAddr[39:32]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_address to be 21.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_address to be 22.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 136 to come from 16-bit PHV container 5.
+Configuring match input crossbar byte 136 to come from 16-bit PHV container 6.
That PHV byte contains {ethernet.etherType[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_address to be 4.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 137 to come from 32-bit PHV container 3.
+Configuring match input crossbar byte 137 to come from 32-bit PHV container 4.
That PHV byte contains {ethernet.dstAddr[23:16]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_address to be 20.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_address to be 21.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 138 to come from 16-bit PHV container 4.
+Configuring match input crossbar byte 138 to come from 16-bit PHV container 5.
That PHV byte contains {ethernet.srcAddr[47:40]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_address to be 21.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_address to be 22.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 139 to come from 16-bit PHV container 5.
+Configuring match input crossbar byte 139 to come from 16-bit PHV container 6.
That PHV byte contains {ethernet.etherType[15:8]}.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_address to be 16.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_enable to be 1.
Configuring match input crossbar byte 140 to come from 16-bit PHV container 0.
That PHV byte contains {ig_intr_md.ingress_port[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_address to be 20.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_address to be 21.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 141 to come from 16-bit PHV container 4.
+Configuring match input crossbar byte 141 to come from 16-bit PHV container 5.
That PHV byte contains {ethernet.dstAddr[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 3.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 142 to come from 8-bit PHV container 2.
+Configuring match input crossbar byte 142 to come from 8-bit PHV container 3.
That PHV byte contains {ethernet.srcAddr[39:32]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 1.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 2.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 143 to come from 8-bit PHV container 1.
+Configuring match input crossbar byte 143 to come from 8-bit PHV container 2.
That PHV byte contains {ethernet.dstAddr[47:40]}.
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x3e. (previous value = 0x26 OR new value = 0x18)
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0xf. (previous value = 0x9 OR new value = 0x6)
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x39. (previous value = 0x8 OR new value = 0x31)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x3e. (previous value = 0xe OR new value = 0x30)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x1f. (previous value = 0x13 OR new value = 0xc)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x79. (previous value = 0x18 OR new value = 0x61)
--> Idletime Table for match table table0 in stage 0
Looking at Map RAM: Row 7 Unit 0
@@ -447,25 +446,25 @@
Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x6 OR new value = 0x4)
-Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a06.
-Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_color to be 0.
-Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_parity to be 1.
-Micro instruction added in VLIW 1 for 16-bit position 6 for table table0.
- Assembled as 0xc7a06 (or decimal 817670)
- Micro Instruction alu_a for PHV Container 134 has bit width 23
- Field Src2 [3:0] : 0x6 (4 bits in instruction bits [3:0])
+Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a07.
+Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_color to be 0.
+Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_parity to be 0.
+Micro instruction added in VLIW 1 for 16-bit position 7 for table table0.
+ Assembled as 0xc7a07 (or decimal 817671)
+ Micro Instruction alu_a for PHV Container 135 has bit width 23
+ Field Src2 [3:0] : 0x7 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20])
-Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a27.
-Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_color to be 0.
-Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_parity to be 1.
-Micro instruction added in VLIW 1 for 16-bit position 7 for table table0.
- Assembled as 0xc7a27 (or decimal 817703)
- Micro Instruction alu_a for PHV Container 135 has bit width 23
- Field Src2 [3:0] : 0x7 (4 bits in instruction bits [3:0])
+Configuring dp.imem.imem_subword16[unit_number=8][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a28.
+Configuring dp.imem.imem_subword16[unit_number=8][vliw_instruction_number=1].imem_subword16_color to be 0.
+Configuring dp.imem.imem_subword16[unit_number=8][vliw_instruction_number=1].imem_subword16_parity to be 1.
+Micro instruction added in VLIW 1 for 16-bit position 8 for table table0.
+ Assembled as 0xc7a28 (or decimal 817704)
+ Micro Instruction alu_a for PHV Container 136 has bit width 23
+ Field Src2 [3:0] : 0x8 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x2 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
@@ -486,13 +485,13 @@
Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
-Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_instr to be 0x593.
-Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_color to be 1.
-Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_parity to be 1.
-Micro instruction added in VLIW 1 for 8-bit position 3 for table table0.
- Assembled as 0x593 (or decimal 1427)
- Micro Instruction deposit-field for PHV Container 67 has bit width 20
- Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_instr to be 0x594.
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_color to be 1.
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_parity to be 0.
+Micro instruction added in VLIW 1 for 8-bit position 4 for table table0.
+ Assembled as 0x594 (or decimal 1428)
+ Micro Instruction deposit-field for PHV Container 68 has bit width 20
+ Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -516,15 +515,15 @@
Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16])
Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20])
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x8. (previous value = 0x8 OR new value = 0x8)
+Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x10. (previous value = 0x10 OR new value = 0x10)
Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x7. (previous value = 0x6 OR new value = 0x7)
-Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_instr to be 0xb7d94.
-Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_color to be 0.
-Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_parity to be 0.
-Micro instruction added in VLIW 2 for 8-bit position 4 for table table0.
- Assembled as 0xb7d94 (or decimal 753044)
- Micro Instruction deposit-field for PHV Container 68 has bit width 20
- Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
+Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_instr to be 0xb7d95.
+Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_color to be 0.
+Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_parity to be 1.
+Micro instruction added in VLIW 2 for 8-bit position 5 for table table0.
+ Assembled as 0xb7d95 (or decimal 753045)
+ Micro Instruction deposit-field for PHV Container 69 has bit width 20
+ Field Src2 [3:0] : 0x5 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -533,7 +532,7 @@
Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16])
Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19])
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x18. (previous value = 0x8 OR new value = 0x10)
+Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x30. (previous value = 0x10 OR new value = 0x20)
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].idletime_adr_payload_shifter_en to be 1.
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].stats_adr_payload_shifter_en to be 1.
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].actiondata_adr_payload_shifter_en to be 1.
@@ -773,12 +772,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -853,23 +855,24 @@
Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=14].mau_stats_adr_default to be 0x80000.
Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 23.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 24.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 0 to come from 16-bit PHV container 7.
+Configuring match input crossbar byte 0 to come from 16-bit PHV container 8.
That PHV byte contains {ecmp_metadata.selector[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 23.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 24.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 1 to come from 16-bit PHV container 7.
+Configuring match input crossbar byte 1 to come from 16-bit PHV container 8.
That PHV byte contains {ecmp_metadata.selector[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 22.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 23.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 2 to come from 16-bit PHV container 6.
+Configuring match input crossbar byte 2 to come from 16-bit PHV container 7.
That PHV byte contains {ecmp_metadata.group_id[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 22.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 23.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 3 to come from 16-bit PHV container 6.
+Configuring match input crossbar byte 3 to come from 16-bit PHV container 7.
That PHV byte contains {ecmp_metadata.group_id[15:8]}.
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0xc0. (previous value = 0x0 OR new value = 0xc0)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x80. (previous value = 0x0 OR new value = 0x80)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=9].match_input_xbar_din_power_ctl to be 0x1. (previous value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.hash.hash_seed[output_bit=2].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.hash.hash_seed[output_bit=3].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.hash.hash_seed[output_bit=5].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
@@ -1765,12 +1768,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -1821,26 +1827,26 @@
Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 18.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 0 to come from 16-bit PHV container 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 18.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 2 to come from 16-bit PHV container 2.
That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 18.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 1 to come from 16-bit PHV container 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 18.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 3 to come from 16-bit PHV container 2.
That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte1 to be 0x1.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=41].byte0 to be 0x1.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=42].byte0 to be 0x2.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=43].byte0 to be 0x4.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=44].byte0 to be 0x8.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=45].byte0 to be 0x10.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=46].byte0 to be 0x20.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=47].byte0 to be 0x40.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=48].byte0 to be 0x80.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=40].byte1 to be 0x1.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=41].byte0 to be 0x1.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=42].byte0 to be 0x2.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=43].byte0 to be 0x4.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=44].byte0 to be 0x8.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=45].byte0 to be 0x10.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=46].byte0 to be 0x20.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=47].byte0 to be 0x40.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=48].byte0 to be 0x80.
Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
@@ -1858,23 +1864,23 @@
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_mode to be 0x2
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff3f
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffff00
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff00
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8
Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x21
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid0 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid1 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][0] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][1] to be 0xffffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff7fff
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xff00ff
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff00ff
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xc (previous value 0x8 OR new value 0x4)
Configuring rams.match.merge.gateway_next_table_lut[0][2] to be 0x21
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid0 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid1 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][0] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][1] to be 0xffffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0x1ffff
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0x3ffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][1] to be 0xffff
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xe (previous value 0xc OR new value 0x2)
Configuring rams.match.merge.gateway_next_table_lut[0][1] to be 0x21
@@ -1900,7 +1906,7 @@
+------------------------------------------------------------------------
| Working on table ingress_port_count_table in stage 2 ---
+------------------------------------------------------------------------
---> Match Table with no key ingress_port_count_table with logical_table_id 0
+--> Hash Action Table ingress_port_count_table with logical_table_id 0
allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
@@ -1920,6 +1926,37 @@
Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2000.
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
+
+---- Hash Distribution Units for table ingress_port_count_table ----
+Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x1)
+Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 16.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 0 to come from 16-bit PHV container 0.
+ That PHV byte contains {ig_intr_md.ingress_port[7:0]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 16.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 1 to come from 16-bit PHV container 0.
+ That PHV byte contains {unused[6:0], ig_intr_md.ingress_port[8:8]}.
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x5. (previous value = 0x4 OR new value = 0x1)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x1)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x1.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte0 to be 0x2.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte0 to be 0x4.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte0 to be 0x8.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte0 to be 0x10.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte0 to be 0x20.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte0 to be 0x40.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte0 to be 0x80.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=8].byte1 to be 0x1.
+Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
+Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 1. (old value = 0 OR new value = 1).
+Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 8. (old value = 0 OR new value = 8).
+Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 1. (old value = 0 OR new value = 1).
+Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x1. (old value = 0x0 OR new value = 0x1).
+Configuring rams.match.merge.mau_hash_group_mask[which_16=0].mau_hash_group_mask to be 0x3ff. (previous value = 0x0 OR new value = 0x3ff)
+Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=3][control_group_index=0].mau_hash_group_xbar_ctl to be 0x8 (old value = 0x0 OR new value = 0x8).
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].stats_adr_payload_shifter_en to be 1.
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
@@ -1931,7 +1968,7 @@
+------------------------------------------------------------------------
| Working on table egress_port_count_table in stage 2 ---
+------------------------------------------------------------------------
---> Match Table with no key egress_port_count_table with logical_table_id 1
+--> Hash Action Table egress_port_count_table with logical_table_id 1
allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
@@ -1951,6 +1988,37 @@
Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2).
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x40.
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
+
+---- Hash Distribution Units for table egress_port_count_table ----
+Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x1 OR new value = 0x2)
+Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_address to be 18.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 8 to come from 16-bit PHV container 2.
+ That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_address to be 18.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 9 to come from 16-bit PHV container 2.
+ That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x5. (previous value = 0x5 OR new value = 0x4)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=1][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=1][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0x1.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=1].byte0 to be 0x2.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=2].byte0 to be 0x4.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=3].byte0 to be 0x8.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=4].byte0 to be 0x10.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=5].byte0 to be 0x20.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=6].byte0 to be 0x40.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=7].byte0 to be 0x80.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=8].byte1 to be 0x1.
+Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x3. (previous value = 0x1 OR new value = 0x2)
+Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 9. (old value = 1 OR new value = 8).
+Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 152. (old value = 8 OR new value = 144).
+Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 65. (old value = 1 OR new value = 64).
+Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x201. (old value = 0x1 OR new value = 0x200).
+Configuring rams.match.merge.mau_hash_group_mask[which_16=3].mau_hash_group_mask to be 0x3ff. (previous value = 0x0 OR new value = 0x3ff)
+Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=3][control_group_index=0].mau_hash_group_xbar_ctl to be 0xb8 (old value = 0x8 OR new value = 0xb0).
--> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 2
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
@@ -1958,11 +2026,11 @@
Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
-Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x0)
+Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x3 OR new value = 0x0)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x0)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
-Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
+Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x3. (previous value = 0x3 OR new value = 0x1)
Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
@@ -2199,12 +2267,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2281,12 +2352,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2363,12 +2437,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2445,12 +2522,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2527,12 +2607,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2609,12 +2692,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2691,12 +2777,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2773,12 +2862,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2855,12 +2947,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2937,12 +3032,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2978,7 +3076,7 @@
Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
+------------------------------------------------------------------------
-| Number of configuration field values set in Match-Action Stages: 2100
+| Number of configuration field values set in Match-Action Stages: 2186
+------------------------------------------------------------------------
+------------------------------------------------------------------------