Gitiles
Code Review Sign In
gerrit.onosproject.org / onos / f1d0a42bab280609366b3d7c54d72318825ba46d / . / tools / test / p4src / p4-14 / p4c-out / tofino / ecmp / mavericks / logs / mau.config.log
blob: fafc0384915f1a662e8cd3d2d95819c6dafd142e [file] [log] [blame]
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame^]1+---------------------------------------------------------------------+
2| Log file: mau.config.log |
3| Compiler version: 5.1.0 (fca32d1) |
4| Created on: Thu Sep 7 14:48:49 2017 |
5+---------------------------------------------------------------------+
6
7Final Stage dependencies are:
8 (0, 'ingress') : match
9 (1, 'ingress') : match
10 (2, 'ingress') : match
11 (3, 'ingress') : match
12 (4, 'ingress') : concurrent
13 (5, 'ingress') : concurrent
14 (6, 'ingress') : match
15 (7, 'ingress') : concurrent
16 (8, 'ingress') : concurrent
17 (9, 'ingress') : concurrent
18 (10, 'ingress') : concurrent
19 (11, 'ingress') : concurrent
20 (0, 'egress') : match
21 (1, 'egress') : concurrent
22 (2, 'egress') : concurrent
23 (3, 'egress') : concurrent
24 (4, 'egress') : concurrent
25 (5, 'egress') : concurrent
26 (6, 'egress') : match
27 (7, 'egress') : concurrent
28 (8, 'egress') : concurrent
29 (9, 'egress') : concurrent
30 (10, 'egress') : concurrent
31 (11, 'egress') : concurrent
32Action/Concurrent chaining in ingress consists of [4, 5]
33Action/Concurrent chaining in ingress consists of [7, 8, 9, 10, 11]
34Action/Concurrent chaining in egress consists of [1, 2, 3, 4, 5]
35Action/Concurrent chaining in egress consists of [7, 8, 9, 10, 11]
36
37+------------------------------------------------------------------------
38| MAU Stage 0
39+------------------------------------------------------------------------
40
41+------------------------------------------------------------------------
42| Working on table _condition_0 in stage 0 ---
43+------------------------------------------------------------------------
44--> Stage Gateway Table for condition _condition_0 in stage 0
45Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
46Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
47Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
48Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
49Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
50Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
51Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
52Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
53Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 4.
54Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
55Configuring match input crossbar byte 1 to come from 8-bit PHV container 4.
56 That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
57Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10)
58Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
59Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
60Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=41].byte1 to be 0x2.
61Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
62Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
63Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
64Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
65Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
66Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x0
67Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0
68Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
69Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
70Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
71Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff
72Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff
73Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xfffffd
74Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff
75Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8
76Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x10
77Configuring rams.match.merge.gateway_en.gateway_en to be 0x1
78Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xe
79Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1
80allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
81Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x0
82Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1
83Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2
84Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x1
85Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0
86Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x1
87Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0
88Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff
89Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff
90
91+------------------------------------------------------------------------
92| Working on table _condition_3 in stage 0 ---
93+------------------------------------------------------------------------
94--> Stage Gateway Table for condition _condition_3 in stage 0
95Configuring rams.match.merge.predication_ctl[direction_index=1].table_thread to be 0x2 (previous_value=0x0 OR new_value=0x2).
96Configuring dp.imem_table_addr_egress to be 0x2 (previous_value = 0x0 OR new_value = 0x2).
97Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=1][copy_index=0].adr_dist_table_thread to be 0x2 (previous_value=0x0 OR new_value=0x2).
98Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=1][copy_index=1].adr_dist_table_thread to be 0x2 (previous_value=0x0 OR new_value=0x2).
99Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_egress to be 0x2 (previous_value=0x0 OR new_value=0x2).
100Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_egress to be 0x2 (previous_value=0x0 OR new_value=0x2).
101Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_egress to be 0x2 (previous_value=0x0 OR new_value=0x2).
102Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=1].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
103Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=1].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
104Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=2][output_byte=0].match_input_xbar_816b_ctl_address to be 0.
105Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=2][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
106Configuring match input crossbar byte 0 to come from 8-bit PHV container 16.
107 That PHV byte contains {unused[6:0], ig_intr_md_for_tm.copy_to_cpu[0:0]}.
108Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=6].match_input_xbar_din_power_ctl to be 0x1. (previous value = 0x0 OR new value = 0x1)
109Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x1)
110Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
111Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte0 to be 0x1.
112Configuring dp.hashout_ctl.hash_group_egress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
113Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
114Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
115Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
116Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
117Configuring cfg_regs.mau_cfg_lt_thread.mau_cfg_lt_thread to be 0x2. (previous value = 0x0 OR new value = 0x2)
118Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
119Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
120Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
121Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
122Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x1
123Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x1
124Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
125Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
126Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
127Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
128Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
129Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xfffffe
130Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffffff
131Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8
132Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0xff
133Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2)
134Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xf
135Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1
136allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
137Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_logical_select to be 0x1
138Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_inhibit_enable to be 0x1
139Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x3 (previous value 0x2 OR new value 0x1)
140Configuring rams.match.merge.gateway_payload_data[0][0][0][0].gateway_payload_data to be 0x1
141Configuring rams.match.merge.gateway_payload_data[0][0][1][0].gateway_payload_data to be 0x0
142Configuring rams.match.merge.gateway_payload_data[0][0][0][1].gateway_payload_data to be 0x1
143Configuring rams.match.merge.gateway_payload_data[0][0][1][1].gateway_payload_data to be 0x0
144Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff
145Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff
146
147+------------------------------------------------------------------------
148| Working on table ingress_pkt__action__ in stage 0 ---
149+------------------------------------------------------------------------
150--> Action Data Table ingress_pkt__action__ with logical_table_id 0 that is reference type is 'direct'
151
152+------------------------------------------------------------------------
153| Working on table ingress_pkt in stage 0 ---
154+------------------------------------------------------------------------
155--> Match Table with no key ingress_pkt with logical_table_id 0
156allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
157Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
158Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
159Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
160Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
161Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
162Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
163Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id).
164Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
165Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id).
166Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
167Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x0.
168Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x1.
169Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x10.
170Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
171Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2080.
172Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
173Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x74412.
174Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1.
175Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 0.
176Micro instruction added in VLIW 0 for 16-bit position 2 for table ingress_pkt.
177 Assembled as 0x74412 (or decimal 476178)
178 Micro Instruction deposit-field for PHV Container 130 has bit width 23
179 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
180 Field Src1 [4:0] : 0x1 (5 bits in instruction bits [8:4])
181 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
182 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
183 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
184 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
185 Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16])
186 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
187
188Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=0].imem_subword8_instr to be 0x74d84.
189Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=0].imem_subword8_color to be 1.
190Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=0].imem_subword8_parity to be 0.
191Micro instruction added in VLIW 0 for 8-bit position 4 for table ingress_pkt.
192 Assembled as 0x74d84 (or decimal 478596)
193 Micro Instruction deposit-field for PHV Container 68 has bit width 20
194 Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
195 Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4])
196 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
197 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
198 Field high_bit [2:0] : 0x1 (3 bits in instruction bits [13:11])
199 Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14])
200 Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16])
201 Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
202
203Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10)
204Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6)
205Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
206
207+------------------------------------------------------------------------
208| Working on table egress_pkt__action__ in stage 0 ---
209+------------------------------------------------------------------------
210--> Action Data Table egress_pkt__action__ with logical_table_id 1 that is reference type is 'direct'
211
212+------------------------------------------------------------------------
213| Working on table egress_pkt in stage 0 ---
214+------------------------------------------------------------------------
215--> Match Table with no key egress_pkt with logical_table_id 1
216allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
217Configuring dp.imem_table_addr_egress to be 0x2 (previous_value = 0x2 OR new_value = 0x2).
218Configuring rams.match.merge.predication_ctl[direction_index=1].table_thread to be 0x2 (previous_value=0x2 OR new_value=0x2).
219Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_egress to be 0x2 (previous_value=0x2 OR new_value=0x2).
220Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_egress to be 0x2 (previous_value=0x2 OR new_value=0x2).
221Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_egress to be 0x2 (previous_value=0x2 OR new_value=0x2).
222Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=1][copy_index=0].adr_dist_table_thread to be 0x2 (previous_value=0x2 OR new_value=0x2).
223Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=1][copy_index=1].adr_dist_table_thread to be 0x2 (previous_value=0x2 OR new_value=0x2).
224Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id).
225Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
226Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id).
227Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
228Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_default to be 0x0.
229Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x1.
230Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0xff.
231Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2).
232Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x2080.
233Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
234Configuring dp.imem.imem_subword8[unit_number=18][vliw_instruction_number=0].imem_subword8_instr to be 0x592.
235Configuring dp.imem.imem_subword8[unit_number=18][vliw_instruction_number=0].imem_subword8_color to be 1.
236Configuring dp.imem.imem_subword8[unit_number=18][vliw_instruction_number=0].imem_subword8_parity to be 0.
237Micro instruction added in VLIW 0 for 8-bit position 18 for table egress_pkt.
238 Assembled as 0x592 (or decimal 1426)
239 Micro Instruction deposit-field for PHV Container 82 has bit width 20
240 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
241 Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
242 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
243 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
244 Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11])
245 Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14])
246 Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16])
247 Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
248
249Configuring dp.imem.imem_subword16[unit_number=17][vliw_instruction_number=0].imem_subword16_instr to be 0x39fc01.
250Configuring dp.imem.imem_subword16[unit_number=17][vliw_instruction_number=0].imem_subword16_color to be 1.
251Configuring dp.imem.imem_subword16[unit_number=17][vliw_instruction_number=0].imem_subword16_parity to be 0.
252Micro instruction added in VLIW 0 for 16-bit position 17 for table egress_pkt.
253 Assembled as 0x39fc01 (or decimal 3800065)
254 Micro Instruction deposit-field for PHV Container 145 has bit width 23
255 Field Src2 [3:0] : 0x1 (4 bits in instruction bits [3:0])
256 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
257 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
258 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
259 Field high_bit [3:0] : 0xf (4 bits in instruction bits [14:11])
260 Field low_bit_lo [0:0] : 0x1 (1 bits in instruction bits [15:15])
261 Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16])
262 Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20])
263
264Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=6].actionmux_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
265Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=10].actionmux_din_power_ctl to be 0x3. (previous value = 0x0 OR new value = 0x3)
266Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=0].action_instruction_adr_payload_shifter_en to be 1.
267+------------------------------------------------------------------------
268Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 10.
269Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
270Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 1.
271Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 10.
272Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
273Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 1.
274Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
275Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
276Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
277Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
278Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
279Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x3.
280Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
281Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
282Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x3.
283Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
284Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x1.
285Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
286Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
287Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
288Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
289Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
290Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
291Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
292Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
293Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
294Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
295Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
296--------------------------------------------
297Configuration for unused statistics ALUs.
298Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
299Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
300Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
301Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
302+------------------------------------------------------------------------
303Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
304Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
305Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
306Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
307Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
308Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
309Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
310Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
311Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
312Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
313Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
314Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
315Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
316Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
317Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
318Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
319Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
320Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
321Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
322Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
323Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
324Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
325Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
326Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
327Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
328Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
329Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
330+------------------------------------------------------------------------
331Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
332Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
333Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
334Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
335Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
336Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
337Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0.
338Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
339Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
340Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0.
341Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
342Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
343Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
344Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
345
346+------------------------------------------------------------------------
347| MAU Stage 1
348+------------------------------------------------------------------------
349
350+------------------------------------------------------------------------
351| Working on table _condition_1 in stage 1 ---
352+------------------------------------------------------------------------
353--> Stage Gateway Table for condition _condition_1 in stage 1
354Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
355Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
356Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
357Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
358Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
359Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
360Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x2. (old value = 0x0 OR new value = 0x2)
361Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
362Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_address to be 4.
363Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_enable to be 1.
364Configuring match input crossbar byte 12 to come from 8-bit PHV container 4.
365 That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
366Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10)
367Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2)
368Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
369Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=6][hash_bit_index=40].byte0 to be 0x2.
370Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
371Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
372Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
373Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
374Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
375Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
376Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
377Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
378Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
379Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0
380Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0
381Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
382Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
383Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
384Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
385Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
386Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff
387Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xfffffe
388Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x10
389Configuring rams.match.merge.gateway_next_table_lut[0][4] to be 0x30
390Configuring rams.match.merge.gateway_en.gateway_en to be 0x1
391Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf
392Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1
393Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_logical_select to be 0x0
394Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_inhibit_enable to be 0x1
395Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff
396Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff
397
398+------------------------------------------------------------------------
399| Working on table table0__action__ in stage 1 ---
400+------------------------------------------------------------------------
401--> Action Data Table table0__action__ with logical_table_id 0 that is reference type is 'direct'
402Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_input_bytemask[array_half=1].action_hv_ixbar_input_bytemask to be 0x3.
403Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_ctl_halfword[slice_group=1][array_half=1].action_hv_ixbar_ctl_halfword_3to0_ctl to be 0.
404Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_ctl_halfword[slice_group=1][array_half=1].action_hv_ixbar_ctl_halfword_3to0_enable to be 1.
405Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_select to be 5.
406Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_enable to be 1.
407Configuring rams.array.switchbox.row[row=6].ctl.r_action_o_mux_select.r_action_o_sel_action_rd_r_i to be 1.
408Configuring rams.array.row[row=6].ram[col=8].unit_ram_ctl.match_ram_write_data_mux_select to be select of 7.
409Configuring rams.array.row[row=6].ram[col=8].unit_ram_ctl.match_ram_read_data_mux_select to be select of 4.
410Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_type to be 2.
411Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_vpn to be 0.
412Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_logical_table to be 0.
413Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_ingress to be 1.
414Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_action_subword_out_en to be 1.
415Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_enable to be 1.
416Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=2].ram_unitram_adr_mux_select to be 1.
417Configuring rams.array.row[row=6].actiondata_error_uram_ctl[direction=0].actiondata_error_uram_ctl to be select of 0x40. (previous value = 0x0 OR new value = 0x40)
418Action data table table0__action__ is used by match table table0.
419Configuring rams.match.adrdist.adr_dist_action_data_adr_icxbar_ctl[match_logical_table_id=0].address_distr_to_logical_rows to be 0x2000.
420
421---- Hash Distribution Units for table table0__action__ ----
422Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x2 OR new value = 0x3)
423Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
424Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_address to be 5.
425Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_lo_enable to be 1.
426Configuring match input crossbar byte 0 to come from 32-bit PHV container 5.
427 That PHV byte contains {udp.dstPort[7:0]}.
428Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_address to be 5.
429Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_lo_enable to be 1.
430Configuring match input crossbar byte 1 to come from 32-bit PHV container 5.
431 That PHV byte contains {udp.dstPort[15:8]}.
432Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_address to be 5.
433Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_lo_enable to be 1.
434Configuring match input crossbar byte 2 to come from 32-bit PHV container 5.
435 That PHV byte contains {udp.srcPort[7:0]}.
436Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_address to be 5.
437Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_lo_enable to be 1.
438Configuring match input crossbar byte 3 to come from 32-bit PHV container 5.
439 That PHV byte contains {udp.srcPort[15:8]}.
440Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_address to be 2.
441Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_lo_enable to be 1.
442Configuring match input crossbar byte 4 to come from 32-bit PHV container 2.
443 That PHV byte contains {ipv4.dstAddr[7:0]}.
444Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=5].match_input_xbar_32b_ctl_address to be 2.
445Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=5].match_input_xbar_32b_ctl_lo_enable to be 1.
446Configuring match input crossbar byte 5 to come from 32-bit PHV container 2.
447 That PHV byte contains {ipv4.dstAddr[15:8]}.
448Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=6].match_input_xbar_32b_ctl_address to be 2.
449Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=6].match_input_xbar_32b_ctl_lo_enable to be 1.
450Configuring match input crossbar byte 6 to come from 32-bit PHV container 2.
451 That PHV byte contains {ipv4.dstAddr[23:16]}.
452Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=7].match_input_xbar_32b_ctl_address to be 2.
453Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=7].match_input_xbar_32b_ctl_lo_enable to be 1.
454Configuring match input crossbar byte 7 to come from 32-bit PHV container 2.
455 That PHV byte contains {ipv4.dstAddr[31:24]}.
456Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=8].match_input_xbar_32b_ctl_address to be 1.
457Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=8].match_input_xbar_32b_ctl_lo_enable to be 1.
458Configuring match input crossbar byte 8 to come from 32-bit PHV container 1.
459 That PHV byte contains {ipv4.srcAddr[31:24]}.
460Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_address to be 19.
461Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_enable to be 1.
462Configuring match input crossbar byte 9 to come from 16-bit PHV container 3.
463 That PHV byte contains {ipv4.srcAddr[15:8]}.
464Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_address to be 19.
465Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_enable to be 1.
466Configuring match input crossbar byte 10 to come from 16-bit PHV container 3.
467 That PHV byte contains {ipv4.srcAddr[7:0]}.
468Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_address to be 1.
469Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_enable to be 1.
470Configuring match input crossbar byte 11 to come from 8-bit PHV container 1.
471 That PHV byte contains {ipv4.srcAddr[23:16]}.
472Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x26. (previous value = 0x0 OR new value = 0x26)
473Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x12. (previous value = 0x10 OR new value = 0x2)
474Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
475Configuring dp.xbar_hash.hash.hash_seed[output_bit=0].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
476Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x3. (previous value = 0x2 OR new value = 0x3)
477Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
478Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x4.
479Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte1 to be 0xd1.
480Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte0 to be 0x1.
481Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte1 to be 0xdf.
482Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte0 to be 0x48.
483Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte1 to be 0x1b.
484Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte0 to be 0x4e.
485Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte1 to be 0x5a.
486Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0x7.
487Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte1 to be 0x82.
488Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte0 to be 0xf1.
489Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte1 to be 0xfa.
490Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
491Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 1. (old value = 0 OR new value = 1).
492Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 8. (old value = 0 OR new value = 8).
493Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 1. (old value = 0 OR new value = 1).
494Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x0. (old value = 0x0 OR new value = 0x0).
495Configuring rams.match.merge.mau_hash_group_mask[which_16=0].mau_hash_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
496Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=1][control_group_index=0].mau_hash_group_xbar_ctl to be 0x8 (old value = 0x0 OR new value = 0x8).
497
498+------------------------------------------------------------------------
499| Working on table table0 in stage 1 ---
500+------------------------------------------------------------------------
501--> Ternary Match Table table0 with logical_table_id 0
502Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
503Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
504Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
505Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
506Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
507Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
508Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id).
509Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
510Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id).
511Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
512Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x7.
513Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_default to be 0x0.
514Configuring rams.match.merge.mau_action_instruction_adr_per_entry_en_mux_ctl[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_per_entry_en_mux_ctl to be 0x3.
515Configuring rams.match.merge.mau_actiondata_adr_default[table_type_index=1][physical_result_bus=0].mau_actiondata_adr_default to be 0x400001.
516Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=1].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
517Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x870a080.
518Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x44.
519Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
520Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x30.
521Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data1 to be 0x20.
522Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x30.
523Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x1.
524Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=1][result_bus_number=0].mau_immediate_data_mask to be 0x0.
525Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=1][result_bus_number=0].mau_stats_adr_mask to be 0xffffe.
526Configuring rams.match.merge.mau_stats_adr_default[table_type_index=1][result_bus_number=0].mau_stats_adr_default to be 0x80000.
527Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x3 OR new value = 0x0)
528Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x3. (old value = 0x0 OR new value = 0x3)
529Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_address to be 16.
530Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_enable to be 1.
531Configuring match input crossbar byte 133 to come from 16-bit PHV container 0.
532 That PHV byte contains version/valid
533{unused[6:0], ig_intr_md.ingress_port[8:8]}.
534Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_address to be 4.
535Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_lo_enable to be 1.
536Configuring match input crossbar byte 128 to come from 32-bit PHV container 4.
537 That PHV byte contains {ethernet.srcAddr[7:0]}.
538Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_address to be 4.
539Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_lo_enable to be 1.
540Configuring match input crossbar byte 129 to come from 32-bit PHV container 4.
541 That PHV byte contains {ethernet.srcAddr[15:8]}.
542Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_address to be 4.
543Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_lo_enable to be 1.
544Configuring match input crossbar byte 130 to come from 32-bit PHV container 4.
545 That PHV byte contains {ethernet.srcAddr[23:16]}.
546Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_address to be 4.
547Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_lo_enable to be 1.
548Configuring match input crossbar byte 131 to come from 32-bit PHV container 4.
549 That PHV byte contains {ethernet.srcAddr[31:24]}.
550Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_address to be 3.
551Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_lo_enable to be 1.
552Configuring match input crossbar byte 132 to come from 32-bit PHV container 3.
553 That PHV byte contains {ethernet.dstAddr[15:8]}.
554Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_address to be 3.
555Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_lo_enable to be 1.
556Configuring match input crossbar byte 134 to come from 32-bit PHV container 3.
557 That PHV byte contains {ethernet.dstAddr[31:24]}.
558Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_address to be 3.
559Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_lo_enable to be 1.
560Configuring match input crossbar byte 135 to come from 32-bit PHV container 3.
561 That PHV byte contains {ethernet.dstAddr[39:32]}.
562Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_address to be 21.
563Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_enable to be 1.
564Configuring match input crossbar byte 136 to come from 16-bit PHV container 5.
565 That PHV byte contains {ethernet.etherType[7:0]}.
566Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_address to be 3.
567Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_lo_enable to be 1.
568Configuring match input crossbar byte 137 to come from 32-bit PHV container 3.
569 That PHV byte contains {ethernet.dstAddr[23:16]}.
570Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_address to be 20.
571Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_enable to be 1.
572Configuring match input crossbar byte 138 to come from 16-bit PHV container 4.
573 That PHV byte contains {ethernet.srcAddr[47:40]}.
574Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_address to be 21.
575Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_enable to be 1.
576Configuring match input crossbar byte 139 to come from 16-bit PHV container 5.
577 That PHV byte contains {ethernet.etherType[15:8]}.
578Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_address to be 16.
579Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_enable to be 1.
580Configuring match input crossbar byte 140 to come from 16-bit PHV container 0.
581 That PHV byte contains {ig_intr_md.ingress_port[7:0]}.
582Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_address to be 20.
583Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_enable to be 1.
584Configuring match input crossbar byte 141 to come from 16-bit PHV container 4.
585 That PHV byte contains {ethernet.dstAddr[7:0]}.
586Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 3.
587Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_enable to be 1.
588Configuring match input crossbar byte 142 to come from 8-bit PHV container 3.
589 That PHV byte contains {ethernet.srcAddr[39:32]}.
590Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 2.
591Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_enable to be 1.
592Configuring match input crossbar byte 143 to come from 8-bit PHV container 2.
593 That PHV byte contains {ethernet.dstAddr[47:40]}.
594Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x3e. (previous value = 0x26 OR new value = 0x18)
595Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x1e. (previous value = 0x12 OR new value = 0xc)
596Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x39. (previous value = 0x8 OR new value = 0x31)
597
598--> Idletime Table for match table table0 in stage 1
599Looking at Map RAM: Row 7 Unit 0
600Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 0.
601Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 1.
602Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].two_way_idletime_notification to be 1.
603Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].per_flow_idletime to be 1.
604Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].idletime_bitwidth to be 2 (precision = 3 bits).
605Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_type to be 4.
606Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
607FIXME: Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn_members to be 0.
608Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn to be 0.
609Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
610Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
611Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
612Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
613Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 2.
614Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
615Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
616Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
617Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_stats_meter_adr_mux_select_idlet to be 1.
618Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0.
619Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1.
620Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0.
621Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1.
622Configuring rams.map_alu.row[row=7].adrmux.idletime_cfg_rd_clear_val[map_ram_index=0].idletime_cfg_rd_clear_val to be 0x36.
623 logical table ID is 0
624Configuring rams.match.adrdist.adr_dist_idletime_adr_oxbar_ctl.[entry_index=2].adr_dist_idletime_adr_oxbar_ctl be 0x4000 (previous value = 0x0 OR new value = 0x4000)
625Note that rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_en must be programmed by run time.
626Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_offset be 0x0.
627Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_size be 0x0.
628Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_pos be 0x0.
629Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_en be 0x0.
630Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_interval be 0x7.
631Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_offset be 0x0.
632Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_size be 0x0.
633Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_pos be 0x0.
634Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_en be 0.
635Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_size be 2.
636Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_direct be 1.
637Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=2].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1)
638Configuring rams.match.merge.mau_idletime_adr_mask[table_type_index=1][result_bus_number=0].mau_idletime_adr_mask to be 0x1ffff8.
639Configuring rams.match.merge.mau_idletime_adr_default[table_type_index=1][result_bus_number=0].idletime_adr_default to be 0x100003.
640Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x4602.
641Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1.
642Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 1.
643Micro instruction added in VLIW 0 for 16-bit position 2 for table table0.
644 Assembled as 0x4602 (or decimal 17922)
645 Micro Instruction deposit-field for PHV Container 130 has bit width 23
646 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
647 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
648 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
649 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
650 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
651 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
652 Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
653 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
654
655Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
656Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a06.
657Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_color to be 0.
658Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_parity to be 1.
659Micro instruction added in VLIW 1 for 16-bit position 6 for table table0.
660 Assembled as 0xc7a06 (or decimal 817670)
661 Micro Instruction alu_a for PHV Container 134 has bit width 23
662 Field Src2 [3:0] : 0x6 (4 bits in instruction bits [3:0])
663 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
664 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
665 Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
666 Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20])
667
668Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a27.
669Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_color to be 0.
670Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_parity to be 1.
671Micro instruction added in VLIW 1 for 16-bit position 7 for table table0.
672 Assembled as 0xc7a27 (or decimal 817703)
673 Micro Instruction alu_a for PHV Container 135 has bit width 23
674 Field Src2 [3:0] : 0x7 (4 bits in instruction bits [3:0])
675 Field Src1 [4:0] : 0x2 (5 bits in instruction bits [8:4])
676 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
677 Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
678 Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20])
679
680Configuring dp.imem.imem_subword8[unit_number=0][vliw_instruction_number=1].imem_subword8_instr to be 0x590.
681Configuring dp.imem.imem_subword8[unit_number=0][vliw_instruction_number=1].imem_subword8_color to be 1.
682Configuring dp.imem.imem_subword8[unit_number=0][vliw_instruction_number=1].imem_subword8_parity to be 1.
683Micro instruction added in VLIW 1 for 8-bit position 0 for table table0.
684 Assembled as 0x590 (or decimal 1424)
685 Micro Instruction deposit-field for PHV Container 64 has bit width 20
686 Field Src2 [3:0] : 0x0 (4 bits in instruction bits [3:0])
687 Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
688 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
689 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
690 Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11])
691 Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14])
692 Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16])
693 Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
694
695Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x1. (previous value = 0x0 OR new value = 0x1)
696Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_instr to be 0xb7d95.
697Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_color to be 0.
698Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_parity to be 1.
699Micro instruction added in VLIW 2 for 8-bit position 5 for table table0.
700 Assembled as 0xb7d95 (or decimal 753045)
701 Micro Instruction deposit-field for PHV Container 69 has bit width 20
702 Field Src2 [3:0] : 0x5 (4 bits in instruction bits [3:0])
703 Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
704 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
705 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
706 Field high_bit [2:0] : 0x7 (3 bits in instruction bits [13:11])
707 Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14])
708 Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16])
709 Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19])
710
711Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x21. (previous value = 0x1 OR new value = 0x20)
712Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].idletime_adr_payload_shifter_en to be 1.
713Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].stats_adr_payload_shifter_en to be 1.
714Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].actiondata_adr_payload_shifter_en to be 1.
715Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].action_instruction_adr_payload_shifter_en to be 1.
716Configuring rams.match.merge.mau_table_counter_ctl[half_index=0].mau_table_counter_ctl to be 0x2. (previous value = 0x0 OR new value = 0x2)
717dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit']
718Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data_dirtcam_mode to be 0x155.
719Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vbit_dirtcam_mode to be 0x1.
720Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data1_select to be 1.
721Configuring tcams.col[col=1].tcam_mode[row=9].tcam_chain_out_enable to be 0.
722Configuring tcams.col[col=1].tcam_mode[row=9].tcam_ingress to be 1.
723Configuring tcams.col[col=1].tcam_mode[row=9].tcam_match_output_enable to be 1.
724Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vpn to be 0.
725Configuring tcams.col[col=1].tcam_mode[row=9].tcam_logical_table to be 0.
726TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit.
727Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=0] to be 15.
728Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=1] to be 15.
729Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=2] to be 15.
730Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=3] to be 15.
731Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=4] to be 15.
732Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=5] to be 15.
733Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=6] to be 15.
734Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=7] to be 15.
735Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_select to be 0 (don't care).
736Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_enable to be 1.
737Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_select to be 2.
738Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_enable to be 1.
739dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit']
740Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data_dirtcam_mode to be 0x155.
741Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vbit_dirtcam_mode to be 0x0.
742Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data1_select to be 1.
743Configuring tcams.col[col=1].tcam_mode[row=10].tcam_chain_out_enable to be 1.
744Configuring tcams.col[col=1].tcam_mode[row=10].tcam_ingress to be 1.
745Configuring tcams.col[col=1].tcam_mode[row=10].tcam_match_output_enable to be 0.
746Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vpn to be 0.
747Configuring tcams.col[col=1].tcam_mode[row=10].tcam_logical_table to be 0.
748TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit.
749Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15.
750Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15.
751Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15.
752Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15.
753Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15.
754Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15.
755Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15.
756Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15.
757Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_select to be 3 (version on [3:2] and valid bits for [1:0]).
758Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_enable to be 1.
759Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0.
760Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1.
761Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_select to be 1.
762Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_enable to be 1.
763dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit']
764Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data_dirtcam_mode to be 0x155.
765Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vbit_dirtcam_mode to be 0x1.
766Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data1_select to be 1.
767Configuring tcams.col[col=1].tcam_mode[row=11].tcam_chain_out_enable to be 1.
768Configuring tcams.col[col=1].tcam_mode[row=11].tcam_ingress to be 1.
769Configuring tcams.col[col=1].tcam_mode[row=11].tcam_match_output_enable to be 0.
770Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vpn to be 0.
771Configuring tcams.col[col=1].tcam_mode[row=11].tcam_logical_table to be 0.
772TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit.
773Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15.
774Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15.
775Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15.
776Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15.
777Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15.
778Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15.
779Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15.
780Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15.
781Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_select to be 0 (extra byte low nibble [3:0]).
782Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_enable to be 1.
783Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0.
784Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1.
785Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_select to be 0.
786Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_enable to be 1.
787Configuring tcams.col[col=0].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x0.
788Configuring tcams.col[col=1].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x200.
789--> Ternary Indirection table for Match Table table0 with logical_table_id 0
790Configuring tcams.tcam_match_adr_shift[tcam_table_id=0] to be left shift of 1.
791Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_write_data_mux_select to be select of 7.
792Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_read_data_mux_select to be select of 7.
793Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.tind_result_bus_select to be select of 1.
794Configuring rams.map_alu.row[row=0].adrmux.ram_address_mux_ctl[column_half=0][column_index=2].ram_unitram_adr_mux_select to be 2.
795Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_type to be 6.
796Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_vpn to be 0.
797Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_logical_table to be 0.
798Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_ingress to be 1.
799Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_enable to be 1.
800Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id).
801Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_enable to be 1.
802Configuring rams.array.row[row=0].tind_ecc_error_uram_ctl[direction=0].tind_ecc_error_uram_ctl to be select of 0x1. (previous value = 0x0 OR new value = 0x1)
803Configuring rams.match.merge.tind_ram_data_size[tind_bus_number=0].tind_ram_data_size to be code 2.
804Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id).
805Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_enable to be 1.
806TODO: rams.match.merge.tind_bus_prop[tind_bus_number=0] is currently always set to 1.
807Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].tcam_piped to be 1.
808Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].enabled to be 1.
809Configuring rams.match.merge.mau_action_instruction_adr_tcam_shiftcount[physical_result_bus=0].mau_action_instruction_adr_tcam_shiftcount to be 1.
810Configuring rams.match.merge.mau_actiondata_adr_mask[table_type_index=1][physical_result_bus=0].mau_actiondata_adr_mask to be 0x3ffffc.
811Configuring rams.match.merge.mau_actiondata_adr_tcam_shiftcount[physical_result_bus=0].mau_actiondata_adr_tcam_shiftcount to be 68.
812Configuring rams.match.merge.mau_idletime_adr_tcam_shiftcount[result_bus_number=0].mau_idletime_adr_tcam_shiftcount to be 0x42.
813Configuring rams.match.merge.mau_stats_adr_tcam_shiftcount[result_bus_index=0].mau_stats_adr_tcam_shiftcount to be 0x47.
814Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_select to be 0 (logical table id).
815Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_enable to be 1.
816TODO: rams.match.merge.tcam_table_prop[tcam_table_id=0] is currently always set to 1.
817Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].tcam_piped to be 1.
818Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].enabled to be 1.
819Configuring tcams.tcam_output_table_thread[tcam_table_id=0].tcam_output_table_thread to be 1.
820TODO: tcams.tcam_piped is currently always set to True for ingress and egress.
821Configuring tcams.tcam_piped to be 3.
822Configuring cfg_regs.mau_cfg_movereg_tcam_only.mau_cfg_movereg_tcam_only to be 0x1. (previous value = 0x0 OR new value = 0x1)
823
824+------------------------------------------------------------------------
825| Working on table table0_counter in stage 1 ---
826+------------------------------------------------------------------------
827Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
828Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
829Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
830Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
831Note that unitram_vpn does not need to be programmed for synthetic two port rams.
832Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0.
833Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
834Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
835Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
836Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
837Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
838Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
839Note that unitram_vpn does not need to be programmed for synthetic two port rams.
840Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0.
841Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
842Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
843Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
844Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
845Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
846Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
847Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
848Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
849Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
850Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
851Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
852Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
853Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
854Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
855Stat table table0_counter is used by match table table0.
856Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8)
857Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
858Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
859Note that map ram vpn does not need to be configured for synthetic two port map rams.
860Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
861Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
862Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
863Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
864Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
865Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
866Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
867Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
868Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0.
869Note that map ram vpn does not need to be configured for synthetic two port map rams.
870Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
871Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
872Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
873Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
874Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
875Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
876Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
877For counter width 32 and N = 4096
878 number iterations = 32
879 b_cur = 379488672.0
880 eqn(b_cur) = 4294964039.26
881 max_counter_value = 4294967295
882Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
883Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
884Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
885Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
886Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
887Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
888Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4.
889Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1.
890Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1.
891TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0.
892Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x0.
893Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4.
894Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1.
895Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0.
896Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0.
897Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0.
898Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0.
899Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0.
900Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
901Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
902Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1.
903Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3.
904Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_direct be 1.
905Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=0].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1)
906Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_tcam be 1.
907Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x0.
908Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x7. ( previous value = 0x0 OR new value = 0x7)
909Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x1.
910+------------------------------------------------------------------------
911Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 21.
912Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
913Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
914Configuring rams.match.merge.exact_match_delay_thread[copy_index=0].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
915Configuring rams.match.merge.exact_match_delay_thread[copy_index=1].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
916Configuring rams.match.merge.exact_match_delay_thread[copy_index=2].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
917Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
918Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
919Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
920Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
921Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
922Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
923Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
924Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x1.
925Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
926Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
927Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
928Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
929Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
930Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
931Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
932Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 16.
933Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 21.
934Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
935Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
936Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
937Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
938Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
939Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
940Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
941Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
942--------------------------------------------
943Configuration for unused statistics ALUs.
944Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
945Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
946Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
947+------------------------------------------------------------------------
948Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
949Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
950Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
951Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
952Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
953Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
954Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
955Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
956Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
957Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
958Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
959Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
960Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
961Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
962Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
963Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
964Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
965Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
966Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
967Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 1.
968Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 1.
969Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
970Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
971Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
972Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
973Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
974Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
975+------------------------------------------------------------------------
976Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 19.
977Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 2.
978Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
979Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
980Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
981Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
982Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
983Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
984Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1.
985Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2.
986Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
987Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
988Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
989Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
990
991+------------------------------------------------------------------------
992| MAU Stage 2
993+------------------------------------------------------------------------
994
995+------------------------------------------------------------------------
996| Working on table ecmp_group_table__action__ in stage 2 ---
997+------------------------------------------------------------------------
998--> Action Data Table ecmp_group_table__action__ with logical_table_id 0 that is reference type is 'direct'
999Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_select to be 4.
1000Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_enable to be 1.
1001
1002+------------------------------------------------------------------------
1003| Working on table ecmp_group_table in stage 2 ---
1004+------------------------------------------------------------------------
1005--> Hash Match Table ecmp_group_table with logical_table_id 0
1006Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
1007Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
1008Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
1009Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
1010Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
1011Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
1012Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=14].enabled_4bit_muxctl_select to be 0 (logical table id).
1013Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=14].enabled_4bit_muxctl_enable to be 1.
1014Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=14].enabled_4bit_muxctl_select to be 0 (logical table id).
1015Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=14].enabled_4bit_muxctl_enable to be 1.
1016Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=14].mau_action_instruction_adr_mask to be 0x0.
1017Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=14].mau_action_instruction_adr_default to be 0x40.
1018Configuring rams.match.merge.mau_action_instruction_adr_per_entry_en_mux_ctl[table_type_index=0][physical_result_bus=14].mau_action_instruction_adr_per_entry_en_mux_ctl to be 0x0.
1019Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
1020Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x41.
1021Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
1022Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
1023Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x30.
1024Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x30.
1025Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x0.
1026Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=0][result_bus_number=14].mau_immediate_data_mask to be 0xffff.
1027Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=0][result_bus_number=14].mau_stats_adr_mask to be 0xffffe.
1028Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=14].mau_stats_adr_default to be 0x80000.
1029Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
1030Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
1031Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 23.
1032Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
1033Configuring match input crossbar byte 0 to come from 16-bit PHV container 7.
1034 That PHV byte contains {ecmp_metadata.selector[7:0]}.
1035Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 23.
1036Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
1037Configuring match input crossbar byte 1 to come from 16-bit PHV container 7.
1038 That PHV byte contains {ecmp_metadata.selector[15:8]}.
1039Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 22.
1040Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_enable to be 1.
1041Configuring match input crossbar byte 2 to come from 16-bit PHV container 6.
1042 That PHV byte contains {ecmp_metadata.groupId[7:0]}.
1043Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 22.
1044Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_enable to be 1.
1045Configuring match input crossbar byte 3 to come from 16-bit PHV container 6.
1046 That PHV byte contains {ecmp_metadata.groupId[15:8]}.
1047Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0xc0. (previous value = 0x0 OR new value = 0xc0)
1048Configuring dp.xbar_hash.hash.hash_seed[output_bit=2].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1049Configuring dp.xbar_hash.hash.hash_seed[output_bit=3].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1050Configuring dp.xbar_hash.hash.hash_seed[output_bit=5].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1051Configuring dp.xbar_hash.hash.hash_seed[output_bit=7].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1052Configuring dp.xbar_hash.hash.hash_seed[output_bit=8].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1053Configuring dp.xbar_hash.hash.hash_seed[output_bit=10].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1054Configuring dp.xbar_hash.hash.hash_seed[output_bit=11].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1055Configuring dp.xbar_hash.hash.hash_seed[output_bit=15].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1056Configuring dp.xbar_hash.hash.hash_seed[output_bit=19].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1057Configuring dp.xbar_hash.hash.hash_seed[output_bit=20].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1058Configuring dp.xbar_hash.hash.hash_seed[output_bit=21].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1059Configuring dp.xbar_hash.hash.hash_seed[output_bit=23].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1060Configuring dp.xbar_hash.hash.hash_seed[output_bit=24].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1061Configuring dp.xbar_hash.hash.hash_seed[output_bit=25].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1062Configuring dp.xbar_hash.hash.hash_seed[output_bit=26].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1063Configuring dp.xbar_hash.hash.hash_seed[output_bit=28].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
1064Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
1065Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
1066Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x1.
1067Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte1 to be 0x84.
1068Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte0 to be 0xa9.
1069Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte1 to be 0xbe.
1070Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte0 to be 0x2.
1071Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte1 to be 0xa0.
1072Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=1].byte0 to be 0xd3.
1073Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=1].byte1 to be 0xc0.
1074Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte0 to be 0x4.
1075Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte1 to be 0xd4.
1076Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=2].byte0 to be 0xdc.
1077Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=2].byte1 to be 0x26.
1078Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte0 to be 0x8.
1079Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte1 to be 0x38.
1080Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=3].byte0 to be 0xd0.
1081Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=3].byte1 to be 0x78.
1082Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte0 to be 0x10.
1083Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte1 to be 0x8.
1084Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=4].byte0 to be 0xdc.
1085Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=4].byte1 to be 0xf4.
1086Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte0 to be 0x20.
1087Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte1 to be 0x24.
1088Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=5].byte0 to be 0xe.
1089Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=5].byte1 to be 0x90.
1090Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte0 to be 0x40.
1091Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte1 to be 0xf4.
1092Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=6].byte0 to be 0x3e.
1093Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=6].byte1 to be 0x8e.
1094Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte0 to be 0x80.
1095Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte1 to be 0x8c.
1096Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=7].byte0 to be 0x7d.
1097Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=7].byte1 to be 0x4.
1098Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=8].byte1 to be 0x79.
1099Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=8].byte0 to be 0x12.
1100Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=8].byte1 to be 0x40.
1101Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=9].byte1 to be 0xee.
1102Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=9].byte0 to be 0x30.
1103Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=9].byte1 to be 0x21.
1104Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=10].byte1 to be 0x7a.
1105Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=10].byte0 to be 0xf0.
1106Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=10].byte1 to be 0x7f.
1107Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=11].byte0 to be 0x1.
1108Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=11].byte1 to be 0x5c.
1109Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=11].byte0 to be 0x54.
1110Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=11].byte1 to be 0x14.
1111Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=12].byte0 to be 0x2.
1112Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=12].byte1 to be 0x94.
1113Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=12].byte0 to be 0x62.
1114Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=12].byte1 to be 0x63.
1115Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=13].byte0 to be 0x4.
1116Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=13].byte1 to be 0xb4.
1117Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=13].byte0 to be 0x47.
1118Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=13].byte1 to be 0x30.
1119Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=14].byte0 to be 0x8.
1120Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=14].byte1 to be 0xfc.
1121Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=14].byte0 to be 0xa5.
1122Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=14].byte1 to be 0xaa.
1123Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=15].byte0 to be 0x10.
1124Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=15].byte1 to be 0x48.
1125Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=15].byte0 to be 0xee.
1126Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=15].byte1 to be 0x84.
1127Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=16].byte0 to be 0x20.
1128Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=16].byte1 to be 0xb4.
1129Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=16].byte0 to be 0xf1.
1130Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=16].byte1 to be 0x93.
1131Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=17].byte0 to be 0x40.
1132Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=17].byte1 to be 0xb4.
1133Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=17].byte0 to be 0xd7.
1134Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=17].byte1 to be 0x19.
1135Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=18].byte0 to be 0x80.
1136Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=18].byte1 to be 0xec.
1137Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=18].byte0 to be 0x62.
1138Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=18].byte1 to be 0x13.
1139Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=19].byte1 to be 0x29.
1140Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=19].byte0 to be 0x12.
1141Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=19].byte1 to be 0x16.
1142Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=20].byte1 to be 0x45.
1143Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=20].byte0 to be 0xe0.
1144Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=20].byte1 to be 0xfe.
1145Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=21].byte1 to be 0x6.
1146Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=21].byte0 to be 0xd1.
1147Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=21].byte1 to be 0x65.
1148Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=22].byte0 to be 0x1.
1149Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=22].byte1 to be 0x84.
1150Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=22].byte0 to be 0x33.
1151Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=22].byte1 to be 0xa4.
1152Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=23].byte0 to be 0x2.
1153Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=23].byte1 to be 0xc.
1154Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=23].byte0 to be 0x7c.
1155Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=23].byte1 to be 0xe.
1156Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=24].byte0 to be 0x4.
1157Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=24].byte1 to be 0x4c.
1158Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=24].byte0 to be 0x8d.
1159Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=24].byte1 to be 0x6f.
1160Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=25].byte0 to be 0x8.
1161Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=25].byte1 to be 0x2c.
1162Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=25].byte0 to be 0xc2.
1163Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=25].byte1 to be 0xf9.
1164Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=26].byte0 to be 0x10.
1165Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=26].byte1 to be 0xd0.
1166Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=26].byte0 to be 0x17.
1167Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=26].byte1 to be 0xf9.
1168Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=27].byte0 to be 0x20.
1169Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=27].byte1 to be 0x8.
1170Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=27].byte0 to be 0x6c.
1171Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=27].byte1 to be 0x32.
1172Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=28].byte0 to be 0x40.
1173Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=28].byte1 to be 0x74.
1174Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=28].byte0 to be 0xdc.
1175Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=28].byte1 to be 0xb7.
1176Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=29].byte0 to be 0x80.
1177Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=29].byte1 to be 0xf8.
1178Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=29].byte0 to be 0x5c.
1179Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=29].byte1 to be 0xa.
1180Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
1181Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x4602.
1182Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1.
1183Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 1.
1184Micro instruction added in VLIW 0 for 16-bit position 2 for table ecmp_group_table.
1185 Assembled as 0x4602 (or decimal 17922)
1186 Micro Instruction deposit-field for PHV Container 130 has bit width 23
1187 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
1188 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
1189 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
1190 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
1191 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
1192 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
1193 Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
1194 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
1195
1196Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
1197Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=14].stats_adr_payload_shifter_en to be 1.
1198Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=14].action_instruction_adr_payload_shifter_en to be 1.
1199Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=14].immediate_data_payload_shifter_en to be 1.
1200Configuring rams.match.merge.mau_table_counter_ctl[half_index=0].mau_table_counter_ctl to be 0x2. (previous value = 0x0 OR new value = 0x2)
1201--> Hash Match Way 0
1202Packed entry for hash way 0 is
1203 [0] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 0))
1204 [1] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 1))
1205 [2] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 2))
1206 [3] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 3))
1207 [4] = (field_bit=4, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 4))
1208 [5] = (field_bit=5, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 5))
1209 [6] = (field_bit=6, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 6))
1210 [7] = (field_bit=7, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 7))
1211 [8] = (field_bit=8, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 8))
1212 [9] = (field_bit=9, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 9))
1213 [10] = (field_bit=10, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 10))
1214 [11] = (field_bit=11, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 11))
1215 [12] = (field_bit=12, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 12))
1216 [13] = (field_bit=13, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 13))
1217 [14] = (field_bit=14, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 14))
1218 [15] = (field_bit=15, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 15))
1219 [16] = (field_bit=0, hash_match_group_bit=16, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 0))
1220 [17] = (field_bit=1, hash_match_group_bit=17, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 1))
1221 [18] = (field_bit=2, hash_match_group_bit=18, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 2))
1222 [19] = (field_bit=3, hash_match_group_bit=19, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 3))
1223 [20] = (field_bit=4, hash_match_group_bit=20, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 4))
1224 [21] = (field_bit=5, hash_match_group_bit=21, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 5))
1225 [22] = (field_bit=6, hash_match_group_bit=22, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 6))
1226 [23] = (field_bit=7, hash_match_group_bit=23, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 7))
1227 [24] = (field_bit=8, hash_match_group_bit=24, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 8))
1228 [25] = (field_bit=9, hash_match_group_bit=25, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 9))
1229 [26] = (field_bit=10, hash_match_group_bit=26, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 10))
1230 [27] = (field_bit=11, hash_match_group_bit=27, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 11))
1231 [28] = (field_bit=12, hash_match_group_bit=28, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 12))
1232 [29] = (field_bit=13, hash_match_group_bit=29, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 13))
1233 [30] = (field_bit=14, hash_match_group_bit=30, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 14))
1234 [31] = (field_bit=15, hash_match_group_bit=31, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 15))
1235 [32] = None
1236 [33] = None
1237 [34] = (field_bit=10, hash_match_group_bit=10, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 10))
1238 [35] = (field_bit=11, hash_match_group_bit=11, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 11))
1239 [36] = (field_bit=12, hash_match_group_bit=12, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 12))
1240 [37] = (field_bit=13, hash_match_group_bit=13, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 13))
1241 [38] = (field_bit=14, hash_match_group_bit=14, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 14))
1242 [39] = (field_bit=15, hash_match_group_bit=15, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 15))
1243 [40] = None
1244 [41] = None
1245 [42] = None
1246 [43] = None
1247 [44] = None
1248 [45] = None
1249 [46] = None
1250 [47] = None
1251 [48] = None
1252 [49] = None
1253 [50] = None
1254 [51] = None
1255 [52] = None
1256 [53] = None
1257 [54] = None
1258 [55] = None
1259 [56] = None
1260 [57] = None
1261 [58] = None
1262 [59] = None
1263 [60] = None
1264 [61] = None
1265 [62] = None
1266 [63] = None
1267 [64] = None
1268 [65] = None
1269 [66] = None
1270 [67] = None
1271 [68] = None
1272 [69] = None
1273 [70] = None
1274 [71] = None
1275 [72] = None
1276 [73] = None
1277 [74] = None
1278 [75] = None
1279 [76] = None
1280 [77] = None
1281 [78] = None
1282 [79] = None
1283 [80] = None
1284 [81] = None
1285 [82] = None
1286 [83] = None
1287 [84] = None
1288 [85] = None
1289 [86] = None
1290 [87] = None
1291 [88] = None
1292 [89] = None
1293 [90] = None
1294 [91] = None
1295 [92] = None
1296 [93] = None
1297 [94] = None
1298 [95] = None
1299 [96] = None
1300 [97] = None
1301 [98] = None
1302 [99] = None
1303 [100] = None
1304 [101] = None
1305 [102] = None
1306 [103] = None
1307 [104] = None
1308 [105] = None
1309 [106] = None
1310 [107] = None
1311 [108] = None
1312 [109] = None
1313 [110] = None
1314 [111] = None
1315 [112] = None
1316 [113] = None
1317 [114] = None
1318 [115] = None
1319 [116] = None
1320 [117] = None
1321 [118] = None
1322 [119] = None
1323 [120] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 0))
1324 [121] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 1))
1325 [122] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 2))
1326 [123] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 3))
1327 [124] = None
1328 [125] = None
1329 [126] = None
1330 [127] = None
1331
1332Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=0].match_mask to be 0xffff.
1333Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=1].match_mask to be 0xffffff03.
1334Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=2].match_mask to be 0xffffffff.
1335Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=3].match_mask to be 0xf0ffffff.
1336Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_ram_write_data_mux_select to be 7.
1337Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_ram_read_data_mux_select to be 7.
1338Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_result_bus_select to be 1.
1339Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_entry_enable to be 1.
1340Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_ram_logical_table to be 0x0.
1341For entry_in_ram_word 0, should have vpn 0, with lower_two_bits of 0 and upper_vpn of 0
1342for entry_in_ram_word 0, use lsbs of 0
1343Configuring rams.array.row[row=7].ram[column=2].match_ram_vpn.match_ram_vpn0 to be 0.
1344Configuring rams.array.row[row=7].ram[column=2].match_ram_vpn.match_ram_vpn_lsbs to be 0x0.
1345version valid nibbles are : [30]
1346Configuring rams.array.row[row=7].ram[column=2].match_nibble_s0q1_enable.match_nibble_s0q1_enable to be 0xbfffffff.
1347Configuring rams.array.row[row=7].ram[column=2].match_nibble_s1q0_enable.match_nibble_s1q0_enable to be 0xffffffff.
1348Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=0].mask_bytes_0_to_13 to be 0x3fe3.
1349Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=0].mask_nibbles_28_to_31 to be 0xb.
1350Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=1].mask_bytes_0_to_13 to be 0x3fff.
1351Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=1].mask_nibbles_28_to_31 to be 0xf.
1352Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=2].mask_bytes_0_to_13 to be 0x3fff.
1353Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=2].mask_nibbles_28_to_31 to be 0xf.
1354Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=3].mask_bytes_0_to_13 to be 0x3fff.
1355Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=3].mask_nibbles_28_to_31 to be 0xf.
1356Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=4].mask_bytes_0_to_13 to be 0x3fff.
1357Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=4].mask_nibbles_28_to_31 to be 0xf.
1358Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1359Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1360Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1361Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1362Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1363Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1364Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1365Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1366Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1367Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1368Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1369Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1370Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1371Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1372Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1373Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1374Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1375Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1376Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1377Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1378Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1379Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1380Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1381Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1382Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1383Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1384Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
1385Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
1386Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_thread to be 0.
1387Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=2].exactmatch_bank_enable_bank_mask to be 0x0.
1388Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=2].exactmatch_bank_enable_bank_id to be 0x0.
1389Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=2].exactmatch_bank_enable_inp_sel to be 1.
1390Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
1391Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
1392Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=2].enabled_4bit_muxctl_select to be 0.
1393Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=2].enabled_4bit_muxctl_enable to be 1.
1394Configuring rams.match.merge.mau_action_instruction_adr_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_action_instruction_adr_exact_shiftcount to be 0.
1395Configuring rams.match.merge.mau_immediate_data_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_immediate_data_exact_shiftcount to be 0.
1396Configuring rams.match.merge.mau_stats_adr_exact_shiftcount[result_bus_number = 14][entry_in_ram_word=0].mau_stats_adr_exact_shiftcount to be 0x46.
1397Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_type to be 1.
1398Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_logical_table to be 0.
1399Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_ingress to be 1.
1400Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_enable to be 1.
1401Configuring rams.array.row[row=7].emm_ecc_error_uram_ctl[direction=0].emm_ecc_error_uram_ctl to be select of 0x1. (previous value = 0x0 OR new value = 0x1)
1402In Ram Word 0:
1403 wide entry 0 occupied ram word entry 0
1404Configuring rams.match.merge.col[col_number=2].row_action_nxtable_bus_drive[row_number=7].row_action_nxtable_bus_drive to be 1.
1405Configuring rams.match.merge.col[col_number=2].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_select to be 14 (hit signal to output on).
1406Configuring rams.match.merge.col[col_number=2].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1.
1407--> Hash Match Way 1
1408Packed entry for hash way 1 is
1409 [0] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 0))
1410 [1] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 1))
1411 [2] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 2))
1412 [3] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 3))
1413 [4] = (field_bit=4, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 4))
1414 [5] = (field_bit=5, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 5))
1415 [6] = (field_bit=6, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 6))
1416 [7] = (field_bit=7, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 7))
1417 [8] = (field_bit=8, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 8))
1418 [9] = (field_bit=9, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 9))
1419 [10] = (field_bit=10, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 10))
1420 [11] = (field_bit=11, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 11))
1421 [12] = (field_bit=12, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 12))
1422 [13] = (field_bit=13, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 13))
1423 [14] = (field_bit=14, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 14))
1424 [15] = (field_bit=15, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 15))
1425 [16] = (field_bit=0, hash_match_group_bit=16, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 0))
1426 [17] = (field_bit=1, hash_match_group_bit=17, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 1))
1427 [18] = (field_bit=2, hash_match_group_bit=18, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 2))
1428 [19] = (field_bit=3, hash_match_group_bit=19, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 3))
1429 [20] = (field_bit=4, hash_match_group_bit=20, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 4))
1430 [21] = (field_bit=5, hash_match_group_bit=21, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 5))
1431 [22] = (field_bit=6, hash_match_group_bit=22, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 6))
1432 [23] = (field_bit=7, hash_match_group_bit=23, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 7))
1433 [24] = (field_bit=8, hash_match_group_bit=24, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 8))
1434 [25] = (field_bit=9, hash_match_group_bit=25, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 9))
1435 [26] = (field_bit=10, hash_match_group_bit=26, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 10))
1436 [27] = (field_bit=11, hash_match_group_bit=27, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 11))
1437 [28] = (field_bit=12, hash_match_group_bit=28, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 12))
1438 [29] = (field_bit=13, hash_match_group_bit=29, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 13))
1439 [30] = (field_bit=14, hash_match_group_bit=30, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 14))
1440 [31] = (field_bit=15, hash_match_group_bit=31, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 15))
1441 [32] = None
1442 [33] = None
1443 [34] = (field_bit=10, hash_match_group_bit=10, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 10))
1444 [35] = (field_bit=11, hash_match_group_bit=11, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 11))
1445 [36] = (field_bit=12, hash_match_group_bit=12, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 12))
1446 [37] = (field_bit=13, hash_match_group_bit=13, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 13))
1447 [38] = (field_bit=14, hash_match_group_bit=14, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 14))
1448 [39] = (field_bit=15, hash_match_group_bit=15, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 15))
1449 [40] = None
1450 [41] = None
1451 [42] = None
1452 [43] = None
1453 [44] = None
1454 [45] = None
1455 [46] = None
1456 [47] = None
1457 [48] = None
1458 [49] = None
1459 [50] = None
1460 [51] = None
1461 [52] = None
1462 [53] = None
1463 [54] = None
1464 [55] = None
1465 [56] = None
1466 [57] = None
1467 [58] = None
1468 [59] = None
1469 [60] = None
1470 [61] = None
1471 [62] = None
1472 [63] = None
1473 [64] = None
1474 [65] = None
1475 [66] = None
1476 [67] = None
1477 [68] = None
1478 [69] = None
1479 [70] = None
1480 [71] = None
1481 [72] = None
1482 [73] = None
1483 [74] = None
1484 [75] = None
1485 [76] = None
1486 [77] = None
1487 [78] = None
1488 [79] = None
1489 [80] = None
1490 [81] = None
1491 [82] = None
1492 [83] = None
1493 [84] = None
1494 [85] = None
1495 [86] = None
1496 [87] = None
1497 [88] = None
1498 [89] = None
1499 [90] = None
1500 [91] = None
1501 [92] = None
1502 [93] = None
1503 [94] = None
1504 [95] = None
1505 [96] = None
1506 [97] = None
1507 [98] = None
1508 [99] = None
1509 [100] = None
1510 [101] = None
1511 [102] = None
1512 [103] = None
1513 [104] = None
1514 [105] = None
1515 [106] = None
1516 [107] = None
1517 [108] = None
1518 [109] = None
1519 [110] = None
1520 [111] = None
1521 [112] = None
1522 [113] = None
1523 [114] = None
1524 [115] = None
1525 [116] = None
1526 [117] = None
1527 [118] = None
1528 [119] = None
1529 [120] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 0))
1530 [121] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 1))
1531 [122] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 2))
1532 [123] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 3))
1533 [124] = None
1534 [125] = None
1535 [126] = None
1536 [127] = None
1537
1538Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=0].match_mask to be 0xffff.
1539Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=1].match_mask to be 0xffffff03.
1540Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=2].match_mask to be 0xffffffff.
1541Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=3].match_mask to be 0xf0ffffff.
1542Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_ram_write_data_mux_select to be 7.
1543Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_ram_read_data_mux_select to be 7.
1544Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_result_bus_select to be 1.
1545Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_entry_enable to be 1.
1546Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_ram_logical_table to be 0x0.
1547For entry_in_ram_word 0, should have vpn 1, with lower_two_bits of 1 and upper_vpn of 0
1548for entry_in_ram_word 0, use lsbs of 1
1549Configuring rams.array.row[row=7].ram[column=3].match_ram_vpn.match_ram_vpn0 to be 0.
1550Configuring rams.array.row[row=7].ram[column=3].match_ram_vpn.match_ram_vpn_lsbs to be 0x1.
1551version valid nibbles are : [30]
1552Configuring rams.array.row[row=7].ram[column=3].match_nibble_s0q1_enable.match_nibble_s0q1_enable to be 0xbfffffff.
1553Configuring rams.array.row[row=7].ram[column=3].match_nibble_s1q0_enable.match_nibble_s1q0_enable to be 0xffffffff.
1554Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=0].mask_bytes_0_to_13 to be 0x3fe3.
1555Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=0].mask_nibbles_28_to_31 to be 0xb.
1556Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=1].mask_bytes_0_to_13 to be 0x3fff.
1557Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=1].mask_nibbles_28_to_31 to be 0xf.
1558Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=2].mask_bytes_0_to_13 to be 0x3fff.
1559Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=2].mask_nibbles_28_to_31 to be 0xf.
1560Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=3].mask_bytes_0_to_13 to be 0x3fff.
1561Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=3].mask_nibbles_28_to_31 to be 0xf.
1562Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=4].mask_bytes_0_to_13 to be 0x3fff.
1563Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=4].mask_nibbles_28_to_31 to be 0xf.
1564Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1565Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1566Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1567Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1568Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1569Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1570Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1571Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1572Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1573Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1574Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1575Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1576Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1577Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1578Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1579Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1580Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1581Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1582Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1583Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1584Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1585Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1586Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1587Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1588Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1589Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1590Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
1591Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
1592Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_thread to be 0.
1593Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=3].exactmatch_bank_enable_bank_mask to be 0x0.
1594Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=3].exactmatch_bank_enable_bank_id to be 0x0.
1595Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=3].exactmatch_bank_enable_inp_sel to be 1.
1596Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
1597Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
1598Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=3].enabled_4bit_muxctl_select to be 1.
1599Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=3].enabled_4bit_muxctl_enable to be 1.
1600Configuring rams.match.merge.mau_action_instruction_adr_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_action_instruction_adr_exact_shiftcount to be 0.
1601Configuring rams.match.merge.mau_immediate_data_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_immediate_data_exact_shiftcount to be 0.
1602Configuring rams.match.merge.mau_stats_adr_exact_shiftcount[result_bus_number = 14][entry_in_ram_word=0].mau_stats_adr_exact_shiftcount to be 0x46.
1603Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_type to be 1.
1604Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_logical_table to be 0.
1605Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_ingress to be 1.
1606Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_enable to be 1.
1607Configuring rams.array.row[row=7].emm_ecc_error_uram_ctl[direction=0].emm_ecc_error_uram_ctl to be select of 0x3. (previous value = 0x1 OR new value = 0x2)
1608In Ram Word 0:
1609 wide entry 0 occupied ram word entry 0
1610Configuring rams.match.merge.col[col_number=3].row_action_nxtable_bus_drive[row_number=7].row_action_nxtable_bus_drive to be 1.
1611Configuring rams.match.merge.col[col_number=3].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_select to be 14 (hit signal to output on).
1612Configuring rams.match.merge.col[col_number=3].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1.
1613--> Hash Match Way 2
1614Packed entry for hash way 2 is
1615 [0] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 0))
1616 [1] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 1))
1617 [2] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 2))
1618 [3] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 3))
1619 [4] = (field_bit=4, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 4))
1620 [5] = (field_bit=5, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 5))
1621 [6] = (field_bit=6, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 6))
1622 [7] = (field_bit=7, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 7))
1623 [8] = (field_bit=8, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 8))
1624 [9] = (field_bit=9, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 9))
1625 [10] = (field_bit=10, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 10))
1626 [11] = (field_bit=11, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 11))
1627 [12] = (field_bit=12, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 12))
1628 [13] = (field_bit=13, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 13))
1629 [14] = (field_bit=14, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 14))
1630 [15] = (field_bit=15, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 15))
1631 [16] = (field_bit=0, hash_match_group_bit=16, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 0))
1632 [17] = (field_bit=1, hash_match_group_bit=17, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 1))
1633 [18] = (field_bit=2, hash_match_group_bit=18, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 2))
1634 [19] = (field_bit=3, hash_match_group_bit=19, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 3))
1635 [20] = (field_bit=4, hash_match_group_bit=20, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 4))
1636 [21] = (field_bit=5, hash_match_group_bit=21, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 5))
1637 [22] = (field_bit=6, hash_match_group_bit=22, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 6))
1638 [23] = (field_bit=7, hash_match_group_bit=23, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 7))
1639 [24] = (field_bit=8, hash_match_group_bit=24, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 8))
1640 [25] = (field_bit=9, hash_match_group_bit=25, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 9))
1641 [26] = (field_bit=10, hash_match_group_bit=26, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 10))
1642 [27] = (field_bit=11, hash_match_group_bit=27, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 11))
1643 [28] = (field_bit=12, hash_match_group_bit=28, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 12))
1644 [29] = (field_bit=13, hash_match_group_bit=29, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 13))
1645 [30] = (field_bit=14, hash_match_group_bit=30, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 14))
1646 [31] = (field_bit=15, hash_match_group_bit=31, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.groupId', 15))
1647 [32] = None
1648 [33] = None
1649 [34] = (field_bit=10, hash_match_group_bit=10, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 10))
1650 [35] = (field_bit=11, hash_match_group_bit=11, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 11))
1651 [36] = (field_bit=12, hash_match_group_bit=12, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 12))
1652 [37] = (field_bit=13, hash_match_group_bit=13, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 13))
1653 [38] = (field_bit=14, hash_match_group_bit=14, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 14))
1654 [39] = (field_bit=15, hash_match_group_bit=15, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 15))
1655 [40] = None
1656 [41] = None
1657 [42] = None
1658 [43] = None
1659 [44] = None
1660 [45] = None
1661 [46] = None
1662 [47] = None
1663 [48] = None
1664 [49] = None
1665 [50] = None
1666 [51] = None
1667 [52] = None
1668 [53] = None
1669 [54] = None
1670 [55] = None
1671 [56] = None
1672 [57] = None
1673 [58] = None
1674 [59] = None
1675 [60] = None
1676 [61] = None
1677 [62] = None
1678 [63] = None
1679 [64] = None
1680 [65] = None
1681 [66] = None
1682 [67] = None
1683 [68] = None
1684 [69] = None
1685 [70] = None
1686 [71] = None
1687 [72] = None
1688 [73] = None
1689 [74] = None
1690 [75] = None
1691 [76] = None
1692 [77] = None
1693 [78] = None
1694 [79] = None
1695 [80] = None
1696 [81] = None
1697 [82] = None
1698 [83] = None
1699 [84] = None
1700 [85] = None
1701 [86] = None
1702 [87] = None
1703 [88] = None
1704 [89] = None
1705 [90] = None
1706 [91] = None
1707 [92] = None
1708 [93] = None
1709 [94] = None
1710 [95] = None
1711 [96] = None
1712 [97] = None
1713 [98] = None
1714 [99] = None
1715 [100] = None
1716 [101] = None
1717 [102] = None
1718 [103] = None
1719 [104] = None
1720 [105] = None
1721 [106] = None
1722 [107] = None
1723 [108] = None
1724 [109] = None
1725 [110] = None
1726 [111] = None
1727 [112] = None
1728 [113] = None
1729 [114] = None
1730 [115] = None
1731 [116] = None
1732 [117] = None
1733 [118] = None
1734 [119] = None
1735 [120] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 0))
1736 [121] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 1))
1737 [122] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 2))
1738 [123] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 3))
1739 [124] = None
1740 [125] = None
1741 [126] = None
1742 [127] = None
1743
1744Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=0].match_mask to be 0xffff.
1745Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=1].match_mask to be 0xffffff03.
1746Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=2].match_mask to be 0xffffffff.
1747Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=3].match_mask to be 0xf0ffffff.
1748Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_ram_write_data_mux_select to be 7.
1749Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_ram_read_data_mux_select to be 7.
1750Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_result_bus_select to be 1.
1751Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_entry_enable to be 1.
1752Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_ram_logical_table to be 0x0.
1753For entry_in_ram_word 0, should have vpn 2, with lower_two_bits of 2 and upper_vpn of 0
1754for entry_in_ram_word 0, use lsbs of 2
1755Configuring rams.array.row[row=7].ram[column=4].match_ram_vpn.match_ram_vpn0 to be 0.
1756Configuring rams.array.row[row=7].ram[column=4].match_ram_vpn.match_ram_vpn_lsbs to be 0x2.
1757version valid nibbles are : [30]
1758Configuring rams.array.row[row=7].ram[column=4].match_nibble_s0q1_enable.match_nibble_s0q1_enable to be 0xbfffffff.
1759Configuring rams.array.row[row=7].ram[column=4].match_nibble_s1q0_enable.match_nibble_s1q0_enable to be 0xffffffff.
1760Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=0].mask_bytes_0_to_13 to be 0x3fe3.
1761Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=0].mask_nibbles_28_to_31 to be 0xb.
1762Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=1].mask_bytes_0_to_13 to be 0x3fff.
1763Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=1].mask_nibbles_28_to_31 to be 0xf.
1764Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=2].mask_bytes_0_to_13 to be 0x3fff.
1765Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=2].mask_nibbles_28_to_31 to be 0xf.
1766Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=3].mask_bytes_0_to_13 to be 0x3fff.
1767Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=3].mask_nibbles_28_to_31 to be 0xf.
1768Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=4].mask_bytes_0_to_13 to be 0x3fff.
1769Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=4].mask_nibbles_28_to_31 to be 0xf.
1770Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1771Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1772Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1773Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1774Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1775Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1776Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1777Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1778Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1779Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1780Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1781Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1782Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1783Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1784Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1785Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1786Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1787Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1788Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1789Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1790Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1791Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1792Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1793Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1794Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1795Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1796Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
1797Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
1798Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_thread to be 0.
1799Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=4].exactmatch_bank_enable_bank_mask to be 0x0.
1800Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=4].exactmatch_bank_enable_bank_id to be 0x0.
1801Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=4].exactmatch_bank_enable_inp_sel to be 1.
1802Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
1803Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
1804Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=4].enabled_4bit_muxctl_select to be 2.
1805Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=4].enabled_4bit_muxctl_enable to be 1.
1806Configuring rams.match.merge.mau_action_instruction_adr_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_action_instruction_adr_exact_shiftcount to be 0.
1807Configuring rams.match.merge.mau_immediate_data_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_immediate_data_exact_shiftcount to be 0.
1808Configuring rams.match.merge.mau_stats_adr_exact_shiftcount[result_bus_number = 14][entry_in_ram_word=0].mau_stats_adr_exact_shiftcount to be 0x46.
1809Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_type to be 1.
1810Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_logical_table to be 0.
1811Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_ingress to be 1.
1812Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_enable to be 1.
1813Configuring rams.array.row[row=7].emm_ecc_error_uram_ctl[direction=0].emm_ecc_error_uram_ctl to be select of 0x7. (previous value = 0x3 OR new value = 0x4)
1814In Ram Word 0:
1815 wide entry 0 occupied ram word entry 0
1816Configuring rams.match.merge.col[col_number=4].row_action_nxtable_bus_drive[row_number=7].row_action_nxtable_bus_drive to be 1.
1817Configuring rams.match.merge.col[col_number=4].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_select to be 14 (hit signal to output on).
1818Configuring rams.match.merge.col[col_number=4].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1.
1819
1820+------------------------------------------------------------------------
1821| Working on table ecmp_group_table_counter in stage 2 ---
1822+------------------------------------------------------------------------
1823Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
1824Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
1825Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
1826Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
1827Note that unitram_vpn does not need to be programmed for synthetic two port rams.
1828Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0.
1829Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
1830Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
1831Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
1832Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
1833Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
1834Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
1835Note that unitram_vpn does not need to be programmed for synthetic two port rams.
1836Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0.
1837Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
1838Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
1839Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
1840Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
1841Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
1842Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
1843Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
1844Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
1845Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
1846Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
1847Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
1848Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
1849Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
1850Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
1851Stat table ecmp_group_table_counter is used by match table ecmp_group_table.
1852Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8)
1853Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
1854Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
1855Note that map ram vpn does not need to be configured for synthetic two port map rams.
1856Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
1857Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
1858Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
1859Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
1860Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
1861Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
1862Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
1863Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
1864Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0.
1865Note that map ram vpn does not need to be configured for synthetic two port map rams.
1866Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
1867Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
1868Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
1869Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
1870Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
1871Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
1872Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
1873For counter width 32 and N = 4096
1874 number iterations = 32
1875 b_cur = 379488672.0
1876 eqn(b_cur) = 4294964039.26
1877 max_counter_value = 4294967295
1878Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
1879Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
1880Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
1881Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
1882Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
1883Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
1884Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4.
1885Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1.
1886Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1.
1887TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0.
1888Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x0.
1889Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4.
1890Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1.
1891Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0.
1892Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0.
1893Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0.
1894Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0.
1895Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0.
1896Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
1897Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
1898Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1.
1899Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3.
1900Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_direct be 1.
1901Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=0].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1)
1902Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x0.
1903Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x7. ( previous value = 0x0 OR new value = 0x7)
1904Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x1.
1905+------------------------------------------------------------------------
1906Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19.
1907Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
1908Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
1909Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1910Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1911Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1912Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1913Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1914Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1915Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1916Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1917Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x1.
1918Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1919Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1920Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1921Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x40.
1922Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1923Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1924Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1925Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
1926Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1927Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1928Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
1929Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1930Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1931Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1932Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1933Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1934--------------------------------------------
1935Configuration for unused statistics ALUs.
1936Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1937Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1938Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1939+------------------------------------------------------------------------
1940Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
1941Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
1942Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
1943Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
1944Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
1945Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
1946Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
1947Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
1948Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
1949Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
1950Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
1951Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
1952Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
1953Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
1954Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
1955Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1956Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1957Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1958Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1959Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1960Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1961Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1962Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1963Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1964Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1965Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1966Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1967+------------------------------------------------------------------------
1968Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1969Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1970Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
1971Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
1972Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1973Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1974Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1975Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
1976Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1.
1977Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2.
1978Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1979Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1980Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1981Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1982
1983+------------------------------------------------------------------------
1984| MAU Stage 3
1985+------------------------------------------------------------------------
1986
1987+------------------------------------------------------------------------
1988| Working on table _condition_2 in stage 3 ---
1989+------------------------------------------------------------------------
1990--> Stage Gateway Table for condition _condition_2 in stage 3
1991Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
1992Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
1993Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
1994Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
1995Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
1996Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
1997Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
1998Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
1999Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 18.
2000Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
2001Configuring match input crossbar byte 0 to come from 16-bit PHV container 2.
2002 That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
2003Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 18.
2004Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
2005Configuring match input crossbar byte 1 to come from 16-bit PHV container 2.
2006 That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
2007Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
2008Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
2009Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
2010Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte1 to be 0x1.
2011Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=41].byte0 to be 0x1.
2012Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=42].byte0 to be 0x2.
2013Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=43].byte0 to be 0x4.
2014Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=44].byte0 to be 0x8.
2015Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=45].byte0 to be 0x10.
2016Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=46].byte0 to be 0x20.
2017Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=47].byte0 to be 0x40.
2018Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=48].byte0 to be 0x80.
2019Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
2020Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
2021Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
2022Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
2023Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
2024Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
2025Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
2026Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
2027Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
2028Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0
2029Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0
2030Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
2031Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
2032Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
2033Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
2034Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
2035Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_mode to be 0x2
2036Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff
2037Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff3f
2038Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8
2039Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x31
2040Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid0 to be 0x3
2041Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid1 to be 0x3
2042Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][0] to be 0xffffffff
2043Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][1] to be 0xffffffff
2044Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xffffff
2045Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff7fff
2046Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xc (previous value 0x8 OR new value 0x4)
2047Configuring rams.match.merge.gateway_next_table_lut[0][2] to be 0x31
2048Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid0 to be 0x3
2049Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid1 to be 0x3
2050Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][0] to be 0xffffffff
2051Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][1] to be 0xffffffff
2052Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0xffff
2053Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][1] to be 0xffff
2054Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xe (previous value 0xc OR new value 0x2)
2055Configuring rams.match.merge.gateway_next_table_lut[0][1] to be 0x31
2056Configuring rams.match.merge.gateway_en.gateway_en to be 0x1
2057Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf
2058Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1
2059allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
2060Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x0
2061Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1
2062Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2
2063Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x1
2064Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0
2065Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x1
2066Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0
2067Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff
2068Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff
2069
2070+------------------------------------------------------------------------
2071| Working on table ingress_port_count_table__action__ in stage 3 ---
2072+------------------------------------------------------------------------
2073--> Action Data Table ingress_port_count_table__action__ with logical_table_id 0 that is reference type is 'direct'
2074
2075+------------------------------------------------------------------------
2076| Working on table ingress_port_count_table in stage 3 ---
2077+------------------------------------------------------------------------
2078--> Match Table with no key ingress_port_count_table with logical_table_id 0
2079allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
2080Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
2081Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
2082Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
2083Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
2084Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
2085Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
2086Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id).
2087Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
2088Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id).
2089Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
2090Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x0.
2091Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x1.
2092Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0xff.
2093Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=1].mau_stats_adr_default to be 0x0.
2094Configuring rams.match.merge.mau_stats_adr_per_entry_en_mux_ctl[table_type_index=0][result_bus_number=1].mau_stats_adr_per_entry_en_mux_ctl to be 0x7.
2095Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
2096Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2000.
2097Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
2098Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].stats_adr_payload_shifter_en to be 1.
2099Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
2100
2101+------------------------------------------------------------------------
2102| Working on table egress_port_count_table__action__ in stage 3 ---
2103+------------------------------------------------------------------------
2104--> Action Data Table egress_port_count_table__action__ with logical_table_id 1 that is reference type is 'direct'
2105
2106+------------------------------------------------------------------------
2107| Working on table egress_port_count_table in stage 3 ---
2108+------------------------------------------------------------------------
2109--> Match Table with no key egress_port_count_table with logical_table_id 1
2110allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
2111Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
2112Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
2113Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
2114Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
2115Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
2116Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
2117Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id).
2118Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
2119Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id).
2120Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
2121Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_default to be 0x40.
2122Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x0.
2123Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0xff.
2124Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0xff.
2125Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=0].mau_stats_adr_default to be 0x80000.
2126Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2).
2127Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x40.
2128Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
2129--> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 3
2130Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
2131Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
2132Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
2133Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
2134Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
2135Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
2136Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x0)
2137Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
2138Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x0)
2139Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
2140Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
2141Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
2142Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
2143Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
2144Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
2145Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1
2146Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0
2147Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
2148Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
2149Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
2150Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff
2151Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff
2152Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff
2153Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff
2154Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8
2155Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0xff
2156Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10)
2157Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0xff
2158Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2)
2159Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe
2160Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1
2161allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
2162Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_logical_select to be 0x1
2163Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_inhibit_enable to be 0x1
2164Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x3 (previous value 0x2 OR new value 0x1)
2165Configuring rams.match.merge.gateway_payload_data[0][0][0][0].gateway_payload_data to be 0x0
2166Configuring rams.match.merge.gateway_payload_data[0][0][1][0].gateway_payload_data to be 0x0
2167Configuring rams.match.merge.gateway_payload_data[0][0][0][1].gateway_payload_data to be 0x0
2168Configuring rams.match.merge.gateway_payload_data[0][0][1][1].gateway_payload_data to be 0x0
2169Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff
2170Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff
2171Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=0].action_instruction_adr_payload_shifter_en to be 1.
2172
2173+------------------------------------------------------------------------
2174| Working on table ingress_port_counter in stage 3 ---
2175+------------------------------------------------------------------------
2176Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
2177Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
2178Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
2179Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
2180Note that unitram_vpn does not need to be programmed for synthetic two port rams.
2181Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0.
2182Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
2183Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
2184Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
2185Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
2186Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
2187Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
2188Note that unitram_vpn does not need to be programmed for synthetic two port rams.
2189Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0.
2190Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
2191Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
2192Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
2193Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
2194Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
2195Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
2196Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
2197Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1.
2198Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
2199Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
2200Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
2201Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
2202Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
2203Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1.
2204Stat table ingress_port_counter is used by match table ingress_port_count_table.
2205Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x4. (previous value = 0x0 OR new value =0x4)
2206Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
2207Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
2208Note that map ram vpn does not need to be configured for synthetic two port map rams.
2209Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
2210Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
2211Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
2212Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
2213Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
2214Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
2215Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
2216Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
2217Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0.
2218Note that map ram vpn does not need to be configured for synthetic two port map rams.
2219Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
2220Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
2221Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
2222Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
2223Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
2224Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
2225Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
2226For counter width 32 and N = 4096
2227 number iterations = 32
2228 b_cur = 379488672.0
2229 eqn(b_cur) = 4294964039.26
2230 max_counter_value = 4294967295
2231Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
2232Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
2233Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
2234Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
2235Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
2236Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
2237Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_entries_per_word to be 4.
2238Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_process_packets to be 1.
2239Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.lrt_enable to be 1.
2240TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_alu_error_enable to be 0.
2241Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0x0.
2242Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4.
2243Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1.
2244Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0.
2245Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0.
2246Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=2].stats_lrt_fsm_sweep_size to be 0x0.
2247Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=2].stats_lrt_fsm_sweep_offset to be 0x0.
2248Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=2].stats_lrt_sweep_adr to be 0x0.
2249Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
2250Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
2251Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=2].packet_action_at_headertime be 1.
2252Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_size be 3.
2253Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_lt be 0x0.
2254Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x6. ( previous value = 0x0 OR new value = 0x6)
2255Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=2].mau_ad_stats_virt_lt be 0x1.
2256
2257+------------------------------------------------------------------------
2258| Working on table egress_port_counter in stage 3 ---
2259+------------------------------------------------------------------------
2260Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
2261Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
2262Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
2263Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
2264Note that unitram_vpn does not need to be programmed for synthetic two port rams.
2265Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 1.
2266Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
2267Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
2268Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
2269Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
2270Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
2271Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
2272Note that unitram_vpn does not need to be programmed for synthetic two port rams.
2273Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 1.
2274Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
2275Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
2276Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
2277Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
2278Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
2279Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
2280Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
2281Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
2282Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
2283Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
2284Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
2285Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
2286Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
2287Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
2288Stat table egress_port_counter is used by match table egress_port_count_table.
2289Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=1].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8)
2290Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
2291Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 1.
2292Note that map ram vpn does not need to be configured for synthetic two port map rams.
2293Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
2294Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
2295Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
2296Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
2297Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
2298Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
2299Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
2300Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
2301Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 1.
2302Note that map ram vpn does not need to be configured for synthetic two port map rams.
2303Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
2304Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
2305Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
2306Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
2307Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
2308Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
2309Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
2310For counter width 32 and N = 4096
2311 number iterations = 32
2312 b_cur = 379488672.0
2313 eqn(b_cur) = 4294964039.26
2314 max_counter_value = 4294967295
2315Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
2316Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
2317Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
2318Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
2319Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
2320Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
2321Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4.
2322Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1.
2323Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1.
2324TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0.
2325Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x1.
2326Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_entries_per_word be 0x4.
2327Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_has_packets be 0x1.
2328Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_offset be 0x0.
2329Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_size be 0x0.
2330Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0.
2331Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0.
2332Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0.
2333Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
2334Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
2335Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1.
2336Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3.
2337Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x1.
2338Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=3].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x3e. ( previous value = 0x6 OR new value = 0x38)
2339Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x2.
2340+------------------------------------------------------------------------
2341Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19.
2342Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
2343Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
2344Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2345Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2346Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2347Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2348Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2349Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2350Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2351Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2352Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x3.
2353Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2354Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2355Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x3.
2356Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2357Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2358Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2359Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2360Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2361Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2362Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2363Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2364Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2365Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2366Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2367Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2368Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2369--------------------------------------------
2370Configuration for unused statistics ALUs.
2371Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2372Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2373+------------------------------------------------------------------------
2374Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2375Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2376Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
2377Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2378Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2379Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
2380Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2381Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2382Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
2383Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
2384Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
2385Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
2386Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
2387Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
2388Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
2389Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2390Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2391Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2392Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2393Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2394Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2395Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2396Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2397Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2398Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2399Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2400Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2401+------------------------------------------------------------------------
2402Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2403Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2404Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
2405Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2406Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2407Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2408Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2409Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2410Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1.
2411Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2.
2412Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2413Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2414Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2415Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2416
2417+------------------------------------------------------------------------
2418| MAU Stage 4
2419+------------------------------------------------------------------------
2420+------------------------------------------------------------------------
2421Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2422Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2423Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2424Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2425Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2426Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2427Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2428Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2429Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2430Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2431Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2432Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2433Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2434Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2435Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2436Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2437Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2438Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2439Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2440Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2441Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2442Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2443Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2444Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2445Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2446Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2447Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2448Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2449--------------------------------------------
2450Configuration for unused statistics ALUs.
2451Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2452Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2453Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2454Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2455+------------------------------------------------------------------------
2456Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2457Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2458Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
2459Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2460Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2461Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
2462Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2463Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2464Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
2465Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
2466Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
2467Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
2468Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
2469Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
2470Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
2471Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2472Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2473Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2474Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2475Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2476Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2477Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2478Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2479Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2480Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2481Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2482Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2483+------------------------------------------------------------------------
2484Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2485Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2486Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2487Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2488Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2489Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2490Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2491Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2492Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2493Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2494Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2495Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2496Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2497Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2498
2499+------------------------------------------------------------------------
2500| MAU Stage 5
2501+------------------------------------------------------------------------
2502+------------------------------------------------------------------------
2503Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2504Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2505Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2506Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2507Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2508Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2509Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2510Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2511Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2512Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2513Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2514Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2515Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2516Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2517Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2518Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2519Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2520Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2521Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2522Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
2523Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2524Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2525Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19.
2526Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2527Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2528Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2529Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2530Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2531--------------------------------------------
2532Configuration for unused statistics ALUs.
2533Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2534Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2535Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2536Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2537+------------------------------------------------------------------------
2538Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2539Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2540Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
2541Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2542Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2543Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
2544Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2545Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2546Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
2547Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
2548Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
2549Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
2550Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
2551Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
2552Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
2553Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2554Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2555Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2556Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2557Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2558Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2559Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2560Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2561Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2562Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2563Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2564Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2565+------------------------------------------------------------------------
2566Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2567Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2568Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2569Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
2570Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2571Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2572Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2573Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0.
2574Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2575Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2576Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2577Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2578Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2579Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2580
2581+------------------------------------------------------------------------
2582| MAU Stage 6
2583+------------------------------------------------------------------------
2584+------------------------------------------------------------------------
2585Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19.
2586Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
2587Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
2588Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 19.
2589Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 9.
2590Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 3.
2591Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2592Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2593Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2594Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2595Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2596Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2597Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2598Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2599Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2600Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2601Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2602Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2603Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2604Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2605Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2606Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2607Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2608Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2609Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2610Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2611Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2612Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2613--------------------------------------------
2614Configuration for unused statistics ALUs.
2615Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2616Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2617Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2618Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2619+------------------------------------------------------------------------
2620Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2621Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2622Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
2623Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2624Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2625Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
2626Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2627Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2628Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
2629Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
2630Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
2631Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
2632Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
2633Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
2634Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
2635Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2636Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2637Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2638Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2639Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2640Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2641Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2642Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2643Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2644Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2645Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2646Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2647+------------------------------------------------------------------------
2648Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2649Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2650Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
2651Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2652Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2653Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2654Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0.
2655Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2656Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 3.
2657Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0.
2658Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2659Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2660Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2661Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2662
2663+------------------------------------------------------------------------
2664| MAU Stage 7
2665+------------------------------------------------------------------------
2666+------------------------------------------------------------------------
2667Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2668Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2669Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2670Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2671Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2672Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2673Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2674Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2675Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2676Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2677Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2678Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2679Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2680Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2681Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2682Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2683Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2684Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2685Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2686Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2687Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2688Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2689Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2690Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2691Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2692Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2693Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2694Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2695--------------------------------------------
2696Configuration for unused statistics ALUs.
2697Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2698Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2699Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2700Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2701+------------------------------------------------------------------------
2702Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2703Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2704Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
2705Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2706Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2707Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
2708Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2709Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2710Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
2711Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
2712Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
2713Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
2714Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
2715Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
2716Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
2717Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2718Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2719Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2720Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2721Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2722Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2723Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2724Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2725Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2726Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2727Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2728Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2729+------------------------------------------------------------------------
2730Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2731Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2732Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2733Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2734Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2735Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2736Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2737Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2738Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2739Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2740Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2741Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2742Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2743Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2744
2745+------------------------------------------------------------------------
2746| MAU Stage 8
2747+------------------------------------------------------------------------
2748+------------------------------------------------------------------------
2749Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2750Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2751Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2752Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2753Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2754Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2755Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2756Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2757Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2758Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2759Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2760Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2761Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2762Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2763Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2764Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2765Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2766Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2767Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2768Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2769Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2770Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2771Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2772Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2773Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2774Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2775Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2776Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2777--------------------------------------------
2778Configuration for unused statistics ALUs.
2779Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2780Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2781Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2782Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2783+------------------------------------------------------------------------
2784Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2785Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2786Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
2787Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2788Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2789Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
2790Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2791Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2792Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
2793Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
2794Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
2795Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
2796Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
2797Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
2798Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
2799Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2800Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2801Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2802Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2803Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2804Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2805Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2806Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2807Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2808Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2809Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2810Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2811+------------------------------------------------------------------------
2812Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2813Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2814Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2815Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2816Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2817Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2818Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2819Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2820Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2821Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2822Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2823Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2824Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2825Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2826
2827+------------------------------------------------------------------------
2828| MAU Stage 9
2829+------------------------------------------------------------------------
2830+------------------------------------------------------------------------
2831Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2832Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2833Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2834Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2835Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2836Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2837Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2838Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2839Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2840Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2841Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2842Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2843Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2844Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2845Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2846Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2847Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2848Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2849Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2850Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2851Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2852Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2853Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2854Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2855Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2856Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2857Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2858Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2859--------------------------------------------
2860Configuration for unused statistics ALUs.
2861Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2862Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2863Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2864Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2865+------------------------------------------------------------------------
2866Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2867Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2868Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
2869Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2870Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2871Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
2872Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2873Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2874Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
2875Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
2876Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
2877Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
2878Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
2879Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
2880Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
2881Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2882Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2883Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2884Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2885Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2886Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2887Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2888Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2889Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2890Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2891Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2892Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2893+------------------------------------------------------------------------
2894Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2895Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2896Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2897Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2898Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2899Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2900Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2901Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2902Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2903Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2904Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2905Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2906Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2907Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2908
2909+------------------------------------------------------------------------
2910| MAU Stage 10
2911+------------------------------------------------------------------------
2912+------------------------------------------------------------------------
2913Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2914Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2915Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2916Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2917Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2918Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2919Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2920Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2921Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2922Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2923Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2924Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2925Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2926Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2927Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2928Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2929Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2930Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2931Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2932Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2933Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2934Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2935Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2936Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2937Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2938Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2939Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2940Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2941--------------------------------------------
2942Configuration for unused statistics ALUs.
2943Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2944Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2945Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2946Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2947+------------------------------------------------------------------------
2948Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2949Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2950Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
2951Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
2952Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
2953Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
2954Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2955Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2956Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
2957Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
2958Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
2959Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
2960Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
2961Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
2962Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
2963Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2964Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2965Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2966Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2967Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2968Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2969Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2970Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2971Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2972Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2973Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2974Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2975+------------------------------------------------------------------------
2976Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2977Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2978Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2979Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2980Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2981Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2982Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2983Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2984Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2985Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2986Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2987Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2988Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2989Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2990
2991+------------------------------------------------------------------------
2992| MAU Stage 11
2993+------------------------------------------------------------------------
2994+------------------------------------------------------------------------
2995Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2996Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2997Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2998Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2999Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
3000Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
3001Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
3002Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
3003Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
3004Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
3005Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
3006Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
3007Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
3008Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
3009Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
3010Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
3011Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
3012Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
3013Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
3014Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
3015Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
3016Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
3017Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19.
3018Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
3019Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
3020Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
3021Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
3022Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
3023--------------------------------------------
3024Configuration for unused statistics ALUs.
3025Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
3026Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
3027Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
3028Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
3029+------------------------------------------------------------------------
3030Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
3031Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
3032Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
3033Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
3034Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
3035Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
3036Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
3037Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
3038Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
3039Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
3040Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
3041Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
3042Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
3043Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
3044Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
3045Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
3046Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
3047Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
3048Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
3049Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
3050Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
3051Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
3052Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
3053Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
3054Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
3055Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
3056Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
3057+------------------------------------------------------------------------
3058Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
3059Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
3060Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
3061Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
3062Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
3063Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
3064Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
3065Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0.
3066Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
3067Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
3068Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
3069Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
3070Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
3071Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
3072
3073+------------------------------------------------------------------------
3074| Number of configuration field values set in Match-Action Stages: 2168
3075+------------------------------------------------------------------------
3076
3077+------------------------------------------------------------------------
3078| MAU Feature Characteristics:
3079+------------------------------------------------------------------------
3080
3081
3082Features per Stage for ingress:
3083-----------------------------------------------------------------------------------------------
3084| Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency |
3085| | | | | LPF | (max words) | | to Previous |
3086-----------------------------------------------------------------------------------------------
3087| 0 | Yes | No | No | No | No (0) | No | match |
3088| 1 | No | Yes | Yes | No | No (0) | No | match |
3089| 2 | Yes | No | Yes | No | No (0) | No | match |
3090| 3 | Yes | No | Yes | No | No (0) | No | match |
3091| 4 | Yes* | No | Yes* | No | No (0) | No | concurrent |
3092| 5 | Yes* | No | Yes* | No | No (0) | No | concurrent |
3093| 6 | No | No | No | No | No (0) | No | match |
3094| 7 | No | No | No | No | No (0) | No | concurrent |
3095| 8 | No | No | No | No | No (0) | No | concurrent |
3096| 9 | No | No | No | No | No (0) | No | concurrent |
3097| 10 | No | No | No | No | No (0) | No | concurrent |
3098| 11 | No | No | No | No | No (0) | No | concurrent |
3099-----------------------------------------------------------------------------------------------
3100
3101A '*' denotes that this feature was added to balance an action/concurrent chain.
3102
3103
3104Features per Stage for egress:
3105-----------------------------------------------------------------------------------------------
3106| Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency |
3107| | | | | LPF | (max words) | | to Previous |
3108-----------------------------------------------------------------------------------------------
3109| 0 | Yes | No | No | No | No (0) | No | match |
3110| 1 | Yes* | No | No | No | No (0) | No | concurrent |
3111| 2 | Yes* | No | No | No | No (0) | No | concurrent |
3112| 3 | Yes* | No | No | No | No (0) | No | concurrent |
3113| 4 | Yes* | No | No | No | No (0) | No | concurrent |
3114| 5 | Yes* | No | No | No | No (0) | No | concurrent |
3115| 6 | No | No | No | No | No (0) | No | match |
3116| 7 | No | No | No | No | No (0) | No | concurrent |
3117| 8 | No | No | No | No | No (0) | No | concurrent |
3118| 9 | No | No | No | No | No (0) | No | concurrent |
3119| 10 | No | No | No | No | No (0) | No | concurrent |
3120| 11 | No | No | No | No | No (0) | No | concurrent |
3121-----------------------------------------------------------------------------------------------
3122
3123A '*' denotes that this feature was added to balance an action/concurrent chain.
3124
3125+------------------------------------------------------------------------
3126| MAU Latency Characteristics:
3127+------------------------------------------------------------------------
3128
3129
3130Clock Cycles Per Stage For ingress:
3131-----------------------------------------------------------------------------------------------------
3132| Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency |
3133-----------------------------------------------------------------------------------------------------
3134| 0 | 20 | 11 | match | 20 |
3135| 1 | 22 | 13 | match | 22 |
3136| 2 | 20 | 11 | match | 20 |
3137| 3 | 20 | 11 | match | 20 |
3138| 4 | 20 | 11 | concurrent | 1 |
3139| 5 | 20 | 11 | concurrent | 1 |
3140| 6 | 20 | 11 | match | 20 |
3141| 7 | 20 | 11 | concurrent | 1 |
3142| 8 | 20 | 11 | concurrent | 1 |
3143| 9 | 20 | 11 | concurrent | 1 |
3144| 10 | 20 | 11 | concurrent | 1 |
3145| 11 | 20 | 11 | concurrent | 1 |
3146-----------------------------------------------------------------------------------------------------
3147
3148Total latency for ingress: 113
3149
3150
3151Clock Cycles Per Stage For egress:
3152-----------------------------------------------------------------------------------------------------
3153| Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency |
3154-----------------------------------------------------------------------------------------------------
3155| 0 | 20 | 11 | match | 20 |
3156| 1 | 20 | 11 | concurrent | 1 |
3157| 2 | 20 | 11 | concurrent | 1 |
3158| 3 | 20 | 11 | concurrent | 1 |
3159| 4 | 20 | 11 | concurrent | 1 |
3160| 5 | 20 | 11 | concurrent | 1 |
3161| 6 | 20 | 11 | match | 20 |
3162| 7 | 20 | 11 | concurrent | 1 |
3163| 8 | 20 | 11 | concurrent | 1 |
3164| 9 | 20 | 11 | concurrent | 1 |
3165| 10 | 20 | 11 | concurrent | 1 |
3166| 11 | 20 | 11 | concurrent | 1 |
3167-----------------------------------------------------------------------------------------------------
3168
3169Total latency for egress: 54