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gerrit.onosproject.org / onos / 465ec2c679d563d445464881c73d9cde8b326431 / . / tools / test / p4src / p4-14 / p4c-out / tofino / ecmp / mavericks / logs / mau.config.log
blob: b0c43cdf5abe27d7c9cd402e41f285957c48cf37 [file] [log] [blame]
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1+---------------------------------------------------------------------+
2| Log file: mau.config.log |
3| Compiler version: 5.1.0 (fca32d1) |
Carmelo Cascone8aa05482017-09-12 13:21:59 +0200[diff] [blame]4| Created on: Tue Sep 12 11:15:53 2017 |
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]5+---------------------------------------------------------------------+
6
7Final Stage dependencies are:
8 (0, 'ingress') : match
9 (1, 'ingress') : match
10 (2, 'ingress') : match
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]11 (3, 'ingress') : concurrent
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]12 (4, 'ingress') : concurrent
13 (5, 'ingress') : concurrent
14 (6, 'ingress') : match
15 (7, 'ingress') : concurrent
16 (8, 'ingress') : concurrent
17 (9, 'ingress') : concurrent
18 (10, 'ingress') : concurrent
19 (11, 'ingress') : concurrent
20 (0, 'egress') : match
21 (1, 'egress') : concurrent
22 (2, 'egress') : concurrent
23 (3, 'egress') : concurrent
24 (4, 'egress') : concurrent
25 (5, 'egress') : concurrent
26 (6, 'egress') : match
27 (7, 'egress') : concurrent
28 (8, 'egress') : concurrent
29 (9, 'egress') : concurrent
30 (10, 'egress') : concurrent
31 (11, 'egress') : concurrent
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]32Action/Concurrent chaining in ingress consists of [3, 4, 5]
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]33Action/Concurrent chaining in ingress consists of [7, 8, 9, 10, 11]
34Action/Concurrent chaining in egress consists of [1, 2, 3, 4, 5]
35Action/Concurrent chaining in egress consists of [7, 8, 9, 10, 11]
36
37+------------------------------------------------------------------------
38| MAU Stage 0
39+------------------------------------------------------------------------
40
41+------------------------------------------------------------------------
42| Working on table _condition_0 in stage 0 ---
43+------------------------------------------------------------------------
44--> Stage Gateway Table for condition _condition_0 in stage 0
45Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
46Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
47Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
48Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
49Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
50Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]51Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x2. (old value = 0x0 OR new value = 0x2)
52Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]53Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_address to be 3.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]54Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_enable to be 1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]55Configuring match input crossbar byte 12 to come from 8-bit PHV container 3.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]56 That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]57Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]58Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2)
59Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
60Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=6][hash_bit_index=40].byte0 to be 0x2.
61Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
62Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
63Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
64Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
65Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
66Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
67Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
68Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
69Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
70Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0
71Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0
72Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
73Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
74Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
75Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
76Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
77Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff
78Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xfffffe
79Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x10
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]80Configuring rams.match.merge.gateway_next_table_lut[0][4] to be 0x1
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]81Configuring rams.match.merge.gateway_en.gateway_en to be 0x1
82Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf
83Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1
84Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_logical_select to be 0x0
85Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_inhibit_enable to be 0x1
86Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff
87Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff
88
89+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]90| Working on table process_packet_out_table__action__ in stage 0 ---
91+------------------------------------------------------------------------
92--> Action Data Table process_packet_out_table__action__ with logical_table_id 1 that is reference type is 'direct'
93
94+------------------------------------------------------------------------
95| Working on table process_packet_out_table in stage 0 ---
96+------------------------------------------------------------------------
97--> Match Table with no key process_packet_out_table with logical_table_id 1
98allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
99Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
100Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
101Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
102Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
103Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
104Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
105Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 1 (logical table id).
106Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
107Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 1 (logical table id).
108Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
109Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x40.
110Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x0.
111Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0x20.
112Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0x20.
113Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x2 (previous_value=0x0 OR new_value=0x2).
114Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x45.
115Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
116Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_instr to be 0x74412.
117Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_color to be 1.
118Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_parity to be 0.
119Micro instruction added in VLIW 2 for 16-bit position 2 for table process_packet_out_table.
120 Assembled as 0x74412 (or decimal 476178)
121 Micro Instruction deposit-field for PHV Container 130 has bit width 23
122 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
123 Field Src1 [4:0] : 0x1 (5 bits in instruction bits [8:4])
124 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
125 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
126 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
127 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
128 Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16])
129 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
130
131Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=2].imem_subword8_instr to be 0x74d83.
132Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=2].imem_subword8_color to be 1.
133Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=2].imem_subword8_parity to be 1.
134Micro instruction added in VLIW 2 for 8-bit position 3 for table process_packet_out_table.
135 Assembled as 0x74d83 (or decimal 478595)
136 Micro Instruction deposit-field for PHV Container 67 has bit width 20
137 Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
138 Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4])
139 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
140 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
141 Field high_bit [2:0] : 0x1 (3 bits in instruction bits [13:11])
142 Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14])
143 Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16])
144 Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
145
146Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
147Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6)
148--> Stage Gateway Table for condition process_packet_out_table_always_true_condition in stage 0
149Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
150Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
151Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
152Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
153Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
154Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
155Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x2. (old value = 0x2 OR new value = 0x0)
156Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
157Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x2 OR new value = 0x0)
158Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
159Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
160Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
161Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
162Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
163Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
164Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1
165Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0
166Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
167Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
168Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
169Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff
170Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff
171Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff
172Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff
173Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8
174Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0x20
175Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10)
176Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0x20
177Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2)
178Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe
179Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1
180allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
181Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x1
182Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1
183Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2
184Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x0
185Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0
186Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x0
187Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0
188Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff
189Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff
190Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
191
192+------------------------------------------------------------------------
193| Working on table table0__action__ in stage 0 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]194+------------------------------------------------------------------------
195--> Action Data Table table0__action__ with logical_table_id 0 that is reference type is 'direct'
196Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_input_bytemask[array_half=1].action_hv_ixbar_input_bytemask to be 0x3.
197Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_ctl_halfword[slice_group=1][array_half=1].action_hv_ixbar_ctl_halfword_3to0_ctl to be 0.
198Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_ctl_halfword[slice_group=1][array_half=1].action_hv_ixbar_ctl_halfword_3to0_enable to be 1.
199Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_select to be 5.
200Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_enable to be 1.
201Configuring rams.array.switchbox.row[row=6].ctl.r_action_o_mux_select.r_action_o_sel_action_rd_r_i to be 1.
202Configuring rams.array.row[row=6].ram[col=8].unit_ram_ctl.match_ram_write_data_mux_select to be select of 7.
203Configuring rams.array.row[row=6].ram[col=8].unit_ram_ctl.match_ram_read_data_mux_select to be select of 4.
204Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_type to be 2.
205Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_vpn to be 0.
206Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_logical_table to be 0.
207Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_ingress to be 1.
208Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_action_subword_out_en to be 1.
209Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_enable to be 1.
210Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=2].ram_unitram_adr_mux_select to be 1.
211Configuring rams.array.row[row=6].actiondata_error_uram_ctl[direction=0].actiondata_error_uram_ctl to be select of 0x40. (previous value = 0x0 OR new value = 0x40)
212Action data table table0__action__ is used by match table table0.
213Configuring rams.match.adrdist.adr_dist_action_data_adr_icxbar_ctl[match_logical_table_id=0].address_distr_to_logical_rows to be 0x2000.
214
215---- Hash Distribution Units for table table0__action__ ----
216Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x2 OR new value = 0x3)
217Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
218Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_address to be 5.
219Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_lo_enable to be 1.
220Configuring match input crossbar byte 0 to come from 32-bit PHV container 5.
221 That PHV byte contains {udp.dstPort[7:0]}.
222Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_address to be 5.
223Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_lo_enable to be 1.
224Configuring match input crossbar byte 1 to come from 32-bit PHV container 5.
225 That PHV byte contains {udp.dstPort[15:8]}.
226Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_address to be 5.
227Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_lo_enable to be 1.
228Configuring match input crossbar byte 2 to come from 32-bit PHV container 5.
229 That PHV byte contains {udp.srcPort[7:0]}.
230Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_address to be 5.
231Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_lo_enable to be 1.
232Configuring match input crossbar byte 3 to come from 32-bit PHV container 5.
233 That PHV byte contains {udp.srcPort[15:8]}.
234Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_address to be 2.
235Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_lo_enable to be 1.
236Configuring match input crossbar byte 4 to come from 32-bit PHV container 2.
237 That PHV byte contains {ipv4.dstAddr[7:0]}.
238Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=5].match_input_xbar_32b_ctl_address to be 2.
239Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=5].match_input_xbar_32b_ctl_lo_enable to be 1.
240Configuring match input crossbar byte 5 to come from 32-bit PHV container 2.
241 That PHV byte contains {ipv4.dstAddr[15:8]}.
242Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=6].match_input_xbar_32b_ctl_address to be 2.
243Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=6].match_input_xbar_32b_ctl_lo_enable to be 1.
244Configuring match input crossbar byte 6 to come from 32-bit PHV container 2.
245 That PHV byte contains {ipv4.dstAddr[23:16]}.
246Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=7].match_input_xbar_32b_ctl_address to be 2.
247Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=7].match_input_xbar_32b_ctl_lo_enable to be 1.
248Configuring match input crossbar byte 7 to come from 32-bit PHV container 2.
249 That PHV byte contains {ipv4.dstAddr[31:24]}.
250Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=8].match_input_xbar_32b_ctl_address to be 1.
251Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=8].match_input_xbar_32b_ctl_lo_enable to be 1.
252Configuring match input crossbar byte 8 to come from 32-bit PHV container 1.
253 That PHV byte contains {ipv4.srcAddr[31:24]}.
254Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_address to be 19.
255Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_enable to be 1.
256Configuring match input crossbar byte 9 to come from 16-bit PHV container 3.
257 That PHV byte contains {ipv4.srcAddr[15:8]}.
258Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_address to be 19.
259Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_enable to be 1.
260Configuring match input crossbar byte 10 to come from 16-bit PHV container 3.
261 That PHV byte contains {ipv4.srcAddr[7:0]}.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]262Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_address to be 0.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]263Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_enable to be 1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]264Configuring match input crossbar byte 11 to come from 8-bit PHV container 0.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]265 That PHV byte contains {ipv4.srcAddr[23:16]}.
266Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x26. (previous value = 0x0 OR new value = 0x26)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]267Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x9. (previous value = 0x8 OR new value = 0x1)
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]268Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
269Configuring dp.xbar_hash.hash.hash_seed[output_bit=0].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
270Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x3. (previous value = 0x2 OR new value = 0x3)
271Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
272Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x4.
273Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte1 to be 0xd1.
274Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte0 to be 0x1.
275Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte1 to be 0xdf.
276Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte0 to be 0x48.
277Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte1 to be 0x1b.
278Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte0 to be 0x4e.
279Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte1 to be 0x5a.
280Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0x7.
281Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte1 to be 0x82.
282Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte0 to be 0xf1.
283Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte1 to be 0xfa.
284Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
285Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 1. (old value = 0 OR new value = 1).
286Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 8. (old value = 0 OR new value = 8).
287Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 1. (old value = 0 OR new value = 1).
288Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x0. (old value = 0x0 OR new value = 0x0).
289Configuring rams.match.merge.mau_hash_group_mask[which_16=0].mau_hash_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
290Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=1][control_group_index=0].mau_hash_group_xbar_ctl to be 0x8 (old value = 0x0 OR new value = 0x8).
291
292+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]293| Working on table table0 in stage 0 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]294+------------------------------------------------------------------------
295--> Ternary Match Table table0 with logical_table_id 0
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]296Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1).
297Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1).
298Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1).
299Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1).
300Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1).
301Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1).
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]302Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id).
303Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
304Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id).
305Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
306Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x7.
307Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_default to be 0x0.
308Configuring rams.match.merge.mau_action_instruction_adr_per_entry_en_mux_ctl[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_per_entry_en_mux_ctl to be 0x3.
309Configuring rams.match.merge.mau_actiondata_adr_default[table_type_index=1][physical_result_bus=0].mau_actiondata_adr_default to be 0x400001.
310Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=1].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
311Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x870a080.
312Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x44.
313Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]314Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x20.
315Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data1 to be 0x10.
316Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x20.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]317Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x1.
318Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=1][result_bus_number=0].mau_immediate_data_mask to be 0x0.
319Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=1][result_bus_number=0].mau_stats_adr_mask to be 0xffffe.
320Configuring rams.match.merge.mau_stats_adr_default[table_type_index=1][result_bus_number=0].mau_stats_adr_default to be 0x80000.
321Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x3 OR new value = 0x0)
322Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x3. (old value = 0x0 OR new value = 0x3)
323Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_address to be 16.
324Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_enable to be 1.
325Configuring match input crossbar byte 133 to come from 16-bit PHV container 0.
326 That PHV byte contains version/valid
327{unused[6:0], ig_intr_md.ingress_port[8:8]}.
328Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_address to be 4.
329Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_lo_enable to be 1.
330Configuring match input crossbar byte 128 to come from 32-bit PHV container 4.
331 That PHV byte contains {ethernet.srcAddr[7:0]}.
332Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_address to be 4.
333Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_lo_enable to be 1.
334Configuring match input crossbar byte 129 to come from 32-bit PHV container 4.
335 That PHV byte contains {ethernet.srcAddr[15:8]}.
336Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_address to be 4.
337Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_lo_enable to be 1.
338Configuring match input crossbar byte 130 to come from 32-bit PHV container 4.
339 That PHV byte contains {ethernet.srcAddr[23:16]}.
340Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_address to be 4.
341Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_lo_enable to be 1.
342Configuring match input crossbar byte 131 to come from 32-bit PHV container 4.
343 That PHV byte contains {ethernet.srcAddr[31:24]}.
344Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_address to be 3.
345Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_lo_enable to be 1.
346Configuring match input crossbar byte 132 to come from 32-bit PHV container 3.
347 That PHV byte contains {ethernet.dstAddr[15:8]}.
348Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_address to be 3.
349Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_lo_enable to be 1.
350Configuring match input crossbar byte 134 to come from 32-bit PHV container 3.
351 That PHV byte contains {ethernet.dstAddr[31:24]}.
352Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_address to be 3.
353Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_lo_enable to be 1.
354Configuring match input crossbar byte 135 to come from 32-bit PHV container 3.
355 That PHV byte contains {ethernet.dstAddr[39:32]}.
356Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_address to be 21.
357Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_enable to be 1.
358Configuring match input crossbar byte 136 to come from 16-bit PHV container 5.
359 That PHV byte contains {ethernet.etherType[7:0]}.
360Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_address to be 3.
361Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_lo_enable to be 1.
362Configuring match input crossbar byte 137 to come from 32-bit PHV container 3.
363 That PHV byte contains {ethernet.dstAddr[23:16]}.
364Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_address to be 20.
365Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_enable to be 1.
366Configuring match input crossbar byte 138 to come from 16-bit PHV container 4.
367 That PHV byte contains {ethernet.srcAddr[47:40]}.
368Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_address to be 21.
369Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_enable to be 1.
370Configuring match input crossbar byte 139 to come from 16-bit PHV container 5.
371 That PHV byte contains {ethernet.etherType[15:8]}.
372Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_address to be 16.
373Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_enable to be 1.
374Configuring match input crossbar byte 140 to come from 16-bit PHV container 0.
375 That PHV byte contains {ig_intr_md.ingress_port[7:0]}.
376Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_address to be 20.
377Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_enable to be 1.
378Configuring match input crossbar byte 141 to come from 16-bit PHV container 4.
379 That PHV byte contains {ethernet.dstAddr[7:0]}.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]380Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]381Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_enable to be 1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]382Configuring match input crossbar byte 142 to come from 8-bit PHV container 2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]383 That PHV byte contains {ethernet.srcAddr[39:32]}.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]384Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]385Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_enable to be 1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]386Configuring match input crossbar byte 143 to come from 8-bit PHV container 1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]387 That PHV byte contains {ethernet.dstAddr[47:40]}.
388Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x3e. (previous value = 0x26 OR new value = 0x18)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]389Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0xf. (previous value = 0x9 OR new value = 0x6)
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]390Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x39. (previous value = 0x8 OR new value = 0x31)
391
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]392--> Idletime Table for match table table0 in stage 0
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]393Looking at Map RAM: Row 7 Unit 0
394Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 0.
395Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 1.
396Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].two_way_idletime_notification to be 1.
397Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].per_flow_idletime to be 1.
398Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].idletime_bitwidth to be 2 (precision = 3 bits).
399Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_type to be 4.
400Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
401FIXME: Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn_members to be 0.
402Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn to be 0.
403Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
404Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
405Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
406Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
407Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 2.
408Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
409Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
410Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
411Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_stats_meter_adr_mux_select_idlet to be 1.
412Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0.
413Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1.
414Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0.
415Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1.
416Configuring rams.map_alu.row[row=7].adrmux.idletime_cfg_rd_clear_val[map_ram_index=0].idletime_cfg_rd_clear_val to be 0x36.
417 logical table ID is 0
418Configuring rams.match.adrdist.adr_dist_idletime_adr_oxbar_ctl.[entry_index=2].adr_dist_idletime_adr_oxbar_ctl be 0x4000 (previous value = 0x0 OR new value = 0x4000)
419Note that rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_en must be programmed by run time.
420Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_offset be 0x0.
421Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_size be 0x0.
422Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_pos be 0x0.
423Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_en be 0x0.
424Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_interval be 0x7.
425Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_offset be 0x0.
426Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_size be 0x0.
427Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_pos be 0x0.
428Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_en be 0.
429Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_size be 2.
430Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_direct be 1.
431Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=2].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1)
432Configuring rams.match.merge.mau_idletime_adr_mask[table_type_index=1][result_bus_number=0].mau_idletime_adr_mask to be 0x1ffff8.
433Configuring rams.match.merge.mau_idletime_adr_default[table_type_index=1][result_bus_number=0].idletime_adr_default to be 0x100003.
434Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x4602.
435Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1.
436Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 1.
437Micro instruction added in VLIW 0 for 16-bit position 2 for table table0.
438 Assembled as 0x4602 (or decimal 17922)
439 Micro Instruction deposit-field for PHV Container 130 has bit width 23
440 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
441 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
442 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
443 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
444 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
445 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
446 Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
447 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
448
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]449Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x6 OR new value = 0x4)
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]450Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a06.
451Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_color to be 0.
452Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_parity to be 1.
453Micro instruction added in VLIW 1 for 16-bit position 6 for table table0.
454 Assembled as 0xc7a06 (or decimal 817670)
455 Micro Instruction alu_a for PHV Container 134 has bit width 23
456 Field Src2 [3:0] : 0x6 (4 bits in instruction bits [3:0])
457 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
458 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
459 Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
460 Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20])
461
462Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a27.
463Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_color to be 0.
464Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_parity to be 1.
465Micro instruction added in VLIW 1 for 16-bit position 7 for table table0.
466 Assembled as 0xc7a27 (or decimal 817703)
467 Micro Instruction alu_a for PHV Container 135 has bit width 23
468 Field Src2 [3:0] : 0x7 (4 bits in instruction bits [3:0])
469 Field Src1 [4:0] : 0x2 (5 bits in instruction bits [8:4])
470 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
471 Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
472 Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20])
473
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]474Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_instr to be 0x4602.
475Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_color to be 1.
476Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_parity to be 1.
477Micro instruction added in VLIW 1 for 16-bit position 2 for table table0.
478 Assembled as 0x4602 (or decimal 17922)
479 Micro Instruction deposit-field for PHV Container 130 has bit width 23
480 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
481 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
482 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
483 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
484 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
485 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
486 Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
487 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
488
489Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_instr to be 0x593.
490Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_color to be 1.
491Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_parity to be 1.
492Micro instruction added in VLIW 1 for 8-bit position 3 for table table0.
493 Assembled as 0x593 (or decimal 1427)
494 Micro Instruction deposit-field for PHV Container 67 has bit width 20
495 Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]496 Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
497 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
498 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
499 Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11])
500 Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14])
501 Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16])
502 Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
503
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]504Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_instr to be 0x39fc01.
505Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_color to be 1.
506Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_parity to be 0.
507Micro instruction added in VLIW 1 for 16-bit position 1 for table table0.
508 Assembled as 0x39fc01 (or decimal 3800065)
509 Micro Instruction deposit-field for PHV Container 129 has bit width 23
510 Field Src2 [3:0] : 0x1 (4 bits in instruction bits [3:0])
511 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
512 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
513 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
514 Field high_bit [3:0] : 0xf (4 bits in instruction bits [14:11])
515 Field low_bit_lo [0:0] : 0x1 (1 bits in instruction bits [15:15])
516 Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16])
517 Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20])
518
519Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x8. (previous value = 0x8 OR new value = 0x8)
520Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x7. (previous value = 0x6 OR new value = 0x7)
521Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_instr to be 0xb7d94.
522Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_color to be 0.
523Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_parity to be 0.
524Micro instruction added in VLIW 2 for 8-bit position 4 for table table0.
525 Assembled as 0xb7d94 (or decimal 753044)
526 Micro Instruction deposit-field for PHV Container 68 has bit width 20
527 Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]528 Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
529 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
530 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
531 Field high_bit [2:0] : 0x7 (3 bits in instruction bits [13:11])
532 Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14])
533 Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16])
534 Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19])
535
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]536Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x18. (previous value = 0x8 OR new value = 0x10)
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]537Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].idletime_adr_payload_shifter_en to be 1.
538Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].stats_adr_payload_shifter_en to be 1.
539Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].actiondata_adr_payload_shifter_en to be 1.
540Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].action_instruction_adr_payload_shifter_en to be 1.
541Configuring rams.match.merge.mau_table_counter_ctl[half_index=0].mau_table_counter_ctl to be 0x2. (previous value = 0x0 OR new value = 0x2)
542dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit']
543Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data_dirtcam_mode to be 0x155.
544Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vbit_dirtcam_mode to be 0x1.
545Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data1_select to be 1.
546Configuring tcams.col[col=1].tcam_mode[row=9].tcam_chain_out_enable to be 0.
547Configuring tcams.col[col=1].tcam_mode[row=9].tcam_ingress to be 1.
548Configuring tcams.col[col=1].tcam_mode[row=9].tcam_match_output_enable to be 1.
549Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vpn to be 0.
550Configuring tcams.col[col=1].tcam_mode[row=9].tcam_logical_table to be 0.
551TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit.
552Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=0] to be 15.
553Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=1] to be 15.
554Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=2] to be 15.
555Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=3] to be 15.
556Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=4] to be 15.
557Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=5] to be 15.
558Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=6] to be 15.
559Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=7] to be 15.
560Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_select to be 0 (don't care).
561Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_enable to be 1.
562Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_select to be 2.
563Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_enable to be 1.
564dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit']
565Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data_dirtcam_mode to be 0x155.
566Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vbit_dirtcam_mode to be 0x0.
567Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data1_select to be 1.
568Configuring tcams.col[col=1].tcam_mode[row=10].tcam_chain_out_enable to be 1.
569Configuring tcams.col[col=1].tcam_mode[row=10].tcam_ingress to be 1.
570Configuring tcams.col[col=1].tcam_mode[row=10].tcam_match_output_enable to be 0.
571Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vpn to be 0.
572Configuring tcams.col[col=1].tcam_mode[row=10].tcam_logical_table to be 0.
573TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit.
574Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15.
575Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15.
576Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15.
577Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15.
578Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15.
579Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15.
580Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15.
581Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15.
582Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_select to be 3 (version on [3:2] and valid bits for [1:0]).
583Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_enable to be 1.
584Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0.
585Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1.
586Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_select to be 1.
587Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_enable to be 1.
588dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit']
589Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data_dirtcam_mode to be 0x155.
590Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vbit_dirtcam_mode to be 0x1.
591Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data1_select to be 1.
592Configuring tcams.col[col=1].tcam_mode[row=11].tcam_chain_out_enable to be 1.
593Configuring tcams.col[col=1].tcam_mode[row=11].tcam_ingress to be 1.
594Configuring tcams.col[col=1].tcam_mode[row=11].tcam_match_output_enable to be 0.
595Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vpn to be 0.
596Configuring tcams.col[col=1].tcam_mode[row=11].tcam_logical_table to be 0.
597TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit.
598Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15.
599Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15.
600Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15.
601Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15.
602Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15.
603Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15.
604Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15.
605Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15.
606Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_select to be 0 (extra byte low nibble [3:0]).
607Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_enable to be 1.
608Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0.
609Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1.
610Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_select to be 0.
611Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_enable to be 1.
612Configuring tcams.col[col=0].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x0.
613Configuring tcams.col[col=1].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x200.
614--> Ternary Indirection table for Match Table table0 with logical_table_id 0
615Configuring tcams.tcam_match_adr_shift[tcam_table_id=0] to be left shift of 1.
616Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_write_data_mux_select to be select of 7.
617Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_read_data_mux_select to be select of 7.
618Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.tind_result_bus_select to be select of 1.
619Configuring rams.map_alu.row[row=0].adrmux.ram_address_mux_ctl[column_half=0][column_index=2].ram_unitram_adr_mux_select to be 2.
620Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_type to be 6.
621Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_vpn to be 0.
622Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_logical_table to be 0.
623Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_ingress to be 1.
624Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_enable to be 1.
625Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id).
626Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_enable to be 1.
627Configuring rams.array.row[row=0].tind_ecc_error_uram_ctl[direction=0].tind_ecc_error_uram_ctl to be select of 0x1. (previous value = 0x0 OR new value = 0x1)
628Configuring rams.match.merge.tind_ram_data_size[tind_bus_number=0].tind_ram_data_size to be code 2.
629Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id).
630Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_enable to be 1.
631TODO: rams.match.merge.tind_bus_prop[tind_bus_number=0] is currently always set to 1.
632Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].tcam_piped to be 1.
633Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].enabled to be 1.
634Configuring rams.match.merge.mau_action_instruction_adr_tcam_shiftcount[physical_result_bus=0].mau_action_instruction_adr_tcam_shiftcount to be 1.
635Configuring rams.match.merge.mau_actiondata_adr_mask[table_type_index=1][physical_result_bus=0].mau_actiondata_adr_mask to be 0x3ffffc.
636Configuring rams.match.merge.mau_actiondata_adr_tcam_shiftcount[physical_result_bus=0].mau_actiondata_adr_tcam_shiftcount to be 68.
637Configuring rams.match.merge.mau_idletime_adr_tcam_shiftcount[result_bus_number=0].mau_idletime_adr_tcam_shiftcount to be 0x42.
638Configuring rams.match.merge.mau_stats_adr_tcam_shiftcount[result_bus_index=0].mau_stats_adr_tcam_shiftcount to be 0x47.
639Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_select to be 0 (logical table id).
640Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_enable to be 1.
641TODO: rams.match.merge.tcam_table_prop[tcam_table_id=0] is currently always set to 1.
642Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].tcam_piped to be 1.
643Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].enabled to be 1.
644Configuring tcams.tcam_output_table_thread[tcam_table_id=0].tcam_output_table_thread to be 1.
645TODO: tcams.tcam_piped is currently always set to True for ingress and egress.
646Configuring tcams.tcam_piped to be 3.
647Configuring cfg_regs.mau_cfg_movereg_tcam_only.mau_cfg_movereg_tcam_only to be 0x1. (previous value = 0x0 OR new value = 0x1)
648
649+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]650| Working on table table0_counter in stage 0 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]651+------------------------------------------------------------------------
652Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
653Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
654Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
655Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
656Note that unitram_vpn does not need to be programmed for synthetic two port rams.
657Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0.
658Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
659Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
660Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
661Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
662Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
663Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
664Note that unitram_vpn does not need to be programmed for synthetic two port rams.
665Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0.
666Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
667Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
668Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
669Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
670Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
671Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
672Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
673Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
674Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
675Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
676Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
677Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
678Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
679Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
680Stat table table0_counter is used by match table table0.
681Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8)
682Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
683Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
684Note that map ram vpn does not need to be configured for synthetic two port map rams.
685Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
686Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
687Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
688Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
689Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
690Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
691Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
692Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
693Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0.
694Note that map ram vpn does not need to be configured for synthetic two port map rams.
695Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
696Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
697Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
698Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
699Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
700Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
701Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
702For counter width 32 and N = 4096
703 number iterations = 32
704 b_cur = 379488672.0
705 eqn(b_cur) = 4294964039.26
706 max_counter_value = 4294967295
707Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
708Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
709Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
710Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
711Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
712Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
713Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4.
714Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1.
715Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1.
716TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0.
717Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x0.
718Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4.
719Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1.
720Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0.
721Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0.
722Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0.
723Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0.
724Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0.
725Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
726Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
727Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1.
728Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3.
729Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_direct be 1.
730Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=0].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1)
731Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_tcam be 1.
732Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x0.
733Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x7. ( previous value = 0x0 OR new value = 0x7)
734Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x1.
735+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]736Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 12.
737Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
738Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]739Configuring rams.match.merge.exact_match_delay_thread[copy_index=0].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
740Configuring rams.match.merge.exact_match_delay_thread[copy_index=1].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
741Configuring rams.match.merge.exact_match_delay_thread[copy_index=2].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]742Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 10.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]743Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]744Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]745Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
746Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
747Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
748Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]749Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x3.
750Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x2.
751Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]752Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]753Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x2.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]754Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
755Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
756Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
757Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 16.
758Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 21.
759Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
760Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
761Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
762Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
763Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
764Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
765Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
766Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
767--------------------------------------------
768Configuration for unused statistics ALUs.
769Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
770Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
771Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
772+------------------------------------------------------------------------
773Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
774Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
775Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]776Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
777Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
778Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]779Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
780Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
781Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]782Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
783Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
784Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
785Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
786Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
787Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]788Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
789Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
790Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
791Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
792Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 1.
793Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 1.
794Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
795Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
796Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
797Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
798Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
799Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
800+------------------------------------------------------------------------
801Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 19.
802Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 2.
803Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
804Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
805Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
806Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]807Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]808Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]809Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
810Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]811Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
812Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
813Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
814Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
815
816+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]817| MAU Stage 1
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]818+------------------------------------------------------------------------
819
820+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]821| Working on table ecmp_group_table__action__ in stage 1 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]822+------------------------------------------------------------------------
823--> Action Data Table ecmp_group_table__action__ with logical_table_id 0 that is reference type is 'direct'
824Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_select to be 4.
825Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_enable to be 1.
826
827+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]828| Working on table ecmp_group_table in stage 1 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]829+------------------------------------------------------------------------
830--> Hash Match Table ecmp_group_table with logical_table_id 0
831Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
832Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
833Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
834Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
835Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
836Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
837Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=14].enabled_4bit_muxctl_select to be 0 (logical table id).
838Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=14].enabled_4bit_muxctl_enable to be 1.
839Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=14].enabled_4bit_muxctl_select to be 0 (logical table id).
840Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=14].enabled_4bit_muxctl_enable to be 1.
841Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=14].mau_action_instruction_adr_mask to be 0x0.
842Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=14].mau_action_instruction_adr_default to be 0x40.
843Configuring rams.match.merge.mau_action_instruction_adr_per_entry_en_mux_ctl[table_type_index=0][physical_result_bus=14].mau_action_instruction_adr_per_entry_en_mux_ctl to be 0x0.
844Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
845Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x41.
846Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
847Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]848Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x20.
849Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x20.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]850Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x0.
851Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=0][result_bus_number=14].mau_immediate_data_mask to be 0xffff.
852Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=0][result_bus_number=14].mau_stats_adr_mask to be 0xffffe.
853Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=14].mau_stats_adr_default to be 0x80000.
854Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
855Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
856Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 23.
857Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
858Configuring match input crossbar byte 0 to come from 16-bit PHV container 7.
859 That PHV byte contains {ecmp_metadata.selector[7:0]}.
860Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 23.
861Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
862Configuring match input crossbar byte 1 to come from 16-bit PHV container 7.
863 That PHV byte contains {ecmp_metadata.selector[15:8]}.
864Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 22.
865Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_enable to be 1.
866Configuring match input crossbar byte 2 to come from 16-bit PHV container 6.
Carmelo Cascone8aa05482017-09-12 13:21:59 +0200[diff] [blame]867 That PHV byte contains {ecmp_metadata.group_id[7:0]}.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]868Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 22.
869Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_enable to be 1.
870Configuring match input crossbar byte 3 to come from 16-bit PHV container 6.
Carmelo Cascone8aa05482017-09-12 13:21:59 +0200[diff] [blame]871 That PHV byte contains {ecmp_metadata.group_id[15:8]}.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]872Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0xc0. (previous value = 0x0 OR new value = 0xc0)
873Configuring dp.xbar_hash.hash.hash_seed[output_bit=2].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
874Configuring dp.xbar_hash.hash.hash_seed[output_bit=3].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
875Configuring dp.xbar_hash.hash.hash_seed[output_bit=5].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
876Configuring dp.xbar_hash.hash.hash_seed[output_bit=7].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
877Configuring dp.xbar_hash.hash.hash_seed[output_bit=8].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
878Configuring dp.xbar_hash.hash.hash_seed[output_bit=10].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
879Configuring dp.xbar_hash.hash.hash_seed[output_bit=11].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
880Configuring dp.xbar_hash.hash.hash_seed[output_bit=15].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
881Configuring dp.xbar_hash.hash.hash_seed[output_bit=19].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
882Configuring dp.xbar_hash.hash.hash_seed[output_bit=20].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
883Configuring dp.xbar_hash.hash.hash_seed[output_bit=21].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
884Configuring dp.xbar_hash.hash.hash_seed[output_bit=23].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
885Configuring dp.xbar_hash.hash.hash_seed[output_bit=24].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
886Configuring dp.xbar_hash.hash.hash_seed[output_bit=25].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
887Configuring dp.xbar_hash.hash.hash_seed[output_bit=26].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
888Configuring dp.xbar_hash.hash.hash_seed[output_bit=28].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
889Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
890Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
891Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x1.
892Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte1 to be 0x84.
893Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte0 to be 0xa9.
894Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte1 to be 0xbe.
895Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte0 to be 0x2.
896Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte1 to be 0xa0.
897Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=1].byte0 to be 0xd3.
898Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=1].byte1 to be 0xc0.
899Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte0 to be 0x4.
900Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte1 to be 0xd4.
901Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=2].byte0 to be 0xdc.
902Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=2].byte1 to be 0x26.
903Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte0 to be 0x8.
904Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte1 to be 0x38.
905Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=3].byte0 to be 0xd0.
906Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=3].byte1 to be 0x78.
907Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte0 to be 0x10.
908Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte1 to be 0x8.
909Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=4].byte0 to be 0xdc.
910Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=4].byte1 to be 0xf4.
911Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte0 to be 0x20.
912Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte1 to be 0x24.
913Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=5].byte0 to be 0xe.
914Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=5].byte1 to be 0x90.
915Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte0 to be 0x40.
916Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte1 to be 0xf4.
917Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=6].byte0 to be 0x3e.
918Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=6].byte1 to be 0x8e.
919Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte0 to be 0x80.
920Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte1 to be 0x8c.
921Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=7].byte0 to be 0x7d.
922Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=7].byte1 to be 0x4.
923Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=8].byte1 to be 0x79.
924Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=8].byte0 to be 0x12.
925Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=8].byte1 to be 0x40.
926Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=9].byte1 to be 0xee.
927Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=9].byte0 to be 0x30.
928Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=9].byte1 to be 0x21.
929Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=10].byte1 to be 0x7a.
930Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=10].byte0 to be 0xf0.
931Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=10].byte1 to be 0x7f.
932Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=11].byte0 to be 0x1.
933Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=11].byte1 to be 0x5c.
934Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=11].byte0 to be 0x54.
935Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=11].byte1 to be 0x14.
936Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=12].byte0 to be 0x2.
937Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=12].byte1 to be 0x94.
938Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=12].byte0 to be 0x62.
939Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=12].byte1 to be 0x63.
940Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=13].byte0 to be 0x4.
941Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=13].byte1 to be 0xb4.
942Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=13].byte0 to be 0x47.
943Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=13].byte1 to be 0x30.
944Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=14].byte0 to be 0x8.
945Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=14].byte1 to be 0xfc.
946Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=14].byte0 to be 0xa5.
947Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=14].byte1 to be 0xaa.
948Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=15].byte0 to be 0x10.
949Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=15].byte1 to be 0x48.
950Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=15].byte0 to be 0xee.
951Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=15].byte1 to be 0x84.
952Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=16].byte0 to be 0x20.
953Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=16].byte1 to be 0xb4.
954Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=16].byte0 to be 0xf1.
955Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=16].byte1 to be 0x93.
956Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=17].byte0 to be 0x40.
957Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=17].byte1 to be 0xb4.
958Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=17].byte0 to be 0xd7.
959Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=17].byte1 to be 0x19.
960Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=18].byte0 to be 0x80.
961Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=18].byte1 to be 0xec.
962Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=18].byte0 to be 0x62.
963Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=18].byte1 to be 0x13.
964Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=19].byte1 to be 0x29.
965Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=19].byte0 to be 0x12.
966Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=19].byte1 to be 0x16.
967Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=20].byte1 to be 0x45.
968Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=20].byte0 to be 0xe0.
969Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=20].byte1 to be 0xfe.
970Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=21].byte1 to be 0x6.
971Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=21].byte0 to be 0xd1.
972Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=21].byte1 to be 0x65.
973Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=22].byte0 to be 0x1.
974Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=22].byte1 to be 0x84.
975Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=22].byte0 to be 0x33.
976Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=22].byte1 to be 0xa4.
977Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=23].byte0 to be 0x2.
978Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=23].byte1 to be 0xc.
979Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=23].byte0 to be 0x7c.
980Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=23].byte1 to be 0xe.
981Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=24].byte0 to be 0x4.
982Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=24].byte1 to be 0x4c.
983Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=24].byte0 to be 0x8d.
984Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=24].byte1 to be 0x6f.
985Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=25].byte0 to be 0x8.
986Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=25].byte1 to be 0x2c.
987Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=25].byte0 to be 0xc2.
988Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=25].byte1 to be 0xf9.
989Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=26].byte0 to be 0x10.
990Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=26].byte1 to be 0xd0.
991Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=26].byte0 to be 0x17.
992Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=26].byte1 to be 0xf9.
993Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=27].byte0 to be 0x20.
994Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=27].byte1 to be 0x8.
995Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=27].byte0 to be 0x6c.
996Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=27].byte1 to be 0x32.
997Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=28].byte0 to be 0x40.
998Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=28].byte1 to be 0x74.
999Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=28].byte0 to be 0xdc.
1000Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=28].byte1 to be 0xb7.
1001Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=29].byte0 to be 0x80.
1002Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=29].byte1 to be 0xf8.
1003Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=29].byte0 to be 0x5c.
1004Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=29].byte1 to be 0xa.
1005Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
1006Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x4602.
1007Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1.
1008Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 1.
1009Micro instruction added in VLIW 0 for 16-bit position 2 for table ecmp_group_table.
1010 Assembled as 0x4602 (or decimal 17922)
1011 Micro Instruction deposit-field for PHV Container 130 has bit width 23
1012 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
1013 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
1014 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
1015 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
1016 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
1017 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
1018 Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
1019 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
1020
1021Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
1022Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=14].stats_adr_payload_shifter_en to be 1.
1023Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=14].action_instruction_adr_payload_shifter_en to be 1.
1024Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=14].immediate_data_payload_shifter_en to be 1.
1025Configuring rams.match.merge.mau_table_counter_ctl[half_index=0].mau_table_counter_ctl to be 0x2. (previous value = 0x0 OR new value = 0x2)
1026--> Hash Match Way 0
1027Packed entry for hash way 0 is
1028 [0] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 0))
1029 [1] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 1))
1030 [2] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 2))
1031 [3] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 3))
1032 [4] = (field_bit=4, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 4))
1033 [5] = (field_bit=5, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 5))
1034 [6] = (field_bit=6, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 6))
1035 [7] = (field_bit=7, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 7))
1036 [8] = (field_bit=8, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 8))
1037 [9] = (field_bit=9, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 9))
1038 [10] = (field_bit=10, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 10))
1039 [11] = (field_bit=11, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 11))
1040 [12] = (field_bit=12, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 12))
1041 [13] = (field_bit=13, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 13))
1042 [14] = (field_bit=14, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 14))
1043 [15] = (field_bit=15, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 15))
Carmelo Cascone8aa05482017-09-12 13:21:59 +0200[diff] [blame]1044 [16] = (field_bit=0, hash_match_group_bit=16, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 0))
1045 [17] = (field_bit=1, hash_match_group_bit=17, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 1))
1046 [18] = (field_bit=2, hash_match_group_bit=18, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 2))
1047 [19] = (field_bit=3, hash_match_group_bit=19, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 3))
1048 [20] = (field_bit=4, hash_match_group_bit=20, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 4))
1049 [21] = (field_bit=5, hash_match_group_bit=21, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 5))
1050 [22] = (field_bit=6, hash_match_group_bit=22, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 6))
1051 [23] = (field_bit=7, hash_match_group_bit=23, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 7))
1052 [24] = (field_bit=8, hash_match_group_bit=24, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 8))
1053 [25] = (field_bit=9, hash_match_group_bit=25, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 9))
1054 [26] = (field_bit=10, hash_match_group_bit=26, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 10))
1055 [27] = (field_bit=11, hash_match_group_bit=27, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 11))
1056 [28] = (field_bit=12, hash_match_group_bit=28, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 12))
1057 [29] = (field_bit=13, hash_match_group_bit=29, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 13))
1058 [30] = (field_bit=14, hash_match_group_bit=30, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 14))
1059 [31] = (field_bit=15, hash_match_group_bit=31, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 15))
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1060 [32] = None
1061 [33] = None
1062 [34] = (field_bit=10, hash_match_group_bit=10, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 10))
1063 [35] = (field_bit=11, hash_match_group_bit=11, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 11))
1064 [36] = (field_bit=12, hash_match_group_bit=12, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 12))
1065 [37] = (field_bit=13, hash_match_group_bit=13, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 13))
1066 [38] = (field_bit=14, hash_match_group_bit=14, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 14))
1067 [39] = (field_bit=15, hash_match_group_bit=15, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 15))
1068 [40] = None
1069 [41] = None
1070 [42] = None
1071 [43] = None
1072 [44] = None
1073 [45] = None
1074 [46] = None
1075 [47] = None
1076 [48] = None
1077 [49] = None
1078 [50] = None
1079 [51] = None
1080 [52] = None
1081 [53] = None
1082 [54] = None
1083 [55] = None
1084 [56] = None
1085 [57] = None
1086 [58] = None
1087 [59] = None
1088 [60] = None
1089 [61] = None
1090 [62] = None
1091 [63] = None
1092 [64] = None
1093 [65] = None
1094 [66] = None
1095 [67] = None
1096 [68] = None
1097 [69] = None
1098 [70] = None
1099 [71] = None
1100 [72] = None
1101 [73] = None
1102 [74] = None
1103 [75] = None
1104 [76] = None
1105 [77] = None
1106 [78] = None
1107 [79] = None
1108 [80] = None
1109 [81] = None
1110 [82] = None
1111 [83] = None
1112 [84] = None
1113 [85] = None
1114 [86] = None
1115 [87] = None
1116 [88] = None
1117 [89] = None
1118 [90] = None
1119 [91] = None
1120 [92] = None
1121 [93] = None
1122 [94] = None
1123 [95] = None
1124 [96] = None
1125 [97] = None
1126 [98] = None
1127 [99] = None
1128 [100] = None
1129 [101] = None
1130 [102] = None
1131 [103] = None
1132 [104] = None
1133 [105] = None
1134 [106] = None
1135 [107] = None
1136 [108] = None
1137 [109] = None
1138 [110] = None
1139 [111] = None
1140 [112] = None
1141 [113] = None
1142 [114] = None
1143 [115] = None
1144 [116] = None
1145 [117] = None
1146 [118] = None
1147 [119] = None
1148 [120] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 0))
1149 [121] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 1))
1150 [122] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 2))
1151 [123] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 3))
1152 [124] = None
1153 [125] = None
1154 [126] = None
1155 [127] = None
1156
1157Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=0].match_mask to be 0xffff.
1158Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=1].match_mask to be 0xffffff03.
1159Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=2].match_mask to be 0xffffffff.
1160Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=3].match_mask to be 0xf0ffffff.
1161Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_ram_write_data_mux_select to be 7.
1162Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_ram_read_data_mux_select to be 7.
1163Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_result_bus_select to be 1.
1164Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_entry_enable to be 1.
1165Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_ram_logical_table to be 0x0.
1166For entry_in_ram_word 0, should have vpn 0, with lower_two_bits of 0 and upper_vpn of 0
1167for entry_in_ram_word 0, use lsbs of 0
1168Configuring rams.array.row[row=7].ram[column=2].match_ram_vpn.match_ram_vpn0 to be 0.
1169Configuring rams.array.row[row=7].ram[column=2].match_ram_vpn.match_ram_vpn_lsbs to be 0x0.
1170version valid nibbles are : [30]
1171Configuring rams.array.row[row=7].ram[column=2].match_nibble_s0q1_enable.match_nibble_s0q1_enable to be 0xbfffffff.
1172Configuring rams.array.row[row=7].ram[column=2].match_nibble_s1q0_enable.match_nibble_s1q0_enable to be 0xffffffff.
1173Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=0].mask_bytes_0_to_13 to be 0x3fe3.
1174Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=0].mask_nibbles_28_to_31 to be 0xb.
1175Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=1].mask_bytes_0_to_13 to be 0x3fff.
1176Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=1].mask_nibbles_28_to_31 to be 0xf.
1177Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=2].mask_bytes_0_to_13 to be 0x3fff.
1178Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=2].mask_nibbles_28_to_31 to be 0xf.
1179Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=3].mask_bytes_0_to_13 to be 0x3fff.
1180Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=3].mask_nibbles_28_to_31 to be 0xf.
1181Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=4].mask_bytes_0_to_13 to be 0x3fff.
1182Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=4].mask_nibbles_28_to_31 to be 0xf.
1183Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1184Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1185Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1186Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1187Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1188Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1189Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1190Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1191Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1192Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1193Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1194Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1195Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1196Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1197Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1198Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1199Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1200Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1201Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1202Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1203Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1204Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1205Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1206Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1207Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1208Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1209Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
1210Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
1211Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_thread to be 0.
1212Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=2].exactmatch_bank_enable_bank_mask to be 0x0.
1213Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=2].exactmatch_bank_enable_bank_id to be 0x0.
1214Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=2].exactmatch_bank_enable_inp_sel to be 1.
1215Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
1216Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
1217Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=2].enabled_4bit_muxctl_select to be 0.
1218Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=2].enabled_4bit_muxctl_enable to be 1.
1219Configuring rams.match.merge.mau_action_instruction_adr_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_action_instruction_adr_exact_shiftcount to be 0.
1220Configuring rams.match.merge.mau_immediate_data_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_immediate_data_exact_shiftcount to be 0.
1221Configuring rams.match.merge.mau_stats_adr_exact_shiftcount[result_bus_number = 14][entry_in_ram_word=0].mau_stats_adr_exact_shiftcount to be 0x46.
1222Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_type to be 1.
1223Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_logical_table to be 0.
1224Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_ingress to be 1.
1225Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_enable to be 1.
1226Configuring rams.array.row[row=7].emm_ecc_error_uram_ctl[direction=0].emm_ecc_error_uram_ctl to be select of 0x1. (previous value = 0x0 OR new value = 0x1)
1227In Ram Word 0:
1228 wide entry 0 occupied ram word entry 0
1229Configuring rams.match.merge.col[col_number=2].row_action_nxtable_bus_drive[row_number=7].row_action_nxtable_bus_drive to be 1.
1230Configuring rams.match.merge.col[col_number=2].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_select to be 14 (hit signal to output on).
1231Configuring rams.match.merge.col[col_number=2].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1.
1232--> Hash Match Way 1
1233Packed entry for hash way 1 is
1234 [0] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 0))
1235 [1] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 1))
1236 [2] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 2))
1237 [3] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 3))
1238 [4] = (field_bit=4, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 4))
1239 [5] = (field_bit=5, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 5))
1240 [6] = (field_bit=6, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 6))
1241 [7] = (field_bit=7, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 7))
1242 [8] = (field_bit=8, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 8))
1243 [9] = (field_bit=9, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 9))
1244 [10] = (field_bit=10, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 10))
1245 [11] = (field_bit=11, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 11))
1246 [12] = (field_bit=12, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 12))
1247 [13] = (field_bit=13, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 13))
1248 [14] = (field_bit=14, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 14))
1249 [15] = (field_bit=15, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 15))
Carmelo Cascone8aa05482017-09-12 13:21:59 +0200[diff] [blame]1250 [16] = (field_bit=0, hash_match_group_bit=16, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 0))
1251 [17] = (field_bit=1, hash_match_group_bit=17, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 1))
1252 [18] = (field_bit=2, hash_match_group_bit=18, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 2))
1253 [19] = (field_bit=3, hash_match_group_bit=19, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 3))
1254 [20] = (field_bit=4, hash_match_group_bit=20, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 4))
1255 [21] = (field_bit=5, hash_match_group_bit=21, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 5))
1256 [22] = (field_bit=6, hash_match_group_bit=22, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 6))
1257 [23] = (field_bit=7, hash_match_group_bit=23, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 7))
1258 [24] = (field_bit=8, hash_match_group_bit=24, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 8))
1259 [25] = (field_bit=9, hash_match_group_bit=25, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 9))
1260 [26] = (field_bit=10, hash_match_group_bit=26, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 10))
1261 [27] = (field_bit=11, hash_match_group_bit=27, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 11))
1262 [28] = (field_bit=12, hash_match_group_bit=28, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 12))
1263 [29] = (field_bit=13, hash_match_group_bit=29, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 13))
1264 [30] = (field_bit=14, hash_match_group_bit=30, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 14))
1265 [31] = (field_bit=15, hash_match_group_bit=31, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 15))
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1266 [32] = None
1267 [33] = None
1268 [34] = (field_bit=10, hash_match_group_bit=10, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 10))
1269 [35] = (field_bit=11, hash_match_group_bit=11, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 11))
1270 [36] = (field_bit=12, hash_match_group_bit=12, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 12))
1271 [37] = (field_bit=13, hash_match_group_bit=13, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 13))
1272 [38] = (field_bit=14, hash_match_group_bit=14, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 14))
1273 [39] = (field_bit=15, hash_match_group_bit=15, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 15))
1274 [40] = None
1275 [41] = None
1276 [42] = None
1277 [43] = None
1278 [44] = None
1279 [45] = None
1280 [46] = None
1281 [47] = None
1282 [48] = None
1283 [49] = None
1284 [50] = None
1285 [51] = None
1286 [52] = None
1287 [53] = None
1288 [54] = None
1289 [55] = None
1290 [56] = None
1291 [57] = None
1292 [58] = None
1293 [59] = None
1294 [60] = None
1295 [61] = None
1296 [62] = None
1297 [63] = None
1298 [64] = None
1299 [65] = None
1300 [66] = None
1301 [67] = None
1302 [68] = None
1303 [69] = None
1304 [70] = None
1305 [71] = None
1306 [72] = None
1307 [73] = None
1308 [74] = None
1309 [75] = None
1310 [76] = None
1311 [77] = None
1312 [78] = None
1313 [79] = None
1314 [80] = None
1315 [81] = None
1316 [82] = None
1317 [83] = None
1318 [84] = None
1319 [85] = None
1320 [86] = None
1321 [87] = None
1322 [88] = None
1323 [89] = None
1324 [90] = None
1325 [91] = None
1326 [92] = None
1327 [93] = None
1328 [94] = None
1329 [95] = None
1330 [96] = None
1331 [97] = None
1332 [98] = None
1333 [99] = None
1334 [100] = None
1335 [101] = None
1336 [102] = None
1337 [103] = None
1338 [104] = None
1339 [105] = None
1340 [106] = None
1341 [107] = None
1342 [108] = None
1343 [109] = None
1344 [110] = None
1345 [111] = None
1346 [112] = None
1347 [113] = None
1348 [114] = None
1349 [115] = None
1350 [116] = None
1351 [117] = None
1352 [118] = None
1353 [119] = None
1354 [120] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 0))
1355 [121] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 1))
1356 [122] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 2))
1357 [123] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 3))
1358 [124] = None
1359 [125] = None
1360 [126] = None
1361 [127] = None
1362
1363Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=0].match_mask to be 0xffff.
1364Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=1].match_mask to be 0xffffff03.
1365Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=2].match_mask to be 0xffffffff.
1366Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=3].match_mask to be 0xf0ffffff.
1367Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_ram_write_data_mux_select to be 7.
1368Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_ram_read_data_mux_select to be 7.
1369Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_result_bus_select to be 1.
1370Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_entry_enable to be 1.
1371Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_ram_logical_table to be 0x0.
1372For entry_in_ram_word 0, should have vpn 1, with lower_two_bits of 1 and upper_vpn of 0
1373for entry_in_ram_word 0, use lsbs of 1
1374Configuring rams.array.row[row=7].ram[column=3].match_ram_vpn.match_ram_vpn0 to be 0.
1375Configuring rams.array.row[row=7].ram[column=3].match_ram_vpn.match_ram_vpn_lsbs to be 0x1.
1376version valid nibbles are : [30]
1377Configuring rams.array.row[row=7].ram[column=3].match_nibble_s0q1_enable.match_nibble_s0q1_enable to be 0xbfffffff.
1378Configuring rams.array.row[row=7].ram[column=3].match_nibble_s1q0_enable.match_nibble_s1q0_enable to be 0xffffffff.
1379Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=0].mask_bytes_0_to_13 to be 0x3fe3.
1380Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=0].mask_nibbles_28_to_31 to be 0xb.
1381Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=1].mask_bytes_0_to_13 to be 0x3fff.
1382Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=1].mask_nibbles_28_to_31 to be 0xf.
1383Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=2].mask_bytes_0_to_13 to be 0x3fff.
1384Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=2].mask_nibbles_28_to_31 to be 0xf.
1385Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=3].mask_bytes_0_to_13 to be 0x3fff.
1386Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=3].mask_nibbles_28_to_31 to be 0xf.
1387Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=4].mask_bytes_0_to_13 to be 0x3fff.
1388Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=4].mask_nibbles_28_to_31 to be 0xf.
1389Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1390Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1391Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1392Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1393Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1394Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1395Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1396Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1397Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1398Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1399Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1400Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1401Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1402Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1403Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1404Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1405Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1406Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1407Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1408Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1409Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1410Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1411Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1412Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1413Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1414Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1415Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
1416Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
1417Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_thread to be 0.
1418Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=3].exactmatch_bank_enable_bank_mask to be 0x0.
1419Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=3].exactmatch_bank_enable_bank_id to be 0x0.
1420Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=3].exactmatch_bank_enable_inp_sel to be 1.
1421Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
1422Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
1423Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=3].enabled_4bit_muxctl_select to be 1.
1424Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=3].enabled_4bit_muxctl_enable to be 1.
1425Configuring rams.match.merge.mau_action_instruction_adr_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_action_instruction_adr_exact_shiftcount to be 0.
1426Configuring rams.match.merge.mau_immediate_data_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_immediate_data_exact_shiftcount to be 0.
1427Configuring rams.match.merge.mau_stats_adr_exact_shiftcount[result_bus_number = 14][entry_in_ram_word=0].mau_stats_adr_exact_shiftcount to be 0x46.
1428Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_type to be 1.
1429Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_logical_table to be 0.
1430Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_ingress to be 1.
1431Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_enable to be 1.
1432Configuring rams.array.row[row=7].emm_ecc_error_uram_ctl[direction=0].emm_ecc_error_uram_ctl to be select of 0x3. (previous value = 0x1 OR new value = 0x2)
1433In Ram Word 0:
1434 wide entry 0 occupied ram word entry 0
1435Configuring rams.match.merge.col[col_number=3].row_action_nxtable_bus_drive[row_number=7].row_action_nxtable_bus_drive to be 1.
1436Configuring rams.match.merge.col[col_number=3].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_select to be 14 (hit signal to output on).
1437Configuring rams.match.merge.col[col_number=3].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1.
1438--> Hash Match Way 2
1439Packed entry for hash way 2 is
1440 [0] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 0))
1441 [1] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 1))
1442 [2] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 2))
1443 [3] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 3))
1444 [4] = (field_bit=4, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 4))
1445 [5] = (field_bit=5, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 5))
1446 [6] = (field_bit=6, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 6))
1447 [7] = (field_bit=7, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 7))
1448 [8] = (field_bit=8, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 8))
1449 [9] = (field_bit=9, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 9))
1450 [10] = (field_bit=10, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 10))
1451 [11] = (field_bit=11, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 11))
1452 [12] = (field_bit=12, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 12))
1453 [13] = (field_bit=13, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 13))
1454 [14] = (field_bit=14, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 14))
1455 [15] = (field_bit=15, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 15))
Carmelo Cascone8aa05482017-09-12 13:21:59 +0200[diff] [blame]1456 [16] = (field_bit=0, hash_match_group_bit=16, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 0))
1457 [17] = (field_bit=1, hash_match_group_bit=17, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 1))
1458 [18] = (field_bit=2, hash_match_group_bit=18, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 2))
1459 [19] = (field_bit=3, hash_match_group_bit=19, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 3))
1460 [20] = (field_bit=4, hash_match_group_bit=20, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 4))
1461 [21] = (field_bit=5, hash_match_group_bit=21, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 5))
1462 [22] = (field_bit=6, hash_match_group_bit=22, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 6))
1463 [23] = (field_bit=7, hash_match_group_bit=23, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 7))
1464 [24] = (field_bit=8, hash_match_group_bit=24, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 8))
1465 [25] = (field_bit=9, hash_match_group_bit=25, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 9))
1466 [26] = (field_bit=10, hash_match_group_bit=26, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 10))
1467 [27] = (field_bit=11, hash_match_group_bit=27, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 11))
1468 [28] = (field_bit=12, hash_match_group_bit=28, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 12))
1469 [29] = (field_bit=13, hash_match_group_bit=29, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 13))
1470 [30] = (field_bit=14, hash_match_group_bit=30, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 14))
1471 [31] = (field_bit=15, hash_match_group_bit=31, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 15))
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1472 [32] = None
1473 [33] = None
1474 [34] = (field_bit=10, hash_match_group_bit=10, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 10))
1475 [35] = (field_bit=11, hash_match_group_bit=11, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 11))
1476 [36] = (field_bit=12, hash_match_group_bit=12, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 12))
1477 [37] = (field_bit=13, hash_match_group_bit=13, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 13))
1478 [38] = (field_bit=14, hash_match_group_bit=14, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 14))
1479 [39] = (field_bit=15, hash_match_group_bit=15, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 15))
1480 [40] = None
1481 [41] = None
1482 [42] = None
1483 [43] = None
1484 [44] = None
1485 [45] = None
1486 [46] = None
1487 [47] = None
1488 [48] = None
1489 [49] = None
1490 [50] = None
1491 [51] = None
1492 [52] = None
1493 [53] = None
1494 [54] = None
1495 [55] = None
1496 [56] = None
1497 [57] = None
1498 [58] = None
1499 [59] = None
1500 [60] = None
1501 [61] = None
1502 [62] = None
1503 [63] = None
1504 [64] = None
1505 [65] = None
1506 [66] = None
1507 [67] = None
1508 [68] = None
1509 [69] = None
1510 [70] = None
1511 [71] = None
1512 [72] = None
1513 [73] = None
1514 [74] = None
1515 [75] = None
1516 [76] = None
1517 [77] = None
1518 [78] = None
1519 [79] = None
1520 [80] = None
1521 [81] = None
1522 [82] = None
1523 [83] = None
1524 [84] = None
1525 [85] = None
1526 [86] = None
1527 [87] = None
1528 [88] = None
1529 [89] = None
1530 [90] = None
1531 [91] = None
1532 [92] = None
1533 [93] = None
1534 [94] = None
1535 [95] = None
1536 [96] = None
1537 [97] = None
1538 [98] = None
1539 [99] = None
1540 [100] = None
1541 [101] = None
1542 [102] = None
1543 [103] = None
1544 [104] = None
1545 [105] = None
1546 [106] = None
1547 [107] = None
1548 [108] = None
1549 [109] = None
1550 [110] = None
1551 [111] = None
1552 [112] = None
1553 [113] = None
1554 [114] = None
1555 [115] = None
1556 [116] = None
1557 [117] = None
1558 [118] = None
1559 [119] = None
1560 [120] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 0))
1561 [121] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 1))
1562 [122] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 2))
1563 [123] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 3))
1564 [124] = None
1565 [125] = None
1566 [126] = None
1567 [127] = None
1568
1569Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=0].match_mask to be 0xffff.
1570Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=1].match_mask to be 0xffffff03.
1571Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=2].match_mask to be 0xffffffff.
1572Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=3].match_mask to be 0xf0ffffff.
1573Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_ram_write_data_mux_select to be 7.
1574Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_ram_read_data_mux_select to be 7.
1575Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_result_bus_select to be 1.
1576Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_entry_enable to be 1.
1577Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_ram_logical_table to be 0x0.
1578For entry_in_ram_word 0, should have vpn 2, with lower_two_bits of 2 and upper_vpn of 0
1579for entry_in_ram_word 0, use lsbs of 2
1580Configuring rams.array.row[row=7].ram[column=4].match_ram_vpn.match_ram_vpn0 to be 0.
1581Configuring rams.array.row[row=7].ram[column=4].match_ram_vpn.match_ram_vpn_lsbs to be 0x2.
1582version valid nibbles are : [30]
1583Configuring rams.array.row[row=7].ram[column=4].match_nibble_s0q1_enable.match_nibble_s0q1_enable to be 0xbfffffff.
1584Configuring rams.array.row[row=7].ram[column=4].match_nibble_s1q0_enable.match_nibble_s1q0_enable to be 0xffffffff.
1585Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=0].mask_bytes_0_to_13 to be 0x3fe3.
1586Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=0].mask_nibbles_28_to_31 to be 0xb.
1587Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=1].mask_bytes_0_to_13 to be 0x3fff.
1588Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=1].mask_nibbles_28_to_31 to be 0xf.
1589Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=2].mask_bytes_0_to_13 to be 0x3fff.
1590Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=2].mask_nibbles_28_to_31 to be 0xf.
1591Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=3].mask_bytes_0_to_13 to be 0x3fff.
1592Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=3].mask_nibbles_28_to_31 to be 0xf.
1593Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=4].mask_bytes_0_to_13 to be 0x3fff.
1594Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=4].mask_nibbles_28_to_31 to be 0xf.
1595Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1596Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1597Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1598Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1599Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1600Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1601Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1602Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12.
1603Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1604Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1605Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1606Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1607Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1608Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1609Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1610Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13.
1611Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1612Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1613Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1614Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1615Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1616Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11.
1617Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1618Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1619Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1620Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8.
1621Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
1622Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
1623Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_thread to be 0.
1624Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=4].exactmatch_bank_enable_bank_mask to be 0x0.
1625Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=4].exactmatch_bank_enable_bank_id to be 0x0.
1626Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=4].exactmatch_bank_enable_inp_sel to be 1.
1627Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
1628Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
1629Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=4].enabled_4bit_muxctl_select to be 2.
1630Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=4].enabled_4bit_muxctl_enable to be 1.
1631Configuring rams.match.merge.mau_action_instruction_adr_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_action_instruction_adr_exact_shiftcount to be 0.
1632Configuring rams.match.merge.mau_immediate_data_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_immediate_data_exact_shiftcount to be 0.
1633Configuring rams.match.merge.mau_stats_adr_exact_shiftcount[result_bus_number = 14][entry_in_ram_word=0].mau_stats_adr_exact_shiftcount to be 0x46.
1634Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_type to be 1.
1635Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_logical_table to be 0.
1636Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_ingress to be 1.
1637Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_enable to be 1.
1638Configuring rams.array.row[row=7].emm_ecc_error_uram_ctl[direction=0].emm_ecc_error_uram_ctl to be select of 0x7. (previous value = 0x3 OR new value = 0x4)
1639In Ram Word 0:
1640 wide entry 0 occupied ram word entry 0
1641Configuring rams.match.merge.col[col_number=4].row_action_nxtable_bus_drive[row_number=7].row_action_nxtable_bus_drive to be 1.
1642Configuring rams.match.merge.col[col_number=4].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_select to be 14 (hit signal to output on).
1643Configuring rams.match.merge.col[col_number=4].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1.
1644
1645+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1646| Working on table ecmp_group_table_counter in stage 1 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1647+------------------------------------------------------------------------
1648Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
1649Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
1650Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
1651Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
1652Note that unitram_vpn does not need to be programmed for synthetic two port rams.
1653Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0.
1654Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
1655Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
1656Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
1657Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
1658Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
1659Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
1660Note that unitram_vpn does not need to be programmed for synthetic two port rams.
1661Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0.
1662Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
1663Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
1664Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
1665Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
1666Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
1667Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
1668Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
1669Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
1670Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
1671Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
1672Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
1673Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
1674Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
1675Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
1676Stat table ecmp_group_table_counter is used by match table ecmp_group_table.
1677Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8)
1678Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
1679Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
1680Note that map ram vpn does not need to be configured for synthetic two port map rams.
1681Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
1682Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
1683Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
1684Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
1685Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
1686Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
1687Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
1688Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
1689Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0.
1690Note that map ram vpn does not need to be configured for synthetic two port map rams.
1691Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
1692Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
1693Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
1694Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
1695Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
1696Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
1697Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
1698For counter width 32 and N = 4096
1699 number iterations = 32
1700 b_cur = 379488672.0
1701 eqn(b_cur) = 4294964039.26
1702 max_counter_value = 4294967295
1703Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
1704Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
1705Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
1706Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
1707Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
1708Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
1709Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4.
1710Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1.
1711Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1.
1712TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0.
1713Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x0.
1714Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4.
1715Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1.
1716Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0.
1717Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0.
1718Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0.
1719Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0.
1720Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0.
1721Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
1722Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
1723Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1.
1724Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3.
1725Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_direct be 1.
1726Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=0].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1)
1727Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x0.
1728Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x7. ( previous value = 0x0 OR new value = 0x7)
1729Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x1.
1730+------------------------------------------------------------------------
1731Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19.
1732Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
1733Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
1734Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1735Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1736Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1737Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1738Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1739Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1740Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1741Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1742Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x1.
1743Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1744Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1745Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1746Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x40.
1747Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1748Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1749Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1750Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
1751Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1752Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1753Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
1754Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1755Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1756Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1757Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1758Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1759--------------------------------------------
1760Configuration for unused statistics ALUs.
1761Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1762Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1763Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1764+------------------------------------------------------------------------
1765Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
1766Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
1767Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1768Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
1769Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
1770Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1771Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
1772Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
1773Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1774Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1775Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1776Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1777Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1778Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1779Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1780Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1781Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1782Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1783Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1784Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1785Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1786Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1787Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1788Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1789Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1790Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1791Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1792+------------------------------------------------------------------------
1793Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1794Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1795Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
1796Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
1797Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1798Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1799Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1800Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
1801Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1.
1802Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2.
1803Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1804Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1805Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1806Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1807
1808+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1809| MAU Stage 2
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1810+------------------------------------------------------------------------
1811
1812+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1813| Working on table _condition_2 in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1814+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1815--> Stage Gateway Table for condition _condition_2 in stage 2
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1816Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
1817Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
1818Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
1819Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
1820Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
1821Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
1822Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
1823Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
1824Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 18.
1825Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
1826Configuring match input crossbar byte 0 to come from 16-bit PHV container 2.
1827 That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
1828Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 18.
1829Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
1830Configuring match input crossbar byte 1 to come from 16-bit PHV container 2.
1831 That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
1832Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
1833Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
1834Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
1835Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte1 to be 0x1.
1836Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=41].byte0 to be 0x1.
1837Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=42].byte0 to be 0x2.
1838Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=43].byte0 to be 0x4.
1839Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=44].byte0 to be 0x8.
1840Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=45].byte0 to be 0x10.
1841Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=46].byte0 to be 0x20.
1842Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=47].byte0 to be 0x40.
1843Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=48].byte0 to be 0x80.
1844Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
1845Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
1846Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
1847Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
1848Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
1849Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
1850Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
1851Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
1852Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
1853Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0
1854Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0
1855Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
1856Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
1857Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
1858Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
1859Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
1860Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_mode to be 0x2
1861Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff
1862Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff3f
1863Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1864Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x21
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1865Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid0 to be 0x3
1866Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid1 to be 0x3
1867Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][0] to be 0xffffffff
1868Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][1] to be 0xffffffff
1869Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xffffff
1870Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff7fff
1871Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xc (previous value 0x8 OR new value 0x4)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1872Configuring rams.match.merge.gateway_next_table_lut[0][2] to be 0x21
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1873Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid0 to be 0x3
1874Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid1 to be 0x3
1875Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][0] to be 0xffffffff
1876Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][1] to be 0xffffffff
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1877Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0x1ffff
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1878Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][1] to be 0xffff
1879Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xe (previous value 0xc OR new value 0x2)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1880Configuring rams.match.merge.gateway_next_table_lut[0][1] to be 0x21
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1881Configuring rams.match.merge.gateway_en.gateway_en to be 0x1
1882Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf
1883Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1
1884allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
1885Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x0
1886Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1
1887Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2
1888Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x1
1889Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0
1890Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x1
1891Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0
1892Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff
1893Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff
1894
1895+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1896| Working on table ingress_port_count_table__action__ in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1897+------------------------------------------------------------------------
1898--> Action Data Table ingress_port_count_table__action__ with logical_table_id 0 that is reference type is 'direct'
1899
1900+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1901| Working on table ingress_port_count_table in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1902+------------------------------------------------------------------------
1903--> Match Table with no key ingress_port_count_table with logical_table_id 0
1904allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
1905Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
1906Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
1907Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
1908Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
1909Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
1910Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
1911Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id).
1912Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
1913Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id).
1914Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
1915Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x0.
1916Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x1.
1917Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0xff.
1918Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=1].mau_stats_adr_default to be 0x0.
1919Configuring rams.match.merge.mau_stats_adr_per_entry_en_mux_ctl[table_type_index=0][result_bus_number=1].mau_stats_adr_per_entry_en_mux_ctl to be 0x7.
1920Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
1921Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2000.
1922Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
1923Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].stats_adr_payload_shifter_en to be 1.
1924Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
1925
1926+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1927| Working on table egress_port_count_table__action__ in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1928+------------------------------------------------------------------------
1929--> Action Data Table egress_port_count_table__action__ with logical_table_id 1 that is reference type is 'direct'
1930
1931+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1932| Working on table egress_port_count_table in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1933+------------------------------------------------------------------------
1934--> Match Table with no key egress_port_count_table with logical_table_id 1
1935allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
1936Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
1937Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
1938Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
1939Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
1940Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
1941Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
1942Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id).
1943Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
1944Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id).
1945Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
1946Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_default to be 0x40.
1947Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x0.
1948Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0xff.
1949Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0xff.
1950Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=0].mau_stats_adr_default to be 0x80000.
1951Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2).
1952Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x40.
1953Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1954--> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 2
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]1955Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
1956Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
1957Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
1958Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
1959Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
1960Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
1961Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x0)
1962Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
1963Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x0)
1964Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
1965Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
1966Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
1967Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
1968Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
1969Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
1970Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1
1971Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0
1972Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
1973Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
1974Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
1975Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff
1976Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff
1977Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff
1978Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff
1979Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8
1980Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0xff
1981Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10)
1982Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0xff
1983Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2)
1984Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe
1985Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1
1986allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
1987Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_logical_select to be 0x1
1988Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_inhibit_enable to be 0x1
1989Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x3 (previous value 0x2 OR new value 0x1)
1990Configuring rams.match.merge.gateway_payload_data[0][0][0][0].gateway_payload_data to be 0x0
1991Configuring rams.match.merge.gateway_payload_data[0][0][1][0].gateway_payload_data to be 0x0
1992Configuring rams.match.merge.gateway_payload_data[0][0][0][1].gateway_payload_data to be 0x0
1993Configuring rams.match.merge.gateway_payload_data[0][0][1][1].gateway_payload_data to be 0x0
1994Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff
1995Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff
1996Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=0].action_instruction_adr_payload_shifter_en to be 1.
1997
1998+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1999| Working on table ingress_port_counter in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2000+------------------------------------------------------------------------
2001Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
2002Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
2003Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
2004Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
2005Note that unitram_vpn does not need to be programmed for synthetic two port rams.
2006Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0.
2007Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
2008Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
2009Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
2010Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
2011Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
2012Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
2013Note that unitram_vpn does not need to be programmed for synthetic two port rams.
2014Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0.
2015Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
2016Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
2017Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
2018Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
2019Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
2020Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
2021Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
2022Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1.
2023Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
2024Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
2025Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
2026Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
2027Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
2028Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1.
2029Stat table ingress_port_counter is used by match table ingress_port_count_table.
2030Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x4. (previous value = 0x0 OR new value =0x4)
2031Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
2032Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
2033Note that map ram vpn does not need to be configured for synthetic two port map rams.
2034Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
2035Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
2036Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
2037Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
2038Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
2039Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
2040Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
2041Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
2042Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0.
2043Note that map ram vpn does not need to be configured for synthetic two port map rams.
2044Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
2045Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
2046Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
2047Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
2048Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
2049Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
2050Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
2051For counter width 32 and N = 4096
2052 number iterations = 32
2053 b_cur = 379488672.0
2054 eqn(b_cur) = 4294964039.26
2055 max_counter_value = 4294967295
2056Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
2057Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
2058Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
2059Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
2060Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
2061Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
2062Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_entries_per_word to be 4.
2063Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_process_packets to be 1.
2064Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.lrt_enable to be 1.
2065TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_alu_error_enable to be 0.
2066Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0x0.
2067Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4.
2068Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1.
2069Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0.
2070Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0.
2071Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=2].stats_lrt_fsm_sweep_size to be 0x0.
2072Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=2].stats_lrt_fsm_sweep_offset to be 0x0.
2073Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=2].stats_lrt_sweep_adr to be 0x0.
2074Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
2075Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
2076Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=2].packet_action_at_headertime be 1.
2077Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_size be 3.
2078Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_lt be 0x0.
2079Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x6. ( previous value = 0x0 OR new value = 0x6)
2080Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=2].mau_ad_stats_virt_lt be 0x1.
2081
2082+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2083| Working on table egress_port_counter in stage 2 ---
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2084+------------------------------------------------------------------------
2085Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
2086Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
2087Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
2088Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
2089Note that unitram_vpn does not need to be programmed for synthetic two port rams.
2090Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 1.
2091Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
2092Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
2093Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
2094Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
2095Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
2096Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
2097Note that unitram_vpn does not need to be programmed for synthetic two port rams.
2098Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 1.
2099Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
2100Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
2101Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
2102Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
2103Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
2104Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
2105Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
2106Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
2107Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
2108Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
2109Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
2110Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
2111Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
2112Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
2113Stat table egress_port_counter is used by match table egress_port_count_table.
2114Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=1].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8)
2115Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
2116Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 1.
2117Note that map ram vpn does not need to be configured for synthetic two port map rams.
2118Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
2119Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
2120Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
2121Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
2122Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
2123Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
2124Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
2125Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
2126Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 1.
2127Note that map ram vpn does not need to be configured for synthetic two port map rams.
2128Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
2129Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
2130Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
2131Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
2132Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
2133Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
2134Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
2135For counter width 32 and N = 4096
2136 number iterations = 32
2137 b_cur = 379488672.0
2138 eqn(b_cur) = 4294964039.26
2139 max_counter_value = 4294967295
2140Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
2141Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
2142Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
2143Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
2144Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
2145Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
2146Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4.
2147Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1.
2148Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1.
2149TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0.
2150Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x1.
2151Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_entries_per_word be 0x4.
2152Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_has_packets be 0x1.
2153Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_offset be 0x0.
2154Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_size be 0x0.
2155Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0.
2156Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0.
2157Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0.
2158Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
2159Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
2160Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1.
2161Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3.
2162Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x1.
2163Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=3].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x3e. ( previous value = 0x6 OR new value = 0x38)
2164Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x2.
2165+------------------------------------------------------------------------
2166Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19.
2167Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
2168Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
2169Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2170Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2171Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2172Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2173Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2174Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2175Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2176Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2177Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x3.
2178Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2179Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2180Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x3.
2181Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2182Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2183Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2184Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2185Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2186Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2187Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2188Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2189Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2190Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2191Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2192Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2193Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2194--------------------------------------------
2195Configuration for unused statistics ALUs.
2196Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2197Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2198+------------------------------------------------------------------------
2199Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2200Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2201Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2202Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
2203Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
2204Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2205Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2206Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2207Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2208Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2209Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2210Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2211Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2212Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2213Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2214Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2215Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2216Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2217Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2218Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2219Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2220Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2221Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2222Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2223Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2224Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2225Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2226+------------------------------------------------------------------------
2227Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2228Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2229Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
2230Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2231Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2232Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2233Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2234Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2235Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1.
2236Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2.
2237Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2238Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2239Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2240Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2241
2242+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2243| MAU Stage 3
2244+------------------------------------------------------------------------
2245+------------------------------------------------------------------------
2246Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2247Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2248Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2249Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2250Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2251Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2252Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2253Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2254Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2255Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2256Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2257Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2258Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2259Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2260Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2261Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2262Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2263Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2264Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2265Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2266Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2267Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2268Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2269Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2270Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2271Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2272Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2273Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2274--------------------------------------------
2275Configuration for unused statistics ALUs.
2276Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2277Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2278Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2279Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2280+------------------------------------------------------------------------
2281Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2282Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2283Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
2284Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
2285Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
2286Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
2287Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2288Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2289Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
2290Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2291Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2292Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2293Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2294Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2295Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
2296Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2297Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2298Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2299Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2300Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2301Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2302Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2303Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2304Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2305Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2306Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2307Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2308+------------------------------------------------------------------------
2309Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2310Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2311Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2312Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2313Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2314Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2315Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2316Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2317Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2318Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2319Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2320Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2321Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2322Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2323
2324+------------------------------------------------------------------------
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2325| MAU Stage 4
2326+------------------------------------------------------------------------
2327+------------------------------------------------------------------------
2328Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2329Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2330Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2331Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2332Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2333Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2334Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2335Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2336Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2337Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2338Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2339Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2340Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2341Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2342Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2343Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2344Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2345Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2346Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2347Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2348Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2349Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2350Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2351Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2352Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2353Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2354Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2355Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2356--------------------------------------------
2357Configuration for unused statistics ALUs.
2358Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2359Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2360Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2361Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2362+------------------------------------------------------------------------
2363Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2364Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2365Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2366Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
2367Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
2368Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2369Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2370Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2371Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2372Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2373Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2374Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2375Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2376Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2377Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2378Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2379Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2380Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2381Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2382Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2383Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2384Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2385Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2386Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2387Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2388Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2389Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2390+------------------------------------------------------------------------
2391Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2392Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2393Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2394Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2395Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2396Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2397Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2398Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2399Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2400Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2401Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2402Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2403Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2404Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2405
2406+------------------------------------------------------------------------
2407| MAU Stage 5
2408+------------------------------------------------------------------------
2409+------------------------------------------------------------------------
2410Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2411Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2412Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2413Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2414Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2415Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2416Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2417Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2418Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2419Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2420Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2421Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2422Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2423Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2424Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2425Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2426Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2427Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2428Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2429Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
2430Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2431Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2432Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19.
2433Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2434Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2435Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2436Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2437Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2438--------------------------------------------
2439Configuration for unused statistics ALUs.
2440Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2441Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2442Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2443Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2444+------------------------------------------------------------------------
2445Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2446Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2447Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2448Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
2449Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
2450Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2451Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2452Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2453Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2454Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2455Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2456Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2457Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2458Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2459Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2460Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2461Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2462Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2463Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2464Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2465Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2466Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2467Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2468Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2469Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2470Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2471Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2472+------------------------------------------------------------------------
2473Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2474Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2475Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2476Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
2477Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2478Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2479Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2480Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0.
2481Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2482Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2483Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2484Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2485Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2486Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2487
2488+------------------------------------------------------------------------
2489| MAU Stage 6
2490+------------------------------------------------------------------------
2491+------------------------------------------------------------------------
2492Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19.
2493Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
2494Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
2495Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 19.
2496Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 9.
2497Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 3.
2498Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2499Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2500Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2501Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2502Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2503Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2504Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2505Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2506Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2507Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2508Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2509Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2510Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2511Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2512Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2513Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2514Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2515Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2516Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2517Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2518Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2519Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2520--------------------------------------------
2521Configuration for unused statistics ALUs.
2522Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2523Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2524Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2525Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2526+------------------------------------------------------------------------
2527Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2528Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2529Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2530Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
2531Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
2532Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2533Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2534Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2535Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2536Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2537Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2538Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2539Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2540Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2541Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2542Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2543Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2544Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2545Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2546Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2547Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2548Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2549Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2550Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2551Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2552Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2553Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2554+------------------------------------------------------------------------
2555Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2556Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2557Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
2558Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2559Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2560Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2561Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0.
2562Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2563Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 3.
2564Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0.
2565Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2566Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2567Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2568Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2569
2570+------------------------------------------------------------------------
2571| MAU Stage 7
2572+------------------------------------------------------------------------
2573+------------------------------------------------------------------------
2574Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2575Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2576Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2577Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2578Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2579Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2580Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2581Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2582Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2583Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2584Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2585Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2586Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2587Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2588Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2589Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2590Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2591Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2592Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2593Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2594Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2595Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2596Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2597Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2598Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2599Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2600Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2601Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2602--------------------------------------------
2603Configuration for unused statistics ALUs.
2604Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2605Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2606Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2607Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2608+------------------------------------------------------------------------
2609Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2610Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2611Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2612Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
2613Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
2614Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2615Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2616Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2617Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2618Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2619Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2620Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2621Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2622Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2623Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2624Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2625Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2626Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2627Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2628Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2629Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2630Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2631Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2632Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2633Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2634Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2635Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2636+------------------------------------------------------------------------
2637Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2638Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2639Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2640Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2641Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2642Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2643Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2644Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2645Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2646Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2647Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2648Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2649Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2650Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2651
2652+------------------------------------------------------------------------
2653| MAU Stage 8
2654+------------------------------------------------------------------------
2655+------------------------------------------------------------------------
2656Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2657Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2658Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2659Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2660Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2661Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2662Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2663Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2664Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2665Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2666Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2667Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2668Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2669Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2670Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2671Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2672Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2673Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2674Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2675Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2676Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2677Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2678Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2679Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2680Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2681Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2682Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2683Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2684--------------------------------------------
2685Configuration for unused statistics ALUs.
2686Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2687Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2688Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2689Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2690+------------------------------------------------------------------------
2691Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2692Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2693Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2694Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
2695Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
2696Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2697Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2698Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2699Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2700Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2701Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2702Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2703Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2704Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2705Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2706Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2707Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2708Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2709Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2710Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2711Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2712Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2713Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2714Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2715Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2716Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2717Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2718+------------------------------------------------------------------------
2719Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2720Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2721Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2722Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2723Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2724Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2725Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2726Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2727Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2728Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2729Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2730Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2731Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2732Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2733
2734+------------------------------------------------------------------------
2735| MAU Stage 9
2736+------------------------------------------------------------------------
2737+------------------------------------------------------------------------
2738Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2739Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2740Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2741Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2742Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2743Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2744Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2745Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2746Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2747Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2748Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2749Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2750Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2751Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2752Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2753Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2754Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2755Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2756Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2757Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2758Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2759Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2760Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2761Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2762Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2763Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2764Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2765Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2766--------------------------------------------
2767Configuration for unused statistics ALUs.
2768Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2769Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2770Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2771Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2772+------------------------------------------------------------------------
2773Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2774Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2775Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2776Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
2777Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
2778Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2779Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2780Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2781Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2782Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2783Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2784Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2785Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2786Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2787Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2788Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2789Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2790Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2791Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2792Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2793Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2794Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2795Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2796Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2797Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2798Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2799Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2800+------------------------------------------------------------------------
2801Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2802Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2803Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2804Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2805Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2806Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2807Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2808Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2809Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2810Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2811Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2812Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2813Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2814Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2815
2816+------------------------------------------------------------------------
2817| MAU Stage 10
2818+------------------------------------------------------------------------
2819+------------------------------------------------------------------------
2820Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2821Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2822Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2823Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2824Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2825Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2826Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2827Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2828Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2829Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2830Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2831Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2832Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2833Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2834Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2835Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2836Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2837Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2838Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2839Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
2840Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2841Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2842Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
2843Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2844Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2845Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2846Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2847Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2848--------------------------------------------
2849Configuration for unused statistics ALUs.
2850Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2851Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2852Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2853Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2854+------------------------------------------------------------------------
2855Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2856Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2857Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2858Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
2859Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
2860Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2861Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2862Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2863Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2864Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2865Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2866Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2867Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2868Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2869Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2870Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2871Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2872Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2873Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2874Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2875Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2876Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2877Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2878Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2879Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2880Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2881Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2882+------------------------------------------------------------------------
2883Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2884Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2885Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2886Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
2887Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2888Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2889Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2890Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
2891Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2892Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2893Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2894Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2895Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2896Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2897
2898+------------------------------------------------------------------------
2899| MAU Stage 11
2900+------------------------------------------------------------------------
2901+------------------------------------------------------------------------
2902Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
2903Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
2904Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
2905Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
2906Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
2907Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
2908Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
2909Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
2910Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
2911Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
2912Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
2913Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
2914Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
2915Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
2916Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
2917Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
2918Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
2919Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
2920Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
2921Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
2922Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
2923Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
2924Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19.
2925Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
2926Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
2927Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
2928Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
2929Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
2930--------------------------------------------
2931Configuration for unused statistics ALUs.
2932Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
2933Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
2934Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
2935Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
2936+------------------------------------------------------------------------
2937Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
2938Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
2939Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2940Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
2941Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
2942Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2943Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
2944Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
2945Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2946Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
2947Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
2948Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
2949Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
2950Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
2951Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2952Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
2953Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
2954Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
2955Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
2956Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
2957Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
2958Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
2959Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
2960Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
2961Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
2962Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
2963Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
2964+------------------------------------------------------------------------
2965Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
2966Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
2967Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
2968Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
2969Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
2970Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
2971Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
2972Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0.
2973Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
2974Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
2975Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
2976Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
2977Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
2978Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
2979
2980+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2981| Number of configuration field values set in Match-Action Stages: 2100
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2982+------------------------------------------------------------------------
2983
2984+------------------------------------------------------------------------
2985| MAU Feature Characteristics:
2986+------------------------------------------------------------------------
2987
2988
2989Features per Stage for ingress:
2990-----------------------------------------------------------------------------------------------
2991| Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency |
2992| | | | | LPF | (max words) | | to Previous |
2993-----------------------------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2994| 0 | Yes | Yes | Yes | No | No (0) | No | match |
2995| 1 | Yes | No | Yes | No | No (0) | No | match |
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2996| 2 | Yes | No | Yes | No | No (0) | No | match |
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2997| 3 | Yes* | No | Yes* | No | No (0) | No | concurrent |
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]2998| 4 | Yes* | No | Yes* | No | No (0) | No | concurrent |
2999| 5 | Yes* | No | Yes* | No | No (0) | No | concurrent |
3000| 6 | No | No | No | No | No (0) | No | match |
3001| 7 | No | No | No | No | No (0) | No | concurrent |
3002| 8 | No | No | No | No | No (0) | No | concurrent |
3003| 9 | No | No | No | No | No (0) | No | concurrent |
3004| 10 | No | No | No | No | No (0) | No | concurrent |
3005| 11 | No | No | No | No | No (0) | No | concurrent |
3006-----------------------------------------------------------------------------------------------
3007
3008A '*' denotes that this feature was added to balance an action/concurrent chain.
3009
3010
3011Features per Stage for egress:
3012-----------------------------------------------------------------------------------------------
3013| Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency |
3014| | | | | LPF | (max words) | | to Previous |
3015-----------------------------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]3016| 0 | No | No | No | No | No (0) | No | match |
3017| 1 | No | No | No | No | No (0) | No | concurrent |
3018| 2 | No | No | No | No | No (0) | No | concurrent |
3019| 3 | No | No | No | No | No (0) | No | concurrent |
3020| 4 | No | No | No | No | No (0) | No | concurrent |
3021| 5 | No | No | No | No | No (0) | No | concurrent |
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3022| 6 | No | No | No | No | No (0) | No | match |
3023| 7 | No | No | No | No | No (0) | No | concurrent |
3024| 8 | No | No | No | No | No (0) | No | concurrent |
3025| 9 | No | No | No | No | No (0) | No | concurrent |
3026| 10 | No | No | No | No | No (0) | No | concurrent |
3027| 11 | No | No | No | No | No (0) | No | concurrent |
3028-----------------------------------------------------------------------------------------------
3029
3030A '*' denotes that this feature was added to balance an action/concurrent chain.
3031
3032+------------------------------------------------------------------------
3033| MAU Latency Characteristics:
3034+------------------------------------------------------------------------
3035
3036
3037Clock Cycles Per Stage For ingress:
3038-----------------------------------------------------------------------------------------------------
3039| Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency |
3040-----------------------------------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]3041| 0 | 22 | 13 | match | 22 |
3042| 1 | 20 | 11 | match | 20 |
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3043| 2 | 20 | 11 | match | 20 |
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]3044| 3 | 20 | 11 | concurrent | 1 |
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3045| 4 | 20 | 11 | concurrent | 1 |
3046| 5 | 20 | 11 | concurrent | 1 |
3047| 6 | 20 | 11 | match | 20 |
3048| 7 | 20 | 11 | concurrent | 1 |
3049| 8 | 20 | 11 | concurrent | 1 |
3050| 9 | 20 | 11 | concurrent | 1 |
3051| 10 | 20 | 11 | concurrent | 1 |
3052| 11 | 20 | 11 | concurrent | 1 |
3053-----------------------------------------------------------------------------------------------------
3054
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]3055Total latency for ingress: 94
Carmelo Casconef1d0a422017-09-07 17:21:46 +0200[diff] [blame]3056
3057
3058Clock Cycles Per Stage For egress:
3059-----------------------------------------------------------------------------------------------------
3060| Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency |
3061-----------------------------------------------------------------------------------------------------
3062| 0 | 20 | 11 | match | 20 |
3063| 1 | 20 | 11 | concurrent | 1 |
3064| 2 | 20 | 11 | concurrent | 1 |
3065| 3 | 20 | 11 | concurrent | 1 |
3066| 4 | 20 | 11 | concurrent | 1 |
3067| 5 | 20 | 11 | concurrent | 1 |
3068| 6 | 20 | 11 | match | 20 |
3069| 7 | 20 | 11 | concurrent | 1 |
3070| 8 | 20 | 11 | concurrent | 1 |
3071| 9 | 20 | 11 | concurrent | 1 |
3072| 10 | 20 | 11 | concurrent | 1 |
3073| 11 | 20 | 11 | concurrent | 1 |
3074-----------------------------------------------------------------------------------------------------
3075
3076Total latency for egress: 54