Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1 | +---------------------------------------------------------------------+ |
| 2 | | Log file: mau.config.log | |
| 3 | | Compiler version: 5.1.0 (fca32d1) | |
Carmelo Cascone | 133c7b1 | 2017-09-13 15:36:08 +0200 | [diff] [blame] | 4 | | Created on: Wed Sep 13 12:57:41 2017 | |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 5 | +---------------------------------------------------------------------+ |
| 6 | |
| 7 | Final Stage dependencies are: |
| 8 | (0, 'ingress') : match |
| 9 | (1, 'ingress') : match |
| 10 | (2, 'ingress') : match |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 11 | (3, 'ingress') : concurrent |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 12 | (4, 'ingress') : concurrent |
| 13 | (5, 'ingress') : concurrent |
| 14 | (6, 'ingress') : match |
| 15 | (7, 'ingress') : concurrent |
| 16 | (8, 'ingress') : concurrent |
| 17 | (9, 'ingress') : concurrent |
| 18 | (10, 'ingress') : concurrent |
| 19 | (11, 'ingress') : concurrent |
| 20 | (0, 'egress') : match |
| 21 | (1, 'egress') : concurrent |
| 22 | (2, 'egress') : concurrent |
| 23 | (3, 'egress') : concurrent |
| 24 | (4, 'egress') : concurrent |
| 25 | (5, 'egress') : concurrent |
| 26 | (6, 'egress') : match |
| 27 | (7, 'egress') : concurrent |
| 28 | (8, 'egress') : concurrent |
| 29 | (9, 'egress') : concurrent |
| 30 | (10, 'egress') : concurrent |
| 31 | (11, 'egress') : concurrent |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 32 | Action/Concurrent chaining in ingress consists of [3, 4, 5] |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 33 | Action/Concurrent chaining in ingress consists of [7, 8, 9, 10, 11] |
| 34 | Action/Concurrent chaining in egress consists of [1, 2, 3, 4, 5] |
| 35 | Action/Concurrent chaining in egress consists of [7, 8, 9, 10, 11] |
| 36 | |
| 37 | +------------------------------------------------------------------------ |
| 38 | | MAU Stage 0 |
| 39 | +------------------------------------------------------------------------ |
| 40 | |
| 41 | +------------------------------------------------------------------------ |
| 42 | | Working on table _condition_0 in stage 0 --- |
| 43 | +------------------------------------------------------------------------ |
| 44 | --> Stage Gateway Table for condition _condition_0 in stage 0 |
| 45 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 46 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 47 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 48 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 49 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 50 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 51 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x2. (old value = 0x0 OR new value = 0x2) |
| 52 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 53 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_address to be 4. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 54 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 55 | Configuring match input crossbar byte 12 to come from 8-bit PHV container 4. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 56 | That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 57 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 58 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2) |
| 59 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| 60 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=6][hash_bit_index=40].byte0 to be 0x2. |
| 61 | Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 62 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0. |
| 63 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1. |
| 64 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0. |
| 65 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1. |
| 66 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| 67 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| 68 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| 69 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| 70 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0 |
| 71 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0 |
| 72 | Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| 73 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| 74 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| 75 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| 76 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| 77 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff |
| 78 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xfffffe |
| 79 | Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x10 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 80 | Configuring rams.match.merge.gateway_next_table_lut[0][4] to be 0x1 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 81 | Configuring rams.match.merge.gateway_en.gateway_en to be 0x1 |
| 82 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf |
| 83 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1 |
| 84 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_logical_select to be 0x0 |
| 85 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_inhibit_enable to be 0x1 |
| 86 | Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff |
| 87 | Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff |
| 88 | |
| 89 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 90 | | Working on table process_packet_out_table__action__ in stage 0 --- |
| 91 | +------------------------------------------------------------------------ |
| 92 | --> Action Data Table process_packet_out_table__action__ with logical_table_id 1 that is reference type is 'direct' |
| 93 | |
| 94 | +------------------------------------------------------------------------ |
| 95 | | Working on table process_packet_out_table in stage 0 --- |
| 96 | +------------------------------------------------------------------------ |
| 97 | --> Match Table with no key process_packet_out_table with logical_table_id 1 |
| 98 | allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits |
| 99 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 100 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 101 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 102 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 103 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 104 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 105 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 1 (logical table id). |
| 106 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1. |
| 107 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 1 (logical table id). |
| 108 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1. |
| 109 | Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x40. |
| 110 | Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x0. |
| 111 | Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0x20. |
| 112 | Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0x20. |
| 113 | Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x2 (previous_value=0x0 OR new_value=0x2). |
| 114 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x45. |
| 115 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
| 116 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_instr to be 0x74412. |
| 117 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_color to be 1. |
| 118 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_parity to be 0. |
| 119 | Micro instruction added in VLIW 2 for 16-bit position 2 for table process_packet_out_table. |
| 120 | Assembled as 0x74412 (or decimal 476178) |
| 121 | Micro Instruction deposit-field for PHV Container 130 has bit width 23 |
| 122 | Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| 123 | Field Src1 [4:0] : 0x1 (5 bits in instruction bits [8:4]) |
| 124 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 125 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 126 | Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11]) |
| 127 | Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15]) |
| 128 | Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16]) |
| 129 | Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| 130 | |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 131 | Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_instr to be 0x74d84. |
| 132 | Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_color to be 1. |
| 133 | Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_parity to be 0. |
| 134 | Micro instruction added in VLIW 2 for 8-bit position 4 for table process_packet_out_table. |
| 135 | Assembled as 0x74d84 (or decimal 478596) |
| 136 | Micro Instruction deposit-field for PHV Container 68 has bit width 20 |
| 137 | Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0]) |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 138 | Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4]) |
| 139 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 140 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 141 | Field high_bit [2:0] : 0x1 (3 bits in instruction bits [13:11]) |
| 142 | Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14]) |
| 143 | Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16]) |
| 144 | Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19]) |
| 145 | |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 146 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10) |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 147 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6) |
| 148 | --> Stage Gateway Table for condition process_packet_out_table_always_true_condition in stage 0 |
| 149 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 150 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 151 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 152 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 153 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 154 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 155 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x2. (old value = 0x2 OR new value = 0x0) |
| 156 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| 157 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x2 OR new value = 0x0) |
| 158 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| 159 | Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1) |
| 160 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| 161 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| 162 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| 163 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| 164 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1 |
| 165 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0 |
| 166 | Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| 167 | Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| 168 | Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| 169 | Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| 170 | Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| 171 | Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff |
| 172 | Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff |
| 173 | Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8 |
| 174 | Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0x20 |
| 175 | Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10) |
| 176 | Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0x20 |
| 177 | Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2) |
| 178 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe |
| 179 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1 |
| 180 | allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits |
| 181 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x1 |
| 182 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1 |
| 183 | Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2 |
| 184 | Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x0 |
| 185 | Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0 |
| 186 | Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x0 |
| 187 | Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0 |
| 188 | Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff |
| 189 | Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff |
| 190 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1. |
| 191 | |
| 192 | +------------------------------------------------------------------------ |
| 193 | | Working on table table0__action__ in stage 0 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 194 | +------------------------------------------------------------------------ |
| 195 | --> Action Data Table table0__action__ with logical_table_id 0 that is reference type is 'direct' |
| 196 | Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_input_bytemask[array_half=1].action_hv_ixbar_input_bytemask to be 0x3. |
| 197 | Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_ctl_halfword[slice_group=1][array_half=1].action_hv_ixbar_ctl_halfword_3to0_ctl to be 0. |
| 198 | Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_ctl_halfword[slice_group=1][array_half=1].action_hv_ixbar_ctl_halfword_3to0_enable to be 1. |
| 199 | Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_select to be 5. |
| 200 | Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_enable to be 1. |
| 201 | Configuring rams.array.switchbox.row[row=6].ctl.r_action_o_mux_select.r_action_o_sel_action_rd_r_i to be 1. |
| 202 | Configuring rams.array.row[row=6].ram[col=8].unit_ram_ctl.match_ram_write_data_mux_select to be select of 7. |
| 203 | Configuring rams.array.row[row=6].ram[col=8].unit_ram_ctl.match_ram_read_data_mux_select to be select of 4. |
| 204 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_type to be 2. |
| 205 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_vpn to be 0. |
| 206 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_logical_table to be 0. |
| 207 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_ingress to be 1. |
| 208 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_action_subword_out_en to be 1. |
| 209 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=2].unitram_enable to be 1. |
| 210 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=2].ram_unitram_adr_mux_select to be 1. |
| 211 | Configuring rams.array.row[row=6].actiondata_error_uram_ctl[direction=0].actiondata_error_uram_ctl to be select of 0x40. (previous value = 0x0 OR new value = 0x40) |
| 212 | Action data table table0__action__ is used by match table table0. |
| 213 | Configuring rams.match.adrdist.adr_dist_action_data_adr_icxbar_ctl[match_logical_table_id=0].address_distr_to_logical_rows to be 0x2000. |
| 214 | |
| 215 | ---- Hash Distribution Units for table table0__action__ ---- |
| 216 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x2 OR new value = 0x3) |
| 217 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 218 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_address to be 2. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 219 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_lo_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 220 | Configuring match input crossbar byte 0 to come from 32-bit PHV container 2. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 221 | That PHV byte contains {ipv4.dstAddr[7:0]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 222 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_address to be 2. |
| 223 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 224 | Configuring match input crossbar byte 1 to come from 32-bit PHV container 2. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 225 | That PHV byte contains {ipv4.dstAddr[15:8]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 226 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_address to be 2. |
| 227 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 228 | Configuring match input crossbar byte 2 to come from 32-bit PHV container 2. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 229 | That PHV byte contains {ipv4.dstAddr[23:16]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 230 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_address to be 3. |
| 231 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 232 | Configuring match input crossbar byte 3 to come from 32-bit PHV container 3. |
| 233 | That PHV byte contains {tcp.dstPort[7:0]}. |
| 234 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_address to be 1. |
| 235 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 236 | Configuring match input crossbar byte 4 to come from 32-bit PHV container 1. |
| 237 | That PHV byte contains {ipv4.srcAddr[31:24]}. |
| 238 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=5].match_input_xbar_816b_ctl_address to be 20. |
| 239 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=5].match_input_xbar_816b_ctl_enable to be 1. |
| 240 | Configuring match input crossbar byte 5 to come from 16-bit PHV container 4. |
| 241 | That PHV byte contains {tcp.srcPort[7:0]}. |
| 242 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=6].match_input_xbar_816b_ctl_address to be 20. |
| 243 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=6].match_input_xbar_816b_ctl_enable to be 1. |
| 244 | Configuring match input crossbar byte 6 to come from 16-bit PHV container 4. |
| 245 | That PHV byte contains {tcp.dstPort[15:8]}. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 246 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=7].match_input_xbar_32b_ctl_address to be 2. |
| 247 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=7].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 248 | Configuring match input crossbar byte 7 to come from 32-bit PHV container 2. |
| 249 | That PHV byte contains {ipv4.dstAddr[31:24]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 250 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_address to be 19. |
| 251 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_enable to be 1. |
| 252 | Configuring match input crossbar byte 8 to come from 16-bit PHV container 3. |
| 253 | That PHV byte contains {ipv4.srcAddr[7:0]}. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 254 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_address to be 19. |
| 255 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_enable to be 1. |
| 256 | Configuring match input crossbar byte 9 to come from 16-bit PHV container 3. |
| 257 | That PHV byte contains {ipv4.srcAddr[15:8]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 258 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_address to be 1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 259 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 260 | Configuring match input crossbar byte 10 to come from 8-bit PHV container 1. |
| 261 | That PHV byte contains {tcp.srcPort[15:8]}. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 262 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_address to be 0. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 263 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_enable to be 1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 264 | Configuring match input crossbar byte 11 to come from 8-bit PHV container 0. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 265 | That PHV byte contains {ipv4.srcAddr[23:16]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 266 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0xe. (previous value = 0x0 OR new value = 0xe) |
| 267 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x13. (previous value = 0x10 OR new value = 0x3) |
| 268 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x18. (previous value = 0x0 OR new value = 0x18) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 269 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x3. (previous value = 0x2 OR new value = 0x3) |
| 270 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 271 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0xff. |
| 272 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte1 to be 0xaf. |
| 273 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte0 to be 0xfe. |
| 274 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte1 to be 0xff. |
| 275 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte0 to be 0x7f. |
| 276 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte1 to be 0xff. |
| 277 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte0 to be 0xfb. |
| 278 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte1 to be 0x1f. |
| 279 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0xfb. |
| 280 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte1 to be 0xbf. |
| 281 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte0 to be 0xe7. |
| 282 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte1 to be 0xe6. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 283 | Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1) |
| 284 | Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 1. (old value = 0 OR new value = 1). |
| 285 | Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 8. (old value = 0 OR new value = 8). |
| 286 | Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 1. (old value = 0 OR new value = 1). |
| 287 | Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x0. (old value = 0x0 OR new value = 0x0). |
| 288 | Configuring rams.match.merge.mau_hash_group_mask[which_16=0].mau_hash_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 289 | Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=1][control_group_index=0].mau_hash_group_xbar_ctl to be 0x8 (old value = 0x0 OR new value = 0x8). |
| 290 | |
| 291 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 292 | | Working on table table0 in stage 0 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 293 | +------------------------------------------------------------------------ |
| 294 | --> Ternary Match Table table0 with logical_table_id 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 295 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1). |
| 296 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1). |
| 297 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1). |
| 298 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1). |
| 299 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1). |
| 300 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1). |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 301 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id). |
| 302 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| 303 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id). |
| 304 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| 305 | Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x7. |
| 306 | Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_default to be 0x0. |
| 307 | Configuring rams.match.merge.mau_action_instruction_adr_per_entry_en_mux_ctl[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_per_entry_en_mux_ctl to be 0x3. |
| 308 | Configuring rams.match.merge.mau_actiondata_adr_default[table_type_index=1][physical_result_bus=0].mau_actiondata_adr_default to be 0x400001. |
| 309 | Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=1].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 310 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x870a080. |
| 311 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x44. |
| 312 | Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1). |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 313 | Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x20. |
| 314 | Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data1 to be 0x10. |
| 315 | Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x20. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 316 | Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x1. |
| 317 | Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=1][result_bus_number=0].mau_immediate_data_mask to be 0x0. |
| 318 | Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=1][result_bus_number=0].mau_stats_adr_mask to be 0xffffe. |
| 319 | Configuring rams.match.merge.mau_stats_adr_default[table_type_index=1][result_bus_number=0].mau_stats_adr_default to be 0x80000. |
| 320 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x3 OR new value = 0x0) |
| 321 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x3. (old value = 0x0 OR new value = 0x3) |
| 322 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_address to be 16. |
| 323 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_enable to be 1. |
| 324 | Configuring match input crossbar byte 133 to come from 16-bit PHV container 0. |
| 325 | That PHV byte contains version/valid |
| 326 | {unused[6:0], ig_intr_md.ingress_port[8:8]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 327 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_address to be 5. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 328 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_lo_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 329 | Configuring match input crossbar byte 128 to come from 32-bit PHV container 5. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 330 | That PHV byte contains {ethernet.srcAddr[7:0]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 331 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_address to be 5. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 332 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_lo_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 333 | Configuring match input crossbar byte 129 to come from 32-bit PHV container 5. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 334 | That PHV byte contains {ethernet.srcAddr[15:8]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 335 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_address to be 5. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 336 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_lo_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 337 | Configuring match input crossbar byte 130 to come from 32-bit PHV container 5. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 338 | That PHV byte contains {ethernet.srcAddr[23:16]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 339 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_address to be 5. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 340 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_lo_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 341 | Configuring match input crossbar byte 131 to come from 32-bit PHV container 5. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 342 | That PHV byte contains {ethernet.srcAddr[31:24]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 343 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_address to be 4. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 344 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_lo_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 345 | Configuring match input crossbar byte 132 to come from 32-bit PHV container 4. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 346 | That PHV byte contains {ethernet.dstAddr[15:8]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 347 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_address to be 4. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 348 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_lo_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 349 | Configuring match input crossbar byte 134 to come from 32-bit PHV container 4. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 350 | That PHV byte contains {ethernet.dstAddr[31:24]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 351 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_address to be 4. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 352 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_lo_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 353 | Configuring match input crossbar byte 135 to come from 32-bit PHV container 4. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 354 | That PHV byte contains {ethernet.dstAddr[39:32]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 355 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_address to be 22. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 356 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 357 | Configuring match input crossbar byte 136 to come from 16-bit PHV container 6. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 358 | That PHV byte contains {ethernet.etherType[7:0]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 359 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_address to be 4. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 360 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_lo_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 361 | Configuring match input crossbar byte 137 to come from 32-bit PHV container 4. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 362 | That PHV byte contains {ethernet.dstAddr[23:16]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 363 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_address to be 21. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 364 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 365 | Configuring match input crossbar byte 138 to come from 16-bit PHV container 5. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 366 | That PHV byte contains {ethernet.srcAddr[47:40]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 367 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_address to be 22. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 368 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 369 | Configuring match input crossbar byte 139 to come from 16-bit PHV container 6. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 370 | That PHV byte contains {ethernet.etherType[15:8]}. |
| 371 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_address to be 16. |
| 372 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_enable to be 1. |
| 373 | Configuring match input crossbar byte 140 to come from 16-bit PHV container 0. |
| 374 | That PHV byte contains {ig_intr_md.ingress_port[7:0]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 375 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_address to be 21. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 376 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 377 | Configuring match input crossbar byte 141 to come from 16-bit PHV container 5. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 378 | That PHV byte contains {ethernet.dstAddr[7:0]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 379 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 3. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 380 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 381 | Configuring match input crossbar byte 142 to come from 8-bit PHV container 3. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 382 | That PHV byte contains {ethernet.srcAddr[39:32]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 383 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 2. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 384 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 385 | Configuring match input crossbar byte 143 to come from 8-bit PHV container 2. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 386 | That PHV byte contains {ethernet.dstAddr[47:40]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 387 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x3e. (previous value = 0xe OR new value = 0x30) |
| 388 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x1f. (previous value = 0x13 OR new value = 0xc) |
| 389 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x79. (previous value = 0x18 OR new value = 0x61) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 390 | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 391 | --> Idletime Table for match table table0 in stage 0 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 392 | Looking at Map RAM: Row 7 Unit 0 |
| 393 | Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 0. |
| 394 | Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 1. |
| 395 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].two_way_idletime_notification to be 1. |
| 396 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].per_flow_idletime to be 1. |
| 397 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].idletime_bitwidth to be 2 (precision = 3 bits). |
| 398 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_type to be 4. |
| 399 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0. |
| 400 | FIXME: Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn_members to be 0. |
| 401 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn to be 0. |
| 402 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| 403 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| 404 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| 405 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| 406 | Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 2. |
| 407 | Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| 408 | Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| 409 | Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 410 | Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_stats_meter_adr_mux_select_idlet to be 1. |
| 411 | Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0. |
| 412 | Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1. |
| 413 | Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0. |
| 414 | Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1. |
| 415 | Configuring rams.map_alu.row[row=7].adrmux.idletime_cfg_rd_clear_val[map_ram_index=0].idletime_cfg_rd_clear_val to be 0x36. |
| 416 | logical table ID is 0 |
| 417 | Configuring rams.match.adrdist.adr_dist_idletime_adr_oxbar_ctl.[entry_index=2].adr_dist_idletime_adr_oxbar_ctl be 0x4000 (previous value = 0x0 OR new value = 0x4000) |
| 418 | Note that rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_en must be programmed by run time. |
| 419 | Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_offset be 0x0. |
| 420 | Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_size be 0x0. |
| 421 | Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_pos be 0x0. |
| 422 | Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_en be 0x0. |
| 423 | Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_interval be 0x7. |
| 424 | Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_offset be 0x0. |
| 425 | Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_size be 0x0. |
| 426 | Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_pos be 0x0. |
| 427 | Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_en be 0. |
| 428 | Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_size be 2. |
| 429 | Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_direct be 1. |
| 430 | Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=2].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 431 | Configuring rams.match.merge.mau_idletime_adr_mask[table_type_index=1][result_bus_number=0].mau_idletime_adr_mask to be 0x1ffff8. |
| 432 | Configuring rams.match.merge.mau_idletime_adr_default[table_type_index=1][result_bus_number=0].idletime_adr_default to be 0x100003. |
| 433 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x4602. |
| 434 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1. |
| 435 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 1. |
| 436 | Micro instruction added in VLIW 0 for 16-bit position 2 for table table0. |
| 437 | Assembled as 0x4602 (or decimal 17922) |
| 438 | Micro Instruction deposit-field for PHV Container 130 has bit width 23 |
| 439 | Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| 440 | Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4]) |
| 441 | Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9]) |
| 442 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 443 | Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11]) |
| 444 | Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15]) |
| 445 | Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16]) |
| 446 | Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| 447 | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 448 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x6 OR new value = 0x4) |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 449 | Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a07. |
| 450 | Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_color to be 0. |
| 451 | Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_parity to be 0. |
| 452 | Micro instruction added in VLIW 1 for 16-bit position 7 for table table0. |
| 453 | Assembled as 0xc7a07 (or decimal 817671) |
| 454 | Micro Instruction alu_a for PHV Container 135 has bit width 23 |
| 455 | Field Src2 [3:0] : 0x7 (4 bits in instruction bits [3:0]) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 456 | Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4]) |
| 457 | Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9]) |
| 458 | Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10]) |
| 459 | Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| 460 | |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 461 | Configuring dp.imem.imem_subword16[unit_number=8][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a28. |
| 462 | Configuring dp.imem.imem_subword16[unit_number=8][vliw_instruction_number=1].imem_subword16_color to be 0. |
| 463 | Configuring dp.imem.imem_subword16[unit_number=8][vliw_instruction_number=1].imem_subword16_parity to be 1. |
| 464 | Micro instruction added in VLIW 1 for 16-bit position 8 for table table0. |
| 465 | Assembled as 0xc7a28 (or decimal 817704) |
| 466 | Micro Instruction alu_a for PHV Container 136 has bit width 23 |
| 467 | Field Src2 [3:0] : 0x8 (4 bits in instruction bits [3:0]) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 468 | Field Src1 [4:0] : 0x2 (5 bits in instruction bits [8:4]) |
| 469 | Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9]) |
| 470 | Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10]) |
| 471 | Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| 472 | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 473 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_instr to be 0x4602. |
| 474 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_color to be 1. |
| 475 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_parity to be 1. |
| 476 | Micro instruction added in VLIW 1 for 16-bit position 2 for table table0. |
| 477 | Assembled as 0x4602 (or decimal 17922) |
| 478 | Micro Instruction deposit-field for PHV Container 130 has bit width 23 |
| 479 | Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| 480 | Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4]) |
| 481 | Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9]) |
| 482 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 483 | Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11]) |
| 484 | Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15]) |
| 485 | Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16]) |
| 486 | Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| 487 | |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 488 | Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_instr to be 0x594. |
| 489 | Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_color to be 1. |
| 490 | Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_parity to be 0. |
| 491 | Micro instruction added in VLIW 1 for 8-bit position 4 for table table0. |
| 492 | Assembled as 0x594 (or decimal 1428) |
| 493 | Micro Instruction deposit-field for PHV Container 68 has bit width 20 |
| 494 | Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0]) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 495 | Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4]) |
| 496 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 497 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 498 | Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11]) |
| 499 | Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14]) |
| 500 | Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16]) |
| 501 | Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19]) |
| 502 | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 503 | Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_instr to be 0x39fc01. |
| 504 | Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_color to be 1. |
| 505 | Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_parity to be 0. |
| 506 | Micro instruction added in VLIW 1 for 16-bit position 1 for table table0. |
| 507 | Assembled as 0x39fc01 (or decimal 3800065) |
| 508 | Micro Instruction deposit-field for PHV Container 129 has bit width 23 |
| 509 | Field Src2 [3:0] : 0x1 (4 bits in instruction bits [3:0]) |
| 510 | Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4]) |
| 511 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 512 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 513 | Field high_bit [3:0] : 0xf (4 bits in instruction bits [14:11]) |
| 514 | Field low_bit_lo [0:0] : 0x1 (1 bits in instruction bits [15:15]) |
| 515 | Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16]) |
| 516 | Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20]) |
| 517 | |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 518 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x10. (previous value = 0x10 OR new value = 0x10) |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 519 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x7. (previous value = 0x6 OR new value = 0x7) |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 520 | Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_instr to be 0xb7d95. |
| 521 | Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_color to be 0. |
| 522 | Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_parity to be 1. |
| 523 | Micro instruction added in VLIW 2 for 8-bit position 5 for table table0. |
| 524 | Assembled as 0xb7d95 (or decimal 753045) |
| 525 | Micro Instruction deposit-field for PHV Container 69 has bit width 20 |
| 526 | Field Src2 [3:0] : 0x5 (4 bits in instruction bits [3:0]) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 527 | Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4]) |
| 528 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 529 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 530 | Field high_bit [2:0] : 0x7 (3 bits in instruction bits [13:11]) |
| 531 | Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14]) |
| 532 | Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16]) |
| 533 | Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19]) |
| 534 | |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 535 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x30. (previous value = 0x10 OR new value = 0x20) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 536 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].idletime_adr_payload_shifter_en to be 1. |
| 537 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].stats_adr_payload_shifter_en to be 1. |
| 538 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].actiondata_adr_payload_shifter_en to be 1. |
| 539 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].action_instruction_adr_payload_shifter_en to be 1. |
| 540 | Configuring rams.match.merge.mau_table_counter_ctl[half_index=0].mau_table_counter_ctl to be 0x2. (previous value = 0x0 OR new value = 0x2) |
| 541 | dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit'] |
| 542 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data_dirtcam_mode to be 0x155. |
| 543 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vbit_dirtcam_mode to be 0x1. |
| 544 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data1_select to be 1. |
| 545 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_chain_out_enable to be 0. |
| 546 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_ingress to be 1. |
| 547 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_match_output_enable to be 1. |
| 548 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vpn to be 0. |
| 549 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_logical_table to be 0. |
| 550 | TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit. |
| 551 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=0] to be 15. |
| 552 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=1] to be 15. |
| 553 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=2] to be 15. |
| 554 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=3] to be 15. |
| 555 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=4] to be 15. |
| 556 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=5] to be 15. |
| 557 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=6] to be 15. |
| 558 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=7] to be 15. |
| 559 | Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_select to be 0 (don't care). |
| 560 | Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_enable to be 1. |
| 561 | Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_select to be 2. |
| 562 | Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_enable to be 1. |
| 563 | dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit'] |
| 564 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data_dirtcam_mode to be 0x155. |
| 565 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vbit_dirtcam_mode to be 0x0. |
| 566 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data1_select to be 1. |
| 567 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_chain_out_enable to be 1. |
| 568 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_ingress to be 1. |
| 569 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_match_output_enable to be 0. |
| 570 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vpn to be 0. |
| 571 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_logical_table to be 0. |
| 572 | TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit. |
| 573 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15. |
| 574 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15. |
| 575 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15. |
| 576 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15. |
| 577 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15. |
| 578 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15. |
| 579 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15. |
| 580 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15. |
| 581 | Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_select to be 3 (version on [3:2] and valid bits for [1:0]). |
| 582 | Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_enable to be 1. |
| 583 | Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0. |
| 584 | Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1. |
| 585 | Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_select to be 1. |
| 586 | Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_enable to be 1. |
| 587 | dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit'] |
| 588 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data_dirtcam_mode to be 0x155. |
| 589 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vbit_dirtcam_mode to be 0x1. |
| 590 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data1_select to be 1. |
| 591 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_chain_out_enable to be 1. |
| 592 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_ingress to be 1. |
| 593 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_match_output_enable to be 0. |
| 594 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vpn to be 0. |
| 595 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_logical_table to be 0. |
| 596 | TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit. |
| 597 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15. |
| 598 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15. |
| 599 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15. |
| 600 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15. |
| 601 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15. |
| 602 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15. |
| 603 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15. |
| 604 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15. |
| 605 | Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_select to be 0 (extra byte low nibble [3:0]). |
| 606 | Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_enable to be 1. |
| 607 | Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0. |
| 608 | Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1. |
| 609 | Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_select to be 0. |
| 610 | Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_enable to be 1. |
| 611 | Configuring tcams.col[col=0].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x0. |
| 612 | Configuring tcams.col[col=1].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x200. |
| 613 | --> Ternary Indirection table for Match Table table0 with logical_table_id 0 |
| 614 | Configuring tcams.tcam_match_adr_shift[tcam_table_id=0] to be left shift of 1. |
| 615 | Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_write_data_mux_select to be select of 7. |
| 616 | Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_read_data_mux_select to be select of 7. |
| 617 | Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.tind_result_bus_select to be select of 1. |
| 618 | Configuring rams.map_alu.row[row=0].adrmux.ram_address_mux_ctl[column_half=0][column_index=2].ram_unitram_adr_mux_select to be 2. |
| 619 | Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_type to be 6. |
| 620 | Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_vpn to be 0. |
| 621 | Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_logical_table to be 0. |
| 622 | Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_ingress to be 1. |
| 623 | Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_enable to be 1. |
| 624 | Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id). |
| 625 | Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_enable to be 1. |
| 626 | Configuring rams.array.row[row=0].tind_ecc_error_uram_ctl[direction=0].tind_ecc_error_uram_ctl to be select of 0x1. (previous value = 0x0 OR new value = 0x1) |
| 627 | Configuring rams.match.merge.tind_ram_data_size[tind_bus_number=0].tind_ram_data_size to be code 2. |
| 628 | Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id). |
| 629 | Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_enable to be 1. |
| 630 | TODO: rams.match.merge.tind_bus_prop[tind_bus_number=0] is currently always set to 1. |
| 631 | Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].tcam_piped to be 1. |
| 632 | Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].enabled to be 1. |
| 633 | Configuring rams.match.merge.mau_action_instruction_adr_tcam_shiftcount[physical_result_bus=0].mau_action_instruction_adr_tcam_shiftcount to be 1. |
| 634 | Configuring rams.match.merge.mau_actiondata_adr_mask[table_type_index=1][physical_result_bus=0].mau_actiondata_adr_mask to be 0x3ffffc. |
| 635 | Configuring rams.match.merge.mau_actiondata_adr_tcam_shiftcount[physical_result_bus=0].mau_actiondata_adr_tcam_shiftcount to be 68. |
| 636 | Configuring rams.match.merge.mau_idletime_adr_tcam_shiftcount[result_bus_number=0].mau_idletime_adr_tcam_shiftcount to be 0x42. |
| 637 | Configuring rams.match.merge.mau_stats_adr_tcam_shiftcount[result_bus_index=0].mau_stats_adr_tcam_shiftcount to be 0x47. |
| 638 | Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_select to be 0 (logical table id). |
| 639 | Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_enable to be 1. |
| 640 | TODO: rams.match.merge.tcam_table_prop[tcam_table_id=0] is currently always set to 1. |
| 641 | Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].tcam_piped to be 1. |
| 642 | Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].enabled to be 1. |
| 643 | Configuring tcams.tcam_output_table_thread[tcam_table_id=0].tcam_output_table_thread to be 1. |
| 644 | TODO: tcams.tcam_piped is currently always set to True for ingress and egress. |
| 645 | Configuring tcams.tcam_piped to be 3. |
| 646 | Configuring cfg_regs.mau_cfg_movereg_tcam_only.mau_cfg_movereg_tcam_only to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 647 | |
| 648 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 649 | | Working on table table0_counter in stage 0 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 650 | +------------------------------------------------------------------------ |
| 651 | Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 652 | Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 653 | Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 654 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3. |
| 655 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 656 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0. |
| 657 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1. |
| 658 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1. |
| 659 | Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 660 | Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 661 | Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 662 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3. |
| 663 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 664 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0. |
| 665 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1. |
| 666 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1. |
| 667 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5. |
| 668 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1. |
| 669 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 670 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1. |
| 671 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 672 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 673 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5. |
| 674 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1. |
| 675 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 676 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1. |
| 677 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2) |
| 678 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 679 | Stat table table0_counter is used by match table table0. |
| 680 | Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8) |
| 681 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1. |
| 682 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0. |
| 683 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 684 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| 685 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| 686 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| 687 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| 688 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1. |
| 689 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| 690 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| 691 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1. |
| 692 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0. |
| 693 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 694 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1. |
| 695 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1. |
| 696 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1. |
| 697 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1. |
| 698 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1. |
| 699 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1. |
| 700 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1. |
| 701 | For counter width 32 and N = 4096 |
| 702 | number iterations = 32 |
| 703 | b_cur = 379488672.0 |
| 704 | eqn(b_cur) = 4294964039.26 |
| 705 | max_counter_value = 4294967295 |
| 706 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a. |
| 707 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff. |
| 708 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a. |
| 709 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff. |
| 710 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a. |
| 711 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff. |
| 712 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4. |
| 713 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1. |
| 714 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1. |
| 715 | TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0. |
| 716 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x0. |
| 717 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4. |
| 718 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1. |
| 719 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0. |
| 720 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0. |
| 721 | Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0. |
| 722 | Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0. |
| 723 | Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0. |
| 724 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0. |
| 725 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0. |
| 726 | Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1. |
| 727 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3. |
| 728 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_direct be 1. |
| 729 | Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=0].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 730 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_tcam be 1. |
| 731 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x0. |
| 732 | Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x7. ( previous value = 0x0 OR new value = 0x7) |
| 733 | Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x1. |
| 734 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 735 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 12. |
| 736 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 737 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 738 | Configuring rams.match.merge.exact_match_delay_thread[copy_index=0].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 739 | Configuring rams.match.merge.exact_match_delay_thread[copy_index=1].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 740 | Configuring rams.match.merge.exact_match_delay_thread[copy_index=2].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1) |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 741 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 10. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 742 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 743 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 744 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 745 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 746 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 747 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 748 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x3. |
| 749 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x2. |
| 750 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x2. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 751 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 752 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x2. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 753 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 754 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 755 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 756 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 16. |
| 757 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 21. |
| 758 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 759 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 760 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 761 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 762 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 763 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 764 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 765 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 766 | -------------------------------------------- |
| 767 | Configuration for unused statistics ALUs. |
| 768 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 769 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 770 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 771 | +------------------------------------------------------------------------ |
| 772 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f. |
| 773 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f. |
| 774 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 775 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f. |
| 776 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f. |
| 777 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 778 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff. |
| 779 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff. |
| 780 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 781 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1. |
| 782 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1. |
| 783 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 784 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 785 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 786 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 787 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 788 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 789 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 790 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 791 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 792 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 793 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 794 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 1. |
| 795 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 1. |
| 796 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 797 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 798 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 799 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 800 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 801 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 802 | +------------------------------------------------------------------------ |
| 803 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 19. |
| 804 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 2. |
| 805 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0. |
| 806 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0. |
| 807 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 808 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 809 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 810 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 811 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 812 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 813 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 814 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 815 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 816 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 817 | |
| 818 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 819 | | MAU Stage 1 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 820 | +------------------------------------------------------------------------ |
| 821 | |
| 822 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 823 | | Working on table ecmp_group_table__action__ in stage 1 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 824 | +------------------------------------------------------------------------ |
| 825 | --> Action Data Table ecmp_group_table__action__ with logical_table_id 0 that is reference type is 'direct' |
| 826 | Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_select to be 4. |
| 827 | Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_enable to be 1. |
| 828 | |
| 829 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 830 | | Working on table ecmp_group_table in stage 1 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 831 | +------------------------------------------------------------------------ |
| 832 | --> Hash Match Table ecmp_group_table with logical_table_id 0 |
| 833 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 834 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 835 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 836 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 837 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 838 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 839 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=14].enabled_4bit_muxctl_select to be 0 (logical table id). |
| 840 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=14].enabled_4bit_muxctl_enable to be 1. |
| 841 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=14].enabled_4bit_muxctl_select to be 0 (logical table id). |
| 842 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=14].enabled_4bit_muxctl_enable to be 1. |
| 843 | Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=14].mau_action_instruction_adr_mask to be 0x0. |
| 844 | Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=14].mau_action_instruction_adr_default to be 0x40. |
| 845 | Configuring rams.match.merge.mau_action_instruction_adr_per_entry_en_mux_ctl[table_type_index=0][physical_result_bus=14].mau_action_instruction_adr_per_entry_en_mux_ctl to be 0x0. |
| 846 | Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 847 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x41. |
| 848 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
| 849 | Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1). |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 850 | Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x20. |
| 851 | Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x20. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 852 | Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x0. |
| 853 | Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=0][result_bus_number=14].mau_immediate_data_mask to be 0xffff. |
| 854 | Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=0][result_bus_number=14].mau_stats_adr_mask to be 0xffffe. |
| 855 | Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=14].mau_stats_adr_default to be 0x80000. |
| 856 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1) |
| 857 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 858 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 24. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 859 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 860 | Configuring match input crossbar byte 0 to come from 16-bit PHV container 8. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 861 | That PHV byte contains {ecmp_metadata.selector[7:0]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 862 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 24. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 863 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 864 | Configuring match input crossbar byte 1 to come from 16-bit PHV container 8. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 865 | That PHV byte contains {ecmp_metadata.selector[15:8]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 866 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 23. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 867 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 868 | Configuring match input crossbar byte 2 to come from 16-bit PHV container 7. |
Carmelo Cascone | 8aa0548 | 2017-09-12 13:21:59 +0200 | [diff] [blame] | 869 | That PHV byte contains {ecmp_metadata.group_id[7:0]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 870 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 23. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 871 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_enable to be 1. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 872 | Configuring match input crossbar byte 3 to come from 16-bit PHV container 7. |
Carmelo Cascone | 8aa0548 | 2017-09-12 13:21:59 +0200 | [diff] [blame] | 873 | That PHV byte contains {ecmp_metadata.group_id[15:8]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 874 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x80. (previous value = 0x0 OR new value = 0x80) |
| 875 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=9].match_input_xbar_din_power_ctl to be 0x1. (previous value = 0x0 OR new value = 0x1) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 876 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=2].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 877 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=3].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 878 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=5].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 879 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=7].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 880 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=8].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 881 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=10].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 882 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=11].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 883 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=15].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 884 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=19].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 885 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=20].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 886 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=21].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 887 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=23].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 888 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=24].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 889 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=25].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 890 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=26].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 891 | Configuring dp.xbar_hash.hash.hash_seed[output_bit=28].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1) |
| 892 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 893 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| 894 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x1. |
| 895 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte1 to be 0x84. |
| 896 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte0 to be 0xa9. |
| 897 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte1 to be 0xbe. |
| 898 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte0 to be 0x2. |
| 899 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte1 to be 0xa0. |
| 900 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=1].byte0 to be 0xd3. |
| 901 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=1].byte1 to be 0xc0. |
| 902 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte0 to be 0x4. |
| 903 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte1 to be 0xd4. |
| 904 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=2].byte0 to be 0xdc. |
| 905 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=2].byte1 to be 0x26. |
| 906 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte0 to be 0x8. |
| 907 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte1 to be 0x38. |
| 908 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=3].byte0 to be 0xd0. |
| 909 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=3].byte1 to be 0x78. |
| 910 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte0 to be 0x10. |
| 911 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte1 to be 0x8. |
| 912 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=4].byte0 to be 0xdc. |
| 913 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=4].byte1 to be 0xf4. |
| 914 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte0 to be 0x20. |
| 915 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte1 to be 0x24. |
| 916 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=5].byte0 to be 0xe. |
| 917 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=5].byte1 to be 0x90. |
| 918 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte0 to be 0x40. |
| 919 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte1 to be 0xf4. |
| 920 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=6].byte0 to be 0x3e. |
| 921 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=6].byte1 to be 0x8e. |
| 922 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte0 to be 0x80. |
| 923 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte1 to be 0x8c. |
| 924 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=7].byte0 to be 0x7d. |
| 925 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=7].byte1 to be 0x4. |
| 926 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=8].byte1 to be 0x79. |
| 927 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=8].byte0 to be 0x12. |
| 928 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=8].byte1 to be 0x40. |
| 929 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=9].byte1 to be 0xee. |
| 930 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=9].byte0 to be 0x30. |
| 931 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=9].byte1 to be 0x21. |
| 932 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=10].byte1 to be 0x7a. |
| 933 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=10].byte0 to be 0xf0. |
| 934 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=10].byte1 to be 0x7f. |
| 935 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=11].byte0 to be 0x1. |
| 936 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=11].byte1 to be 0x5c. |
| 937 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=11].byte0 to be 0x54. |
| 938 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=11].byte1 to be 0x14. |
| 939 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=12].byte0 to be 0x2. |
| 940 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=12].byte1 to be 0x94. |
| 941 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=12].byte0 to be 0x62. |
| 942 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=12].byte1 to be 0x63. |
| 943 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=13].byte0 to be 0x4. |
| 944 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=13].byte1 to be 0xb4. |
| 945 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=13].byte0 to be 0x47. |
| 946 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=13].byte1 to be 0x30. |
| 947 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=14].byte0 to be 0x8. |
| 948 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=14].byte1 to be 0xfc. |
| 949 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=14].byte0 to be 0xa5. |
| 950 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=14].byte1 to be 0xaa. |
| 951 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=15].byte0 to be 0x10. |
| 952 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=15].byte1 to be 0x48. |
| 953 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=15].byte0 to be 0xee. |
| 954 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=15].byte1 to be 0x84. |
| 955 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=16].byte0 to be 0x20. |
| 956 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=16].byte1 to be 0xb4. |
| 957 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=16].byte0 to be 0xf1. |
| 958 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=16].byte1 to be 0x93. |
| 959 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=17].byte0 to be 0x40. |
| 960 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=17].byte1 to be 0xb4. |
| 961 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=17].byte0 to be 0xd7. |
| 962 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=17].byte1 to be 0x19. |
| 963 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=18].byte0 to be 0x80. |
| 964 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=18].byte1 to be 0xec. |
| 965 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=18].byte0 to be 0x62. |
| 966 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=18].byte1 to be 0x13. |
| 967 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=19].byte1 to be 0x29. |
| 968 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=19].byte0 to be 0x12. |
| 969 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=19].byte1 to be 0x16. |
| 970 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=20].byte1 to be 0x45. |
| 971 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=20].byte0 to be 0xe0. |
| 972 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=20].byte1 to be 0xfe. |
| 973 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=21].byte1 to be 0x6. |
| 974 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=21].byte0 to be 0xd1. |
| 975 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=21].byte1 to be 0x65. |
| 976 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=22].byte0 to be 0x1. |
| 977 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=22].byte1 to be 0x84. |
| 978 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=22].byte0 to be 0x33. |
| 979 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=22].byte1 to be 0xa4. |
| 980 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=23].byte0 to be 0x2. |
| 981 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=23].byte1 to be 0xc. |
| 982 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=23].byte0 to be 0x7c. |
| 983 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=23].byte1 to be 0xe. |
| 984 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=24].byte0 to be 0x4. |
| 985 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=24].byte1 to be 0x4c. |
| 986 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=24].byte0 to be 0x8d. |
| 987 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=24].byte1 to be 0x6f. |
| 988 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=25].byte0 to be 0x8. |
| 989 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=25].byte1 to be 0x2c. |
| 990 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=25].byte0 to be 0xc2. |
| 991 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=25].byte1 to be 0xf9. |
| 992 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=26].byte0 to be 0x10. |
| 993 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=26].byte1 to be 0xd0. |
| 994 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=26].byte0 to be 0x17. |
| 995 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=26].byte1 to be 0xf9. |
| 996 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=27].byte0 to be 0x20. |
| 997 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=27].byte1 to be 0x8. |
| 998 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=27].byte0 to be 0x6c. |
| 999 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=27].byte1 to be 0x32. |
| 1000 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=28].byte0 to be 0x40. |
| 1001 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=28].byte1 to be 0x74. |
| 1002 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=28].byte0 to be 0xdc. |
| 1003 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=28].byte1 to be 0xb7. |
| 1004 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=29].byte0 to be 0x80. |
| 1005 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=29].byte1 to be 0xf8. |
| 1006 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=29].byte0 to be 0x5c. |
| 1007 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=29].byte1 to be 0xa. |
| 1008 | Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 1009 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x4602. |
| 1010 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1. |
| 1011 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 1. |
| 1012 | Micro instruction added in VLIW 0 for 16-bit position 2 for table ecmp_group_table. |
| 1013 | Assembled as 0x4602 (or decimal 17922) |
| 1014 | Micro Instruction deposit-field for PHV Container 130 has bit width 23 |
| 1015 | Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| 1016 | Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4]) |
| 1017 | Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9]) |
| 1018 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 1019 | Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11]) |
| 1020 | Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15]) |
| 1021 | Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16]) |
| 1022 | Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| 1023 | |
| 1024 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4) |
| 1025 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=14].stats_adr_payload_shifter_en to be 1. |
| 1026 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=14].action_instruction_adr_payload_shifter_en to be 1. |
| 1027 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=14].immediate_data_payload_shifter_en to be 1. |
| 1028 | Configuring rams.match.merge.mau_table_counter_ctl[half_index=0].mau_table_counter_ctl to be 0x2. (previous value = 0x0 OR new value = 0x2) |
| 1029 | --> Hash Match Way 0 |
| 1030 | Packed entry for hash way 0 is |
| 1031 | [0] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 0)) |
| 1032 | [1] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 1)) |
| 1033 | [2] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 2)) |
| 1034 | [3] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 3)) |
| 1035 | [4] = (field_bit=4, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 4)) |
| 1036 | [5] = (field_bit=5, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 5)) |
| 1037 | [6] = (field_bit=6, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 6)) |
| 1038 | [7] = (field_bit=7, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 7)) |
| 1039 | [8] = (field_bit=8, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 8)) |
| 1040 | [9] = (field_bit=9, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 9)) |
| 1041 | [10] = (field_bit=10, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 10)) |
| 1042 | [11] = (field_bit=11, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 11)) |
| 1043 | [12] = (field_bit=12, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 12)) |
| 1044 | [13] = (field_bit=13, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 13)) |
| 1045 | [14] = (field_bit=14, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 14)) |
| 1046 | [15] = (field_bit=15, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 15)) |
Carmelo Cascone | 8aa0548 | 2017-09-12 13:21:59 +0200 | [diff] [blame] | 1047 | [16] = (field_bit=0, hash_match_group_bit=16, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 0)) |
| 1048 | [17] = (field_bit=1, hash_match_group_bit=17, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 1)) |
| 1049 | [18] = (field_bit=2, hash_match_group_bit=18, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 2)) |
| 1050 | [19] = (field_bit=3, hash_match_group_bit=19, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 3)) |
| 1051 | [20] = (field_bit=4, hash_match_group_bit=20, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 4)) |
| 1052 | [21] = (field_bit=5, hash_match_group_bit=21, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 5)) |
| 1053 | [22] = (field_bit=6, hash_match_group_bit=22, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 6)) |
| 1054 | [23] = (field_bit=7, hash_match_group_bit=23, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 7)) |
| 1055 | [24] = (field_bit=8, hash_match_group_bit=24, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 8)) |
| 1056 | [25] = (field_bit=9, hash_match_group_bit=25, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 9)) |
| 1057 | [26] = (field_bit=10, hash_match_group_bit=26, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 10)) |
| 1058 | [27] = (field_bit=11, hash_match_group_bit=27, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 11)) |
| 1059 | [28] = (field_bit=12, hash_match_group_bit=28, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 12)) |
| 1060 | [29] = (field_bit=13, hash_match_group_bit=29, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 13)) |
| 1061 | [30] = (field_bit=14, hash_match_group_bit=30, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 14)) |
| 1062 | [31] = (field_bit=15, hash_match_group_bit=31, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 15)) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1063 | [32] = None |
| 1064 | [33] = None |
| 1065 | [34] = (field_bit=10, hash_match_group_bit=10, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 10)) |
| 1066 | [35] = (field_bit=11, hash_match_group_bit=11, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 11)) |
| 1067 | [36] = (field_bit=12, hash_match_group_bit=12, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 12)) |
| 1068 | [37] = (field_bit=13, hash_match_group_bit=13, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 13)) |
| 1069 | [38] = (field_bit=14, hash_match_group_bit=14, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 14)) |
| 1070 | [39] = (field_bit=15, hash_match_group_bit=15, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 15)) |
| 1071 | [40] = None |
| 1072 | [41] = None |
| 1073 | [42] = None |
| 1074 | [43] = None |
| 1075 | [44] = None |
| 1076 | [45] = None |
| 1077 | [46] = None |
| 1078 | [47] = None |
| 1079 | [48] = None |
| 1080 | [49] = None |
| 1081 | [50] = None |
| 1082 | [51] = None |
| 1083 | [52] = None |
| 1084 | [53] = None |
| 1085 | [54] = None |
| 1086 | [55] = None |
| 1087 | [56] = None |
| 1088 | [57] = None |
| 1089 | [58] = None |
| 1090 | [59] = None |
| 1091 | [60] = None |
| 1092 | [61] = None |
| 1093 | [62] = None |
| 1094 | [63] = None |
| 1095 | [64] = None |
| 1096 | [65] = None |
| 1097 | [66] = None |
| 1098 | [67] = None |
| 1099 | [68] = None |
| 1100 | [69] = None |
| 1101 | [70] = None |
| 1102 | [71] = None |
| 1103 | [72] = None |
| 1104 | [73] = None |
| 1105 | [74] = None |
| 1106 | [75] = None |
| 1107 | [76] = None |
| 1108 | [77] = None |
| 1109 | [78] = None |
| 1110 | [79] = None |
| 1111 | [80] = None |
| 1112 | [81] = None |
| 1113 | [82] = None |
| 1114 | [83] = None |
| 1115 | [84] = None |
| 1116 | [85] = None |
| 1117 | [86] = None |
| 1118 | [87] = None |
| 1119 | [88] = None |
| 1120 | [89] = None |
| 1121 | [90] = None |
| 1122 | [91] = None |
| 1123 | [92] = None |
| 1124 | [93] = None |
| 1125 | [94] = None |
| 1126 | [95] = None |
| 1127 | [96] = None |
| 1128 | [97] = None |
| 1129 | [98] = None |
| 1130 | [99] = None |
| 1131 | [100] = None |
| 1132 | [101] = None |
| 1133 | [102] = None |
| 1134 | [103] = None |
| 1135 | [104] = None |
| 1136 | [105] = None |
| 1137 | [106] = None |
| 1138 | [107] = None |
| 1139 | [108] = None |
| 1140 | [109] = None |
| 1141 | [110] = None |
| 1142 | [111] = None |
| 1143 | [112] = None |
| 1144 | [113] = None |
| 1145 | [114] = None |
| 1146 | [115] = None |
| 1147 | [116] = None |
| 1148 | [117] = None |
| 1149 | [118] = None |
| 1150 | [119] = None |
| 1151 | [120] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 0)) |
| 1152 | [121] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 1)) |
| 1153 | [122] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 2)) |
| 1154 | [123] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 3)) |
| 1155 | [124] = None |
| 1156 | [125] = None |
| 1157 | [126] = None |
| 1158 | [127] = None |
| 1159 | |
| 1160 | Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=0].match_mask to be 0xffff. |
| 1161 | Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=1].match_mask to be 0xffffff03. |
| 1162 | Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=2].match_mask to be 0xffffffff. |
| 1163 | Configuring rams.array.row[row=7].ram[column=2].match_mask[entry_index=3].match_mask to be 0xf0ffffff. |
| 1164 | Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_ram_write_data_mux_select to be 7. |
| 1165 | Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_ram_read_data_mux_select to be 7. |
| 1166 | Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_result_bus_select to be 1. |
| 1167 | Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_entry_enable to be 1. |
| 1168 | Configuring rams.array.row[row=7].ram[column=2].unit_ram_ctl.match_ram_logical_table to be 0x0. |
| 1169 | For entry_in_ram_word 0, should have vpn 0, with lower_two_bits of 0 and upper_vpn of 0 |
| 1170 | for entry_in_ram_word 0, use lsbs of 0 |
| 1171 | Configuring rams.array.row[row=7].ram[column=2].match_ram_vpn.match_ram_vpn0 to be 0. |
| 1172 | Configuring rams.array.row[row=7].ram[column=2].match_ram_vpn.match_ram_vpn_lsbs to be 0x0. |
| 1173 | version valid nibbles are : [30] |
| 1174 | Configuring rams.array.row[row=7].ram[column=2].match_nibble_s0q1_enable.match_nibble_s0q1_enable to be 0xbfffffff. |
| 1175 | Configuring rams.array.row[row=7].ram[column=2].match_nibble_s1q0_enable.match_nibble_s1q0_enable to be 0xffffffff. |
| 1176 | Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=0].mask_bytes_0_to_13 to be 0x3fe3. |
| 1177 | Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=0].mask_nibbles_28_to_31 to be 0xb. |
| 1178 | Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=1].mask_bytes_0_to_13 to be 0x3fff. |
| 1179 | Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=1].mask_nibbles_28_to_31 to be 0xf. |
| 1180 | Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=2].mask_bytes_0_to_13 to be 0x3fff. |
| 1181 | Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=2].mask_nibbles_28_to_31 to be 0xf. |
| 1182 | Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=3].mask_bytes_0_to_13 to be 0x3fff. |
| 1183 | Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=3].mask_nibbles_28_to_31 to be 0xf. |
| 1184 | Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=4].mask_bytes_0_to_13 to be 0x3fff. |
| 1185 | Configuring rams.array.row[row=7].ram[column=2].match_bytemask[entry_in_ram_word=4].mask_nibbles_28_to_31 to be 0xf. |
| 1186 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1187 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1188 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1189 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1190 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1191 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1192 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1193 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1194 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1195 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1196 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1197 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1198 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1199 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1200 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1201 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1202 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1203 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1204 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1205 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1206 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1207 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1208 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8. |
| 1209 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8. |
| 1210 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8. |
| 1211 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8. |
| 1212 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0. |
| 1213 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1. |
| 1214 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_thread to be 0. |
| 1215 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=2].exactmatch_bank_enable_bank_mask to be 0x0. |
| 1216 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=2].exactmatch_bank_enable_bank_id to be 0x0. |
| 1217 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=2].exactmatch_bank_enable_inp_sel to be 1. |
| 1218 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0. |
| 1219 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1. |
| 1220 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=2].enabled_4bit_muxctl_select to be 0. |
| 1221 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=2].enabled_4bit_muxctl_enable to be 1. |
| 1222 | Configuring rams.match.merge.mau_action_instruction_adr_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_action_instruction_adr_exact_shiftcount to be 0. |
| 1223 | Configuring rams.match.merge.mau_immediate_data_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_immediate_data_exact_shiftcount to be 0. |
| 1224 | Configuring rams.match.merge.mau_stats_adr_exact_shiftcount[result_bus_number = 14][entry_in_ram_word=0].mau_stats_adr_exact_shiftcount to be 0x46. |
| 1225 | Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_type to be 1. |
| 1226 | Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_logical_table to be 0. |
| 1227 | Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_ingress to be 1. |
| 1228 | Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=2].unitram_enable to be 1. |
| 1229 | Configuring rams.array.row[row=7].emm_ecc_error_uram_ctl[direction=0].emm_ecc_error_uram_ctl to be select of 0x1. (previous value = 0x0 OR new value = 0x1) |
| 1230 | In Ram Word 0: |
| 1231 | wide entry 0 occupied ram word entry 0 |
| 1232 | Configuring rams.match.merge.col[col_number=2].row_action_nxtable_bus_drive[row_number=7].row_action_nxtable_bus_drive to be 1. |
| 1233 | Configuring rams.match.merge.col[col_number=2].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_select to be 14 (hit signal to output on). |
| 1234 | Configuring rams.match.merge.col[col_number=2].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1. |
| 1235 | --> Hash Match Way 1 |
| 1236 | Packed entry for hash way 1 is |
| 1237 | [0] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 0)) |
| 1238 | [1] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 1)) |
| 1239 | [2] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 2)) |
| 1240 | [3] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 3)) |
| 1241 | [4] = (field_bit=4, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 4)) |
| 1242 | [5] = (field_bit=5, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 5)) |
| 1243 | [6] = (field_bit=6, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 6)) |
| 1244 | [7] = (field_bit=7, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 7)) |
| 1245 | [8] = (field_bit=8, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 8)) |
| 1246 | [9] = (field_bit=9, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 9)) |
| 1247 | [10] = (field_bit=10, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 10)) |
| 1248 | [11] = (field_bit=11, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 11)) |
| 1249 | [12] = (field_bit=12, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 12)) |
| 1250 | [13] = (field_bit=13, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 13)) |
| 1251 | [14] = (field_bit=14, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 14)) |
| 1252 | [15] = (field_bit=15, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 15)) |
Carmelo Cascone | 8aa0548 | 2017-09-12 13:21:59 +0200 | [diff] [blame] | 1253 | [16] = (field_bit=0, hash_match_group_bit=16, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 0)) |
| 1254 | [17] = (field_bit=1, hash_match_group_bit=17, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 1)) |
| 1255 | [18] = (field_bit=2, hash_match_group_bit=18, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 2)) |
| 1256 | [19] = (field_bit=3, hash_match_group_bit=19, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 3)) |
| 1257 | [20] = (field_bit=4, hash_match_group_bit=20, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 4)) |
| 1258 | [21] = (field_bit=5, hash_match_group_bit=21, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 5)) |
| 1259 | [22] = (field_bit=6, hash_match_group_bit=22, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 6)) |
| 1260 | [23] = (field_bit=7, hash_match_group_bit=23, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 7)) |
| 1261 | [24] = (field_bit=8, hash_match_group_bit=24, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 8)) |
| 1262 | [25] = (field_bit=9, hash_match_group_bit=25, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 9)) |
| 1263 | [26] = (field_bit=10, hash_match_group_bit=26, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 10)) |
| 1264 | [27] = (field_bit=11, hash_match_group_bit=27, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 11)) |
| 1265 | [28] = (field_bit=12, hash_match_group_bit=28, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 12)) |
| 1266 | [29] = (field_bit=13, hash_match_group_bit=29, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 13)) |
| 1267 | [30] = (field_bit=14, hash_match_group_bit=30, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 14)) |
| 1268 | [31] = (field_bit=15, hash_match_group_bit=31, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 15)) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1269 | [32] = None |
| 1270 | [33] = None |
| 1271 | [34] = (field_bit=10, hash_match_group_bit=10, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 10)) |
| 1272 | [35] = (field_bit=11, hash_match_group_bit=11, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 11)) |
| 1273 | [36] = (field_bit=12, hash_match_group_bit=12, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 12)) |
| 1274 | [37] = (field_bit=13, hash_match_group_bit=13, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 13)) |
| 1275 | [38] = (field_bit=14, hash_match_group_bit=14, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 14)) |
| 1276 | [39] = (field_bit=15, hash_match_group_bit=15, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 15)) |
| 1277 | [40] = None |
| 1278 | [41] = None |
| 1279 | [42] = None |
| 1280 | [43] = None |
| 1281 | [44] = None |
| 1282 | [45] = None |
| 1283 | [46] = None |
| 1284 | [47] = None |
| 1285 | [48] = None |
| 1286 | [49] = None |
| 1287 | [50] = None |
| 1288 | [51] = None |
| 1289 | [52] = None |
| 1290 | [53] = None |
| 1291 | [54] = None |
| 1292 | [55] = None |
| 1293 | [56] = None |
| 1294 | [57] = None |
| 1295 | [58] = None |
| 1296 | [59] = None |
| 1297 | [60] = None |
| 1298 | [61] = None |
| 1299 | [62] = None |
| 1300 | [63] = None |
| 1301 | [64] = None |
| 1302 | [65] = None |
| 1303 | [66] = None |
| 1304 | [67] = None |
| 1305 | [68] = None |
| 1306 | [69] = None |
| 1307 | [70] = None |
| 1308 | [71] = None |
| 1309 | [72] = None |
| 1310 | [73] = None |
| 1311 | [74] = None |
| 1312 | [75] = None |
| 1313 | [76] = None |
| 1314 | [77] = None |
| 1315 | [78] = None |
| 1316 | [79] = None |
| 1317 | [80] = None |
| 1318 | [81] = None |
| 1319 | [82] = None |
| 1320 | [83] = None |
| 1321 | [84] = None |
| 1322 | [85] = None |
| 1323 | [86] = None |
| 1324 | [87] = None |
| 1325 | [88] = None |
| 1326 | [89] = None |
| 1327 | [90] = None |
| 1328 | [91] = None |
| 1329 | [92] = None |
| 1330 | [93] = None |
| 1331 | [94] = None |
| 1332 | [95] = None |
| 1333 | [96] = None |
| 1334 | [97] = None |
| 1335 | [98] = None |
| 1336 | [99] = None |
| 1337 | [100] = None |
| 1338 | [101] = None |
| 1339 | [102] = None |
| 1340 | [103] = None |
| 1341 | [104] = None |
| 1342 | [105] = None |
| 1343 | [106] = None |
| 1344 | [107] = None |
| 1345 | [108] = None |
| 1346 | [109] = None |
| 1347 | [110] = None |
| 1348 | [111] = None |
| 1349 | [112] = None |
| 1350 | [113] = None |
| 1351 | [114] = None |
| 1352 | [115] = None |
| 1353 | [116] = None |
| 1354 | [117] = None |
| 1355 | [118] = None |
| 1356 | [119] = None |
| 1357 | [120] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 0)) |
| 1358 | [121] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 1)) |
| 1359 | [122] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 2)) |
| 1360 | [123] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 3)) |
| 1361 | [124] = None |
| 1362 | [125] = None |
| 1363 | [126] = None |
| 1364 | [127] = None |
| 1365 | |
| 1366 | Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=0].match_mask to be 0xffff. |
| 1367 | Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=1].match_mask to be 0xffffff03. |
| 1368 | Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=2].match_mask to be 0xffffffff. |
| 1369 | Configuring rams.array.row[row=7].ram[column=3].match_mask[entry_index=3].match_mask to be 0xf0ffffff. |
| 1370 | Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_ram_write_data_mux_select to be 7. |
| 1371 | Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_ram_read_data_mux_select to be 7. |
| 1372 | Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_result_bus_select to be 1. |
| 1373 | Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_entry_enable to be 1. |
| 1374 | Configuring rams.array.row[row=7].ram[column=3].unit_ram_ctl.match_ram_logical_table to be 0x0. |
| 1375 | For entry_in_ram_word 0, should have vpn 1, with lower_two_bits of 1 and upper_vpn of 0 |
| 1376 | for entry_in_ram_word 0, use lsbs of 1 |
| 1377 | Configuring rams.array.row[row=7].ram[column=3].match_ram_vpn.match_ram_vpn0 to be 0. |
| 1378 | Configuring rams.array.row[row=7].ram[column=3].match_ram_vpn.match_ram_vpn_lsbs to be 0x1. |
| 1379 | version valid nibbles are : [30] |
| 1380 | Configuring rams.array.row[row=7].ram[column=3].match_nibble_s0q1_enable.match_nibble_s0q1_enable to be 0xbfffffff. |
| 1381 | Configuring rams.array.row[row=7].ram[column=3].match_nibble_s1q0_enable.match_nibble_s1q0_enable to be 0xffffffff. |
| 1382 | Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=0].mask_bytes_0_to_13 to be 0x3fe3. |
| 1383 | Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=0].mask_nibbles_28_to_31 to be 0xb. |
| 1384 | Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=1].mask_bytes_0_to_13 to be 0x3fff. |
| 1385 | Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=1].mask_nibbles_28_to_31 to be 0xf. |
| 1386 | Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=2].mask_bytes_0_to_13 to be 0x3fff. |
| 1387 | Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=2].mask_nibbles_28_to_31 to be 0xf. |
| 1388 | Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=3].mask_bytes_0_to_13 to be 0x3fff. |
| 1389 | Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=3].mask_nibbles_28_to_31 to be 0xf. |
| 1390 | Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=4].mask_bytes_0_to_13 to be 0x3fff. |
| 1391 | Configuring rams.array.row[row=7].ram[column=3].match_bytemask[entry_in_ram_word=4].mask_nibbles_28_to_31 to be 0xf. |
| 1392 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1393 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1394 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1395 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1396 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1397 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1398 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1399 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1400 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1401 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1402 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1403 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1404 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1405 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1406 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1407 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1408 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1409 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1410 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1411 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1412 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1413 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1414 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8. |
| 1415 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8. |
| 1416 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8. |
| 1417 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8. |
| 1418 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0. |
| 1419 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1. |
| 1420 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_thread to be 0. |
| 1421 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=3].exactmatch_bank_enable_bank_mask to be 0x0. |
| 1422 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=3].exactmatch_bank_enable_bank_id to be 0x0. |
| 1423 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=3].exactmatch_bank_enable_inp_sel to be 1. |
| 1424 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0. |
| 1425 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1. |
| 1426 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=3].enabled_4bit_muxctl_select to be 1. |
| 1427 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=3].enabled_4bit_muxctl_enable to be 1. |
| 1428 | Configuring rams.match.merge.mau_action_instruction_adr_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_action_instruction_adr_exact_shiftcount to be 0. |
| 1429 | Configuring rams.match.merge.mau_immediate_data_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_immediate_data_exact_shiftcount to be 0. |
| 1430 | Configuring rams.match.merge.mau_stats_adr_exact_shiftcount[result_bus_number = 14][entry_in_ram_word=0].mau_stats_adr_exact_shiftcount to be 0x46. |
| 1431 | Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_type to be 1. |
| 1432 | Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_logical_table to be 0. |
| 1433 | Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_ingress to be 1. |
| 1434 | Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=3].unitram_enable to be 1. |
| 1435 | Configuring rams.array.row[row=7].emm_ecc_error_uram_ctl[direction=0].emm_ecc_error_uram_ctl to be select of 0x3. (previous value = 0x1 OR new value = 0x2) |
| 1436 | In Ram Word 0: |
| 1437 | wide entry 0 occupied ram word entry 0 |
| 1438 | Configuring rams.match.merge.col[col_number=3].row_action_nxtable_bus_drive[row_number=7].row_action_nxtable_bus_drive to be 1. |
| 1439 | Configuring rams.match.merge.col[col_number=3].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_select to be 14 (hit signal to output on). |
| 1440 | Configuring rams.match.merge.col[col_number=3].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1. |
| 1441 | --> Hash Match Way 2 |
| 1442 | Packed entry for hash way 2 is |
| 1443 | [0] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 0)) |
| 1444 | [1] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 1)) |
| 1445 | [2] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 2)) |
| 1446 | [3] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 3)) |
| 1447 | [4] = (field_bit=4, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 4)) |
| 1448 | [5] = (field_bit=5, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 5)) |
| 1449 | [6] = (field_bit=6, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 6)) |
| 1450 | [7] = (field_bit=7, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 7)) |
| 1451 | [8] = (field_bit=8, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 8)) |
| 1452 | [9] = (field_bit=9, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 9)) |
| 1453 | [10] = (field_bit=10, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 10)) |
| 1454 | [11] = (field_bit=11, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 11)) |
| 1455 | [12] = (field_bit=12, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 12)) |
| 1456 | [13] = (field_bit=13, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 13)) |
| 1457 | [14] = (field_bit=14, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 14)) |
| 1458 | [15] = (field_bit=15, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=overhead, mg=0, field_tuple=('--entry-overhead-0----immediate--', 15)) |
Carmelo Cascone | 8aa0548 | 2017-09-12 13:21:59 +0200 | [diff] [blame] | 1459 | [16] = (field_bit=0, hash_match_group_bit=16, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 0)) |
| 1460 | [17] = (field_bit=1, hash_match_group_bit=17, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 1)) |
| 1461 | [18] = (field_bit=2, hash_match_group_bit=18, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 2)) |
| 1462 | [19] = (field_bit=3, hash_match_group_bit=19, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 3)) |
| 1463 | [20] = (field_bit=4, hash_match_group_bit=20, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 4)) |
| 1464 | [21] = (field_bit=5, hash_match_group_bit=21, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 5)) |
| 1465 | [22] = (field_bit=6, hash_match_group_bit=22, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 6)) |
| 1466 | [23] = (field_bit=7, hash_match_group_bit=23, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 7)) |
| 1467 | [24] = (field_bit=8, hash_match_group_bit=24, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 8)) |
| 1468 | [25] = (field_bit=9, hash_match_group_bit=25, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 9)) |
| 1469 | [26] = (field_bit=10, hash_match_group_bit=26, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 10)) |
| 1470 | [27] = (field_bit=11, hash_match_group_bit=27, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 11)) |
| 1471 | [28] = (field_bit=12, hash_match_group_bit=28, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 12)) |
| 1472 | [29] = (field_bit=13, hash_match_group_bit=29, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 13)) |
| 1473 | [30] = (field_bit=14, hash_match_group_bit=30, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 14)) |
| 1474 | [31] = (field_bit=15, hash_match_group_bit=31, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.group_id', 15)) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1475 | [32] = None |
| 1476 | [33] = None |
| 1477 | [34] = (field_bit=10, hash_match_group_bit=10, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 10)) |
| 1478 | [35] = (field_bit=11, hash_match_group_bit=11, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 11)) |
| 1479 | [36] = (field_bit=12, hash_match_group_bit=12, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 12)) |
| 1480 | [37] = (field_bit=13, hash_match_group_bit=13, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 13)) |
| 1481 | [38] = (field_bit=14, hash_match_group_bit=14, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 14)) |
| 1482 | [39] = (field_bit=15, hash_match_group_bit=15, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-0--ecmp_metadata.selector', 15)) |
| 1483 | [40] = None |
| 1484 | [41] = None |
| 1485 | [42] = None |
| 1486 | [43] = None |
| 1487 | [44] = None |
| 1488 | [45] = None |
| 1489 | [46] = None |
| 1490 | [47] = None |
| 1491 | [48] = None |
| 1492 | [49] = None |
| 1493 | [50] = None |
| 1494 | [51] = None |
| 1495 | [52] = None |
| 1496 | [53] = None |
| 1497 | [54] = None |
| 1498 | [55] = None |
| 1499 | [56] = None |
| 1500 | [57] = None |
| 1501 | [58] = None |
| 1502 | [59] = None |
| 1503 | [60] = None |
| 1504 | [61] = None |
| 1505 | [62] = None |
| 1506 | [63] = None |
| 1507 | [64] = None |
| 1508 | [65] = None |
| 1509 | [66] = None |
| 1510 | [67] = None |
| 1511 | [68] = None |
| 1512 | [69] = None |
| 1513 | [70] = None |
| 1514 | [71] = None |
| 1515 | [72] = None |
| 1516 | [73] = None |
| 1517 | [74] = None |
| 1518 | [75] = None |
| 1519 | [76] = None |
| 1520 | [77] = None |
| 1521 | [78] = None |
| 1522 | [79] = None |
| 1523 | [80] = None |
| 1524 | [81] = None |
| 1525 | [82] = None |
| 1526 | [83] = None |
| 1527 | [84] = None |
| 1528 | [85] = None |
| 1529 | [86] = None |
| 1530 | [87] = None |
| 1531 | [88] = None |
| 1532 | [89] = None |
| 1533 | [90] = None |
| 1534 | [91] = None |
| 1535 | [92] = None |
| 1536 | [93] = None |
| 1537 | [94] = None |
| 1538 | [95] = None |
| 1539 | [96] = None |
| 1540 | [97] = None |
| 1541 | [98] = None |
| 1542 | [99] = None |
| 1543 | [100] = None |
| 1544 | [101] = None |
| 1545 | [102] = None |
| 1546 | [103] = None |
| 1547 | [104] = None |
| 1548 | [105] = None |
| 1549 | [106] = None |
| 1550 | [107] = None |
| 1551 | [108] = None |
| 1552 | [109] = None |
| 1553 | [110] = None |
| 1554 | [111] = None |
| 1555 | [112] = None |
| 1556 | [113] = None |
| 1557 | [114] = None |
| 1558 | [115] = None |
| 1559 | [116] = None |
| 1560 | [117] = None |
| 1561 | [118] = None |
| 1562 | [119] = None |
| 1563 | [120] = (field_bit=0, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 0)) |
| 1564 | [121] = (field_bit=1, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 1)) |
| 1565 | [122] = (field_bit=2, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 2)) |
| 1566 | [123] = (field_bit=3, hash_match_group_bit=-1, entry_in_ram_word=0, entry_in_wide_word=0, data_type=match_data, mg=0, field_tuple=('--entry-overhead-0----version_valid--', 3)) |
| 1567 | [124] = None |
| 1568 | [125] = None |
| 1569 | [126] = None |
| 1570 | [127] = None |
| 1571 | |
| 1572 | Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=0].match_mask to be 0xffff. |
| 1573 | Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=1].match_mask to be 0xffffff03. |
| 1574 | Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=2].match_mask to be 0xffffffff. |
| 1575 | Configuring rams.array.row[row=7].ram[column=4].match_mask[entry_index=3].match_mask to be 0xf0ffffff. |
| 1576 | Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_ram_write_data_mux_select to be 7. |
| 1577 | Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_ram_read_data_mux_select to be 7. |
| 1578 | Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_result_bus_select to be 1. |
| 1579 | Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_entry_enable to be 1. |
| 1580 | Configuring rams.array.row[row=7].ram[column=4].unit_ram_ctl.match_ram_logical_table to be 0x0. |
| 1581 | For entry_in_ram_word 0, should have vpn 2, with lower_two_bits of 2 and upper_vpn of 0 |
| 1582 | for entry_in_ram_word 0, use lsbs of 2 |
| 1583 | Configuring rams.array.row[row=7].ram[column=4].match_ram_vpn.match_ram_vpn0 to be 0. |
| 1584 | Configuring rams.array.row[row=7].ram[column=4].match_ram_vpn.match_ram_vpn_lsbs to be 0x2. |
| 1585 | version valid nibbles are : [30] |
| 1586 | Configuring rams.array.row[row=7].ram[column=4].match_nibble_s0q1_enable.match_nibble_s0q1_enable to be 0xbfffffff. |
| 1587 | Configuring rams.array.row[row=7].ram[column=4].match_nibble_s1q0_enable.match_nibble_s1q0_enable to be 0xffffffff. |
| 1588 | Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=0].mask_bytes_0_to_13 to be 0x3fe3. |
| 1589 | Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=0].mask_nibbles_28_to_31 to be 0xb. |
| 1590 | Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=1].mask_bytes_0_to_13 to be 0x3fff. |
| 1591 | Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=1].mask_nibbles_28_to_31 to be 0xf. |
| 1592 | Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=2].mask_bytes_0_to_13 to be 0x3fff. |
| 1593 | Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=2].mask_nibbles_28_to_31 to be 0xf. |
| 1594 | Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=3].mask_bytes_0_to_13 to be 0x3fff. |
| 1595 | Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=3].mask_nibbles_28_to_31 to be 0xf. |
| 1596 | Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=4].mask_bytes_0_to_13 to be 0x3fff. |
| 1597 | Configuring rams.array.row[row=7].ram[column=4].match_bytemask[entry_in_ram_word=4].mask_nibbles_28_to_31 to be 0xf. |
| 1598 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1599 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1600 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1601 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1602 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1603 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1604 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1605 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=2][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x12. |
| 1606 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1607 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1608 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1609 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1610 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1611 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1612 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1613 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=3][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x13. |
| 1614 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1615 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1616 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=4].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1617 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=5].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1618 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=6].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1619 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=4][bit_number=7].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x11. |
| 1620 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=0].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8. |
| 1621 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=1].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8. |
| 1622 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=2].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8. |
| 1623 | Configuring rams.array.row[row=7].exactmatch_row_vh_xbar_byteswizzle_ctl[search_bus_index=0][ram_byte=15][bit_number=3].exactmatch_row_vh_xbar_byteswizzle_ctl to be 0x8. |
| 1624 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0. |
| 1625 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1. |
| 1626 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_thread to be 0. |
| 1627 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=4].exactmatch_bank_enable_bank_mask to be 0x0. |
| 1628 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=4].exactmatch_bank_enable_bank_id to be 0x0. |
| 1629 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_bank_enable[sram_col=4].exactmatch_bank_enable_inp_sel to be 1. |
| 1630 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0. |
| 1631 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1. |
| 1632 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=4].enabled_4bit_muxctl_select to be 2. |
| 1633 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_mem_hashadr_xbar_ctl[sram_col=4].enabled_4bit_muxctl_enable to be 1. |
| 1634 | Configuring rams.match.merge.mau_action_instruction_adr_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_action_instruction_adr_exact_shiftcount to be 0. |
| 1635 | Configuring rams.match.merge.mau_immediate_data_exact_shiftcount[physical_result_bus=14][entry_in_ram_word=0].mau_immediate_data_exact_shiftcount to be 0. |
| 1636 | Configuring rams.match.merge.mau_stats_adr_exact_shiftcount[result_bus_number = 14][entry_in_ram_word=0].mau_stats_adr_exact_shiftcount to be 0x46. |
| 1637 | Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_type to be 1. |
| 1638 | Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_logical_table to be 0. |
| 1639 | Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_ingress to be 1. |
| 1640 | Configuring rams.map_alu.row[row=7].adrmux.unitram_config[column_half=0][column_index=4].unitram_enable to be 1. |
| 1641 | Configuring rams.array.row[row=7].emm_ecc_error_uram_ctl[direction=0].emm_ecc_error_uram_ctl to be select of 0x7. (previous value = 0x3 OR new value = 0x4) |
| 1642 | In Ram Word 0: |
| 1643 | wide entry 0 occupied ram word entry 0 |
| 1644 | Configuring rams.match.merge.col[col_number=4].row_action_nxtable_bus_drive[row_number=7].row_action_nxtable_bus_drive to be 1. |
| 1645 | Configuring rams.match.merge.col[col_number=4].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_select to be 14 (hit signal to output on). |
| 1646 | Configuring rams.match.merge.col[col_number=4].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1. |
| 1647 | |
| 1648 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 1649 | | Working on table ecmp_group_table_counter in stage 1 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1650 | +------------------------------------------------------------------------ |
| 1651 | Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 1652 | Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 1653 | Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 1654 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3. |
| 1655 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 1656 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0. |
| 1657 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1. |
| 1658 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1. |
| 1659 | Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 1660 | Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 1661 | Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 1662 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3. |
| 1663 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 1664 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0. |
| 1665 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1. |
| 1666 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1. |
| 1667 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5. |
| 1668 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1. |
| 1669 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 1670 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1. |
| 1671 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 1672 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 1673 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5. |
| 1674 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1. |
| 1675 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 1676 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1. |
| 1677 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2) |
| 1678 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 1679 | Stat table ecmp_group_table_counter is used by match table ecmp_group_table. |
| 1680 | Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8) |
| 1681 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1. |
| 1682 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0. |
| 1683 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 1684 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| 1685 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| 1686 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| 1687 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| 1688 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1. |
| 1689 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| 1690 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| 1691 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1. |
| 1692 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0. |
| 1693 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 1694 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1. |
| 1695 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1. |
| 1696 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1. |
| 1697 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1. |
| 1698 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1. |
| 1699 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1. |
| 1700 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1. |
| 1701 | For counter width 32 and N = 4096 |
| 1702 | number iterations = 32 |
| 1703 | b_cur = 379488672.0 |
| 1704 | eqn(b_cur) = 4294964039.26 |
| 1705 | max_counter_value = 4294967295 |
| 1706 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a. |
| 1707 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff. |
| 1708 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a. |
| 1709 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff. |
| 1710 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a. |
| 1711 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff. |
| 1712 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4. |
| 1713 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1. |
| 1714 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1. |
| 1715 | TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0. |
| 1716 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x0. |
| 1717 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4. |
| 1718 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1. |
| 1719 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0. |
| 1720 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0. |
| 1721 | Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0. |
| 1722 | Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0. |
| 1723 | Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0. |
| 1724 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0. |
| 1725 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0. |
| 1726 | Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1. |
| 1727 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3. |
| 1728 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_direct be 1. |
| 1729 | Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=0].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 1730 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x0. |
| 1731 | Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x7. ( previous value = 0x0 OR new value = 0x7) |
| 1732 | Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x1. |
| 1733 | +------------------------------------------------------------------------ |
| 1734 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19. |
| 1735 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9. |
| 1736 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3. |
| 1737 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 1738 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 1739 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 1740 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1741 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1742 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1743 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1744 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 1745 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x1. |
| 1746 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 1747 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 1748 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 1749 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x40. |
| 1750 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 1751 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 1752 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 1753 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19. |
| 1754 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 1755 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 1756 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 1757 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 1758 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 1759 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 1760 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 1761 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 1762 | -------------------------------------------- |
| 1763 | Configuration for unused statistics ALUs. |
| 1764 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 1765 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 1766 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 1767 | +------------------------------------------------------------------------ |
| 1768 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f. |
| 1769 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f. |
| 1770 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1771 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f. |
| 1772 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f. |
| 1773 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1774 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff. |
| 1775 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff. |
| 1776 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1777 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1. |
| 1778 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1. |
| 1779 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 1780 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 1781 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 1782 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 1783 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 1784 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 1785 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1786 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 1787 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 1788 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 1789 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 1790 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 1791 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 1792 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 1793 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 1794 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 1795 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 1796 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 1797 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 1798 | +------------------------------------------------------------------------ |
| 1799 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 1800 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 1801 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0. |
| 1802 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0. |
| 1803 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 1804 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 1805 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 1806 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 1807 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1. |
| 1808 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2. |
| 1809 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 1810 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 1811 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 1812 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 1813 | |
| 1814 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 1815 | | MAU Stage 2 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1816 | +------------------------------------------------------------------------ |
| 1817 | |
| 1818 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 1819 | | Working on table _condition_2 in stage 2 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1820 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 1821 | --> Stage Gateway Table for condition _condition_2 in stage 2 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1822 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 1823 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 1824 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 1825 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 1826 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 1827 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 1828 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1) |
| 1829 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1830 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 18. |
| 1831 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_enable to be 1. |
| 1832 | Configuring match input crossbar byte 2 to come from 16-bit PHV container 2. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1833 | That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1834 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 18. |
| 1835 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_enable to be 1. |
| 1836 | Configuring match input crossbar byte 3 to come from 16-bit PHV container 2. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1837 | That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}. |
| 1838 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4) |
| 1839 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 1840 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1841 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=40].byte1 to be 0x1. |
| 1842 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=41].byte0 to be 0x1. |
| 1843 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=42].byte0 to be 0x2. |
| 1844 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=43].byte0 to be 0x4. |
| 1845 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=44].byte0 to be 0x8. |
| 1846 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=45].byte0 to be 0x10. |
| 1847 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=46].byte0 to be 0x20. |
| 1848 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=47].byte0 to be 0x40. |
| 1849 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=48].byte0 to be 0x80. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1850 | Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 1851 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0. |
| 1852 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1. |
| 1853 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0. |
| 1854 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1. |
| 1855 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| 1856 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| 1857 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| 1858 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| 1859 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0 |
| 1860 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0 |
| 1861 | Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| 1862 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| 1863 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| 1864 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| 1865 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| 1866 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_mode to be 0x2 |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1867 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffff00 |
| 1868 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff00 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1869 | Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 1870 | Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x21 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1871 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid0 to be 0x3 |
| 1872 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid1 to be 0x3 |
| 1873 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][0] to be 0xffffffff |
| 1874 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][1] to be 0xffffffff |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1875 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xff00ff |
| 1876 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff00ff |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1877 | Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xc (previous value 0x8 OR new value 0x4) |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 1878 | Configuring rams.match.merge.gateway_next_table_lut[0][2] to be 0x21 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1879 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid0 to be 0x3 |
| 1880 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid1 to be 0x3 |
| 1881 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][0] to be 0xffffffff |
| 1882 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][1] to be 0xffffffff |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1883 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0x3ffff |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1884 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][1] to be 0xffff |
| 1885 | Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xe (previous value 0xc OR new value 0x2) |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 1886 | Configuring rams.match.merge.gateway_next_table_lut[0][1] to be 0x21 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1887 | Configuring rams.match.merge.gateway_en.gateway_en to be 0x1 |
| 1888 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf |
| 1889 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1 |
| 1890 | allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits |
| 1891 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x0 |
| 1892 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1 |
| 1893 | Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2 |
| 1894 | Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x1 |
| 1895 | Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0 |
| 1896 | Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x1 |
| 1897 | Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0 |
| 1898 | Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff |
| 1899 | Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff |
| 1900 | |
| 1901 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 1902 | | Working on table ingress_port_count_table__action__ in stage 2 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1903 | +------------------------------------------------------------------------ |
| 1904 | --> Action Data Table ingress_port_count_table__action__ with logical_table_id 0 that is reference type is 'direct' |
| 1905 | |
| 1906 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 1907 | | Working on table ingress_port_count_table in stage 2 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1908 | +------------------------------------------------------------------------ |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1909 | --> Hash Action Table ingress_port_count_table with logical_table_id 0 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1910 | allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits |
| 1911 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| 1912 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| 1913 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| 1914 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| 1915 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| 1916 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| 1917 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id). |
| 1918 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1. |
| 1919 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id). |
| 1920 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1. |
| 1921 | Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x0. |
| 1922 | Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x1. |
| 1923 | Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0xff. |
| 1924 | Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=1].mau_stats_adr_default to be 0x0. |
| 1925 | Configuring rams.match.merge.mau_stats_adr_per_entry_en_mux_ctl[table_type_index=0][result_bus_number=1].mau_stats_adr_per_entry_en_mux_ctl to be 0x7. |
| 1926 | Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 1927 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2000. |
| 1928 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1929 | |
| 1930 | ---- Hash Distribution Units for table ingress_port_count_table ---- |
| 1931 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x1) |
| 1932 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| 1933 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 16. |
| 1934 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1. |
| 1935 | Configuring match input crossbar byte 0 to come from 16-bit PHV container 0. |
| 1936 | That PHV byte contains {ig_intr_md.ingress_port[7:0]}. |
| 1937 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 16. |
| 1938 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1. |
| 1939 | Configuring match input crossbar byte 1 to come from 16-bit PHV container 0. |
| 1940 | That PHV byte contains {unused[6:0], ig_intr_md.ingress_port[8:8]}. |
| 1941 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x5. (previous value = 0x4 OR new value = 0x1) |
| 1942 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x1) |
| 1943 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| 1944 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x1. |
| 1945 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte0 to be 0x2. |
| 1946 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte0 to be 0x4. |
| 1947 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte0 to be 0x8. |
| 1948 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte0 to be 0x10. |
| 1949 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte0 to be 0x20. |
| 1950 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte0 to be 0x40. |
| 1951 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte0 to be 0x80. |
| 1952 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=8].byte1 to be 0x1. |
| 1953 | Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1) |
| 1954 | Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 1. (old value = 0 OR new value = 1). |
| 1955 | Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 8. (old value = 0 OR new value = 8). |
| 1956 | Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 1. (old value = 0 OR new value = 1). |
Carmelo Cascone | 133c7b1 | 2017-09-13 15:36:08 +0200 | [diff] [blame] | 1957 | Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x2. (old value = 0x0 OR new value = 0x2). |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1958 | Configuring rams.match.merge.mau_hash_group_mask[which_16=0].mau_hash_group_mask to be 0x3ff. (previous value = 0x0 OR new value = 0x3ff) |
| 1959 | Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=3][control_group_index=0].mau_hash_group_xbar_ctl to be 0x8 (old value = 0x0 OR new value = 0x8). |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1960 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].stats_adr_payload_shifter_en to be 1. |
| 1961 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1. |
| 1962 | |
| 1963 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 1964 | | Working on table egress_port_count_table__action__ in stage 2 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1965 | +------------------------------------------------------------------------ |
| 1966 | --> Action Data Table egress_port_count_table__action__ with logical_table_id 1 that is reference type is 'direct' |
| 1967 | |
| 1968 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 1969 | | Working on table egress_port_count_table in stage 2 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1970 | +------------------------------------------------------------------------ |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1971 | --> Hash Action Table egress_port_count_table with logical_table_id 1 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1972 | allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits |
| 1973 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 1974 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 1975 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 1976 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 1977 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 1978 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 1979 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id). |
| 1980 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| 1981 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id). |
| 1982 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| 1983 | Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_default to be 0x40. |
| 1984 | Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x0. |
| 1985 | Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0xff. |
| 1986 | Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0xff. |
| 1987 | Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=0].mau_stats_adr_default to be 0x80000. |
| 1988 | Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 1989 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x40. |
| 1990 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 1991 | |
| 1992 | ---- Hash Distribution Units for table egress_port_count_table ---- |
| 1993 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x1 OR new value = 0x2) |
| 1994 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| 1995 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_address to be 18. |
| 1996 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_enable to be 1. |
| 1997 | Configuring match input crossbar byte 8 to come from 16-bit PHV container 2. |
| 1998 | That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}. |
| 1999 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_address to be 18. |
| 2000 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_enable to be 1. |
| 2001 | Configuring match input crossbar byte 9 to come from 16-bit PHV container 2. |
| 2002 | That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}. |
| 2003 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x5. (previous value = 0x5 OR new value = 0x4) |
| 2004 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=1][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2) |
| 2005 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=1][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| 2006 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0x1. |
| 2007 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=1].byte0 to be 0x2. |
| 2008 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=2].byte0 to be 0x4. |
| 2009 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=3].byte0 to be 0x8. |
| 2010 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=4].byte0 to be 0x10. |
| 2011 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=5].byte0 to be 0x20. |
| 2012 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=6].byte0 to be 0x40. |
| 2013 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=7].byte0 to be 0x80. |
| 2014 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=8].byte1 to be 0x1. |
| 2015 | Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x3. (previous value = 0x1 OR new value = 0x2) |
| 2016 | Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 9. (old value = 1 OR new value = 8). |
| 2017 | Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 152. (old value = 8 OR new value = 144). |
| 2018 | Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 65. (old value = 1 OR new value = 64). |
Carmelo Cascone | 133c7b1 | 2017-09-13 15:36:08 +0200 | [diff] [blame] | 2019 | Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x402. (old value = 0x2 OR new value = 0x400). |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2020 | Configuring rams.match.merge.mau_hash_group_mask[which_16=3].mau_hash_group_mask to be 0x3ff. (previous value = 0x0 OR new value = 0x3ff) |
| 2021 | Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=3][control_group_index=0].mau_hash_group_xbar_ctl to be 0xb8 (old value = 0x8 OR new value = 0xb0). |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2022 | --> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 2 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2023 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 2024 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 2025 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 2026 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 2027 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 2028 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2029 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x3 OR new value = 0x0) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2030 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| 2031 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x0) |
| 2032 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2033 | Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x3. (previous value = 0x3 OR new value = 0x1) |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2034 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| 2035 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| 2036 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| 2037 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| 2038 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1 |
| 2039 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0 |
| 2040 | Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| 2041 | Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| 2042 | Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| 2043 | Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| 2044 | Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| 2045 | Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff |
| 2046 | Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff |
| 2047 | Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8 |
| 2048 | Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0xff |
| 2049 | Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10) |
| 2050 | Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0xff |
| 2051 | Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2) |
| 2052 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe |
| 2053 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1 |
| 2054 | allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits |
| 2055 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_logical_select to be 0x1 |
| 2056 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_inhibit_enable to be 0x1 |
| 2057 | Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x3 (previous value 0x2 OR new value 0x1) |
| 2058 | Configuring rams.match.merge.gateway_payload_data[0][0][0][0].gateway_payload_data to be 0x0 |
| 2059 | Configuring rams.match.merge.gateway_payload_data[0][0][1][0].gateway_payload_data to be 0x0 |
| 2060 | Configuring rams.match.merge.gateway_payload_data[0][0][0][1].gateway_payload_data to be 0x0 |
| 2061 | Configuring rams.match.merge.gateway_payload_data[0][0][1][1].gateway_payload_data to be 0x0 |
| 2062 | Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff |
| 2063 | Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff |
| 2064 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=0].action_instruction_adr_payload_shifter_en to be 1. |
| 2065 | |
| 2066 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2067 | | Working on table ingress_port_counter in stage 2 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2068 | +------------------------------------------------------------------------ |
| 2069 | Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 2070 | Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 2071 | Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 2072 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3. |
| 2073 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 2074 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0. |
| 2075 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1. |
| 2076 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1. |
| 2077 | Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 2078 | Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 2079 | Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 2080 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3. |
| 2081 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 2082 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0. |
| 2083 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1. |
| 2084 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1. |
| 2085 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5. |
| 2086 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1. |
| 2087 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 2088 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1. |
| 2089 | Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 2090 | Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 2091 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5. |
| 2092 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1. |
| 2093 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 2094 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1. |
| 2095 | Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2) |
| 2096 | Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 2097 | Stat table ingress_port_counter is used by match table ingress_port_count_table. |
| 2098 | Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x4. (previous value = 0x0 OR new value =0x4) |
| 2099 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1. |
| 2100 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0. |
| 2101 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 2102 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| 2103 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| 2104 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| 2105 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| 2106 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1. |
| 2107 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| 2108 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| 2109 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1. |
| 2110 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0. |
| 2111 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 2112 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1. |
| 2113 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1. |
| 2114 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1. |
| 2115 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1. |
| 2116 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1. |
| 2117 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1. |
| 2118 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1. |
Carmelo Cascone | 133c7b1 | 2017-09-13 15:36:08 +0200 | [diff] [blame] | 2119 | Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_entries_per_word to be 2. |
Carmelo Cascone | 0ce8f5d | 2017-09-13 03:50:36 +0200 | [diff] [blame] | 2120 | Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_process_bytes to be 1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2121 | TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_alu_error_enable to be 0. |
| 2122 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0x0. |
Carmelo Cascone | 133c7b1 | 2017-09-13 15:36:08 +0200 | [diff] [blame] | 2123 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x2. |
Carmelo Cascone | 0ce8f5d | 2017-09-13 03:50:36 +0200 | [diff] [blame] | 2124 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_bytes be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2125 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0. |
| 2126 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2127 | Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0. |
| 2128 | Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0. |
Carmelo Cascone | 0ce8f5d | 2017-09-13 03:50:36 +0200 | [diff] [blame] | 2129 | Configuring rams.match.adrdist.deferred_ram_ctl[deferred_ram_type=0][deferred_ram_index=2].deferred_ram_en to be 1. |
Carmelo Cascone | 133c7b1 | 2017-09-13 15:36:08 +0200 | [diff] [blame] | 2130 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_size be 1. |
Carmelo Cascone | 0ce8f5d | 2017-09-13 03:50:36 +0200 | [diff] [blame] | 2131 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_deferred be 1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2132 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_lt be 0x0. |
| 2133 | Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x6. ( previous value = 0x0 OR new value = 0x6) |
| 2134 | Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=2].mau_ad_stats_virt_lt be 0x1. |
| 2135 | |
| 2136 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2137 | | Working on table egress_port_counter in stage 2 --- |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2138 | +------------------------------------------------------------------------ |
| 2139 | Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 2140 | Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 2141 | Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 2142 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3. |
| 2143 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 2144 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 1. |
| 2145 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1. |
| 2146 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1. |
| 2147 | Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 2148 | Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 2149 | Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 2150 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3. |
| 2151 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 2152 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 1. |
| 2153 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1. |
| 2154 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1. |
| 2155 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5. |
| 2156 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1. |
| 2157 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 2158 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1. |
| 2159 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 2160 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 2161 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5. |
| 2162 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1. |
| 2163 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 2164 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1. |
| 2165 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2) |
| 2166 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 2167 | Stat table egress_port_counter is used by match table egress_port_count_table. |
| 2168 | Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=1].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8) |
| 2169 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1. |
| 2170 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 1. |
| 2171 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 2172 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| 2173 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| 2174 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| 2175 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| 2176 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1. |
| 2177 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| 2178 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| 2179 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1. |
| 2180 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 1. |
| 2181 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 2182 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1. |
| 2183 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1. |
| 2184 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1. |
| 2185 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1. |
| 2186 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1. |
| 2187 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1. |
| 2188 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1. |
Carmelo Cascone | 133c7b1 | 2017-09-13 15:36:08 +0200 | [diff] [blame] | 2189 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 2. |
Carmelo Cascone | 0ce8f5d | 2017-09-13 03:50:36 +0200 | [diff] [blame] | 2190 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_bytes to be 1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2191 | TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0. |
| 2192 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x1. |
Carmelo Cascone | 133c7b1 | 2017-09-13 15:36:08 +0200 | [diff] [blame] | 2193 | Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_entries_per_word be 0x2. |
Carmelo Cascone | 0ce8f5d | 2017-09-13 03:50:36 +0200 | [diff] [blame] | 2194 | Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_has_bytes be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2195 | Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_offset be 0x0. |
| 2196 | Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_size be 0x0. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2197 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0. |
| 2198 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0. |
Carmelo Cascone | 0ce8f5d | 2017-09-13 03:50:36 +0200 | [diff] [blame] | 2199 | Configuring rams.match.adrdist.deferred_ram_ctl[deferred_ram_type=0][deferred_ram_index=3].deferred_ram_en to be 1. |
Carmelo Cascone | 133c7b1 | 2017-09-13 15:36:08 +0200 | [diff] [blame] | 2200 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 1. |
Carmelo Cascone | 0ce8f5d | 2017-09-13 03:50:36 +0200 | [diff] [blame] | 2201 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_deferred be 1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2202 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x1. |
| 2203 | Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=3].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x3e. ( previous value = 0x6 OR new value = 0x38) |
| 2204 | Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x2. |
| 2205 | +------------------------------------------------------------------------ |
| 2206 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19. |
| 2207 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9. |
| 2208 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3. |
| 2209 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 2210 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 2211 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 2212 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2213 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2214 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2215 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2216 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 2217 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x3. |
| 2218 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 2219 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 2220 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x3. |
| 2221 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 2222 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 2223 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 2224 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 2225 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 2226 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 2227 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 2228 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 2229 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 2230 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 2231 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 2232 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 2233 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 2234 | -------------------------------------------- |
| 2235 | Configuration for unused statistics ALUs. |
| 2236 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 2237 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 2238 | +------------------------------------------------------------------------ |
| 2239 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f. |
| 2240 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f. |
| 2241 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2242 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f. |
| 2243 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f. |
| 2244 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2245 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff. |
| 2246 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff. |
| 2247 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2248 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1. |
| 2249 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1. |
| 2250 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2251 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 2252 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 2253 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 2254 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 2255 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 2256 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2257 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 2258 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 2259 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 2260 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 2261 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 2262 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 2263 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 2264 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 2265 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 2266 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 2267 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 2268 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 2269 | +------------------------------------------------------------------------ |
| 2270 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 2271 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 2272 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0. |
| 2273 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 2274 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 2275 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 2276 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 2277 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 2278 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1. |
| 2279 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2. |
| 2280 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 2281 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 2282 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 2283 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 2284 | |
| 2285 | +------------------------------------------------------------------------ |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2286 | | MAU Stage 3 |
| 2287 | +------------------------------------------------------------------------ |
| 2288 | +------------------------------------------------------------------------ |
| 2289 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 2290 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 2291 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 2292 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 2293 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 2294 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 2295 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2296 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2297 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2298 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2299 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 2300 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 2301 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 2302 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 2303 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 2304 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 2305 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 2306 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 2307 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 2308 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 2309 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 2310 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 2311 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 2312 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 2313 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 2314 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 2315 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 2316 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 2317 | -------------------------------------------- |
| 2318 | Configuration for unused statistics ALUs. |
| 2319 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 2320 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 2321 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 2322 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 2323 | +------------------------------------------------------------------------ |
| 2324 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f. |
| 2325 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f. |
| 2326 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2327 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f. |
| 2328 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f. |
| 2329 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2330 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff. |
| 2331 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff. |
| 2332 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2333 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1. |
| 2334 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1. |
| 2335 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2336 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 2337 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 2338 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 2339 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 2340 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 2341 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| 2342 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 2343 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 2344 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 2345 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 2346 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 2347 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 2348 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 2349 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 2350 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 2351 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 2352 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 2353 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 2354 | +------------------------------------------------------------------------ |
| 2355 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 2356 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 2357 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 2358 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 2359 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 2360 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 2361 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 2362 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 2363 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 2364 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 2365 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 2366 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 2367 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 2368 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 2369 | |
| 2370 | +------------------------------------------------------------------------ |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2371 | | MAU Stage 4 |
| 2372 | +------------------------------------------------------------------------ |
| 2373 | +------------------------------------------------------------------------ |
| 2374 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 2375 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 2376 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 2377 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 2378 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 2379 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 2380 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2381 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2382 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2383 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2384 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 2385 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 2386 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 2387 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 2388 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 2389 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 2390 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 2391 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 2392 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 2393 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 2394 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 2395 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 2396 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 2397 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 2398 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 2399 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 2400 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 2401 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 2402 | -------------------------------------------- |
| 2403 | Configuration for unused statistics ALUs. |
| 2404 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 2405 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 2406 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 2407 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 2408 | +------------------------------------------------------------------------ |
| 2409 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f. |
| 2410 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f. |
| 2411 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2412 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f. |
| 2413 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f. |
| 2414 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2415 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff. |
| 2416 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff. |
| 2417 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2418 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1. |
| 2419 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1. |
| 2420 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2421 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 2422 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 2423 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 2424 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 2425 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 2426 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2427 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 2428 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 2429 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 2430 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 2431 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 2432 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 2433 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 2434 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 2435 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 2436 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 2437 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 2438 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 2439 | +------------------------------------------------------------------------ |
| 2440 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 2441 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 2442 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 2443 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 2444 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 2445 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 2446 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 2447 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 2448 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 2449 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 2450 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 2451 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 2452 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 2453 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 2454 | |
| 2455 | +------------------------------------------------------------------------ |
| 2456 | | MAU Stage 5 |
| 2457 | +------------------------------------------------------------------------ |
| 2458 | +------------------------------------------------------------------------ |
| 2459 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 2460 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 2461 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 2462 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 2463 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 2464 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 2465 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2466 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2467 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2468 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2469 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 2470 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 2471 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 2472 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 2473 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 2474 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 2475 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 2476 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 2477 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 2478 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19. |
| 2479 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 2480 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 2481 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19. |
| 2482 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 2483 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 2484 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 2485 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 2486 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 2487 | -------------------------------------------- |
| 2488 | Configuration for unused statistics ALUs. |
| 2489 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 2490 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 2491 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 2492 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 2493 | +------------------------------------------------------------------------ |
| 2494 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f. |
| 2495 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f. |
| 2496 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2497 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f. |
| 2498 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f. |
| 2499 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2500 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff. |
| 2501 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff. |
| 2502 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2503 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1. |
| 2504 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1. |
| 2505 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2506 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 2507 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 2508 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 2509 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 2510 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 2511 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2512 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 2513 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 2514 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 2515 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 2516 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 2517 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 2518 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 2519 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 2520 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 2521 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 2522 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 2523 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 2524 | +------------------------------------------------------------------------ |
| 2525 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 2526 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 2527 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 2528 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0. |
| 2529 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 2530 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 2531 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 2532 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0. |
| 2533 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 2534 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 2535 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 2536 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 2537 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 2538 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 2539 | |
| 2540 | +------------------------------------------------------------------------ |
| 2541 | | MAU Stage 6 |
| 2542 | +------------------------------------------------------------------------ |
| 2543 | +------------------------------------------------------------------------ |
| 2544 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19. |
| 2545 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9. |
| 2546 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3. |
| 2547 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 19. |
| 2548 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 9. |
| 2549 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 3. |
| 2550 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2551 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2552 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2553 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2554 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 2555 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 2556 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 2557 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 2558 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 2559 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 2560 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 2561 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 2562 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 2563 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 2564 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 2565 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 2566 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 2567 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 2568 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 2569 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 2570 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 2571 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 2572 | -------------------------------------------- |
| 2573 | Configuration for unused statistics ALUs. |
| 2574 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 2575 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 2576 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 2577 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 2578 | +------------------------------------------------------------------------ |
| 2579 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f. |
| 2580 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f. |
| 2581 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2582 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f. |
| 2583 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f. |
| 2584 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2585 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff. |
| 2586 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff. |
| 2587 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2588 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1. |
| 2589 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1. |
| 2590 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2591 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 2592 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 2593 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 2594 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 2595 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 2596 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2597 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 2598 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 2599 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 2600 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 2601 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 2602 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 2603 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 2604 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 2605 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 2606 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 2607 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 2608 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 2609 | +------------------------------------------------------------------------ |
| 2610 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 2611 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 2612 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0. |
| 2613 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 2614 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 2615 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 2616 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0. |
| 2617 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 2618 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 3. |
| 2619 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0. |
| 2620 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 2621 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 2622 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 2623 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 2624 | |
| 2625 | +------------------------------------------------------------------------ |
| 2626 | | MAU Stage 7 |
| 2627 | +------------------------------------------------------------------------ |
| 2628 | +------------------------------------------------------------------------ |
| 2629 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 2630 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 2631 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 2632 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 2633 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 2634 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 2635 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2636 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2637 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2638 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2639 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 2640 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 2641 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 2642 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 2643 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 2644 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 2645 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 2646 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 2647 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 2648 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 2649 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 2650 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 2651 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 2652 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 2653 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 2654 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 2655 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 2656 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 2657 | -------------------------------------------- |
| 2658 | Configuration for unused statistics ALUs. |
| 2659 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 2660 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 2661 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 2662 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 2663 | +------------------------------------------------------------------------ |
| 2664 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f. |
| 2665 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f. |
| 2666 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2667 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f. |
| 2668 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f. |
| 2669 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2670 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff. |
| 2671 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff. |
| 2672 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2673 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1. |
| 2674 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1. |
| 2675 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2676 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 2677 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 2678 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 2679 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 2680 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 2681 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2682 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 2683 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 2684 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 2685 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 2686 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 2687 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 2688 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 2689 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 2690 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 2691 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 2692 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 2693 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 2694 | +------------------------------------------------------------------------ |
| 2695 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 2696 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 2697 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 2698 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 2699 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 2700 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 2701 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 2702 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 2703 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 2704 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 2705 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 2706 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 2707 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 2708 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 2709 | |
| 2710 | +------------------------------------------------------------------------ |
| 2711 | | MAU Stage 8 |
| 2712 | +------------------------------------------------------------------------ |
| 2713 | +------------------------------------------------------------------------ |
| 2714 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 2715 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 2716 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 2717 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 2718 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 2719 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 2720 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2721 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2722 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2723 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2724 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 2725 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 2726 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 2727 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 2728 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 2729 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 2730 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 2731 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 2732 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 2733 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 2734 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 2735 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 2736 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 2737 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 2738 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 2739 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 2740 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 2741 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 2742 | -------------------------------------------- |
| 2743 | Configuration for unused statistics ALUs. |
| 2744 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 2745 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 2746 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 2747 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 2748 | +------------------------------------------------------------------------ |
| 2749 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f. |
| 2750 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f. |
| 2751 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2752 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f. |
| 2753 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f. |
| 2754 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2755 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff. |
| 2756 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff. |
| 2757 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2758 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1. |
| 2759 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1. |
| 2760 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2761 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 2762 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 2763 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 2764 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 2765 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 2766 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2767 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 2768 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 2769 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 2770 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 2771 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 2772 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 2773 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 2774 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 2775 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 2776 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 2777 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 2778 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 2779 | +------------------------------------------------------------------------ |
| 2780 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 2781 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 2782 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 2783 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 2784 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 2785 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 2786 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 2787 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 2788 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 2789 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 2790 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 2791 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 2792 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 2793 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 2794 | |
| 2795 | +------------------------------------------------------------------------ |
| 2796 | | MAU Stage 9 |
| 2797 | +------------------------------------------------------------------------ |
| 2798 | +------------------------------------------------------------------------ |
| 2799 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 2800 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 2801 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 2802 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 2803 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 2804 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 2805 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2806 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2807 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2808 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2809 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 2810 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 2811 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 2812 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 2813 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 2814 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 2815 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 2816 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 2817 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 2818 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 2819 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 2820 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 2821 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 2822 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 2823 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 2824 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 2825 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 2826 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 2827 | -------------------------------------------- |
| 2828 | Configuration for unused statistics ALUs. |
| 2829 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 2830 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 2831 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 2832 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 2833 | +------------------------------------------------------------------------ |
| 2834 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f. |
| 2835 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f. |
| 2836 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2837 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f. |
| 2838 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f. |
| 2839 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2840 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff. |
| 2841 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff. |
| 2842 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2843 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1. |
| 2844 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1. |
| 2845 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2846 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 2847 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 2848 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 2849 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 2850 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 2851 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2852 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 2853 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 2854 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 2855 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 2856 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 2857 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 2858 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 2859 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 2860 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 2861 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 2862 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 2863 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 2864 | +------------------------------------------------------------------------ |
| 2865 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 2866 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 2867 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 2868 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 2869 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 2870 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 2871 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 2872 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 2873 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 2874 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 2875 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 2876 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 2877 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 2878 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 2879 | |
| 2880 | +------------------------------------------------------------------------ |
| 2881 | | MAU Stage 10 |
| 2882 | +------------------------------------------------------------------------ |
| 2883 | +------------------------------------------------------------------------ |
| 2884 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 2885 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 2886 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 2887 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 2888 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 2889 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 2890 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2891 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2892 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2893 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2894 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 2895 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 2896 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 2897 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 2898 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 2899 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 2900 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 2901 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 2902 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 2903 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 2904 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 2905 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 2906 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 2907 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 2908 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 2909 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 2910 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 2911 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 2912 | -------------------------------------------- |
| 2913 | Configuration for unused statistics ALUs. |
| 2914 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 2915 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 2916 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 2917 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 2918 | +------------------------------------------------------------------------ |
| 2919 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f. |
| 2920 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f. |
| 2921 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2922 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f. |
| 2923 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f. |
| 2924 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2925 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff. |
| 2926 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff. |
| 2927 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 2928 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1. |
| 2929 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1. |
| 2930 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 2931 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 2932 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 2933 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 2934 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 2935 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 2936 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 2937 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 2938 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 2939 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 2940 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 2941 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 2942 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 2943 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 2944 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 2945 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 2946 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 2947 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 2948 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 2949 | +------------------------------------------------------------------------ |
| 2950 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 2951 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 2952 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 2953 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 2954 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 2955 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 2956 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 2957 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 2958 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 2959 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 2960 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 2961 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 2962 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 2963 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 2964 | |
| 2965 | +------------------------------------------------------------------------ |
| 2966 | | MAU Stage 11 |
| 2967 | +------------------------------------------------------------------------ |
| 2968 | +------------------------------------------------------------------------ |
| 2969 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 2970 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 2971 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 2972 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 2973 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 2974 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 2975 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2976 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2977 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 2978 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 2979 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 2980 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 2981 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 2982 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 2983 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 2984 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 2985 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 2986 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 2987 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 2988 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19. |
| 2989 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 2990 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 2991 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19. |
| 2992 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 2993 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 2994 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 2995 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 2996 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 2997 | -------------------------------------------- |
| 2998 | Configuration for unused statistics ALUs. |
| 2999 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 3000 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 3001 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 3002 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 3003 | +------------------------------------------------------------------------ |
| 3004 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f. |
| 3005 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f. |
| 3006 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 3007 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f. |
| 3008 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f. |
| 3009 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 3010 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff. |
| 3011 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff. |
| 3012 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff. |
Carmelo Cascone | 6230a61 | 2017-09-13 03:25:41 +0200 | [diff] [blame] | 3013 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1. |
| 3014 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1. |
| 3015 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 3016 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 3017 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 3018 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 3019 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 3020 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 3021 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 3022 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 3023 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 3024 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 3025 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 3026 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 3027 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 3028 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 3029 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 3030 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 3031 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 3032 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 3033 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 3034 | +------------------------------------------------------------------------ |
| 3035 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 3036 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 3037 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 3038 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0. |
| 3039 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 3040 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 3041 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 3042 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0. |
| 3043 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 3044 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 3045 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 3046 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 3047 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 3048 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 3049 | |
| 3050 | +------------------------------------------------------------------------ |
Carmelo Cascone | 133c7b1 | 2017-09-13 15:36:08 +0200 | [diff] [blame] | 3051 | | Number of configuration field values set in Match-Action Stages: 2168 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 3052 | +------------------------------------------------------------------------ |
| 3053 | |
| 3054 | +------------------------------------------------------------------------ |
| 3055 | | MAU Feature Characteristics: |
| 3056 | +------------------------------------------------------------------------ |
| 3057 | |
| 3058 | |
| 3059 | Features per Stage for ingress: |
| 3060 | ----------------------------------------------------------------------------------------------- |
| 3061 | | Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency | |
| 3062 | | | | | | LPF | (max words) | | to Previous | |
| 3063 | ----------------------------------------------------------------------------------------------- |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 3064 | | 0 | Yes | Yes | Yes | No | No (0) | No | match | |
| 3065 | | 1 | Yes | No | Yes | No | No (0) | No | match | |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 3066 | | 2 | Yes | No | Yes | No | No (0) | No | match | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 3067 | | 3 | Yes* | No | Yes* | No | No (0) | No | concurrent | |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 3068 | | 4 | Yes* | No | Yes* | No | No (0) | No | concurrent | |
| 3069 | | 5 | Yes* | No | Yes* | No | No (0) | No | concurrent | |
| 3070 | | 6 | No | No | No | No | No (0) | No | match | |
| 3071 | | 7 | No | No | No | No | No (0) | No | concurrent | |
| 3072 | | 8 | No | No | No | No | No (0) | No | concurrent | |
| 3073 | | 9 | No | No | No | No | No (0) | No | concurrent | |
| 3074 | | 10 | No | No | No | No | No (0) | No | concurrent | |
| 3075 | | 11 | No | No | No | No | No (0) | No | concurrent | |
| 3076 | ----------------------------------------------------------------------------------------------- |
| 3077 | |
| 3078 | A '*' denotes that this feature was added to balance an action/concurrent chain. |
| 3079 | |
| 3080 | |
| 3081 | Features per Stage for egress: |
| 3082 | ----------------------------------------------------------------------------------------------- |
| 3083 | | Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency | |
| 3084 | | | | | | LPF | (max words) | | to Previous | |
| 3085 | ----------------------------------------------------------------------------------------------- |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 3086 | | 0 | No | No | No | No | No (0) | No | match | |
| 3087 | | 1 | No | No | No | No | No (0) | No | concurrent | |
| 3088 | | 2 | No | No | No | No | No (0) | No | concurrent | |
| 3089 | | 3 | No | No | No | No | No (0) | No | concurrent | |
| 3090 | | 4 | No | No | No | No | No (0) | No | concurrent | |
| 3091 | | 5 | No | No | No | No | No (0) | No | concurrent | |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 3092 | | 6 | No | No | No | No | No (0) | No | match | |
| 3093 | | 7 | No | No | No | No | No (0) | No | concurrent | |
| 3094 | | 8 | No | No | No | No | No (0) | No | concurrent | |
| 3095 | | 9 | No | No | No | No | No (0) | No | concurrent | |
| 3096 | | 10 | No | No | No | No | No (0) | No | concurrent | |
| 3097 | | 11 | No | No | No | No | No (0) | No | concurrent | |
| 3098 | ----------------------------------------------------------------------------------------------- |
| 3099 | |
| 3100 | A '*' denotes that this feature was added to balance an action/concurrent chain. |
| 3101 | |
| 3102 | +------------------------------------------------------------------------ |
| 3103 | | MAU Latency Characteristics: |
| 3104 | +------------------------------------------------------------------------ |
| 3105 | |
| 3106 | |
| 3107 | Clock Cycles Per Stage For ingress: |
| 3108 | ----------------------------------------------------------------------------------------------------- |
| 3109 | | Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency | |
| 3110 | ----------------------------------------------------------------------------------------------------- |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 3111 | | 0 | 22 | 13 | match | 22 | |
| 3112 | | 1 | 20 | 11 | match | 20 | |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 3113 | | 2 | 20 | 11 | match | 20 | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 3114 | | 3 | 20 | 11 | concurrent | 1 | |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 3115 | | 4 | 20 | 11 | concurrent | 1 | |
| 3116 | | 5 | 20 | 11 | concurrent | 1 | |
| 3117 | | 6 | 20 | 11 | match | 20 | |
| 3118 | | 7 | 20 | 11 | concurrent | 1 | |
| 3119 | | 8 | 20 | 11 | concurrent | 1 | |
| 3120 | | 9 | 20 | 11 | concurrent | 1 | |
| 3121 | | 10 | 20 | 11 | concurrent | 1 | |
| 3122 | | 11 | 20 | 11 | concurrent | 1 | |
| 3123 | ----------------------------------------------------------------------------------------------------- |
| 3124 | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 3125 | Total latency for ingress: 94 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 3126 | |
| 3127 | |
| 3128 | Clock Cycles Per Stage For egress: |
| 3129 | ----------------------------------------------------------------------------------------------------- |
| 3130 | | Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency | |
| 3131 | ----------------------------------------------------------------------------------------------------- |
| 3132 | | 0 | 20 | 11 | match | 20 | |
| 3133 | | 1 | 20 | 11 | concurrent | 1 | |
| 3134 | | 2 | 20 | 11 | concurrent | 1 | |
| 3135 | | 3 | 20 | 11 | concurrent | 1 | |
| 3136 | | 4 | 20 | 11 | concurrent | 1 | |
| 3137 | | 5 | 20 | 11 | concurrent | 1 | |
| 3138 | | 6 | 20 | 11 | match | 20 | |
| 3139 | | 7 | 20 | 11 | concurrent | 1 | |
| 3140 | | 8 | 20 | 11 | concurrent | 1 | |
| 3141 | | 9 | 20 | 11 | concurrent | 1 | |
| 3142 | | 10 | 20 | 11 | concurrent | 1 | |
| 3143 | | 11 | 20 | 11 | concurrent | 1 | |
| 3144 | ----------------------------------------------------------------------------------------------------- |
| 3145 | |
| 3146 | Total latency for egress: 54 |