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gerrit.onosproject.org / onos / 753db82e2b9c88352bcc6c2fb9705ff7d8475a76 / . / tools / test / p4src / p4-14 / p4c-out / tofino / default / mavericks / logs / mau.config.log
blob: 0ecaef8f6f4c2d15c60a1a06b96e23fae93e2c2c [file] [log] [blame]
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1+---------------------------------------------------------------------+
2| Log file: mau.config.log |
3| Compiler version: 5.1.0 (fca32d1) |
Carmelo Cascone133c7b12017-09-13 15:36:08 +0200[diff] [blame]4| Created on: Wed Sep 13 12:56:12 2017 |
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]5+---------------------------------------------------------------------+
6
7Final Stage dependencies are:
8 (0, 'ingress') : match
9 (1, 'ingress') : match
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]10 (2, 'ingress') : concurrent
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]11 (3, 'ingress') : concurrent
12 (4, 'ingress') : concurrent
13 (5, 'ingress') : concurrent
14 (6, 'ingress') : match
15 (7, 'ingress') : concurrent
16 (8, 'ingress') : concurrent
17 (9, 'ingress') : concurrent
18 (10, 'ingress') : concurrent
19 (11, 'ingress') : concurrent
20 (0, 'egress') : match
21 (1, 'egress') : concurrent
22 (2, 'egress') : concurrent
23 (3, 'egress') : concurrent
24 (4, 'egress') : concurrent
25 (5, 'egress') : concurrent
26 (6, 'egress') : match
27 (7, 'egress') : concurrent
28 (8, 'egress') : concurrent
29 (9, 'egress') : concurrent
30 (10, 'egress') : concurrent
31 (11, 'egress') : concurrent
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]32Action/Concurrent chaining in ingress consists of [2, 3, 4, 5]
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]33Action/Concurrent chaining in ingress consists of [7, 8, 9, 10, 11]
34Action/Concurrent chaining in egress consists of [1, 2, 3, 4, 5]
35Action/Concurrent chaining in egress consists of [7, 8, 9, 10, 11]
36
37+------------------------------------------------------------------------
38| MAU Stage 0
39+------------------------------------------------------------------------
40
41+------------------------------------------------------------------------
42| Working on table _condition_0 in stage 0 ---
43+------------------------------------------------------------------------
44--> Stage Gateway Table for condition _condition_0 in stage 0
45Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
46Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
47Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
48Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
49Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
50Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
51Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
52Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]53Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 2.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]54Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]55Configuring match input crossbar byte 0 to come from 8-bit PHV container 2.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]56 That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]57Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]58Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
59Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
60Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte0 to be 0x2.
61Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
62Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
63Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
64Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
65Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
66Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
67Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
68Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
69Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
70Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0
71Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0
72Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
73Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
74Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
75Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
76Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
77Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff
78Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xfffffe
79Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x10
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]80Configuring rams.match.merge.gateway_next_table_lut[0][4] to be 0x1
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]81Configuring rams.match.merge.gateway_en.gateway_en to be 0x1
82Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf
83Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1
84Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_logical_select to be 0x0
85Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_inhibit_enable to be 0x1
86Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff
87Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff
88
89+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]90| Working on table process_packet_out_table__action__ in stage 0 ---
91+------------------------------------------------------------------------
92--> Action Data Table process_packet_out_table__action__ with logical_table_id 1 that is reference type is 'direct'
93
94+------------------------------------------------------------------------
95| Working on table process_packet_out_table in stage 0 ---
96+------------------------------------------------------------------------
97--> Match Table with no key process_packet_out_table with logical_table_id 1
98allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
99Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
100Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
101Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
102Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
103Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
104Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
105Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 1 (logical table id).
106Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
107Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 1 (logical table id).
108Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
109Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x40.
110Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x0.
111Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0x10.
112Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0x10.
113Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x2 (previous_value=0x0 OR new_value=0x2).
114Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x44.
115Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
116Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_instr to be 0x74412.
117Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_color to be 0.
118Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_parity to be 1.
119Micro instruction added in VLIW 2 for 16-bit position 2 for table process_packet_out_table.
120 Assembled as 0x74412 (or decimal 476178)
121 Micro Instruction deposit-field for PHV Container 130 has bit width 23
122 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
123 Field Src1 [4:0] : 0x1 (5 bits in instruction bits [8:4])
124 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
125 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
126 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
127 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
128 Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16])
129 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
130
131Configuring dp.imem.imem_subword8[unit_number=2][vliw_instruction_number=2].imem_subword8_instr to be 0x74d82.
132Configuring dp.imem.imem_subword8[unit_number=2][vliw_instruction_number=2].imem_subword8_color to be 0.
133Configuring dp.imem.imem_subword8[unit_number=2][vliw_instruction_number=2].imem_subword8_parity to be 1.
134Micro instruction added in VLIW 2 for 8-bit position 2 for table process_packet_out_table.
135 Assembled as 0x74d82 (or decimal 478594)
136 Micro Instruction deposit-field for PHV Container 66 has bit width 20
137 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
138 Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4])
139 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
140 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
141 Field high_bit [2:0] : 0x1 (3 bits in instruction bits [13:11])
142 Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14])
143 Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16])
144 Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
145
146Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
147Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6)
148--> Stage Gateway Table for condition process_packet_out_table_always_true_condition in stage 0
149Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
150Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
151Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
152Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
153Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
154Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
155Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x0)
156Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
157Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x0)
158Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
159Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
160Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
161Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
162Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
163Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
164Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1
165Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0
166Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
167Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
168Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
169Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff
170Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff
171Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff
172Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff
173Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8
174Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0x10
175Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10)
176Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0x10
177Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2)
178Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe
179Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1
180allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
181Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x1
182Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1
183Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2
184Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x0
185Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0
186Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x0
187Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0
188Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff
189Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff
190Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
191
192+------------------------------------------------------------------------
193| Working on table table0__action__ in stage 0 ---
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]194+------------------------------------------------------------------------
195--> Action Data Table table0__action__ with logical_table_id 0 that is reference type is 'direct'
196Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_select to be 4.
197Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_enable to be 1.
198
199+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]200| Working on table table0 in stage 0 ---
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]201+------------------------------------------------------------------------
202--> Ternary Match Table table0 with logical_table_id 0
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]203Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1).
204Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1).
205Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1).
206Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1).
207Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1).
208Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1).
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]209Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id).
210Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
211Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id).
212Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
213Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x3.
214Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_default to be 0x0.
215Configuring rams.match.merge.mau_action_instruction_adr_per_entry_en_mux_ctl[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_per_entry_en_mux_ctl to be 0x2.
216Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=1].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
217Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x870a080.
218Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
219Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]220Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x10.
221Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x10.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]222Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x0.
223Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=1][result_bus_number=0].mau_immediate_data_mask to be 0xffff.
224Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=1][result_bus_number=0].mau_stats_adr_mask to be 0xffffe.
225Configuring rams.match.merge.mau_stats_adr_default[table_type_index=1][result_bus_number=0].mau_stats_adr_default to be 0x80000.
226Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x0)
227Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x3. (old value = 0x0 OR new value = 0x3)
228Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_address to be 16.
229Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_enable to be 1.
230Configuring match input crossbar byte 133 to come from 16-bit PHV container 0.
231 That PHV byte contains version/valid
232{unused[6:0], ig_intr_md.ingress_port[8:8]}.
233Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_address to be 2.
234Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_lo_enable to be 1.
235Configuring match input crossbar byte 128 to come from 32-bit PHV container 2.
236 That PHV byte contains {ethernet.srcAddr[7:0]}.
237Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_address to be 2.
238Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_lo_enable to be 1.
239Configuring match input crossbar byte 129 to come from 32-bit PHV container 2.
240 That PHV byte contains {ethernet.srcAddr[15:8]}.
241Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_address to be 2.
242Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_lo_enable to be 1.
243Configuring match input crossbar byte 130 to come from 32-bit PHV container 2.
244 That PHV byte contains {ethernet.srcAddr[23:16]}.
245Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_address to be 2.
246Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_lo_enable to be 1.
247Configuring match input crossbar byte 131 to come from 32-bit PHV container 2.
248 That PHV byte contains {ethernet.srcAddr[31:24]}.
249Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_address to be 1.
250Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_lo_enable to be 1.
251Configuring match input crossbar byte 132 to come from 32-bit PHV container 1.
252 That PHV byte contains {ethernet.dstAddr[15:8]}.
253Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_address to be 1.
254Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_lo_enable to be 1.
255Configuring match input crossbar byte 134 to come from 32-bit PHV container 1.
256 That PHV byte contains {ethernet.dstAddr[31:24]}.
257Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_address to be 1.
258Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_lo_enable to be 1.
259Configuring match input crossbar byte 135 to come from 32-bit PHV container 1.
260 That PHV byte contains {ethernet.dstAddr[39:32]}.
261Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_address to be 20.
262Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_enable to be 1.
263Configuring match input crossbar byte 136 to come from 16-bit PHV container 4.
264 That PHV byte contains {ethernet.etherType[7:0]}.
265Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_address to be 1.
266Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_lo_enable to be 1.
267Configuring match input crossbar byte 137 to come from 32-bit PHV container 1.
268 That PHV byte contains {ethernet.dstAddr[23:16]}.
269Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_address to be 19.
270Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_enable to be 1.
271Configuring match input crossbar byte 138 to come from 16-bit PHV container 3.
272 That PHV byte contains {ethernet.srcAddr[47:40]}.
273Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_address to be 20.
274Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_enable to be 1.
275Configuring match input crossbar byte 139 to come from 16-bit PHV container 4.
276 That PHV byte contains {ethernet.etherType[15:8]}.
277Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_address to be 16.
278Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_enable to be 1.
279Configuring match input crossbar byte 140 to come from 16-bit PHV container 0.
280 That PHV byte contains {ig_intr_md.ingress_port[7:0]}.
281Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_address to be 19.
282Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_enable to be 1.
283Configuring match input crossbar byte 141 to come from 16-bit PHV container 3.
284 That PHV byte contains {ethernet.dstAddr[7:0]}.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]285Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]286Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_enable to be 1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]287Configuring match input crossbar byte 142 to come from 8-bit PHV container 1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]288 That PHV byte contains {ethernet.srcAddr[39:32]}.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]289Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 0.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]290Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_enable to be 1.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]291Configuring match input crossbar byte 143 to come from 8-bit PHV container 0.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]292 That PHV byte contains {ethernet.dstAddr[47:40]}.
293Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]294Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x7. (previous value = 0x4 OR new value = 0x3)
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]295Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x19. (previous value = 0x0 OR new value = 0x19)
296
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]297--> Idletime Table for match table table0 in stage 0
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]298Looking at Map RAM: Row 7 Unit 0
299Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 0.
300Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 1.
301Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].two_way_idletime_notification to be 1.
302Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].per_flow_idletime to be 1.
303Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].idletime_bitwidth to be 2 (precision = 3 bits).
304Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_type to be 4.
305Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
306FIXME: Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn_members to be 0.
307Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn to be 0.
308Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
309Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
310Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
311Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
312Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 2.
313Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
314Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
315Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
316Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_stats_meter_adr_mux_select_idlet to be 1.
317Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0.
318Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1.
319Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0.
320Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1.
321Configuring rams.map_alu.row[row=7].adrmux.idletime_cfg_rd_clear_val[map_ram_index=0].idletime_cfg_rd_clear_val to be 0x36.
322 logical table ID is 0
323Configuring rams.match.adrdist.adr_dist_idletime_adr_oxbar_ctl.[entry_index=2].adr_dist_idletime_adr_oxbar_ctl be 0x4000 (previous value = 0x0 OR new value = 0x4000)
324Note that rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_en must be programmed by run time.
325Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_offset be 0x0.
326Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_size be 0x0.
327Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_pos be 0x0.
328Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_en be 0x0.
329Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_interval be 0x7.
330Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_offset be 0x0.
331Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_size be 0x0.
332Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_pos be 0x0.
333Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_en be 0.
334Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_size be 2.
335Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_direct be 1.
336Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=2].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1)
337Configuring rams.match.merge.mau_idletime_adr_mask[table_type_index=1][result_bus_number=0].mau_idletime_adr_mask to be 0x1ffff8.
338Configuring rams.match.merge.mau_idletime_adr_default[table_type_index=1][result_bus_number=0].idletime_adr_default to be 0x100003.
339Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x4602.
340Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1.
341Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 1.
342Micro instruction added in VLIW 0 for 16-bit position 2 for table table0.
343 Assembled as 0x4602 (or decimal 17922)
344 Micro Instruction deposit-field for PHV Container 130 has bit width 23
345 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
346 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
347 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
348 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
349 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
350 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
351 Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
352 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
353
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]354Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x6 OR new value = 0x4)
355Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_instr to be 0x4602.
356Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_color to be 0.
357Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_parity to be 0.
358Micro instruction added in VLIW 1 for 16-bit position 2 for table table0.
359 Assembled as 0x4602 (or decimal 17922)
360 Micro Instruction deposit-field for PHV Container 130 has bit width 23
361 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
362 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
363 Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
364 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
365 Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
366 Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
367 Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
368 Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
369
370Configuring dp.imem.imem_subword8[unit_number=2][vliw_instruction_number=1].imem_subword8_instr to be 0x592.
371Configuring dp.imem.imem_subword8[unit_number=2][vliw_instruction_number=1].imem_subword8_color to be 0.
372Configuring dp.imem.imem_subword8[unit_number=2][vliw_instruction_number=1].imem_subword8_parity to be 1.
373Micro instruction added in VLIW 1 for 8-bit position 2 for table table0.
374 Assembled as 0x592 (or decimal 1426)
375 Micro Instruction deposit-field for PHV Container 66 has bit width 20
376 Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]377 Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
378 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
379 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
380 Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11])
381 Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14])
382 Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16])
383 Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
384
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]385Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_instr to be 0x39fc01.
386Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_color to be 0.
387Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_parity to be 1.
388Micro instruction added in VLIW 1 for 16-bit position 1 for table table0.
389 Assembled as 0x39fc01 (or decimal 3800065)
390 Micro Instruction deposit-field for PHV Container 129 has bit width 23
391 Field Src2 [3:0] : 0x1 (4 bits in instruction bits [3:0])
392 Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
393 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
394 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
395 Field high_bit [3:0] : 0xf (4 bits in instruction bits [14:11])
396 Field low_bit_lo [0:0] : 0x1 (1 bits in instruction bits [15:15])
397 Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16])
398 Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20])
399
400Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x4. (previous value = 0x4 OR new value = 0x4)
401Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x7. (previous value = 0x6 OR new value = 0x7)
402Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_instr to be 0xb7d93.
403Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_color to be 1.
404Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_parity to be 0.
405Micro instruction added in VLIW 1 for 8-bit position 3 for table table0.
406 Assembled as 0xb7d93 (or decimal 753043)
407 Micro Instruction deposit-field for PHV Container 67 has bit width 20
408 Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]409 Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
410 Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
411 Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
412 Field high_bit [2:0] : 0x7 (3 bits in instruction bits [13:11])
413 Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14])
414 Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16])
415 Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19])
416
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]417Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0xc. (previous value = 0x4 OR new value = 0x8)
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]418Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].idletime_adr_payload_shifter_en to be 1.
419Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].stats_adr_payload_shifter_en to be 1.
420Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].action_instruction_adr_payload_shifter_en to be 1.
421Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].immediate_data_payload_shifter_en to be 1.
422Configuring rams.match.merge.mau_table_counter_ctl[half_index=0].mau_table_counter_ctl to be 0x2. (previous value = 0x0 OR new value = 0x2)
423dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit']
424Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data_dirtcam_mode to be 0x155.
425Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vbit_dirtcam_mode to be 0x1.
426Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data1_select to be 1.
427Configuring tcams.col[col=1].tcam_mode[row=9].tcam_chain_out_enable to be 0.
428Configuring tcams.col[col=1].tcam_mode[row=9].tcam_ingress to be 1.
429Configuring tcams.col[col=1].tcam_mode[row=9].tcam_match_output_enable to be 1.
430Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vpn to be 0.
431Configuring tcams.col[col=1].tcam_mode[row=9].tcam_logical_table to be 0.
432TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit.
433Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=0] to be 15.
434Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=1] to be 15.
435Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=2] to be 15.
436Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=3] to be 15.
437Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=4] to be 15.
438Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=5] to be 15.
439Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=6] to be 15.
440Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=7] to be 15.
441Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_select to be 0 (don't care).
442Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_enable to be 1.
443Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_select to be 2.
444Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_enable to be 1.
445dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit']
446Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data_dirtcam_mode to be 0x155.
447Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vbit_dirtcam_mode to be 0x0.
448Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data1_select to be 1.
449Configuring tcams.col[col=1].tcam_mode[row=10].tcam_chain_out_enable to be 1.
450Configuring tcams.col[col=1].tcam_mode[row=10].tcam_ingress to be 1.
451Configuring tcams.col[col=1].tcam_mode[row=10].tcam_match_output_enable to be 0.
452Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vpn to be 0.
453Configuring tcams.col[col=1].tcam_mode[row=10].tcam_logical_table to be 0.
454TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit.
455Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15.
456Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15.
457Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15.
458Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15.
459Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15.
460Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15.
461Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15.
462Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15.
463Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_select to be 3 (version on [3:2] and valid bits for [1:0]).
464Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_enable to be 1.
465Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0.
466Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1.
467Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_select to be 1.
468Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_enable to be 1.
469dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit']
470Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data_dirtcam_mode to be 0x155.
471Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vbit_dirtcam_mode to be 0x1.
472Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data1_select to be 1.
473Configuring tcams.col[col=1].tcam_mode[row=11].tcam_chain_out_enable to be 1.
474Configuring tcams.col[col=1].tcam_mode[row=11].tcam_ingress to be 1.
475Configuring tcams.col[col=1].tcam_mode[row=11].tcam_match_output_enable to be 0.
476Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vpn to be 0.
477Configuring tcams.col[col=1].tcam_mode[row=11].tcam_logical_table to be 0.
478TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit.
479Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15.
480Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15.
481Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15.
482Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15.
483Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15.
484Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15.
485Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15.
486Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15.
487Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_select to be 0 (extra byte low nibble [3:0]).
488Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_enable to be 1.
489Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0.
490Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1.
491Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_select to be 0.
492Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_enable to be 1.
493Configuring tcams.col[col=0].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x0.
494Configuring tcams.col[col=1].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x200.
495--> Ternary Indirection table for Match Table table0 with logical_table_id 0
496Configuring tcams.tcam_match_adr_shift[tcam_table_id=0] to be left shift of 3.
497Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_write_data_mux_select to be select of 7.
498Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_read_data_mux_select to be select of 7.
499Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.tind_result_bus_select to be select of 1.
500Configuring rams.map_alu.row[row=0].adrmux.ram_address_mux_ctl[column_half=0][column_index=2].ram_unitram_adr_mux_select to be 2.
501Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_type to be 6.
502Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_vpn to be 0.
503Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_logical_table to be 0.
504Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_ingress to be 1.
505Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_enable to be 1.
506Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id).
507Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_enable to be 1.
508Configuring rams.array.row[row=0].tind_ecc_error_uram_ctl[direction=0].tind_ecc_error_uram_ctl to be select of 0x1. (previous value = 0x0 OR new value = 0x1)
509Configuring rams.match.merge.tind_ram_data_size[tind_bus_number=0].tind_ram_data_size to be code 4.
510Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id).
511Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_enable to be 1.
512TODO: rams.match.merge.tind_bus_prop[tind_bus_number=0] is currently always set to 1.
513Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].tcam_piped to be 1.
514Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].enabled to be 1.
515Configuring rams.match.merge.mau_action_instruction_adr_tcam_shiftcount[physical_result_bus=0].mau_action_instruction_adr_tcam_shiftcount to be 0.
516Configuring rams.match.merge.mau_immediate_data_tcam_shiftcount[tind_bus_number=0].mau_immediate_data_tcam_shiftcount to be 3.
517Configuring rams.match.merge.mau_idletime_adr_tcam_shiftcount[result_bus_number=0].mau_idletime_adr_tcam_shiftcount to be 0x44.
518Configuring rams.match.merge.mau_stats_adr_tcam_shiftcount[result_bus_index=0].mau_stats_adr_tcam_shiftcount to be 0x49.
519Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_select to be 0 (logical table id).
520Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_enable to be 1.
521TODO: rams.match.merge.tcam_table_prop[tcam_table_id=0] is currently always set to 1.
522Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].tcam_piped to be 1.
523Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].enabled to be 1.
524Configuring tcams.tcam_output_table_thread[tcam_table_id=0].tcam_output_table_thread to be 1.
525TODO: tcams.tcam_piped is currently always set to True for ingress and egress.
526Configuring tcams.tcam_piped to be 3.
527Configuring cfg_regs.mau_cfg_movereg_tcam_only.mau_cfg_movereg_tcam_only to be 0x1. (previous value = 0x0 OR new value = 0x1)
528
529+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]530| Working on table table0_counter in stage 0 ---
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]531+------------------------------------------------------------------------
532Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
533Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
534Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
535Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
536Note that unitram_vpn does not need to be programmed for synthetic two port rams.
537Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0.
538Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
539Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
540Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
541Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
542Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
543Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
544Note that unitram_vpn does not need to be programmed for synthetic two port rams.
545Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0.
546Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
547Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
548Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
549Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
550Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
551Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
552Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
553Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
554Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
555Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
556Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
557Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
558Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
559Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
560Stat table table0_counter is used by match table table0.
561Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8)
562Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
563Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
564Note that map ram vpn does not need to be configured for synthetic two port map rams.
565Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
566Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
567Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
568Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
569Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
570Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
571Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
572Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
573Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0.
574Note that map ram vpn does not need to be configured for synthetic two port map rams.
575Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
576Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
577Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
578Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
579Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
580Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
581Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
582For counter width 32 and N = 4096
583 number iterations = 32
584 b_cur = 379488672.0
585 eqn(b_cur) = 4294964039.26
586 max_counter_value = 4294967295
587Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a.
588Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff.
589Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a.
590Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff.
591Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a.
592Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff.
593Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4.
594Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1.
595Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1.
596TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0.
597Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x0.
598Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4.
599Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1.
600Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0.
601Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0.
602Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0.
603Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0.
604Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0.
605Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
606Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
607Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1.
608Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3.
609Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_direct be 1.
610Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=0].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1)
611Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_tcam be 1.
612Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x0.
613Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x7. ( previous value = 0x0 OR new value = 0x7)
614Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x1.
615+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]616Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 12.
617Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
618Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]619Configuring rams.match.merge.exact_match_delay_thread[copy_index=0].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
620Configuring rams.match.merge.exact_match_delay_thread[copy_index=1].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
621Configuring rams.match.merge.exact_match_delay_thread[copy_index=2].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]622Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 10.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]623Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]624Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]625Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
626Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
627Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
628Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]629Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x3.
630Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x2.
631Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x2.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]632Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]633Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x2.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]634Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
635Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
636Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
637Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 16.
638Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 21.
639Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
640Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
641Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
642Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
643Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
644Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
645Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
646Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
647--------------------------------------------
648Configuration for unused statistics ALUs.
649Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
650Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
651Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
652+------------------------------------------------------------------------
653Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7.
654Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7.
655Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]656Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf.
657Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf.
658Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]659Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f.
660Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f.
661Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]662Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
663Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
664Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
665Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
666Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
667Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]668Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
669Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
670Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
671Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
672Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 1.
673Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 1.
674Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
675Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
676Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
677Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
678Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
679Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
680+------------------------------------------------------------------------
681Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 19.
682Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 2.
683Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
684Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
685Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
686Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]687Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]688Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]689Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
690Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]691Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
692Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
693Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
694Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
695
696+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]697| MAU Stage 1
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]698+------------------------------------------------------------------------
699
700+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]701| Working on table _condition_2 in stage 1 ---
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]702+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]703--> Stage Gateway Table for condition _condition_2 in stage 1
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]704Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
705Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
706Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
707Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
708Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
709Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
710Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
711Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]712Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 18.
713Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_enable to be 1.
714Configuring match input crossbar byte 2 to come from 16-bit PHV container 2.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]715 That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]716Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 18.
717Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_enable to be 1.
718Configuring match input crossbar byte 3 to come from 16-bit PHV container 2.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]719 That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
720Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
721Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
722Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]723Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=40].byte1 to be 0x1.
724Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=41].byte0 to be 0x1.
725Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=42].byte0 to be 0x2.
726Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=43].byte0 to be 0x4.
727Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=44].byte0 to be 0x8.
728Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=45].byte0 to be 0x10.
729Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=46].byte0 to be 0x20.
730Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=47].byte0 to be 0x40.
731Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=48].byte0 to be 0x80.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]732Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
733Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
734Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
735Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
736Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
737Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
738Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
739Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
740Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
741Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0
742Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0
743Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
744Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
745Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
746Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
747Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
748Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_mode to be 0x2
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]749Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffff00
750Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff00
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]751Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]752Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x11
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]753Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid0 to be 0x3
754Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid1 to be 0x3
755Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][0] to be 0xffffffff
756Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][1] to be 0xffffffff
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]757Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xff00ff
758Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff00ff
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]759Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xc (previous value 0x8 OR new value 0x4)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]760Configuring rams.match.merge.gateway_next_table_lut[0][2] to be 0x11
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]761Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid0 to be 0x3
762Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid1 to be 0x3
763Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][0] to be 0xffffffff
764Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][1] to be 0xffffffff
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]765Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0x3ffff
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]766Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][1] to be 0xffff
767Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xe (previous value 0xc OR new value 0x2)
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]768Configuring rams.match.merge.gateway_next_table_lut[0][1] to be 0x11
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]769Configuring rams.match.merge.gateway_en.gateway_en to be 0x1
770Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf
771Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1
772allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
773Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x0
774Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1
775Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2
776Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x1
777Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0
778Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x1
779Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0
780Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff
781Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff
782
783+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]784| Working on table ingress_port_count_table__action__ in stage 1 ---
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]785+------------------------------------------------------------------------
786--> Action Data Table ingress_port_count_table__action__ with logical_table_id 0 that is reference type is 'direct'
787
788+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]789| Working on table ingress_port_count_table in stage 1 ---
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]790+------------------------------------------------------------------------
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]791--> Hash Action Table ingress_port_count_table with logical_table_id 0
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]792allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
793Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
794Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
795Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
796Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
797Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
798Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
799Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id).
800Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
801Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id).
802Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
803Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x0.
804Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x1.
805Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0xff.
806Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=1].mau_stats_adr_default to be 0x0.
807Configuring rams.match.merge.mau_stats_adr_per_entry_en_mux_ctl[table_type_index=0][result_bus_number=1].mau_stats_adr_per_entry_en_mux_ctl to be 0x7.
808Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
809Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2000.
810Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]811
812---- Hash Distribution Units for table ingress_port_count_table ----
813Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x1)
814Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
815Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 16.
816Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
817Configuring match input crossbar byte 0 to come from 16-bit PHV container 0.
818 That PHV byte contains {ig_intr_md.ingress_port[7:0]}.
819Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 16.
820Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
821Configuring match input crossbar byte 1 to come from 16-bit PHV container 0.
822 That PHV byte contains {unused[6:0], ig_intr_md.ingress_port[8:8]}.
823Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x5. (previous value = 0x4 OR new value = 0x1)
824Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x1)
825Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
826Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x1.
827Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte0 to be 0x2.
828Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte0 to be 0x4.
829Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte0 to be 0x8.
830Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte0 to be 0x10.
831Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte0 to be 0x20.
832Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte0 to be 0x40.
833Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte0 to be 0x80.
834Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=8].byte1 to be 0x1.
835Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
836Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 1. (old value = 0 OR new value = 1).
837Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 8. (old value = 0 OR new value = 8).
838Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 1. (old value = 0 OR new value = 1).
Carmelo Cascone133c7b12017-09-13 15:36:08 +0200[diff] [blame]839Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x2. (old value = 0x0 OR new value = 0x2).
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]840Configuring rams.match.merge.mau_hash_group_mask[which_16=0].mau_hash_group_mask to be 0x3ff. (previous value = 0x0 OR new value = 0x3ff)
841Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=3][control_group_index=0].mau_hash_group_xbar_ctl to be 0x8 (old value = 0x0 OR new value = 0x8).
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]842Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].stats_adr_payload_shifter_en to be 1.
843Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
844
845+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]846| Working on table egress_port_count_table__action__ in stage 1 ---
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]847+------------------------------------------------------------------------
848--> Action Data Table egress_port_count_table__action__ with logical_table_id 1 that is reference type is 'direct'
849
850+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]851| Working on table egress_port_count_table in stage 1 ---
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]852+------------------------------------------------------------------------
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]853--> Hash Action Table egress_port_count_table with logical_table_id 1
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]854allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
855Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
856Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
857Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
858Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
859Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
860Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
861Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id).
862Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
863Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id).
864Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
865Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_default to be 0x40.
866Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x0.
867Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0xff.
868Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0xff.
869Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=0].mau_stats_adr_default to be 0x80000.
870Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2).
871Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x40.
872Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]873
874---- Hash Distribution Units for table egress_port_count_table ----
875Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x1 OR new value = 0x2)
876Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
877Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_address to be 18.
878Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_enable to be 1.
879Configuring match input crossbar byte 8 to come from 16-bit PHV container 2.
880 That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
881Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_address to be 18.
882Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_enable to be 1.
883Configuring match input crossbar byte 9 to come from 16-bit PHV container 2.
884 That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
885Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x5. (previous value = 0x5 OR new value = 0x4)
886Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=1][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2)
887Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=1][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
888Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0x1.
889Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=1].byte0 to be 0x2.
890Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=2].byte0 to be 0x4.
891Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=3].byte0 to be 0x8.
892Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=4].byte0 to be 0x10.
893Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=5].byte0 to be 0x20.
894Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=6].byte0 to be 0x40.
895Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=7].byte0 to be 0x80.
896Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=8].byte1 to be 0x1.
897Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x3. (previous value = 0x1 OR new value = 0x2)
898Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 9. (old value = 1 OR new value = 8).
899Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 152. (old value = 8 OR new value = 144).
900Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 65. (old value = 1 OR new value = 64).
Carmelo Cascone133c7b12017-09-13 15:36:08 +0200[diff] [blame]901Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x402. (old value = 0x2 OR new value = 0x400).
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]902Configuring rams.match.merge.mau_hash_group_mask[which_16=3].mau_hash_group_mask to be 0x3ff. (previous value = 0x0 OR new value = 0x3ff)
903Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=3][control_group_index=0].mau_hash_group_xbar_ctl to be 0xb8 (old value = 0x8 OR new value = 0xb0).
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]904--> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 1
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]905Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
906Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
907Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
908Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
909Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
910Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]911Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x3 OR new value = 0x0)
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]912Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
913Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x0)
914Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
Carmelo Cascone6230a612017-09-13 03:25:41 +0200[diff] [blame]915Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x3. (previous value = 0x3 OR new value = 0x1)
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]916Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
917Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
918Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
919Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
920Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1
921Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0
922Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
923Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
924Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
925Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff
926Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff
927Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff
928Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff
929Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8
930Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0xff
931Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10)
932Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0xff
933Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2)
934Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe
935Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1
936allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
937Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_logical_select to be 0x1
938Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_inhibit_enable to be 0x1
939Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x3 (previous value 0x2 OR new value 0x1)
940Configuring rams.match.merge.gateway_payload_data[0][0][0][0].gateway_payload_data to be 0x0
941Configuring rams.match.merge.gateway_payload_data[0][0][1][0].gateway_payload_data to be 0x0
942Configuring rams.match.merge.gateway_payload_data[0][0][0][1].gateway_payload_data to be 0x0
943Configuring rams.match.merge.gateway_payload_data[0][0][1][1].gateway_payload_data to be 0x0
944Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff
945Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff
946Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=0].action_instruction_adr_payload_shifter_en to be 1.
947
948+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]949| Working on table ingress_port_counter in stage 1 ---
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]950+------------------------------------------------------------------------
951Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
952Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
953Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
954Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
955Note that unitram_vpn does not need to be programmed for synthetic two port rams.
956Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0.
957Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
958Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
959Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
960Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
961Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
962Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
963Note that unitram_vpn does not need to be programmed for synthetic two port rams.
964Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0.
965Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
966Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
967Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
968Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
969Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
970Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
971Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
972Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1.
973Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
974Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
975Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
976Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
977Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
978Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1.
979Stat table ingress_port_counter is used by match table ingress_port_count_table.
980Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x4. (previous value = 0x0 OR new value =0x4)
981Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
982Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0.
983Note that map ram vpn does not need to be configured for synthetic two port map rams.
984Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
985Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
986Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
987Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
988Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
989Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
990Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
991Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
992Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0.
993Note that map ram vpn does not need to be configured for synthetic two port map rams.
994Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
995Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
996Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
997Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
998Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
999Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
1000Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
Carmelo Cascone133c7b12017-09-13 15:36:08 +0200[diff] [blame]1001Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_entries_per_word to be 2.
Carmelo Cascone0ce8f5d2017-09-13 03:50:36 +0200[diff] [blame]1002Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_process_bytes to be 1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1003TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_alu_error_enable to be 0.
1004Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0x0.
Carmelo Cascone133c7b12017-09-13 15:36:08 +0200[diff] [blame]1005Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x2.
Carmelo Cascone0ce8f5d2017-09-13 03:50:36 +0200[diff] [blame]1006Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_bytes be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1007Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0.
1008Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1009Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
1010Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
Carmelo Cascone0ce8f5d2017-09-13 03:50:36 +0200[diff] [blame]1011Configuring rams.match.adrdist.deferred_ram_ctl[deferred_ram_type=0][deferred_ram_index=2].deferred_ram_en to be 1.
Carmelo Cascone133c7b12017-09-13 15:36:08 +0200[diff] [blame]1012Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_size be 1.
Carmelo Cascone0ce8f5d2017-09-13 03:50:36 +0200[diff] [blame]1013Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_deferred be 1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1014Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_lt be 0x0.
1015Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x6. ( previous value = 0x0 OR new value = 0x6)
1016Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=2].mau_ad_stats_virt_lt be 0x1.
1017
1018+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1019| Working on table egress_port_counter in stage 1 ---
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1020+------------------------------------------------------------------------
1021Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
1022Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
1023Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
1024Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3.
1025Note that unitram_vpn does not need to be programmed for synthetic two port rams.
1026Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 1.
1027Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1.
1028Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1.
1029Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
1030Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
1031Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0.
1032Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3.
1033Note that unitram_vpn does not need to be programmed for synthetic two port rams.
1034Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 1.
1035Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1.
1036Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1.
1037Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5.
1038Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1.
1039Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1.
1040Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1.
1041Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1)
1042Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
1043Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5.
1044Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1.
1045Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1.
1046Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1.
1047Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2)
1048Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1.
1049Stat table egress_port_counter is used by match table egress_port_count_table.
1050Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=1].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8)
1051Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1.
1052Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 1.
1053Note that map ram vpn does not need to be configured for synthetic two port map rams.
1054Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1.
1055Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1.
1056Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1.
1057Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1.
1058Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1.
1059Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1.
1060Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1.
1061Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1.
1062Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 1.
1063Note that map ram vpn does not need to be configured for synthetic two port map rams.
1064Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1.
1065Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1.
1066Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1.
1067Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1.
1068Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1.
1069Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1.
1070Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1.
Carmelo Cascone133c7b12017-09-13 15:36:08 +0200[diff] [blame]1071Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 2.
Carmelo Cascone0ce8f5d2017-09-13 03:50:36 +0200[diff] [blame]1072Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_bytes to be 1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1073TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0.
1074Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x1.
Carmelo Cascone133c7b12017-09-13 15:36:08 +0200[diff] [blame]1075Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_entries_per_word be 0x2.
Carmelo Cascone0ce8f5d2017-09-13 03:50:36 +0200[diff] [blame]1076Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_has_bytes be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1077Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_offset be 0x0.
1078Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_size be 0x0.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1079Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0.
1080Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0.
Carmelo Cascone0ce8f5d2017-09-13 03:50:36 +0200[diff] [blame]1081Configuring rams.match.adrdist.deferred_ram_ctl[deferred_ram_type=0][deferred_ram_index=3].deferred_ram_en to be 1.
Carmelo Cascone133c7b12017-09-13 15:36:08 +0200[diff] [blame]1082Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 1.
Carmelo Cascone0ce8f5d2017-09-13 03:50:36 +0200[diff] [blame]1083Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_deferred be 1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1084Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x1.
1085Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=3].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x3e. ( previous value = 0x6 OR new value = 0x38)
1086Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x2.
1087+------------------------------------------------------------------------
1088Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19.
1089Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
1090Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
1091Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1092Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1093Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1094Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1095Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1096Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1097Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1098Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1099Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x3.
1100Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1101Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1102Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x3.
1103Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
1104Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1105Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1106Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1107Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
1108Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1109Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1110Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
1111Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1112Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1113Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1114Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1115Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1116--------------------------------------------
1117Configuration for unused statistics ALUs.
1118Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1119Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1120+------------------------------------------------------------------------
1121Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7.
1122Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7.
1123Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1124Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf.
1125Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf.
1126Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1127Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f.
1128Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f.
1129Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1130Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1131Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1132Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1133Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1134Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1135Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1136Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1137Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1138Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1139Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1140Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1141Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1142Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1143Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1144Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1145Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1146Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1147Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1148+------------------------------------------------------------------------
1149Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1150Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1151Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
1152Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
1153Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1154Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1155Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1156Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
1157Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1.
1158Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2.
1159Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1160Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1161Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1162Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1163
1164+------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1165| MAU Stage 2
1166+------------------------------------------------------------------------
1167+------------------------------------------------------------------------
1168Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
1169Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
1170Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
1171Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1172Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1173Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1174Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1175Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1176Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1177Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1178Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1179Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
1180Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1181Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1182Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1183Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
1184Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1185Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1186Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1187Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
1188Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1189Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1190Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
1191Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1192Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1193Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1194Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1195Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1196--------------------------------------------
1197Configuration for unused statistics ALUs.
1198Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1199Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1200Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1201Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
1202+------------------------------------------------------------------------
1203Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7.
1204Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7.
1205Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7.
1206Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf.
1207Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf.
1208Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf.
1209Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f.
1210Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f.
1211Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f.
1212Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1213Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1214Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1215Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1216Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1217Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
1218Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1219Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1220Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1221Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1222Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1223Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1224Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1225Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1226Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1227Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1228Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1229Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1230+------------------------------------------------------------------------
1231Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1232Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1233Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
1234Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
1235Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1236Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1237Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1238Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
1239Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
1240Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
1241Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1242Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1243Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1244Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1245
1246+------------------------------------------------------------------------
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1247| MAU Stage 3
1248+------------------------------------------------------------------------
1249+------------------------------------------------------------------------
1250Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
1251Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
1252Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
1253Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1254Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1255Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1256Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1257Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1258Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1259Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1260Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1261Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
1262Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1263Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1264Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1265Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
1266Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1267Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1268Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1269Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
1270Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1271Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1272Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
1273Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1274Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1275Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1276Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1277Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1278--------------------------------------------
1279Configuration for unused statistics ALUs.
1280Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1281Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1282Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1283Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
1284+------------------------------------------------------------------------
1285Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7.
1286Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7.
1287Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1288Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf.
1289Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf.
1290Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1291Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f.
1292Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f.
1293Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1294Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1295Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1296Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1297Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1298Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1299Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1300Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1301Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1302Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1303Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1304Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1305Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1306Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1307Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1308Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1309Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1310Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1311Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1312+------------------------------------------------------------------------
1313Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1314Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1315Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
1316Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
1317Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1318Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1319Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1320Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
1321Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
1322Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
1323Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1324Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1325Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1326Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1327
1328+------------------------------------------------------------------------
1329| MAU Stage 4
1330+------------------------------------------------------------------------
1331+------------------------------------------------------------------------
1332Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
1333Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
1334Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
1335Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1336Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1337Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1338Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1339Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1340Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1341Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1342Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1343Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
1344Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1345Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1346Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1347Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
1348Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1349Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1350Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1351Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
1352Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1353Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1354Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
1355Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1356Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1357Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1358Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1359Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1360--------------------------------------------
1361Configuration for unused statistics ALUs.
1362Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1363Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1364Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1365Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
1366+------------------------------------------------------------------------
1367Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7.
1368Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7.
1369Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1370Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf.
1371Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf.
1372Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1373Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f.
1374Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f.
1375Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1376Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1377Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1378Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1379Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1380Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1381Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1382Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1383Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1384Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1385Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1386Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1387Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1388Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1389Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1390Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1391Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1392Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1393Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1394+------------------------------------------------------------------------
1395Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1396Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1397Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
1398Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
1399Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1400Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1401Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1402Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
1403Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
1404Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
1405Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1406Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1407Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1408Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1409
1410+------------------------------------------------------------------------
1411| MAU Stage 5
1412+------------------------------------------------------------------------
1413+------------------------------------------------------------------------
1414Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
1415Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
1416Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
1417Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1418Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1419Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1420Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1421Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1422Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1423Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1424Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1425Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
1426Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1427Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1428Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1429Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
1430Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1431Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1432Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1433Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
1434Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1435Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1436Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19.
1437Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1438Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1439Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1440Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1441Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1442--------------------------------------------
1443Configuration for unused statistics ALUs.
1444Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1445Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1446Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1447Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
1448+------------------------------------------------------------------------
1449Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7.
1450Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7.
1451Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1452Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf.
1453Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf.
1454Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1455Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f.
1456Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f.
1457Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1458Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1459Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1460Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1461Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1462Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1463Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1464Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1465Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1466Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1467Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1468Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1469Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1470Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1471Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1472Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1473Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1474Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1475Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1476+------------------------------------------------------------------------
1477Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1478Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1479Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
1480Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
1481Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1482Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1483Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1484Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0.
1485Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
1486Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
1487Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1488Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1489Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1490Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1491
1492+------------------------------------------------------------------------
1493| MAU Stage 6
1494+------------------------------------------------------------------------
1495+------------------------------------------------------------------------
1496Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19.
1497Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
1498Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
1499Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 19.
1500Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 9.
1501Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 3.
1502Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1503Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1504Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1505Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1506Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1507Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
1508Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1509Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1510Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1511Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
1512Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1513Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1514Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1515Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
1516Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1517Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1518Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
1519Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1520Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1521Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1522Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1523Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1524--------------------------------------------
1525Configuration for unused statistics ALUs.
1526Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1527Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1528Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1529Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
1530+------------------------------------------------------------------------
1531Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7.
1532Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7.
1533Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1534Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf.
1535Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf.
1536Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1537Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f.
1538Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f.
1539Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1540Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1541Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1542Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1543Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1544Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1545Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1546Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1547Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1548Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1549Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1550Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1551Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1552Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1553Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1554Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1555Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1556Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1557Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1558+------------------------------------------------------------------------
1559Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1560Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1561Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
1562Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
1563Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1564Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1565Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0.
1566Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
1567Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 3.
1568Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0.
1569Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1570Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1571Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1572Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1573
1574+------------------------------------------------------------------------
1575| MAU Stage 7
1576+------------------------------------------------------------------------
1577+------------------------------------------------------------------------
1578Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
1579Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
1580Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
1581Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1582Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1583Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1584Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1585Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1586Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1587Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1588Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1589Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
1590Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1591Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1592Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1593Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
1594Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1595Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1596Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1597Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
1598Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1599Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1600Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
1601Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1602Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1603Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1604Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1605Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1606--------------------------------------------
1607Configuration for unused statistics ALUs.
1608Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1609Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1610Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1611Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
1612+------------------------------------------------------------------------
1613Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7.
1614Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7.
1615Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1616Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf.
1617Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf.
1618Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1619Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f.
1620Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f.
1621Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1622Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1623Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1624Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1625Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1626Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1627Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1628Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1629Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1630Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1631Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1632Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1633Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1634Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1635Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1636Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1637Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1638Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1639Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1640+------------------------------------------------------------------------
1641Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1642Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1643Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
1644Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
1645Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1646Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1647Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1648Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
1649Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
1650Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
1651Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1652Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1653Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1654Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1655
1656+------------------------------------------------------------------------
1657| MAU Stage 8
1658+------------------------------------------------------------------------
1659+------------------------------------------------------------------------
1660Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
1661Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
1662Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
1663Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1664Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1665Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1666Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1667Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1668Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1669Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1670Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1671Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
1672Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1673Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1674Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1675Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
1676Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1677Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1678Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1679Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
1680Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1681Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1682Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
1683Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1684Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1685Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1686Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1687Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1688--------------------------------------------
1689Configuration for unused statistics ALUs.
1690Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1691Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1692Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1693Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
1694+------------------------------------------------------------------------
1695Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7.
1696Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7.
1697Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1698Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf.
1699Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf.
1700Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1701Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f.
1702Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f.
1703Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1704Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1705Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1706Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1707Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1708Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1709Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1710Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1711Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1712Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1713Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1714Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1715Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1716Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1717Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1718Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1719Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1720Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1721Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1722+------------------------------------------------------------------------
1723Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1724Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1725Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
1726Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
1727Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1728Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1729Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1730Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
1731Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
1732Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
1733Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1734Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1735Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1736Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1737
1738+------------------------------------------------------------------------
1739| MAU Stage 9
1740+------------------------------------------------------------------------
1741+------------------------------------------------------------------------
1742Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
1743Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
1744Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
1745Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1746Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1747Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1748Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1749Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1750Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1751Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1752Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1753Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
1754Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1755Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1756Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1757Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
1758Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1759Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1760Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1761Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
1762Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1763Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1764Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
1765Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1766Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1767Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1768Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1769Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1770--------------------------------------------
1771Configuration for unused statistics ALUs.
1772Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1773Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1774Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1775Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
1776+------------------------------------------------------------------------
1777Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7.
1778Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7.
1779Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1780Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf.
1781Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf.
1782Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1783Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f.
1784Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f.
1785Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1786Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1787Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1788Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1789Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1790Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1791Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1792Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1793Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1794Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1795Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1796Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1797Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1798Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1799Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1800Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1801Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1802Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1803Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1804+------------------------------------------------------------------------
1805Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1806Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1807Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
1808Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
1809Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1810Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1811Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1812Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
1813Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
1814Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
1815Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1816Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1817Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1818Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1819
1820+------------------------------------------------------------------------
1821| MAU Stage 10
1822+------------------------------------------------------------------------
1823+------------------------------------------------------------------------
1824Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
1825Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
1826Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
1827Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1828Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1829Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1830Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1831Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1832Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1833Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1834Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1835Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
1836Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1837Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1838Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1839Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
1840Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1841Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1842Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1843Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
1844Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1845Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1846Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
1847Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1848Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1849Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1850Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1851Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1852--------------------------------------------
1853Configuration for unused statistics ALUs.
1854Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1855Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1856Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1857Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
1858+------------------------------------------------------------------------
1859Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7.
1860Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7.
1861Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1862Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf.
1863Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf.
1864Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1865Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f.
1866Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f.
1867Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1868Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1869Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1870Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1871Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1872Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1873Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1874Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1875Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1876Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1877Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1878Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1879Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1880Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1881Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1882Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1883Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1884Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1885Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1886+------------------------------------------------------------------------
1887Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1888Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1889Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
1890Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
1891Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1892Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1893Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1894Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
1895Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
1896Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
1897Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1898Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1899Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1900Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1901
1902+------------------------------------------------------------------------
1903| MAU Stage 11
1904+------------------------------------------------------------------------
1905+------------------------------------------------------------------------
1906Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
1907Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
1908Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
1909Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
1910Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
1911Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
1912Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
1913Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
1914Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
1915Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
1916Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
1917Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
1918Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
1919Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
1920Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
1921Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
1922Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
1923Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
1924Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
1925Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
1926Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
1927Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
1928Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19.
1929Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
1930Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
1931Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
1932Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
1933Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
1934--------------------------------------------
1935Configuration for unused statistics ALUs.
1936Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
1937Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
1938Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
1939Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
1940+------------------------------------------------------------------------
1941Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7.
1942Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7.
1943Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1944Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf.
1945Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf.
1946Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1947Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f.
1948Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f.
1949Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f.
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1950Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
1951Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
1952Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
1953Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
1954Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
1955Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1956Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
1957Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
1958Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
1959Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
1960Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
1961Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
1962Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
1963Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
1964Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
1965Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
1966Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
1967Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
1968+------------------------------------------------------------------------
1969Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
1970Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
1971Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
1972Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
1973Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
1974Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
1975Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
1976Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0.
1977Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
1978Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
1979Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
1980Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
1981Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
1982Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
1983
1984+------------------------------------------------------------------------
Carmelo Cascone133c7b12017-09-13 15:36:08 +0200[diff] [blame]1985| Number of configuration field values set in Match-Action Stages: 1599
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]1986+------------------------------------------------------------------------
1987
1988+------------------------------------------------------------------------
1989| MAU Feature Characteristics:
1990+------------------------------------------------------------------------
1991
1992
1993Features per Stage for ingress:
1994-----------------------------------------------------------------------------------------------
1995| Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency |
1996| | | | | LPF | (max words) | | to Previous |
1997-----------------------------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]1998| 0 | Yes | Yes | Yes | No | No (0) | No | match |
1999| 1 | Yes | No | Yes | No | No (0) | No | match |
2000| 2 | Yes* | No | Yes* | No | No (0) | No | concurrent |
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]2001| 3 | Yes* | No | Yes* | No | No (0) | No | concurrent |
2002| 4 | Yes* | No | Yes* | No | No (0) | No | concurrent |
2003| 5 | Yes* | No | Yes* | No | No (0) | No | concurrent |
2004| 6 | No | No | No | No | No (0) | No | match |
2005| 7 | No | No | No | No | No (0) | No | concurrent |
2006| 8 | No | No | No | No | No (0) | No | concurrent |
2007| 9 | No | No | No | No | No (0) | No | concurrent |
2008| 10 | No | No | No | No | No (0) | No | concurrent |
2009| 11 | No | No | No | No | No (0) | No | concurrent |
2010-----------------------------------------------------------------------------------------------
2011
2012A '*' denotes that this feature was added to balance an action/concurrent chain.
2013
2014
2015Features per Stage for egress:
2016-----------------------------------------------------------------------------------------------
2017| Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency |
2018| | | | | LPF | (max words) | | to Previous |
2019-----------------------------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2020| 0 | No | No | No | No | No (0) | No | match |
2021| 1 | No | No | No | No | No (0) | No | concurrent |
2022| 2 | No | No | No | No | No (0) | No | concurrent |
2023| 3 | No | No | No | No | No (0) | No | concurrent |
2024| 4 | No | No | No | No | No (0) | No | concurrent |
2025| 5 | No | No | No | No | No (0) | No | concurrent |
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]2026| 6 | No | No | No | No | No (0) | No | match |
2027| 7 | No | No | No | No | No (0) | No | concurrent |
2028| 8 | No | No | No | No | No (0) | No | concurrent |
2029| 9 | No | No | No | No | No (0) | No | concurrent |
2030| 10 | No | No | No | No | No (0) | No | concurrent |
2031| 11 | No | No | No | No | No (0) | No | concurrent |
2032-----------------------------------------------------------------------------------------------
2033
2034A '*' denotes that this feature was added to balance an action/concurrent chain.
2035
2036+------------------------------------------------------------------------
2037| MAU Latency Characteristics:
2038+------------------------------------------------------------------------
2039
2040
2041Clock Cycles Per Stage For ingress:
2042-----------------------------------------------------------------------------------------------------
2043| Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency |
2044-----------------------------------------------------------------------------------------------------
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2045| 0 | 22 | 13 | match | 22 |
2046| 1 | 20 | 11 | match | 20 |
2047| 2 | 20 | 11 | concurrent | 1 |
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]2048| 3 | 20 | 11 | concurrent | 1 |
2049| 4 | 20 | 11 | concurrent | 1 |
2050| 5 | 20 | 11 | concurrent | 1 |
2051| 6 | 20 | 11 | match | 20 |
2052| 7 | 20 | 11 | concurrent | 1 |
2053| 8 | 20 | 11 | concurrent | 1 |
2054| 9 | 20 | 11 | concurrent | 1 |
2055| 10 | 20 | 11 | concurrent | 1 |
2056| 11 | 20 | 11 | concurrent | 1 |
2057-----------------------------------------------------------------------------------------------------
2058
Brian O'Connora6862e02017-09-08 01:17:39 -0700[diff] [blame]2059Total latency for ingress: 75
Carmelo Cascone5db39682017-09-07 16:36:42 +0200[diff] [blame]2060
2061
2062Clock Cycles Per Stage For egress:
2063-----------------------------------------------------------------------------------------------------
2064| Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency |
2065-----------------------------------------------------------------------------------------------------
2066| 0 | 20 | 11 | match | 20 |
2067| 1 | 20 | 11 | concurrent | 1 |
2068| 2 | 20 | 11 | concurrent | 1 |
2069| 3 | 20 | 11 | concurrent | 1 |
2070| 4 | 20 | 11 | concurrent | 1 |
2071| 5 | 20 | 11 | concurrent | 1 |
2072| 6 | 20 | 11 | match | 20 |
2073| 7 | 20 | 11 | concurrent | 1 |
2074| 8 | 20 | 11 | concurrent | 1 |
2075| 9 | 20 | 11 | concurrent | 1 |
2076| 10 | 20 | 11 | concurrent | 1 |
2077| 11 | 20 | 11 | concurrent | 1 |
2078-----------------------------------------------------------------------------------------------------
2079
2080Total latency for egress: 54