| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1 | +---------------------------------------------------------------------+ |
| 2 | | Log file: mau.config.log | |
| 3 | | Compiler version: 5.1.0 (fca32d1) | |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 4 | | Created on: Fri Sep 8 08:23:45 2017 | |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 5 | +---------------------------------------------------------------------+ |
| 6 | |
| 7 | Final Stage dependencies are: |
| 8 | (0, 'ingress') : match |
| 9 | (1, 'ingress') : match |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 10 | (2, 'ingress') : concurrent |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 11 | (3, 'ingress') : concurrent |
| 12 | (4, 'ingress') : concurrent |
| 13 | (5, 'ingress') : concurrent |
| 14 | (6, 'ingress') : match |
| 15 | (7, 'ingress') : concurrent |
| 16 | (8, 'ingress') : concurrent |
| 17 | (9, 'ingress') : concurrent |
| 18 | (10, 'ingress') : concurrent |
| 19 | (11, 'ingress') : concurrent |
| 20 | (0, 'egress') : match |
| 21 | (1, 'egress') : concurrent |
| 22 | (2, 'egress') : concurrent |
| 23 | (3, 'egress') : concurrent |
| 24 | (4, 'egress') : concurrent |
| 25 | (5, 'egress') : concurrent |
| 26 | (6, 'egress') : match |
| 27 | (7, 'egress') : concurrent |
| 28 | (8, 'egress') : concurrent |
| 29 | (9, 'egress') : concurrent |
| 30 | (10, 'egress') : concurrent |
| 31 | (11, 'egress') : concurrent |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 32 | Action/Concurrent chaining in ingress consists of [2, 3, 4, 5] |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 33 | Action/Concurrent chaining in ingress consists of [7, 8, 9, 10, 11] |
| 34 | Action/Concurrent chaining in egress consists of [1, 2, 3, 4, 5] |
| 35 | Action/Concurrent chaining in egress consists of [7, 8, 9, 10, 11] |
| 36 | |
| 37 | +------------------------------------------------------------------------ |
| 38 | | MAU Stage 0 |
| 39 | +------------------------------------------------------------------------ |
| 40 | |
| 41 | +------------------------------------------------------------------------ |
| 42 | | Working on table _condition_0 in stage 0 --- |
| 43 | +------------------------------------------------------------------------ |
| 44 | --> Stage Gateway Table for condition _condition_0 in stage 0 |
| 45 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 46 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 47 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 48 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 49 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 50 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 51 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1) |
| 52 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 53 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 2. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 54 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 55 | Configuring match input crossbar byte 0 to come from 8-bit PHV container 2. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 56 | That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 57 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4) |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 58 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 59 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| 60 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte0 to be 0x2. |
| 61 | Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 62 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0. |
| 63 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1. |
| 64 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0. |
| 65 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1. |
| 66 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| 67 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| 68 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| 69 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| 70 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0 |
| 71 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0 |
| 72 | Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| 73 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| 74 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| 75 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| 76 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| 77 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff |
| 78 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xfffffe |
| 79 | Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x10 |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 80 | Configuring rams.match.merge.gateway_next_table_lut[0][4] to be 0x1 |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 81 | Configuring rams.match.merge.gateway_en.gateway_en to be 0x1 |
| 82 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf |
| 83 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1 |
| 84 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_logical_select to be 0x0 |
| 85 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_inhibit_enable to be 0x1 |
| 86 | Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff |
| 87 | Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff |
| 88 | |
| 89 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 90 | | Working on table process_packet_out_table__action__ in stage 0 --- |
| 91 | +------------------------------------------------------------------------ |
| 92 | --> Action Data Table process_packet_out_table__action__ with logical_table_id 1 that is reference type is 'direct' |
| 93 | |
| 94 | +------------------------------------------------------------------------ |
| 95 | | Working on table process_packet_out_table in stage 0 --- |
| 96 | +------------------------------------------------------------------------ |
| 97 | --> Match Table with no key process_packet_out_table with logical_table_id 1 |
| 98 | allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits |
| 99 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 100 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 101 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 102 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 103 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 104 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 105 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 1 (logical table id). |
| 106 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1. |
| 107 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 1 (logical table id). |
| 108 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1. |
| 109 | Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x40. |
| 110 | Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x0. |
| 111 | Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0x10. |
| 112 | Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0x10. |
| 113 | Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x2 (previous_value=0x0 OR new_value=0x2). |
| 114 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x44. |
| 115 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
| 116 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_instr to be 0x74412. |
| 117 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_color to be 0. |
| 118 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_parity to be 1. |
| 119 | Micro instruction added in VLIW 2 for 16-bit position 2 for table process_packet_out_table. |
| 120 | Assembled as 0x74412 (or decimal 476178) |
| 121 | Micro Instruction deposit-field for PHV Container 130 has bit width 23 |
| 122 | Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| 123 | Field Src1 [4:0] : 0x1 (5 bits in instruction bits [8:4]) |
| 124 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 125 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 126 | Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11]) |
| 127 | Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15]) |
| 128 | Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16]) |
| 129 | Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| 130 | |
| 131 | Configuring dp.imem.imem_subword8[unit_number=2][vliw_instruction_number=2].imem_subword8_instr to be 0x74d82. |
| 132 | Configuring dp.imem.imem_subword8[unit_number=2][vliw_instruction_number=2].imem_subword8_color to be 0. |
| 133 | Configuring dp.imem.imem_subword8[unit_number=2][vliw_instruction_number=2].imem_subword8_parity to be 1. |
| 134 | Micro instruction added in VLIW 2 for 8-bit position 2 for table process_packet_out_table. |
| 135 | Assembled as 0x74d82 (or decimal 478594) |
| 136 | Micro Instruction deposit-field for PHV Container 66 has bit width 20 |
| 137 | Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| 138 | Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4]) |
| 139 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 140 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 141 | Field high_bit [2:0] : 0x1 (3 bits in instruction bits [13:11]) |
| 142 | Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14]) |
| 143 | Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16]) |
| 144 | Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19]) |
| 145 | |
| 146 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4) |
| 147 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6) |
| 148 | --> Stage Gateway Table for condition process_packet_out_table_always_true_condition in stage 0 |
| 149 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 150 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 151 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 152 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 153 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 154 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 155 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x0) |
| 156 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| 157 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x0) |
| 158 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| 159 | Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1) |
| 160 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| 161 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| 162 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| 163 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| 164 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1 |
| 165 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0 |
| 166 | Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| 167 | Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| 168 | Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| 169 | Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| 170 | Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| 171 | Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff |
| 172 | Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff |
| 173 | Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8 |
| 174 | Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0x10 |
| 175 | Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10) |
| 176 | Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0x10 |
| 177 | Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2) |
| 178 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe |
| 179 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1 |
| 180 | allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits |
| 181 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x1 |
| 182 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1 |
| 183 | Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2 |
| 184 | Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x0 |
| 185 | Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0 |
| 186 | Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x0 |
| 187 | Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0 |
| 188 | Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff |
| 189 | Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff |
| 190 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1. |
| 191 | |
| 192 | +------------------------------------------------------------------------ |
| 193 | | Working on table table0__action__ in stage 0 --- |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 194 | +------------------------------------------------------------------------ |
| 195 | --> Action Data Table table0__action__ with logical_table_id 0 that is reference type is 'direct' |
| 196 | Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_select to be 4. |
| 197 | Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_enable to be 1. |
| 198 | |
| 199 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 200 | | Working on table table0 in stage 0 --- |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 201 | +------------------------------------------------------------------------ |
| 202 | --> Ternary Match Table table0 with logical_table_id 0 |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 203 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1). |
| 204 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1). |
| 205 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1). |
| 206 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1). |
| 207 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1). |
| 208 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1). |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 209 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id). |
| 210 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| 211 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id). |
| 212 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| 213 | Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x3. |
| 214 | Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_default to be 0x0. |
| 215 | Configuring rams.match.merge.mau_action_instruction_adr_per_entry_en_mux_ctl[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_per_entry_en_mux_ctl to be 0x2. |
| 216 | Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=1].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 217 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x870a080. |
| 218 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
| 219 | Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 220 | Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x10. |
| 221 | Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x10. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 222 | Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x0. |
| 223 | Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=1][result_bus_number=0].mau_immediate_data_mask to be 0xffff. |
| 224 | Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=1][result_bus_number=0].mau_stats_adr_mask to be 0xffffe. |
| 225 | Configuring rams.match.merge.mau_stats_adr_default[table_type_index=1][result_bus_number=0].mau_stats_adr_default to be 0x80000. |
| 226 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x0) |
| 227 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x3. (old value = 0x0 OR new value = 0x3) |
| 228 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_address to be 16. |
| 229 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_enable to be 1. |
| 230 | Configuring match input crossbar byte 133 to come from 16-bit PHV container 0. |
| 231 | That PHV byte contains version/valid |
| 232 | {unused[6:0], ig_intr_md.ingress_port[8:8]}. |
| 233 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_address to be 2. |
| 234 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 235 | Configuring match input crossbar byte 128 to come from 32-bit PHV container 2. |
| 236 | That PHV byte contains {ethernet.srcAddr[7:0]}. |
| 237 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_address to be 2. |
| 238 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 239 | Configuring match input crossbar byte 129 to come from 32-bit PHV container 2. |
| 240 | That PHV byte contains {ethernet.srcAddr[15:8]}. |
| 241 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_address to be 2. |
| 242 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 243 | Configuring match input crossbar byte 130 to come from 32-bit PHV container 2. |
| 244 | That PHV byte contains {ethernet.srcAddr[23:16]}. |
| 245 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_address to be 2. |
| 246 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 247 | Configuring match input crossbar byte 131 to come from 32-bit PHV container 2. |
| 248 | That PHV byte contains {ethernet.srcAddr[31:24]}. |
| 249 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_address to be 1. |
| 250 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 251 | Configuring match input crossbar byte 132 to come from 32-bit PHV container 1. |
| 252 | That PHV byte contains {ethernet.dstAddr[15:8]}. |
| 253 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_address to be 1. |
| 254 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 255 | Configuring match input crossbar byte 134 to come from 32-bit PHV container 1. |
| 256 | That PHV byte contains {ethernet.dstAddr[31:24]}. |
| 257 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_address to be 1. |
| 258 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 259 | Configuring match input crossbar byte 135 to come from 32-bit PHV container 1. |
| 260 | That PHV byte contains {ethernet.dstAddr[39:32]}. |
| 261 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_address to be 20. |
| 262 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_enable to be 1. |
| 263 | Configuring match input crossbar byte 136 to come from 16-bit PHV container 4. |
| 264 | That PHV byte contains {ethernet.etherType[7:0]}. |
| 265 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_address to be 1. |
| 266 | Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_lo_enable to be 1. |
| 267 | Configuring match input crossbar byte 137 to come from 32-bit PHV container 1. |
| 268 | That PHV byte contains {ethernet.dstAddr[23:16]}. |
| 269 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_address to be 19. |
| 270 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_enable to be 1. |
| 271 | Configuring match input crossbar byte 138 to come from 16-bit PHV container 3. |
| 272 | That PHV byte contains {ethernet.srcAddr[47:40]}. |
| 273 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_address to be 20. |
| 274 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_enable to be 1. |
| 275 | Configuring match input crossbar byte 139 to come from 16-bit PHV container 4. |
| 276 | That PHV byte contains {ethernet.etherType[15:8]}. |
| 277 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_address to be 16. |
| 278 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_enable to be 1. |
| 279 | Configuring match input crossbar byte 140 to come from 16-bit PHV container 0. |
| 280 | That PHV byte contains {ig_intr_md.ingress_port[7:0]}. |
| 281 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_address to be 19. |
| 282 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_enable to be 1. |
| 283 | Configuring match input crossbar byte 141 to come from 16-bit PHV container 3. |
| 284 | That PHV byte contains {ethernet.dstAddr[7:0]}. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 285 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 286 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_enable to be 1. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 287 | Configuring match input crossbar byte 142 to come from 8-bit PHV container 1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 288 | That PHV byte contains {ethernet.srcAddr[39:32]}. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 289 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 0. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 290 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_enable to be 1. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 291 | Configuring match input crossbar byte 143 to come from 8-bit PHV container 0. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 292 | That PHV byte contains {ethernet.dstAddr[47:40]}. |
| 293 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6) |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 294 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x7. (previous value = 0x4 OR new value = 0x3) |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 295 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x19. (previous value = 0x0 OR new value = 0x19) |
| 296 | |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 297 | --> Idletime Table for match table table0 in stage 0 |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 298 | Looking at Map RAM: Row 7 Unit 0 |
| 299 | Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 0. |
| 300 | Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 1. |
| 301 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].two_way_idletime_notification to be 1. |
| 302 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].per_flow_idletime to be 1. |
| 303 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].idletime_bitwidth to be 2 (precision = 3 bits). |
| 304 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_type to be 4. |
| 305 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0. |
| 306 | FIXME: Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn_members to be 0. |
| 307 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn to be 0. |
| 308 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| 309 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| 310 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| 311 | Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| 312 | Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 2. |
| 313 | Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| 314 | Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| 315 | Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 316 | Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_stats_meter_adr_mux_select_idlet to be 1. |
| 317 | Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0. |
| 318 | Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1. |
| 319 | Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0. |
| 320 | Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1. |
| 321 | Configuring rams.map_alu.row[row=7].adrmux.idletime_cfg_rd_clear_val[map_ram_index=0].idletime_cfg_rd_clear_val to be 0x36. |
| 322 | logical table ID is 0 |
| 323 | Configuring rams.match.adrdist.adr_dist_idletime_adr_oxbar_ctl.[entry_index=2].adr_dist_idletime_adr_oxbar_ctl be 0x4000 (previous value = 0x0 OR new value = 0x4000) |
| 324 | Note that rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_en must be programmed by run time. |
| 325 | Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_offset be 0x0. |
| 326 | Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_size be 0x0. |
| 327 | Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_pos be 0x0. |
| 328 | Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_en be 0x0. |
| 329 | Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_interval be 0x7. |
| 330 | Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_offset be 0x0. |
| 331 | Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_size be 0x0. |
| 332 | Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_pos be 0x0. |
| 333 | Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_en be 0. |
| 334 | Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_size be 2. |
| 335 | Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_direct be 1. |
| 336 | Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=2].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 337 | Configuring rams.match.merge.mau_idletime_adr_mask[table_type_index=1][result_bus_number=0].mau_idletime_adr_mask to be 0x1ffff8. |
| 338 | Configuring rams.match.merge.mau_idletime_adr_default[table_type_index=1][result_bus_number=0].idletime_adr_default to be 0x100003. |
| 339 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x4602. |
| 340 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1. |
| 341 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 1. |
| 342 | Micro instruction added in VLIW 0 for 16-bit position 2 for table table0. |
| 343 | Assembled as 0x4602 (or decimal 17922) |
| 344 | Micro Instruction deposit-field for PHV Container 130 has bit width 23 |
| 345 | Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| 346 | Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4]) |
| 347 | Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9]) |
| 348 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 349 | Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11]) |
| 350 | Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15]) |
| 351 | Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16]) |
| 352 | Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| 353 | |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 354 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x6 OR new value = 0x4) |
| 355 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_instr to be 0x4602. |
| 356 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_color to be 0. |
| 357 | Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_parity to be 0. |
| 358 | Micro instruction added in VLIW 1 for 16-bit position 2 for table table0. |
| 359 | Assembled as 0x4602 (or decimal 17922) |
| 360 | Micro Instruction deposit-field for PHV Container 130 has bit width 23 |
| 361 | Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| 362 | Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4]) |
| 363 | Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9]) |
| 364 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 365 | Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11]) |
| 366 | Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15]) |
| 367 | Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16]) |
| 368 | Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| 369 | |
| 370 | Configuring dp.imem.imem_subword8[unit_number=2][vliw_instruction_number=1].imem_subword8_instr to be 0x592. |
| 371 | Configuring dp.imem.imem_subword8[unit_number=2][vliw_instruction_number=1].imem_subword8_color to be 0. |
| 372 | Configuring dp.imem.imem_subword8[unit_number=2][vliw_instruction_number=1].imem_subword8_parity to be 1. |
| 373 | Micro instruction added in VLIW 1 for 8-bit position 2 for table table0. |
| 374 | Assembled as 0x592 (or decimal 1426) |
| 375 | Micro Instruction deposit-field for PHV Container 66 has bit width 20 |
| 376 | Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 377 | Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4]) |
| 378 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 379 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 380 | Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11]) |
| 381 | Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14]) |
| 382 | Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16]) |
| 383 | Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19]) |
| 384 | |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 385 | Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_instr to be 0x39fc01. |
| 386 | Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_color to be 0. |
| 387 | Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_parity to be 1. |
| 388 | Micro instruction added in VLIW 1 for 16-bit position 1 for table table0. |
| 389 | Assembled as 0x39fc01 (or decimal 3800065) |
| 390 | Micro Instruction deposit-field for PHV Container 129 has bit width 23 |
| 391 | Field Src2 [3:0] : 0x1 (4 bits in instruction bits [3:0]) |
| 392 | Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4]) |
| 393 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 394 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 395 | Field high_bit [3:0] : 0xf (4 bits in instruction bits [14:11]) |
| 396 | Field low_bit_lo [0:0] : 0x1 (1 bits in instruction bits [15:15]) |
| 397 | Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16]) |
| 398 | Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20]) |
| 399 | |
| 400 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x4. (previous value = 0x4 OR new value = 0x4) |
| 401 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x7. (previous value = 0x6 OR new value = 0x7) |
| 402 | Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_instr to be 0xb7d93. |
| 403 | Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_color to be 1. |
| 404 | Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_parity to be 0. |
| 405 | Micro instruction added in VLIW 1 for 8-bit position 3 for table table0. |
| 406 | Assembled as 0xb7d93 (or decimal 753043) |
| 407 | Micro Instruction deposit-field for PHV Container 67 has bit width 20 |
| 408 | Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0]) |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 409 | Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4]) |
| 410 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 411 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 412 | Field high_bit [2:0] : 0x7 (3 bits in instruction bits [13:11]) |
| 413 | Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14]) |
| 414 | Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16]) |
| 415 | Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19]) |
| 416 | |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 417 | Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0xc. (previous value = 0x4 OR new value = 0x8) |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 418 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].idletime_adr_payload_shifter_en to be 1. |
| 419 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].stats_adr_payload_shifter_en to be 1. |
| 420 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].action_instruction_adr_payload_shifter_en to be 1. |
| 421 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].immediate_data_payload_shifter_en to be 1. |
| 422 | Configuring rams.match.merge.mau_table_counter_ctl[half_index=0].mau_table_counter_ctl to be 0x2. (previous value = 0x0 OR new value = 0x2) |
| 423 | dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit'] |
| 424 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data_dirtcam_mode to be 0x155. |
| 425 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vbit_dirtcam_mode to be 0x1. |
| 426 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data1_select to be 1. |
| 427 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_chain_out_enable to be 0. |
| 428 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_ingress to be 1. |
| 429 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_match_output_enable to be 1. |
| 430 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vpn to be 0. |
| 431 | Configuring tcams.col[col=1].tcam_mode[row=9].tcam_logical_table to be 0. |
| 432 | TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit. |
| 433 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=0] to be 15. |
| 434 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=1] to be 15. |
| 435 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=2] to be 15. |
| 436 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=3] to be 15. |
| 437 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=4] to be 15. |
| 438 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=5] to be 15. |
| 439 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=6] to be 15. |
| 440 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=7] to be 15. |
| 441 | Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_select to be 0 (don't care). |
| 442 | Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_enable to be 1. |
| 443 | Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_select to be 2. |
| 444 | Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_enable to be 1. |
| 445 | dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit'] |
| 446 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data_dirtcam_mode to be 0x155. |
| 447 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vbit_dirtcam_mode to be 0x0. |
| 448 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data1_select to be 1. |
| 449 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_chain_out_enable to be 1. |
| 450 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_ingress to be 1. |
| 451 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_match_output_enable to be 0. |
| 452 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vpn to be 0. |
| 453 | Configuring tcams.col[col=1].tcam_mode[row=10].tcam_logical_table to be 0. |
| 454 | TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit. |
| 455 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15. |
| 456 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15. |
| 457 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15. |
| 458 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15. |
| 459 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15. |
| 460 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15. |
| 461 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15. |
| 462 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15. |
| 463 | Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_select to be 3 (version on [3:2] and valid bits for [1:0]). |
| 464 | Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_enable to be 1. |
| 465 | Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0. |
| 466 | Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1. |
| 467 | Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_select to be 1. |
| 468 | Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_enable to be 1. |
| 469 | dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit'] |
| 470 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data_dirtcam_mode to be 0x155. |
| 471 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vbit_dirtcam_mode to be 0x1. |
| 472 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data1_select to be 1. |
| 473 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_chain_out_enable to be 1. |
| 474 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_ingress to be 1. |
| 475 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_match_output_enable to be 0. |
| 476 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vpn to be 0. |
| 477 | Configuring tcams.col[col=1].tcam_mode[row=11].tcam_logical_table to be 0. |
| 478 | TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit. |
| 479 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15. |
| 480 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15. |
| 481 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15. |
| 482 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15. |
| 483 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15. |
| 484 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15. |
| 485 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15. |
| 486 | Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15. |
| 487 | Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_select to be 0 (extra byte low nibble [3:0]). |
| 488 | Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_enable to be 1. |
| 489 | Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0. |
| 490 | Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1. |
| 491 | Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_select to be 0. |
| 492 | Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_enable to be 1. |
| 493 | Configuring tcams.col[col=0].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x0. |
| 494 | Configuring tcams.col[col=1].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x200. |
| 495 | --> Ternary Indirection table for Match Table table0 with logical_table_id 0 |
| 496 | Configuring tcams.tcam_match_adr_shift[tcam_table_id=0] to be left shift of 3. |
| 497 | Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_write_data_mux_select to be select of 7. |
| 498 | Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_read_data_mux_select to be select of 7. |
| 499 | Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.tind_result_bus_select to be select of 1. |
| 500 | Configuring rams.map_alu.row[row=0].adrmux.ram_address_mux_ctl[column_half=0][column_index=2].ram_unitram_adr_mux_select to be 2. |
| 501 | Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_type to be 6. |
| 502 | Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_vpn to be 0. |
| 503 | Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_logical_table to be 0. |
| 504 | Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_ingress to be 1. |
| 505 | Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_enable to be 1. |
| 506 | Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id). |
| 507 | Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_enable to be 1. |
| 508 | Configuring rams.array.row[row=0].tind_ecc_error_uram_ctl[direction=0].tind_ecc_error_uram_ctl to be select of 0x1. (previous value = 0x0 OR new value = 0x1) |
| 509 | Configuring rams.match.merge.tind_ram_data_size[tind_bus_number=0].tind_ram_data_size to be code 4. |
| 510 | Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id). |
| 511 | Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_enable to be 1. |
| 512 | TODO: rams.match.merge.tind_bus_prop[tind_bus_number=0] is currently always set to 1. |
| 513 | Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].tcam_piped to be 1. |
| 514 | Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].enabled to be 1. |
| 515 | Configuring rams.match.merge.mau_action_instruction_adr_tcam_shiftcount[physical_result_bus=0].mau_action_instruction_adr_tcam_shiftcount to be 0. |
| 516 | Configuring rams.match.merge.mau_immediate_data_tcam_shiftcount[tind_bus_number=0].mau_immediate_data_tcam_shiftcount to be 3. |
| 517 | Configuring rams.match.merge.mau_idletime_adr_tcam_shiftcount[result_bus_number=0].mau_idletime_adr_tcam_shiftcount to be 0x44. |
| 518 | Configuring rams.match.merge.mau_stats_adr_tcam_shiftcount[result_bus_index=0].mau_stats_adr_tcam_shiftcount to be 0x49. |
| 519 | Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_select to be 0 (logical table id). |
| 520 | Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_enable to be 1. |
| 521 | TODO: rams.match.merge.tcam_table_prop[tcam_table_id=0] is currently always set to 1. |
| 522 | Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].tcam_piped to be 1. |
| 523 | Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].enabled to be 1. |
| 524 | Configuring tcams.tcam_output_table_thread[tcam_table_id=0].tcam_output_table_thread to be 1. |
| 525 | TODO: tcams.tcam_piped is currently always set to True for ingress and egress. |
| 526 | Configuring tcams.tcam_piped to be 3. |
| 527 | Configuring cfg_regs.mau_cfg_movereg_tcam_only.mau_cfg_movereg_tcam_only to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 528 | |
| 529 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 530 | | Working on table table0_counter in stage 0 --- |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 531 | +------------------------------------------------------------------------ |
| 532 | Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 533 | Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 534 | Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 535 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3. |
| 536 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 537 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0. |
| 538 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1. |
| 539 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1. |
| 540 | Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 541 | Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 542 | Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 543 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3. |
| 544 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 545 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0. |
| 546 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1. |
| 547 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1. |
| 548 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5. |
| 549 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1. |
| 550 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 551 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1. |
| 552 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 553 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 554 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5. |
| 555 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1. |
| 556 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 557 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1. |
| 558 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2) |
| 559 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 560 | Stat table table0_counter is used by match table table0. |
| 561 | Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8) |
| 562 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1. |
| 563 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0. |
| 564 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 565 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| 566 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| 567 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| 568 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| 569 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1. |
| 570 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| 571 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| 572 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1. |
| 573 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0. |
| 574 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 575 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1. |
| 576 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1. |
| 577 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1. |
| 578 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1. |
| 579 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1. |
| 580 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1. |
| 581 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1. |
| 582 | For counter width 32 and N = 4096 |
| 583 | number iterations = 32 |
| 584 | b_cur = 379488672.0 |
| 585 | eqn(b_cur) = 4294964039.26 |
| 586 | max_counter_value = 4294967295 |
| 587 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a. |
| 588 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff. |
| 589 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a. |
| 590 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff. |
| 591 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a. |
| 592 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff. |
| 593 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4. |
| 594 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1. |
| 595 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1. |
| 596 | TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0. |
| 597 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x0. |
| 598 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4. |
| 599 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1. |
| 600 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0. |
| 601 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0. |
| 602 | Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0. |
| 603 | Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0. |
| 604 | Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0. |
| 605 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0. |
| 606 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0. |
| 607 | Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1. |
| 608 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3. |
| 609 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_direct be 1. |
| 610 | Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=0].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 611 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_tcam be 1. |
| 612 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x0. |
| 613 | Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x7. ( previous value = 0x0 OR new value = 0x7) |
| 614 | Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x1. |
| 615 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 616 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 12. |
| 617 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 618 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 619 | Configuring rams.match.merge.exact_match_delay_thread[copy_index=0].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 620 | Configuring rams.match.merge.exact_match_delay_thread[copy_index=1].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 621 | Configuring rams.match.merge.exact_match_delay_thread[copy_index=2].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 622 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 10. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 623 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 624 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 625 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 626 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 627 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 628 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 629 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x3. |
| 630 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x2. |
| 631 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x2. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 632 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 633 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x2. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 634 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 635 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 636 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 637 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 16. |
| 638 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 21. |
| 639 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 640 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 641 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 642 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 643 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 644 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 645 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 646 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 647 | -------------------------------------------- |
| 648 | Configuration for unused statistics ALUs. |
| 649 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 650 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 651 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 652 | +------------------------------------------------------------------------ |
| 653 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| 654 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| 655 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 656 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf. |
| 657 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf. |
| 658 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 659 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| 660 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| 661 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 662 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 663 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 664 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 665 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 666 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 667 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 668 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 669 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 670 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 671 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 672 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 1. |
| 673 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 1. |
| 674 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 675 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 676 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 677 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 678 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 679 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 680 | +------------------------------------------------------------------------ |
| 681 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 19. |
| 682 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 2. |
| 683 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0. |
| 684 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0. |
| 685 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 686 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 687 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 688 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 689 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 690 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 691 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 692 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 693 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 694 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 695 | |
| 696 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 697 | | MAU Stage 1 |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 698 | +------------------------------------------------------------------------ |
| 699 | |
| 700 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 701 | | Working on table _condition_2 in stage 1 --- |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 702 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 703 | --> Stage Gateway Table for condition _condition_2 in stage 1 |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 704 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 705 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 706 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 707 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 708 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 709 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 710 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1) |
| 711 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| 712 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 18. |
| 713 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1. |
| 714 | Configuring match input crossbar byte 0 to come from 16-bit PHV container 2. |
| 715 | That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}. |
| 716 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 18. |
| 717 | Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1. |
| 718 | Configuring match input crossbar byte 1 to come from 16-bit PHV container 2. |
| 719 | That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}. |
| 720 | Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4) |
| 721 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 722 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| 723 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte1 to be 0x1. |
| 724 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=41].byte0 to be 0x1. |
| 725 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=42].byte0 to be 0x2. |
| 726 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=43].byte0 to be 0x4. |
| 727 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=44].byte0 to be 0x8. |
| 728 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=45].byte0 to be 0x10. |
| 729 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=46].byte0 to be 0x20. |
| 730 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=47].byte0 to be 0x40. |
| 731 | Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=48].byte0 to be 0x80. |
| 732 | Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 733 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0. |
| 734 | Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1. |
| 735 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0. |
| 736 | Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1. |
| 737 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| 738 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| 739 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| 740 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| 741 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0 |
| 742 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0 |
| 743 | Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| 744 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| 745 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| 746 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| 747 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| 748 | Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_mode to be 0x2 |
| 749 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff |
| 750 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff3f |
| 751 | Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8 |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 752 | Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x11 |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 753 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid0 to be 0x3 |
| 754 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid1 to be 0x3 |
| 755 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][0] to be 0xffffffff |
| 756 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][1] to be 0xffffffff |
| 757 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xffffff |
| 758 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff7fff |
| 759 | Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xc (previous value 0x8 OR new value 0x4) |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 760 | Configuring rams.match.merge.gateway_next_table_lut[0][2] to be 0x11 |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 761 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid0 to be 0x3 |
| 762 | Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid1 to be 0x3 |
| 763 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][0] to be 0xffffffff |
| 764 | Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][1] to be 0xffffffff |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 765 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0x1ffff |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 766 | Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][1] to be 0xffff |
| 767 | Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xe (previous value 0xc OR new value 0x2) |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 768 | Configuring rams.match.merge.gateway_next_table_lut[0][1] to be 0x11 |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 769 | Configuring rams.match.merge.gateway_en.gateway_en to be 0x1 |
| 770 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf |
| 771 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1 |
| 772 | allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits |
| 773 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x0 |
| 774 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1 |
| 775 | Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2 |
| 776 | Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x1 |
| 777 | Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0 |
| 778 | Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x1 |
| 779 | Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0 |
| 780 | Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff |
| 781 | Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff |
| 782 | |
| 783 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 784 | | Working on table ingress_port_count_table__action__ in stage 1 --- |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 785 | +------------------------------------------------------------------------ |
| 786 | --> Action Data Table ingress_port_count_table__action__ with logical_table_id 0 that is reference type is 'direct' |
| 787 | |
| 788 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 789 | | Working on table ingress_port_count_table in stage 1 --- |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 790 | +------------------------------------------------------------------------ |
| 791 | --> Match Table with no key ingress_port_count_table with logical_table_id 0 |
| 792 | allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits |
| 793 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| 794 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| 795 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| 796 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| 797 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| 798 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| 799 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id). |
| 800 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1. |
| 801 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id). |
| 802 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1. |
| 803 | Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x0. |
| 804 | Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x1. |
| 805 | Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0xff. |
| 806 | Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=1].mau_stats_adr_default to be 0x0. |
| 807 | Configuring rams.match.merge.mau_stats_adr_per_entry_en_mux_ctl[table_type_index=0][result_bus_number=1].mau_stats_adr_per_entry_en_mux_ctl to be 0x7. |
| 808 | Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| 809 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2000. |
| 810 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
| 811 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].stats_adr_payload_shifter_en to be 1. |
| 812 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1. |
| 813 | |
| 814 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 815 | | Working on table egress_port_count_table__action__ in stage 1 --- |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 816 | +------------------------------------------------------------------------ |
| 817 | --> Action Data Table egress_port_count_table__action__ with logical_table_id 1 that is reference type is 'direct' |
| 818 | |
| 819 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 820 | | Working on table egress_port_count_table in stage 1 --- |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 821 | +------------------------------------------------------------------------ |
| 822 | --> Match Table with no key egress_port_count_table with logical_table_id 1 |
| 823 | allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits |
| 824 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 825 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 826 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 827 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 828 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 829 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 830 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id). |
| 831 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| 832 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id). |
| 833 | Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| 834 | Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_default to be 0x40. |
| 835 | Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x0. |
| 836 | Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0xff. |
| 837 | Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0xff. |
| 838 | Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=0].mau_stats_adr_default to be 0x80000. |
| 839 | Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| 840 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x40. |
| 841 | Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 842 | --> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 1 |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 843 | Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 844 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 845 | Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 846 | Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 847 | Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 848 | Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| 849 | Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x0) |
| 850 | Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| 851 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x0) |
| 852 | Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| 853 | Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1) |
| 854 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| 855 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| 856 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| 857 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| 858 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1 |
| 859 | Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0 |
| 860 | Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| 861 | Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| 862 | Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| 863 | Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| 864 | Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| 865 | Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff |
| 866 | Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff |
| 867 | Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8 |
| 868 | Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0xff |
| 869 | Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10) |
| 870 | Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0xff |
| 871 | Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2) |
| 872 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe |
| 873 | Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1 |
| 874 | allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits |
| 875 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_logical_select to be 0x1 |
| 876 | Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_inhibit_enable to be 0x1 |
| 877 | Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x3 (previous value 0x2 OR new value 0x1) |
| 878 | Configuring rams.match.merge.gateway_payload_data[0][0][0][0].gateway_payload_data to be 0x0 |
| 879 | Configuring rams.match.merge.gateway_payload_data[0][0][1][0].gateway_payload_data to be 0x0 |
| 880 | Configuring rams.match.merge.gateway_payload_data[0][0][0][1].gateway_payload_data to be 0x0 |
| 881 | Configuring rams.match.merge.gateway_payload_data[0][0][1][1].gateway_payload_data to be 0x0 |
| 882 | Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff |
| 883 | Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff |
| 884 | Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=0].action_instruction_adr_payload_shifter_en to be 1. |
| 885 | |
| 886 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 887 | | Working on table ingress_port_counter in stage 1 --- |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 888 | +------------------------------------------------------------------------ |
| 889 | Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 890 | Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 891 | Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 892 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3. |
| 893 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 894 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0. |
| 895 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1. |
| 896 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1. |
| 897 | Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 898 | Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 899 | Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 900 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3. |
| 901 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 902 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0. |
| 903 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1. |
| 904 | Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1. |
| 905 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5. |
| 906 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1. |
| 907 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 908 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1. |
| 909 | Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 910 | Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 911 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5. |
| 912 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1. |
| 913 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 914 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1. |
| 915 | Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2) |
| 916 | Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 917 | Stat table ingress_port_counter is used by match table ingress_port_count_table. |
| 918 | Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x4. (previous value = 0x0 OR new value =0x4) |
| 919 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1. |
| 920 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0. |
| 921 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 922 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| 923 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| 924 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| 925 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| 926 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1. |
| 927 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| 928 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| 929 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1. |
| 930 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0. |
| 931 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 932 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1. |
| 933 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1. |
| 934 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1. |
| 935 | Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1. |
| 936 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1. |
| 937 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1. |
| 938 | Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1. |
| 939 | For counter width 32 and N = 4096 |
| 940 | number iterations = 32 |
| 941 | b_cur = 379488672.0 |
| 942 | eqn(b_cur) = 4294964039.26 |
| 943 | max_counter_value = 4294967295 |
| 944 | Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a. |
| 945 | Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff. |
| 946 | Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a. |
| 947 | Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff. |
| 948 | Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a. |
| 949 | Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff. |
| 950 | Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_entries_per_word to be 4. |
| 951 | Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_process_packets to be 1. |
| 952 | Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.lrt_enable to be 1. |
| 953 | TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_alu_error_enable to be 0. |
| 954 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0x0. |
| 955 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4. |
| 956 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1. |
| 957 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0. |
| 958 | Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0. |
| 959 | Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=2].stats_lrt_fsm_sweep_size to be 0x0. |
| 960 | Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=2].stats_lrt_fsm_sweep_offset to be 0x0. |
| 961 | Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=2].stats_lrt_sweep_adr to be 0x0. |
| 962 | Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0. |
| 963 | Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0. |
| 964 | Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=2].packet_action_at_headertime be 1. |
| 965 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_size be 3. |
| 966 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_lt be 0x0. |
| 967 | Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x6. ( previous value = 0x0 OR new value = 0x6) |
| 968 | Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=2].mau_ad_stats_virt_lt be 0x1. |
| 969 | |
| 970 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 971 | | Working on table egress_port_counter in stage 1 --- |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 972 | +------------------------------------------------------------------------ |
| 973 | Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 974 | Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 975 | Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 976 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3. |
| 977 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 978 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 1. |
| 979 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1. |
| 980 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1. |
| 981 | Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| 982 | Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| 983 | Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| 984 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3. |
| 985 | Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| 986 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 1. |
| 987 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1. |
| 988 | Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1. |
| 989 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5. |
| 990 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1. |
| 991 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 992 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1. |
| 993 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| 994 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 995 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5. |
| 996 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1. |
| 997 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1. |
| 998 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1. |
| 999 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2) |
| 1000 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| 1001 | Stat table egress_port_counter is used by match table egress_port_count_table. |
| 1002 | Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=1].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8) |
| 1003 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1. |
| 1004 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 1. |
| 1005 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 1006 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| 1007 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| 1008 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| 1009 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| 1010 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1. |
| 1011 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| 1012 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| 1013 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1. |
| 1014 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 1. |
| 1015 | Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| 1016 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1. |
| 1017 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1. |
| 1018 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1. |
| 1019 | Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1. |
| 1020 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1. |
| 1021 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1. |
| 1022 | Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1. |
| 1023 | For counter width 32 and N = 4096 |
| 1024 | number iterations = 32 |
| 1025 | b_cur = 379488672.0 |
| 1026 | eqn(b_cur) = 4294964039.26 |
| 1027 | max_counter_value = 4294967295 |
| 1028 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a. |
| 1029 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff. |
| 1030 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a. |
| 1031 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff. |
| 1032 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a. |
| 1033 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff. |
| 1034 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4. |
| 1035 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1. |
| 1036 | Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1. |
| 1037 | TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0. |
| 1038 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x1. |
| 1039 | Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_entries_per_word be 0x4. |
| 1040 | Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_has_packets be 0x1. |
| 1041 | Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_offset be 0x0. |
| 1042 | Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_size be 0x0. |
| 1043 | Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0. |
| 1044 | Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0. |
| 1045 | Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0. |
| 1046 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0. |
| 1047 | Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0. |
| 1048 | Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1. |
| 1049 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3. |
| 1050 | Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x1. |
| 1051 | Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=3].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x3e. ( previous value = 0x6 OR new value = 0x38) |
| 1052 | Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x2. |
| 1053 | +------------------------------------------------------------------------ |
| 1054 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19. |
| 1055 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9. |
| 1056 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3. |
| 1057 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 1058 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 1059 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 1060 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1061 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1062 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1063 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1064 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 1065 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x3. |
| 1066 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 1067 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 1068 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x3. |
| 1069 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 1070 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 1071 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 1072 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 1073 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 1074 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 1075 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 1076 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 1077 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 1078 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 1079 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 1080 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 1081 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 1082 | -------------------------------------------- |
| 1083 | Configuration for unused statistics ALUs. |
| 1084 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 1085 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 1086 | +------------------------------------------------------------------------ |
| 1087 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| 1088 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| 1089 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1090 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf. |
| 1091 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf. |
| 1092 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1093 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| 1094 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| 1095 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1096 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 1097 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 1098 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 1099 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 1100 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 1101 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1102 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 1103 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 1104 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 1105 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 1106 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 1107 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 1108 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 1109 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 1110 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 1111 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 1112 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 1113 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 1114 | +------------------------------------------------------------------------ |
| 1115 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 1116 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 1117 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0. |
| 1118 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 1119 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 1120 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 1121 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 1122 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 1123 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1. |
| 1124 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2. |
| 1125 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 1126 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 1127 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 1128 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 1129 | |
| 1130 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1131 | | MAU Stage 2 |
| 1132 | +------------------------------------------------------------------------ |
| 1133 | +------------------------------------------------------------------------ |
| 1134 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 1135 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 1136 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 1137 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 1138 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 1139 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 1140 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1141 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1142 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1143 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1144 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 1145 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 1146 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 1147 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 1148 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 1149 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 1150 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 1151 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 1152 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 1153 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 1154 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 1155 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 1156 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 1157 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 1158 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 1159 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 1160 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 1161 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 1162 | -------------------------------------------- |
| 1163 | Configuration for unused statistics ALUs. |
| 1164 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 1165 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 1166 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 1167 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 1168 | +------------------------------------------------------------------------ |
| 1169 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| 1170 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| 1171 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| 1172 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf. |
| 1173 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf. |
| 1174 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf. |
| 1175 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| 1176 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| 1177 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| 1178 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 1179 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 1180 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 1181 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 1182 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 1183 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| 1184 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 1185 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 1186 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 1187 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 1188 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 1189 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 1190 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 1191 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 1192 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 1193 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 1194 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 1195 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 1196 | +------------------------------------------------------------------------ |
| 1197 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 1198 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 1199 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 1200 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 1201 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 1202 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 1203 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 1204 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 1205 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 1206 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 1207 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 1208 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 1209 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 1210 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 1211 | |
| 1212 | +------------------------------------------------------------------------ |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1213 | | MAU Stage 3 |
| 1214 | +------------------------------------------------------------------------ |
| 1215 | +------------------------------------------------------------------------ |
| 1216 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 1217 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 1218 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 1219 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 1220 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 1221 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 1222 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1223 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1224 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1225 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1226 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 1227 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 1228 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 1229 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 1230 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 1231 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 1232 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 1233 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 1234 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 1235 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 1236 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 1237 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 1238 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 1239 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 1240 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 1241 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 1242 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 1243 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 1244 | -------------------------------------------- |
| 1245 | Configuration for unused statistics ALUs. |
| 1246 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 1247 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 1248 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 1249 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 1250 | +------------------------------------------------------------------------ |
| 1251 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| 1252 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| 1253 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1254 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf. |
| 1255 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf. |
| 1256 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1257 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| 1258 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| 1259 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1260 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 1261 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 1262 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 1263 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 1264 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 1265 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1266 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 1267 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 1268 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 1269 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 1270 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 1271 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 1272 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 1273 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 1274 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 1275 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 1276 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 1277 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 1278 | +------------------------------------------------------------------------ |
| 1279 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 1280 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 1281 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 1282 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 1283 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 1284 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 1285 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 1286 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 1287 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 1288 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 1289 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 1290 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 1291 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 1292 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 1293 | |
| 1294 | +------------------------------------------------------------------------ |
| 1295 | | MAU Stage 4 |
| 1296 | +------------------------------------------------------------------------ |
| 1297 | +------------------------------------------------------------------------ |
| 1298 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 1299 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 1300 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 1301 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 1302 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 1303 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 1304 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1305 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1306 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1307 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1308 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 1309 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 1310 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 1311 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 1312 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 1313 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 1314 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 1315 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 1316 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 1317 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 1318 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 1319 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 1320 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 1321 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 1322 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 1323 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 1324 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 1325 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 1326 | -------------------------------------------- |
| 1327 | Configuration for unused statistics ALUs. |
| 1328 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 1329 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 1330 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 1331 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 1332 | +------------------------------------------------------------------------ |
| 1333 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| 1334 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| 1335 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1336 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf. |
| 1337 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf. |
| 1338 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1339 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| 1340 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| 1341 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1342 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 1343 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 1344 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 1345 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 1346 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 1347 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1348 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 1349 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 1350 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 1351 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 1352 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 1353 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 1354 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 1355 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 1356 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 1357 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 1358 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 1359 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 1360 | +------------------------------------------------------------------------ |
| 1361 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 1362 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 1363 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 1364 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 1365 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 1366 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 1367 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 1368 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 1369 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 1370 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 1371 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 1372 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 1373 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 1374 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 1375 | |
| 1376 | +------------------------------------------------------------------------ |
| 1377 | | MAU Stage 5 |
| 1378 | +------------------------------------------------------------------------ |
| 1379 | +------------------------------------------------------------------------ |
| 1380 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 1381 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 1382 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 1383 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 1384 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 1385 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 1386 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1387 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1388 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1389 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1390 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 1391 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 1392 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 1393 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 1394 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 1395 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 1396 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 1397 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 1398 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 1399 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19. |
| 1400 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 1401 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 1402 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19. |
| 1403 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 1404 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 1405 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 1406 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 1407 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 1408 | -------------------------------------------- |
| 1409 | Configuration for unused statistics ALUs. |
| 1410 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 1411 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 1412 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 1413 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 1414 | +------------------------------------------------------------------------ |
| 1415 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| 1416 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| 1417 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1418 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf. |
| 1419 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf. |
| 1420 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1421 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| 1422 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| 1423 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1424 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 1425 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 1426 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 1427 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 1428 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 1429 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1430 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 1431 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 1432 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 1433 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 1434 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 1435 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 1436 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 1437 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 1438 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 1439 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 1440 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 1441 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 1442 | +------------------------------------------------------------------------ |
| 1443 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 1444 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 1445 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 1446 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0. |
| 1447 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 1448 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 1449 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 1450 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0. |
| 1451 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 1452 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 1453 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 1454 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 1455 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 1456 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 1457 | |
| 1458 | +------------------------------------------------------------------------ |
| 1459 | | MAU Stage 6 |
| 1460 | +------------------------------------------------------------------------ |
| 1461 | +------------------------------------------------------------------------ |
| 1462 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19. |
| 1463 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9. |
| 1464 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3. |
| 1465 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 19. |
| 1466 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 9. |
| 1467 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 3. |
| 1468 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1469 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1470 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1471 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1472 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 1473 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 1474 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 1475 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 1476 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 1477 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 1478 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 1479 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 1480 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 1481 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 1482 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 1483 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 1484 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 1485 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 1486 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 1487 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 1488 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 1489 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 1490 | -------------------------------------------- |
| 1491 | Configuration for unused statistics ALUs. |
| 1492 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 1493 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 1494 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 1495 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 1496 | +------------------------------------------------------------------------ |
| 1497 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| 1498 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| 1499 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1500 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf. |
| 1501 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf. |
| 1502 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1503 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| 1504 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| 1505 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1506 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 1507 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 1508 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 1509 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 1510 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 1511 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1512 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 1513 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 1514 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 1515 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 1516 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 1517 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 1518 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 1519 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 1520 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 1521 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 1522 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 1523 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 1524 | +------------------------------------------------------------------------ |
| 1525 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 1526 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 1527 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0. |
| 1528 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 1529 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 1530 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 1531 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0. |
| 1532 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 1533 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 3. |
| 1534 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0. |
| 1535 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 1536 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 1537 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 1538 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 1539 | |
| 1540 | +------------------------------------------------------------------------ |
| 1541 | | MAU Stage 7 |
| 1542 | +------------------------------------------------------------------------ |
| 1543 | +------------------------------------------------------------------------ |
| 1544 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 1545 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 1546 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 1547 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 1548 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 1549 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 1550 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1551 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1552 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1553 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1554 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 1555 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 1556 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 1557 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 1558 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 1559 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 1560 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 1561 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 1562 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 1563 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 1564 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 1565 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 1566 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 1567 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 1568 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 1569 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 1570 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 1571 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 1572 | -------------------------------------------- |
| 1573 | Configuration for unused statistics ALUs. |
| 1574 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 1575 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 1576 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 1577 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 1578 | +------------------------------------------------------------------------ |
| 1579 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| 1580 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| 1581 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1582 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf. |
| 1583 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf. |
| 1584 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1585 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| 1586 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| 1587 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1588 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 1589 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 1590 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 1591 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 1592 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 1593 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1594 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 1595 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 1596 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 1597 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 1598 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 1599 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 1600 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 1601 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 1602 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 1603 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 1604 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 1605 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 1606 | +------------------------------------------------------------------------ |
| 1607 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 1608 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 1609 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 1610 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 1611 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 1612 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 1613 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 1614 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 1615 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 1616 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 1617 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 1618 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 1619 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 1620 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 1621 | |
| 1622 | +------------------------------------------------------------------------ |
| 1623 | | MAU Stage 8 |
| 1624 | +------------------------------------------------------------------------ |
| 1625 | +------------------------------------------------------------------------ |
| 1626 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 1627 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 1628 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 1629 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 1630 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 1631 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 1632 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1633 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1634 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1635 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1636 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 1637 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 1638 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 1639 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 1640 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 1641 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 1642 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 1643 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 1644 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 1645 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 1646 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 1647 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 1648 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 1649 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 1650 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 1651 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 1652 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 1653 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 1654 | -------------------------------------------- |
| 1655 | Configuration for unused statistics ALUs. |
| 1656 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 1657 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 1658 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 1659 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 1660 | +------------------------------------------------------------------------ |
| 1661 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| 1662 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| 1663 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1664 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf. |
| 1665 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf. |
| 1666 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1667 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| 1668 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| 1669 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1670 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 1671 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 1672 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 1673 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 1674 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 1675 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1676 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 1677 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 1678 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 1679 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 1680 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 1681 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 1682 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 1683 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 1684 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 1685 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 1686 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 1687 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 1688 | +------------------------------------------------------------------------ |
| 1689 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 1690 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 1691 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 1692 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 1693 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 1694 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 1695 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 1696 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 1697 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 1698 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 1699 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 1700 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 1701 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 1702 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 1703 | |
| 1704 | +------------------------------------------------------------------------ |
| 1705 | | MAU Stage 9 |
| 1706 | +------------------------------------------------------------------------ |
| 1707 | +------------------------------------------------------------------------ |
| 1708 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 1709 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 1710 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 1711 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 1712 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 1713 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 1714 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1715 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1716 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1717 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1718 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 1719 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 1720 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 1721 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 1722 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 1723 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 1724 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 1725 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 1726 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 1727 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 1728 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 1729 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 1730 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 1731 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 1732 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 1733 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 1734 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 1735 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 1736 | -------------------------------------------- |
| 1737 | Configuration for unused statistics ALUs. |
| 1738 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 1739 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 1740 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 1741 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 1742 | +------------------------------------------------------------------------ |
| 1743 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| 1744 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| 1745 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1746 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf. |
| 1747 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf. |
| 1748 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1749 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| 1750 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| 1751 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1752 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 1753 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 1754 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 1755 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 1756 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 1757 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1758 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 1759 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 1760 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 1761 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 1762 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 1763 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 1764 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 1765 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 1766 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 1767 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 1768 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 1769 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 1770 | +------------------------------------------------------------------------ |
| 1771 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 1772 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 1773 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 1774 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 1775 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 1776 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 1777 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 1778 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 1779 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 1780 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 1781 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 1782 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 1783 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 1784 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 1785 | |
| 1786 | +------------------------------------------------------------------------ |
| 1787 | | MAU Stage 10 |
| 1788 | +------------------------------------------------------------------------ |
| 1789 | +------------------------------------------------------------------------ |
| 1790 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 1791 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 1792 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 1793 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 1794 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 1795 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 1796 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1797 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1798 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1799 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1800 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 1801 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 1802 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 1803 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 1804 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 1805 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 1806 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 1807 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 1808 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 1809 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| 1810 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 1811 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 1812 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| 1813 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 1814 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 1815 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 1816 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 1817 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 1818 | -------------------------------------------- |
| 1819 | Configuration for unused statistics ALUs. |
| 1820 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 1821 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 1822 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 1823 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 1824 | +------------------------------------------------------------------------ |
| 1825 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| 1826 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| 1827 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1828 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf. |
| 1829 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf. |
| 1830 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1831 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| 1832 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| 1833 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1834 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 1835 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 1836 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 1837 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 1838 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 1839 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1840 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 1841 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 1842 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 1843 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 1844 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 1845 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 1846 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 1847 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 1848 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 1849 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 1850 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 1851 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 1852 | +------------------------------------------------------------------------ |
| 1853 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 1854 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 1855 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 1856 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| 1857 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 1858 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 1859 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 1860 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| 1861 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 1862 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 1863 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 1864 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 1865 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 1866 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 1867 | |
| 1868 | +------------------------------------------------------------------------ |
| 1869 | | MAU Stage 11 |
| 1870 | +------------------------------------------------------------------------ |
| 1871 | +------------------------------------------------------------------------ |
| 1872 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| 1873 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| 1874 | Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| 1875 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| 1876 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| 1877 | Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| 1878 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1879 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1880 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| 1881 | Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| 1882 | Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| 1883 | Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| 1884 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| 1885 | Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| 1886 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| 1887 | Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| 1888 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| 1889 | Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| 1890 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| 1891 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19. |
| 1892 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| 1893 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| 1894 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19. |
| 1895 | Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| 1896 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| 1897 | Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| 1898 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| 1899 | Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| 1900 | -------------------------------------------- |
| 1901 | Configuration for unused statistics ALUs. |
| 1902 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| 1903 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| 1904 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| 1905 | Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| 1906 | +------------------------------------------------------------------------ |
| 1907 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| 1908 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| 1909 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1910 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0xf. |
| 1911 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0xf. |
| 1912 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0xf. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1913 | Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| 1914 | Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| 1915 | Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1916 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3. |
| 1917 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3. |
| 1918 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3. |
| 1919 | Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1. |
| 1920 | Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1. |
| 1921 | Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1. |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1922 | Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| 1923 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| 1924 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| 1925 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| 1926 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| 1927 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| 1928 | Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| 1929 | Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| 1930 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| 1931 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| 1932 | Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| 1933 | Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| 1934 | +------------------------------------------------------------------------ |
| 1935 | Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| 1936 | Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| 1937 | Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| 1938 | Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0. |
| 1939 | Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| 1940 | Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| 1941 | Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| 1942 | Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0. |
| 1943 | Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| 1944 | Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| 1945 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| 1946 | Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| 1947 | Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| 1948 | Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| 1949 | |
| 1950 | +------------------------------------------------------------------------ |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1951 | | Number of configuration field values set in Match-Action Stages: 1567 |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1952 | +------------------------------------------------------------------------ |
| 1953 | |
| 1954 | +------------------------------------------------------------------------ |
| 1955 | | MAU Feature Characteristics: |
| 1956 | +------------------------------------------------------------------------ |
| 1957 | |
| 1958 | |
| 1959 | Features per Stage for ingress: |
| 1960 | ----------------------------------------------------------------------------------------------- |
| 1961 | | Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency | |
| 1962 | | | | | | LPF | (max words) | | to Previous | |
| 1963 | ----------------------------------------------------------------------------------------------- |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1964 | | 0 | Yes | Yes | Yes | No | No (0) | No | match | |
| 1965 | | 1 | Yes | No | Yes | No | No (0) | No | match | |
| 1966 | | 2 | Yes* | No | Yes* | No | No (0) | No | concurrent | |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1967 | | 3 | Yes* | No | Yes* | No | No (0) | No | concurrent | |
| 1968 | | 4 | Yes* | No | Yes* | No | No (0) | No | concurrent | |
| 1969 | | 5 | Yes* | No | Yes* | No | No (0) | No | concurrent | |
| 1970 | | 6 | No | No | No | No | No (0) | No | match | |
| 1971 | | 7 | No | No | No | No | No (0) | No | concurrent | |
| 1972 | | 8 | No | No | No | No | No (0) | No | concurrent | |
| 1973 | | 9 | No | No | No | No | No (0) | No | concurrent | |
| 1974 | | 10 | No | No | No | No | No (0) | No | concurrent | |
| 1975 | | 11 | No | No | No | No | No (0) | No | concurrent | |
| 1976 | ----------------------------------------------------------------------------------------------- |
| 1977 | |
| 1978 | A '*' denotes that this feature was added to balance an action/concurrent chain. |
| 1979 | |
| 1980 | |
| 1981 | Features per Stage for egress: |
| 1982 | ----------------------------------------------------------------------------------------------- |
| 1983 | | Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency | |
| 1984 | | | | | | LPF | (max words) | | to Previous | |
| 1985 | ----------------------------------------------------------------------------------------------- |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 1986 | | 0 | No | No | No | No | No (0) | No | match | |
| 1987 | | 1 | No | No | No | No | No (0) | No | concurrent | |
| 1988 | | 2 | No | No | No | No | No (0) | No | concurrent | |
| 1989 | | 3 | No | No | No | No | No (0) | No | concurrent | |
| 1990 | | 4 | No | No | No | No | No (0) | No | concurrent | |
| 1991 | | 5 | No | No | No | No | No (0) | No | concurrent | |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1992 | | 6 | No | No | No | No | No (0) | No | match | |
| 1993 | | 7 | No | No | No | No | No (0) | No | concurrent | |
| 1994 | | 8 | No | No | No | No | No (0) | No | concurrent | |
| 1995 | | 9 | No | No | No | No | No (0) | No | concurrent | |
| 1996 | | 10 | No | No | No | No | No (0) | No | concurrent | |
| 1997 | | 11 | No | No | No | No | No (0) | No | concurrent | |
| 1998 | ----------------------------------------------------------------------------------------------- |
| 1999 | |
| 2000 | A '*' denotes that this feature was added to balance an action/concurrent chain. |
| 2001 | |
| 2002 | +------------------------------------------------------------------------ |
| 2003 | | MAU Latency Characteristics: |
| 2004 | +------------------------------------------------------------------------ |
| 2005 | |
| 2006 | |
| 2007 | Clock Cycles Per Stage For ingress: |
| 2008 | ----------------------------------------------------------------------------------------------------- |
| 2009 | | Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency | |
| 2010 | ----------------------------------------------------------------------------------------------------- |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 2011 | | 0 | 22 | 13 | match | 22 | |
| 2012 | | 1 | 20 | 11 | match | 20 | |
| 2013 | | 2 | 20 | 11 | concurrent | 1 | |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 2014 | | 3 | 20 | 11 | concurrent | 1 | |
| 2015 | | 4 | 20 | 11 | concurrent | 1 | |
| 2016 | | 5 | 20 | 11 | concurrent | 1 | |
| 2017 | | 6 | 20 | 11 | match | 20 | |
| 2018 | | 7 | 20 | 11 | concurrent | 1 | |
| 2019 | | 8 | 20 | 11 | concurrent | 1 | |
| 2020 | | 9 | 20 | 11 | concurrent | 1 | |
| 2021 | | 10 | 20 | 11 | concurrent | 1 | |
| 2022 | | 11 | 20 | 11 | concurrent | 1 | |
| 2023 | ----------------------------------------------------------------------------------------------------- |
| 2024 | |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame^] | 2025 | Total latency for ingress: 75 |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 2026 | |
| 2027 | |
| 2028 | Clock Cycles Per Stage For egress: |
| 2029 | ----------------------------------------------------------------------------------------------------- |
| 2030 | | Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency | |
| 2031 | ----------------------------------------------------------------------------------------------------- |
| 2032 | | 0 | 20 | 11 | match | 20 | |
| 2033 | | 1 | 20 | 11 | concurrent | 1 | |
| 2034 | | 2 | 20 | 11 | concurrent | 1 | |
| 2035 | | 3 | 20 | 11 | concurrent | 1 | |
| 2036 | | 4 | 20 | 11 | concurrent | 1 | |
| 2037 | | 5 | 20 | 11 | concurrent | 1 | |
| 2038 | | 6 | 20 | 11 | match | 20 | |
| 2039 | | 7 | 20 | 11 | concurrent | 1 | |
| 2040 | | 8 | 20 | 11 | concurrent | 1 | |
| 2041 | | 9 | 20 | 11 | concurrent | 1 | |
| 2042 | | 10 | 20 | 11 | concurrent | 1 | |
| 2043 | | 11 | 20 | 11 | concurrent | 1 | |
| 2044 | ----------------------------------------------------------------------------------------------------- |
| 2045 | |
| 2046 | Total latency for egress: 54 |