blob: 5eae9b3c3abb0a845c9ba042e3730cc1defeefbb [file] [log] [blame]
Carmelo Casconef1d0a422017-09-07 17:21:46 +02001+---------------------------------------------------------------------+
2| Log file: mau.resources.log |
3| Compiler version: 5.1.0 (fca32d1) |
4| Created on: Thu Sep 7 14:48:49 2017 |
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9| Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
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11| 0 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |
12| 1 | 13 | 16 | 2 | 1 | 1 | 4 | 3 | 3 | 3 | 0 | 1 | 0 | 8 | 0 | 4 | 2 | 1 |
13| 2 | 4 | 0 | 30 | 0 | 0 | 5 | 2 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 2 | 1 | 1 |
14| 3 | 2 | 0 | 9 | 0 | 2 | 4 | 4 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 |
15| 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
16| 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
17| 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
18| 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
19| 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
20| 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
21| 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
22| 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
23| | | | | | | | | | | | | | | | | | |
24| Totals | 21 | 16 | 43 | 1 | 5 | 13 | 9 | 3 | 6 | 0 | 4 | 0 | 12 | 0 | 6 | 3 | 6 |
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29| Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
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31| 0 | 1.56% | 0.00% | 0.48% | 0.00% | 12.50% | 0.00% | 0.00% | 0.00% | 3.12% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% |
32| 1 | 10.16% | 24.24% | 0.48% | 16.67% | 6.25% | 5.00% | 6.25% | 12.50% | 9.38% | 0.00% | 25.00% | 0.00% | 6.25% | 0.00% | 12.50% | 6.25% | 6.25% |
33| 2 | 3.12% | 0.00% | 7.21% | 0.00% | 0.00% | 6.25% | 4.17% | 0.00% | 3.12% | 0.00% | 25.00% | 0.00% | 3.12% | 0.00% | 6.25% | 3.12% | 6.25% |
34| 3 | 1.56% | 0.00% | 2.16% | 0.00% | 12.50% | 5.00% | 8.33% | 0.00% | 3.12% | 0.00% | 50.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% |
35| 4 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
36| 5 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
37| 6 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
38| 7 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
39| 8 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
40| 9 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
41| 10 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
42| 11 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
43| | | | | | | | | | | | | | | | | | |
44| Average | 1.37% | 2.02% | 0.86% | 1.39% | 2.60% | 1.35% | 1.56% | 1.04% | 1.56% | 0.00% | 8.33% | 0.00% | 0.78% | 0.00% | 1.56% | 0.78% | 3.12% |
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46
47
48Allocated Resource Usage
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50| Table | Stage | Crossbar | Hash | Gateways | RAMs | TCAMs | Map | Action | VLIW |
51| Name | Number | Bytes | Bits | | | | RAMs | Data | Slots |
52| | | | | | | | | Bus | |
53| | | | | | | | | Bytes | |
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55| _condition_0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
56| _condition_3 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
57| ingress_pkt__action__ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
58| ingress_pkt | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
59| egress_pkt__action__ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
60| egress_pkt | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
61| _condition_1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
62| table0__action__ | 1 | 12 | 1 | 0 | 1 | 0 | 0 | 8 | 0 |
63| table0 | 1 | 16 | 0 | 0 | 1 | 3 | 1 | 0 | 4 |
64| table0_counter | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
65| ecmp_group_table__action__ | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 |
66| ecmp_group_table | 2 | 4 | 30 | 0 | 3 | 0 | 0 | 0 | 1 |
67| ecmp_group_table_counter | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
68| _condition_2 | 3 | 2 | 9 | 1 | 0 | 0 | 0 | 0 | 0 |
69| ingress_port_count_table__action__ | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
70| ingress_port_count_table | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
71| egress_port_count_table__action__ | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
72| egress_port_count_table | 3 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
73| ingress_port_counter | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
74| egress_port_counter | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
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