Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame^] | 1 | +---------------------------------------------------------------------+ |
| 2 | | Log file: mau.sram.log | |
| 3 | | Compiler version: 5.1.0 (fca32d1) | |
| 4 | | Created on: Thu Sep 7 13:56:53 2017 | |
| 5 | +---------------------------------------------------------------------+ |
| 6 | |
| 7 | |
| 8 | |
| 9 | ======================================================= |
| 10 | |
| 11 | calling allocate and add with SRAM Resource Request for table ingress_pkt (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 12 | ======================================================= |
| 13 | |
| 14 | Requesting to use 0 RAMs and have 80 available. |
| 15 | Requesting to use 0 Map RAMs and have 48 available. |
| 16 | |
| 17 | ======================================================== |
| 18 | Run Placement on Request List of size 1 in stage 0 |
| 19 | open_up_all_for_match=False |
| 20 | synth_two_port_first=False |
| 21 | ======================================================== |
| 22 | |
| 23 | Match Rams Need is 0 |
| 24 | Algorithmic TCAM Match RAMs Need is 0 |
| 25 | Other Rams Need is 0 |
| 26 | |
| 27 | +========================================= |
| 28 | | Placing algorithmic tcam |
| 29 | +========================================= |
| 30 | |
| 31 | sorted algorithmic tcam requests: (0) |
| 32 | |
| 33 | |
| 34 | ------------------------------------- |
| 35 | Columns need for match is 0 |
| 36 | columns for width is 0 |
| 37 | other columns is 0 |
| 38 | reserved columns is 10 |
| 39 | reserved columns for tind 0 |
| 40 | reserved columns for stateful 0 |
| 41 | Ternary Indirection Rams Need is 0 |
| 42 | Depth sorted requested |
| 43 | Requesting to use 0 RAMs and have 32 available. |
| 44 | Result bus only needs (1): |
| 45 | ingress_pkt |
| 46 | Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 0 |
| 47 | |
| 48 | +========================================= |
| 49 | | Placing action/stats/meters/selection |
| 50 | +========================================= |
| 51 | |
| 52 | Requesting to use 0 RAMs and have 80 available. |
| 53 | Depth sorted idletime requests: |
| 54 | |
| 55 | |
| 56 | ======================================================= |
| 57 | |
| 58 | calling allocate and add with SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
| 59 | ======================================================= |
| 60 | |
| 61 | Requesting to use 2 RAMs and have 80 available. |
| 62 | Requesting to use 0 Map RAMs and have 48 available. |
| 63 | |
| 64 | ======================================================== |
| 65 | Run Placement on Request List of size 1 in stage 1 |
| 66 | open_up_all_for_match=False |
| 67 | synth_two_port_first=False |
| 68 | ======================================================== |
| 69 | |
| 70 | Match Rams Need is 0 |
| 71 | Algorithmic TCAM Match RAMs Need is 0 |
| 72 | Other Rams Need is 2 |
| 73 | |
| 74 | +========================================= |
| 75 | | Placing algorithmic tcam |
| 76 | +========================================= |
| 77 | |
| 78 | sorted algorithmic tcam requests: (0) |
| 79 | |
| 80 | |
| 81 | ------------------------------------- |
| 82 | Columns need for match is 0 |
| 83 | columns for width is 0 |
| 84 | other columns is 1 |
| 85 | reserved columns is 9 |
| 86 | reserved columns for tind 0 |
| 87 | reserved columns for stateful 1 |
| 88 | Ternary Indirection Rams Need is 0 |
| 89 | Depth sorted requested |
| 90 | Requesting to use 0 RAMs and have 32 available. |
| 91 | Result bus only needs (0): |
| 92 | |
| 93 | +========================================= |
| 94 | | Placing action/stats/meters/selection |
| 95 | +========================================= |
| 96 | |
| 97 | Requesting to use 2 RAMs and have 80 available. |
| 98 | SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 99 | NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 100 | |
| 101 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 102 | Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table table0_counter. |
| 103 | Allocating: SRAM: Row 6 Col 6 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 104 | Allocating: Map RAM: Row 6 Unit 0 in stage 1 for table0_counter. |
| 105 | Allocating: SRAM: Row 6 Col 7 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 106 | Allocating: Map RAM: Row 6 Unit 1 in stage 1 for table0_counter. |
| 107 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for table0_counter. |
| 108 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for table0_counter. |
| 109 | Depth sorted idletime requests: |
| 110 | |
| 111 | |
| 112 | ======================================================= |
| 113 | |
| 114 | calling allocate and add with SRAM Resource Request for table table0 (of type ternary_indirection), with 1 ways wants 1 rams. (open-all=False, synth_two_port_first=False) |
| 115 | ======================================================= |
| 116 | |
| 117 | Requesting to use 1 RAMs and have 78 available. |
| 118 | Requesting to use 0 Map RAMs and have 46 available. |
| 119 | |
| 120 | ======================================================== |
| 121 | Run Placement on Request List of size 2 in stage 1 |
| 122 | open_up_all_for_match=False |
| 123 | synth_two_port_first=False |
| 124 | ======================================================== |
| 125 | |
| 126 | Match Rams Need is 0 |
| 127 | Algorithmic TCAM Match RAMs Need is 0 |
| 128 | Other Rams Need is 3 |
| 129 | |
| 130 | +========================================= |
| 131 | | Placing algorithmic tcam |
| 132 | +========================================= |
| 133 | |
| 134 | sorted algorithmic tcam requests: (0) |
| 135 | |
| 136 | |
| 137 | ------------------------------------- |
| 138 | Columns need for match is 0 |
| 139 | columns for width is 0 |
| 140 | other columns is 1 |
| 141 | reserved columns is 9 |
| 142 | reserved columns for tind 1 |
| 143 | reserved columns for stateful 1 |
| 144 | Ternary Indirection Rams Need is 1 |
| 145 | Depth sorted requested |
| 146 | Group 0 |
| 147 | Sram Resource Request for P4 table table0 with handle 16777221 of type ternary_indirection in stage 1 |
| 148 | table_type : ternary_indirection |
| 149 | rams_for_width : 1 |
| 150 | use_stash : False |
| 151 | number_ways : 1 |
| 152 | way #0 |
| 153 | SRAM Request Group 0 |
| 154 | rams_for_depth : 1 |
| 155 | map_rams : 0 |
| 156 | way_number : 0 |
| 157 | ram_word_select_bits : 0 |
| 158 | ram_enable_select_bits : 0 |
| 159 | |
| 160 | Requesting to use 1 RAMs and have 32 available. |
| 161 | Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 1 |
| 162 | Allocating: SRAM: Row 0 Col 2 in stage 1 for table table0's ternary indirection word range Words 0 to 1023. |
| 163 | Result bus only needs (0): |
| 164 | |
| 165 | +========================================= |
| 166 | | Placing action/stats/meters/selection |
| 167 | +========================================= |
| 168 | |
| 169 | Requesting to use 2 RAMs and have 79 available. |
| 170 | SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 171 | NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 172 | |
| 173 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 174 | Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table table0_counter. |
| 175 | Allocating: SRAM: Row 6 Col 6 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 176 | Allocating: Map RAM: Row 6 Unit 0 in stage 1 for table0_counter. |
| 177 | Allocating: SRAM: Row 6 Col 7 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 178 | Allocating: Map RAM: Row 6 Unit 1 in stage 1 for table0_counter. |
| 179 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for table0_counter. |
| 180 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for table0_counter. |
| 181 | Depth sorted idletime requests: |
| 182 | |
| 183 | |
| 184 | ======================================================= |
| 185 | |
| 186 | calling allocate and add with SRAM Resource Request for table table0 (of type idletime), with 1 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 187 | ======================================================= |
| 188 | |
| 189 | Requesting to use 0 RAMs and have 77 available. |
| 190 | Requesting to use 1 Map RAMs and have 46 available. |
| 191 | |
| 192 | ======================================================== |
| 193 | Run Placement on Request List of size 3 in stage 1 |
| 194 | open_up_all_for_match=False |
| 195 | synth_two_port_first=False |
| 196 | ======================================================== |
| 197 | |
| 198 | Match Rams Need is 0 |
| 199 | Algorithmic TCAM Match RAMs Need is 0 |
| 200 | Other Rams Need is 3 |
| 201 | |
| 202 | +========================================= |
| 203 | | Placing algorithmic tcam |
| 204 | +========================================= |
| 205 | |
| 206 | sorted algorithmic tcam requests: (0) |
| 207 | |
| 208 | |
| 209 | ------------------------------------- |
| 210 | Columns need for match is 0 |
| 211 | columns for width is 0 |
| 212 | other columns is 1 |
| 213 | reserved columns is 9 |
| 214 | reserved columns for tind 1 |
| 215 | reserved columns for stateful 1 |
| 216 | Ternary Indirection Rams Need is 1 |
| 217 | Depth sorted requested |
| 218 | Group 0 |
| 219 | Sram Resource Request for P4 table table0 with handle 16777221 of type ternary_indirection in stage 1 |
| 220 | table_type : ternary_indirection |
| 221 | rams_for_width : 1 |
| 222 | use_stash : False |
| 223 | number_ways : 1 |
| 224 | way #0 |
| 225 | SRAM Request Group 0 |
| 226 | rams_for_depth : 1 |
| 227 | map_rams : 0 |
| 228 | way_number : 0 |
| 229 | ram_word_select_bits : 0 |
| 230 | ram_enable_select_bits : 0 |
| 231 | |
| 232 | Requesting to use 1 RAMs and have 32 available. |
| 233 | Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 1 |
| 234 | Allocating: SRAM: Row 0 Col 2 in stage 1 for table table0's ternary indirection word range Words 0 to 1023. |
| 235 | Result bus only needs (0): |
| 236 | |
| 237 | +========================================= |
| 238 | | Placing action/stats/meters/selection |
| 239 | +========================================= |
| 240 | |
| 241 | Requesting to use 2 RAMs and have 79 available. |
| 242 | SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 243 | NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 244 | |
| 245 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 246 | Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table table0_counter. |
| 247 | Allocating: SRAM: Row 6 Col 6 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 248 | Allocating: Map RAM: Row 6 Unit 0 in stage 1 for table0_counter. |
| 249 | Allocating: SRAM: Row 6 Col 7 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 250 | Allocating: Map RAM: Row 6 Unit 1 in stage 1 for table0_counter. |
| 251 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for table0_counter. |
| 252 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for table0_counter. |
| 253 | Depth sorted idletime requests: |
| 254 | Sram Resource Request for P4 table table0 with handle 16777221 of type idletime in stage 1 |
| 255 | table_type : idletime |
| 256 | rams_for_width : 0 |
| 257 | use_stash : False |
| 258 | number_ways : 1 |
| 259 | way #0 |
| 260 | SRAM Request Group 0 |
| 261 | rams_for_depth : 0 |
| 262 | map_rams : 1 |
| 263 | way_number : 0 |
| 264 | ram_word_select_bits : 0 |
| 265 | ram_enable_select_bits : 0 |
| 266 | |
| 267 | Requesting to use 1 RAMs and have 46 available. |
| 268 | top_cnt = 1 and num requests = 1 |
| 269 | bottom_cnt = 0 and num requests = 0 |
| 270 | Working on idletime request SRAM Resource Request for table table0 (of type idletime), with 1 ways wants 0 rams. |
| 271 | >> wants 1 map rams |
| 272 | Allocating: Map RAM: Row 7 Unit 0 in stage 1 for table0. |
| 273 | Allocating: Ram Data Bus IdletimeHalfLogicalRow 0 top is 19 bits in stage 1 for table0. |
| 274 | |
| 275 | |
| 276 | ======================================================= |
| 277 | |
| 278 | calling allocate and add with SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
| 279 | ======================================================= |
| 280 | |
| 281 | Requesting to use 2 RAMs and have 80 available. |
| 282 | Requesting to use 0 Map RAMs and have 48 available. |
| 283 | |
| 284 | ======================================================== |
| 285 | Run Placement on Request List of size 1 in stage 2 |
| 286 | open_up_all_for_match=False |
| 287 | synth_two_port_first=False |
| 288 | ======================================================== |
| 289 | |
| 290 | Match Rams Need is 0 |
| 291 | Algorithmic TCAM Match RAMs Need is 0 |
| 292 | Other Rams Need is 2 |
| 293 | |
| 294 | +========================================= |
| 295 | | Placing algorithmic tcam |
| 296 | +========================================= |
| 297 | |
| 298 | sorted algorithmic tcam requests: (0) |
| 299 | |
| 300 | |
| 301 | ------------------------------------- |
| 302 | Columns need for match is 0 |
| 303 | columns for width is 0 |
| 304 | other columns is 1 |
| 305 | reserved columns is 9 |
| 306 | reserved columns for tind 0 |
| 307 | reserved columns for stateful 1 |
| 308 | Ternary Indirection Rams Need is 0 |
| 309 | Depth sorted requested |
| 310 | Requesting to use 0 RAMs and have 32 available. |
| 311 | Result bus only needs (0): |
| 312 | |
| 313 | +========================================= |
| 314 | | Placing action/stats/meters/selection |
| 315 | +========================================= |
| 316 | |
| 317 | Requesting to use 2 RAMs and have 80 available. |
| 318 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 319 | NO Spill Required off of logical row 13 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 320 | |
| 321 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 322 | Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table ingress_port_counter. |
| 323 | Allocating: SRAM: Row 6 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 324 | Allocating: Map RAM: Row 6 Unit 0 in stage 2 for ingress_port_counter. |
| 325 | Allocating: SRAM: Row 6 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 326 | Allocating: Map RAM: Row 6 Unit 1 in stage 2 for ingress_port_counter. |
| 327 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for ingress_port_counter. |
| 328 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for ingress_port_counter. |
| 329 | Depth sorted idletime requests: |
| 330 | |
| 331 | |
| 332 | ======================================================= |
| 333 | |
| 334 | calling allocate and add with SRAM Resource Request for table ingress_port_count_table (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 335 | ======================================================= |
| 336 | |
| 337 | Requesting to use 0 RAMs and have 78 available. |
| 338 | Requesting to use 0 Map RAMs and have 46 available. |
| 339 | |
| 340 | ======================================================== |
| 341 | Run Placement on Request List of size 2 in stage 2 |
| 342 | open_up_all_for_match=False |
| 343 | synth_two_port_first=False |
| 344 | ======================================================== |
| 345 | |
| 346 | Match Rams Need is 0 |
| 347 | Algorithmic TCAM Match RAMs Need is 0 |
| 348 | Other Rams Need is 2 |
| 349 | |
| 350 | +========================================= |
| 351 | | Placing algorithmic tcam |
| 352 | +========================================= |
| 353 | |
| 354 | sorted algorithmic tcam requests: (0) |
| 355 | |
| 356 | |
| 357 | ------------------------------------- |
| 358 | Columns need for match is 0 |
| 359 | columns for width is 0 |
| 360 | other columns is 1 |
| 361 | reserved columns is 9 |
| 362 | reserved columns for tind 0 |
| 363 | reserved columns for stateful 1 |
| 364 | Ternary Indirection Rams Need is 0 |
| 365 | Depth sorted requested |
| 366 | Requesting to use 0 RAMs and have 32 available. |
| 367 | Result bus only needs (1): |
| 368 | ingress_port_count_table |
| 369 | Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 2 |
| 370 | |
| 371 | +========================================= |
| 372 | | Placing action/stats/meters/selection |
| 373 | +========================================= |
| 374 | |
| 375 | Requesting to use 2 RAMs and have 80 available. |
| 376 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 377 | NO Spill Required off of logical row 13 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 378 | |
| 379 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 380 | Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table ingress_port_counter. |
| 381 | Allocating: SRAM: Row 6 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 382 | Allocating: Map RAM: Row 6 Unit 0 in stage 2 for ingress_port_counter. |
| 383 | Allocating: SRAM: Row 6 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 384 | Allocating: Map RAM: Row 6 Unit 1 in stage 2 for ingress_port_counter. |
| 385 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for ingress_port_counter. |
| 386 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for ingress_port_counter. |
| 387 | Depth sorted idletime requests: |
| 388 | |
| 389 | |
| 390 | ======================================================= |
| 391 | |
| 392 | calling allocate and add with SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
| 393 | ======================================================= |
| 394 | |
| 395 | Requesting to use 2 RAMs and have 78 available. |
| 396 | Requesting to use 0 Map RAMs and have 46 available. |
| 397 | |
| 398 | ======================================================== |
| 399 | Run Placement on Request List of size 3 in stage 2 |
| 400 | open_up_all_for_match=False |
| 401 | synth_two_port_first=False |
| 402 | ======================================================== |
| 403 | |
| 404 | Match Rams Need is 0 |
| 405 | Algorithmic TCAM Match RAMs Need is 0 |
| 406 | Other Rams Need is 4 |
| 407 | |
| 408 | +========================================= |
| 409 | | Placing algorithmic tcam |
| 410 | +========================================= |
| 411 | |
| 412 | sorted algorithmic tcam requests: (0) |
| 413 | |
| 414 | |
| 415 | ------------------------------------- |
| 416 | Columns need for match is 0 |
| 417 | columns for width is 0 |
| 418 | other columns is 1 |
| 419 | reserved columns is 9 |
| 420 | reserved columns for tind 0 |
| 421 | reserved columns for stateful 1 |
| 422 | Ternary Indirection Rams Need is 0 |
| 423 | Depth sorted requested |
| 424 | Requesting to use 0 RAMs and have 32 available. |
| 425 | Result bus only needs (1): |
| 426 | ingress_port_count_table |
| 427 | Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 2 |
| 428 | |
| 429 | +========================================= |
| 430 | | Placing action/stats/meters/selection |
| 431 | +========================================= |
| 432 | |
| 433 | Requesting to use 4 RAMs and have 80 available. |
| 434 | SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 435 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 436 | NO Spill Required off of logical row 13 for SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 437 | |
| 438 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 439 | Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table egress_port_counter. |
| 440 | Allocating: SRAM: Row 6 Col 6 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 441 | Allocating: Map RAM: Row 6 Unit 0 in stage 2 for egress_port_counter. |
| 442 | Allocating: SRAM: Row 6 Col 7 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 443 | Allocating: Map RAM: Row 6 Unit 1 in stage 2 for egress_port_counter. |
| 444 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for egress_port_counter. |
| 445 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for egress_port_counter. |
| 446 | NO Spill Required off of logical row 9 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 447 | |
| 448 | call to place_table_on_logical_row --- logical row 9 and rams to place is 2 and depth index is 0 |
| 449 | Allocating: Statistics ALU 4 on right (128 bits) in stage 2 for table ingress_port_counter. |
| 450 | Allocating: SRAM: Row 4 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 451 | Allocating: Map RAM: Row 4 Unit 0 in stage 2 for ingress_port_counter. |
| 452 | Allocating: SRAM: Row 4 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 453 | Allocating: Map RAM: Row 4 Unit 1 in stage 2 for ingress_port_counter. |
| 454 | Allocating: Ram Data Bus StatsR 4 right is 128 bits in stage 2 for ingress_port_counter. |
| 455 | Allocating: Ram Data Bus StatsW 4 right is 128 bits in stage 2 for ingress_port_counter. |
| 456 | Depth sorted idletime requests: |
| 457 | |
| 458 | |
| 459 | ======================================================= |
| 460 | |
| 461 | calling allocate and add with SRAM Resource Request for table egress_port_count_table (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 462 | ======================================================= |
| 463 | |
| 464 | Requesting to use 0 RAMs and have 76 available. |
| 465 | Requesting to use 0 Map RAMs and have 44 available. |
| 466 | |
| 467 | ======================================================== |
| 468 | Run Placement on Request List of size 4 in stage 2 |
| 469 | open_up_all_for_match=False |
| 470 | synth_two_port_first=False |
| 471 | ======================================================== |
| 472 | |
| 473 | Match Rams Need is 0 |
| 474 | Algorithmic TCAM Match RAMs Need is 0 |
| 475 | Other Rams Need is 4 |
| 476 | |
| 477 | +========================================= |
| 478 | | Placing algorithmic tcam |
| 479 | +========================================= |
| 480 | |
| 481 | sorted algorithmic tcam requests: (0) |
| 482 | |
| 483 | |
| 484 | ------------------------------------- |
| 485 | Columns need for match is 0 |
| 486 | columns for width is 0 |
| 487 | other columns is 1 |
| 488 | reserved columns is 9 |
| 489 | reserved columns for tind 0 |
| 490 | reserved columns for stateful 1 |
| 491 | Ternary Indirection Rams Need is 0 |
| 492 | Depth sorted requested |
| 493 | Requesting to use 0 RAMs and have 32 available. |
| 494 | Result bus only needs (2): |
| 495 | egress_port_count_table |
| 496 | ingress_port_count_table |
| 497 | Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 2 |
| 498 | Allocating: Ram Data Bus MatchResult2R 0 left_and_right is 83 bits in stage 2 |
| 499 | |
| 500 | +========================================= |
| 501 | | Placing action/stats/meters/selection |
| 502 | +========================================= |
| 503 | |
| 504 | Requesting to use 4 RAMs and have 80 available. |
| 505 | SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 506 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 507 | NO Spill Required off of logical row 13 for SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 508 | |
| 509 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 510 | Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table egress_port_counter. |
| 511 | Allocating: SRAM: Row 6 Col 6 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 512 | Allocating: Map RAM: Row 6 Unit 0 in stage 2 for egress_port_counter. |
| 513 | Allocating: SRAM: Row 6 Col 7 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 514 | Allocating: Map RAM: Row 6 Unit 1 in stage 2 for egress_port_counter. |
| 515 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for egress_port_counter. |
| 516 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for egress_port_counter. |
| 517 | NO Spill Required off of logical row 9 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 518 | |
| 519 | call to place_table_on_logical_row --- logical row 9 and rams to place is 2 and depth index is 0 |
| 520 | Allocating: Statistics ALU 4 on right (128 bits) in stage 2 for table ingress_port_counter. |
| 521 | Allocating: SRAM: Row 4 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 522 | Allocating: Map RAM: Row 4 Unit 0 in stage 2 for ingress_port_counter. |
| 523 | Allocating: SRAM: Row 4 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 524 | Allocating: Map RAM: Row 4 Unit 1 in stage 2 for ingress_port_counter. |
| 525 | Allocating: Ram Data Bus StatsR 4 right is 128 bits in stage 2 for ingress_port_counter. |
| 526 | Allocating: Ram Data Bus StatsW 4 right is 128 bits in stage 2 for ingress_port_counter. |
| 527 | Depth sorted idletime requests: |
| 528 | |
| 529 | |
| 530 | ======================================================= |
| 531 | |
| 532 | calling allocate and add with SRAM Resource Request for table egress_pkt (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 533 | ======================================================= |
| 534 | |
| 535 | Requesting to use 0 RAMs and have 80 available. |
| 536 | Requesting to use 0 Map RAMs and have 48 available. |
| 537 | |
| 538 | ======================================================== |
| 539 | Run Placement on Request List of size 2 in stage 0 |
| 540 | open_up_all_for_match=False |
| 541 | synth_two_port_first=False |
| 542 | ======================================================== |
| 543 | |
| 544 | Match Rams Need is 0 |
| 545 | Algorithmic TCAM Match RAMs Need is 0 |
| 546 | Other Rams Need is 0 |
| 547 | |
| 548 | +========================================= |
| 549 | | Placing algorithmic tcam |
| 550 | +========================================= |
| 551 | |
| 552 | sorted algorithmic tcam requests: (0) |
| 553 | |
| 554 | |
| 555 | ------------------------------------- |
| 556 | Columns need for match is 0 |
| 557 | columns for width is 0 |
| 558 | other columns is 0 |
| 559 | reserved columns is 10 |
| 560 | reserved columns for tind 0 |
| 561 | reserved columns for stateful 0 |
| 562 | Ternary Indirection Rams Need is 0 |
| 563 | Depth sorted requested |
| 564 | Requesting to use 0 RAMs and have 32 available. |
| 565 | Result bus only needs (2): |
| 566 | egress_pkt |
| 567 | ingress_pkt |
| 568 | Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 0 |
| 569 | Allocating: Ram Data Bus MatchResult2R 0 left_and_right is 83 bits in stage 0 |
| 570 | |
| 571 | +========================================= |
| 572 | | Placing action/stats/meters/selection |
| 573 | +========================================= |
| 574 | |
| 575 | Requesting to use 0 RAMs and have 80 available. |
| 576 | Depth sorted idletime requests: |