| +---------------------------------------------------------------------+ |
| | Log file: mau.sram.log | |
| | Compiler version: 5.1.0 (fca32d1) | |
| | Created on: Thu Sep 7 13:56:53 2017 | |
| +---------------------------------------------------------------------+ |
| |
| |
| |
| ======================================================= |
| |
| calling allocate and add with SRAM Resource Request for table ingress_pkt (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| ======================================================= |
| |
| Requesting to use 0 RAMs and have 80 available. |
| Requesting to use 0 Map RAMs and have 48 available. |
| |
| ======================================================== |
| Run Placement on Request List of size 1 in stage 0 |
| open_up_all_for_match=False |
| synth_two_port_first=False |
| ======================================================== |
| |
| Match Rams Need is 0 |
| Algorithmic TCAM Match RAMs Need is 0 |
| Other Rams Need is 0 |
| |
| +========================================= |
| | Placing algorithmic tcam |
| +========================================= |
| |
| sorted algorithmic tcam requests: (0) |
| |
| |
| ------------------------------------- |
| Columns need for match is 0 |
| columns for width is 0 |
| other columns is 0 |
| reserved columns is 10 |
| reserved columns for tind 0 |
| reserved columns for stateful 0 |
| Ternary Indirection Rams Need is 0 |
| Depth sorted requested |
| Requesting to use 0 RAMs and have 32 available. |
| Result bus only needs (1): |
| ingress_pkt |
| Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 0 |
| |
| +========================================= |
| | Placing action/stats/meters/selection |
| +========================================= |
| |
| Requesting to use 0 RAMs and have 80 available. |
| Depth sorted idletime requests: |
| |
| |
| ======================================================= |
| |
| calling allocate and add with SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
| ======================================================= |
| |
| Requesting to use 2 RAMs and have 80 available. |
| Requesting to use 0 Map RAMs and have 48 available. |
| |
| ======================================================== |
| Run Placement on Request List of size 1 in stage 1 |
| open_up_all_for_match=False |
| synth_two_port_first=False |
| ======================================================== |
| |
| Match Rams Need is 0 |
| Algorithmic TCAM Match RAMs Need is 0 |
| Other Rams Need is 2 |
| |
| +========================================= |
| | Placing algorithmic tcam |
| +========================================= |
| |
| sorted algorithmic tcam requests: (0) |
| |
| |
| ------------------------------------- |
| Columns need for match is 0 |
| columns for width is 0 |
| other columns is 1 |
| reserved columns is 9 |
| reserved columns for tind 0 |
| reserved columns for stateful 1 |
| Ternary Indirection Rams Need is 0 |
| Depth sorted requested |
| Requesting to use 0 RAMs and have 32 available. |
| Result bus only needs (0): |
| |
| +========================================= |
| | Placing action/stats/meters/selection |
| +========================================= |
| |
| Requesting to use 2 RAMs and have 80 available. |
| SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| |
| call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table table0_counter. |
| Allocating: SRAM: Row 6 Col 6 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| Allocating: Map RAM: Row 6 Unit 0 in stage 1 for table0_counter. |
| Allocating: SRAM: Row 6 Col 7 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| Allocating: Map RAM: Row 6 Unit 1 in stage 1 for table0_counter. |
| Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for table0_counter. |
| Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for table0_counter. |
| Depth sorted idletime requests: |
| |
| |
| ======================================================= |
| |
| calling allocate and add with SRAM Resource Request for table table0 (of type ternary_indirection), with 1 ways wants 1 rams. (open-all=False, synth_two_port_first=False) |
| ======================================================= |
| |
| Requesting to use 1 RAMs and have 78 available. |
| Requesting to use 0 Map RAMs and have 46 available. |
| |
| ======================================================== |
| Run Placement on Request List of size 2 in stage 1 |
| open_up_all_for_match=False |
| synth_two_port_first=False |
| ======================================================== |
| |
| Match Rams Need is 0 |
| Algorithmic TCAM Match RAMs Need is 0 |
| Other Rams Need is 3 |
| |
| +========================================= |
| | Placing algorithmic tcam |
| +========================================= |
| |
| sorted algorithmic tcam requests: (0) |
| |
| |
| ------------------------------------- |
| Columns need for match is 0 |
| columns for width is 0 |
| other columns is 1 |
| reserved columns is 9 |
| reserved columns for tind 1 |
| reserved columns for stateful 1 |
| Ternary Indirection Rams Need is 1 |
| Depth sorted requested |
| Group 0 |
| Sram Resource Request for P4 table table0 with handle 16777221 of type ternary_indirection in stage 1 |
| table_type : ternary_indirection |
| rams_for_width : 1 |
| use_stash : False |
| number_ways : 1 |
| way #0 |
| SRAM Request Group 0 |
| rams_for_depth : 1 |
| map_rams : 0 |
| way_number : 0 |
| ram_word_select_bits : 0 |
| ram_enable_select_bits : 0 |
| |
| Requesting to use 1 RAMs and have 32 available. |
| Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 1 |
| Allocating: SRAM: Row 0 Col 2 in stage 1 for table table0's ternary indirection word range Words 0 to 1023. |
| Result bus only needs (0): |
| |
| +========================================= |
| | Placing action/stats/meters/selection |
| +========================================= |
| |
| Requesting to use 2 RAMs and have 79 available. |
| SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| |
| call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table table0_counter. |
| Allocating: SRAM: Row 6 Col 6 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| Allocating: Map RAM: Row 6 Unit 0 in stage 1 for table0_counter. |
| Allocating: SRAM: Row 6 Col 7 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| Allocating: Map RAM: Row 6 Unit 1 in stage 1 for table0_counter. |
| Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for table0_counter. |
| Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for table0_counter. |
| Depth sorted idletime requests: |
| |
| |
| ======================================================= |
| |
| calling allocate and add with SRAM Resource Request for table table0 (of type idletime), with 1 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| ======================================================= |
| |
| Requesting to use 0 RAMs and have 77 available. |
| Requesting to use 1 Map RAMs and have 46 available. |
| |
| ======================================================== |
| Run Placement on Request List of size 3 in stage 1 |
| open_up_all_for_match=False |
| synth_two_port_first=False |
| ======================================================== |
| |
| Match Rams Need is 0 |
| Algorithmic TCAM Match RAMs Need is 0 |
| Other Rams Need is 3 |
| |
| +========================================= |
| | Placing algorithmic tcam |
| +========================================= |
| |
| sorted algorithmic tcam requests: (0) |
| |
| |
| ------------------------------------- |
| Columns need for match is 0 |
| columns for width is 0 |
| other columns is 1 |
| reserved columns is 9 |
| reserved columns for tind 1 |
| reserved columns for stateful 1 |
| Ternary Indirection Rams Need is 1 |
| Depth sorted requested |
| Group 0 |
| Sram Resource Request for P4 table table0 with handle 16777221 of type ternary_indirection in stage 1 |
| table_type : ternary_indirection |
| rams_for_width : 1 |
| use_stash : False |
| number_ways : 1 |
| way #0 |
| SRAM Request Group 0 |
| rams_for_depth : 1 |
| map_rams : 0 |
| way_number : 0 |
| ram_word_select_bits : 0 |
| ram_enable_select_bits : 0 |
| |
| Requesting to use 1 RAMs and have 32 available. |
| Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 1 |
| Allocating: SRAM: Row 0 Col 2 in stage 1 for table table0's ternary indirection word range Words 0 to 1023. |
| Result bus only needs (0): |
| |
| +========================================= |
| | Placing action/stats/meters/selection |
| +========================================= |
| |
| Requesting to use 2 RAMs and have 79 available. |
| SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| |
| call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table table0_counter. |
| Allocating: SRAM: Row 6 Col 6 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| Allocating: Map RAM: Row 6 Unit 0 in stage 1 for table0_counter. |
| Allocating: SRAM: Row 6 Col 7 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| Allocating: Map RAM: Row 6 Unit 1 in stage 1 for table0_counter. |
| Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for table0_counter. |
| Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for table0_counter. |
| Depth sorted idletime requests: |
| Sram Resource Request for P4 table table0 with handle 16777221 of type idletime in stage 1 |
| table_type : idletime |
| rams_for_width : 0 |
| use_stash : False |
| number_ways : 1 |
| way #0 |
| SRAM Request Group 0 |
| rams_for_depth : 0 |
| map_rams : 1 |
| way_number : 0 |
| ram_word_select_bits : 0 |
| ram_enable_select_bits : 0 |
| |
| Requesting to use 1 RAMs and have 46 available. |
| top_cnt = 1 and num requests = 1 |
| bottom_cnt = 0 and num requests = 0 |
| Working on idletime request SRAM Resource Request for table table0 (of type idletime), with 1 ways wants 0 rams. |
| >> wants 1 map rams |
| Allocating: Map RAM: Row 7 Unit 0 in stage 1 for table0. |
| Allocating: Ram Data Bus IdletimeHalfLogicalRow 0 top is 19 bits in stage 1 for table0. |
| |
| |
| ======================================================= |
| |
| calling allocate and add with SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
| ======================================================= |
| |
| Requesting to use 2 RAMs and have 80 available. |
| Requesting to use 0 Map RAMs and have 48 available. |
| |
| ======================================================== |
| Run Placement on Request List of size 1 in stage 2 |
| open_up_all_for_match=False |
| synth_two_port_first=False |
| ======================================================== |
| |
| Match Rams Need is 0 |
| Algorithmic TCAM Match RAMs Need is 0 |
| Other Rams Need is 2 |
| |
| +========================================= |
| | Placing algorithmic tcam |
| +========================================= |
| |
| sorted algorithmic tcam requests: (0) |
| |
| |
| ------------------------------------- |
| Columns need for match is 0 |
| columns for width is 0 |
| other columns is 1 |
| reserved columns is 9 |
| reserved columns for tind 0 |
| reserved columns for stateful 1 |
| Ternary Indirection Rams Need is 0 |
| Depth sorted requested |
| Requesting to use 0 RAMs and have 32 available. |
| Result bus only needs (0): |
| |
| +========================================= |
| | Placing action/stats/meters/selection |
| +========================================= |
| |
| Requesting to use 2 RAMs and have 80 available. |
| SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| NO Spill Required off of logical row 13 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| |
| call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table ingress_port_counter. |
| Allocating: SRAM: Row 6 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| Allocating: Map RAM: Row 6 Unit 0 in stage 2 for ingress_port_counter. |
| Allocating: SRAM: Row 6 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| Allocating: Map RAM: Row 6 Unit 1 in stage 2 for ingress_port_counter. |
| Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for ingress_port_counter. |
| Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for ingress_port_counter. |
| Depth sorted idletime requests: |
| |
| |
| ======================================================= |
| |
| calling allocate and add with SRAM Resource Request for table ingress_port_count_table (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| ======================================================= |
| |
| Requesting to use 0 RAMs and have 78 available. |
| Requesting to use 0 Map RAMs and have 46 available. |
| |
| ======================================================== |
| Run Placement on Request List of size 2 in stage 2 |
| open_up_all_for_match=False |
| synth_two_port_first=False |
| ======================================================== |
| |
| Match Rams Need is 0 |
| Algorithmic TCAM Match RAMs Need is 0 |
| Other Rams Need is 2 |
| |
| +========================================= |
| | Placing algorithmic tcam |
| +========================================= |
| |
| sorted algorithmic tcam requests: (0) |
| |
| |
| ------------------------------------- |
| Columns need for match is 0 |
| columns for width is 0 |
| other columns is 1 |
| reserved columns is 9 |
| reserved columns for tind 0 |
| reserved columns for stateful 1 |
| Ternary Indirection Rams Need is 0 |
| Depth sorted requested |
| Requesting to use 0 RAMs and have 32 available. |
| Result bus only needs (1): |
| ingress_port_count_table |
| Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 2 |
| |
| +========================================= |
| | Placing action/stats/meters/selection |
| +========================================= |
| |
| Requesting to use 2 RAMs and have 80 available. |
| SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| NO Spill Required off of logical row 13 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| |
| call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table ingress_port_counter. |
| Allocating: SRAM: Row 6 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| Allocating: Map RAM: Row 6 Unit 0 in stage 2 for ingress_port_counter. |
| Allocating: SRAM: Row 6 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| Allocating: Map RAM: Row 6 Unit 1 in stage 2 for ingress_port_counter. |
| Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for ingress_port_counter. |
| Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for ingress_port_counter. |
| Depth sorted idletime requests: |
| |
| |
| ======================================================= |
| |
| calling allocate and add with SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
| ======================================================= |
| |
| Requesting to use 2 RAMs and have 78 available. |
| Requesting to use 0 Map RAMs and have 46 available. |
| |
| ======================================================== |
| Run Placement on Request List of size 3 in stage 2 |
| open_up_all_for_match=False |
| synth_two_port_first=False |
| ======================================================== |
| |
| Match Rams Need is 0 |
| Algorithmic TCAM Match RAMs Need is 0 |
| Other Rams Need is 4 |
| |
| +========================================= |
| | Placing algorithmic tcam |
| +========================================= |
| |
| sorted algorithmic tcam requests: (0) |
| |
| |
| ------------------------------------- |
| Columns need for match is 0 |
| columns for width is 0 |
| other columns is 1 |
| reserved columns is 9 |
| reserved columns for tind 0 |
| reserved columns for stateful 1 |
| Ternary Indirection Rams Need is 0 |
| Depth sorted requested |
| Requesting to use 0 RAMs and have 32 available. |
| Result bus only needs (1): |
| ingress_port_count_table |
| Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 2 |
| |
| +========================================= |
| | Placing action/stats/meters/selection |
| +========================================= |
| |
| Requesting to use 4 RAMs and have 80 available. |
| SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| NO Spill Required off of logical row 13 for SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| |
| call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table egress_port_counter. |
| Allocating: SRAM: Row 6 Col 6 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| Allocating: Map RAM: Row 6 Unit 0 in stage 2 for egress_port_counter. |
| Allocating: SRAM: Row 6 Col 7 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| Allocating: Map RAM: Row 6 Unit 1 in stage 2 for egress_port_counter. |
| Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for egress_port_counter. |
| Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for egress_port_counter. |
| NO Spill Required off of logical row 9 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| |
| call to place_table_on_logical_row --- logical row 9 and rams to place is 2 and depth index is 0 |
| Allocating: Statistics ALU 4 on right (128 bits) in stage 2 for table ingress_port_counter. |
| Allocating: SRAM: Row 4 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| Allocating: Map RAM: Row 4 Unit 0 in stage 2 for ingress_port_counter. |
| Allocating: SRAM: Row 4 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| Allocating: Map RAM: Row 4 Unit 1 in stage 2 for ingress_port_counter. |
| Allocating: Ram Data Bus StatsR 4 right is 128 bits in stage 2 for ingress_port_counter. |
| Allocating: Ram Data Bus StatsW 4 right is 128 bits in stage 2 for ingress_port_counter. |
| Depth sorted idletime requests: |
| |
| |
| ======================================================= |
| |
| calling allocate and add with SRAM Resource Request for table egress_port_count_table (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| ======================================================= |
| |
| Requesting to use 0 RAMs and have 76 available. |
| Requesting to use 0 Map RAMs and have 44 available. |
| |
| ======================================================== |
| Run Placement on Request List of size 4 in stage 2 |
| open_up_all_for_match=False |
| synth_two_port_first=False |
| ======================================================== |
| |
| Match Rams Need is 0 |
| Algorithmic TCAM Match RAMs Need is 0 |
| Other Rams Need is 4 |
| |
| +========================================= |
| | Placing algorithmic tcam |
| +========================================= |
| |
| sorted algorithmic tcam requests: (0) |
| |
| |
| ------------------------------------- |
| Columns need for match is 0 |
| columns for width is 0 |
| other columns is 1 |
| reserved columns is 9 |
| reserved columns for tind 0 |
| reserved columns for stateful 1 |
| Ternary Indirection Rams Need is 0 |
| Depth sorted requested |
| Requesting to use 0 RAMs and have 32 available. |
| Result bus only needs (2): |
| egress_port_count_table |
| ingress_port_count_table |
| Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 2 |
| Allocating: Ram Data Bus MatchResult2R 0 left_and_right is 83 bits in stage 2 |
| |
| +========================================= |
| | Placing action/stats/meters/selection |
| +========================================= |
| |
| Requesting to use 4 RAMs and have 80 available. |
| SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| NO Spill Required off of logical row 13 for SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| |
| call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table egress_port_counter. |
| Allocating: SRAM: Row 6 Col 6 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| Allocating: Map RAM: Row 6 Unit 0 in stage 2 for egress_port_counter. |
| Allocating: SRAM: Row 6 Col 7 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| Allocating: Map RAM: Row 6 Unit 1 in stage 2 for egress_port_counter. |
| Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for egress_port_counter. |
| Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for egress_port_counter. |
| NO Spill Required off of logical row 9 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| |
| call to place_table_on_logical_row --- logical row 9 and rams to place is 2 and depth index is 0 |
| Allocating: Statistics ALU 4 on right (128 bits) in stage 2 for table ingress_port_counter. |
| Allocating: SRAM: Row 4 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| Allocating: Map RAM: Row 4 Unit 0 in stage 2 for ingress_port_counter. |
| Allocating: SRAM: Row 4 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| Allocating: Map RAM: Row 4 Unit 1 in stage 2 for ingress_port_counter. |
| Allocating: Ram Data Bus StatsR 4 right is 128 bits in stage 2 for ingress_port_counter. |
| Allocating: Ram Data Bus StatsW 4 right is 128 bits in stage 2 for ingress_port_counter. |
| Depth sorted idletime requests: |
| |
| |
| ======================================================= |
| |
| calling allocate and add with SRAM Resource Request for table egress_pkt (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| ======================================================= |
| |
| Requesting to use 0 RAMs and have 80 available. |
| Requesting to use 0 Map RAMs and have 48 available. |
| |
| ======================================================== |
| Run Placement on Request List of size 2 in stage 0 |
| open_up_all_for_match=False |
| synth_two_port_first=False |
| ======================================================== |
| |
| Match Rams Need is 0 |
| Algorithmic TCAM Match RAMs Need is 0 |
| Other Rams Need is 0 |
| |
| +========================================= |
| | Placing algorithmic tcam |
| +========================================= |
| |
| sorted algorithmic tcam requests: (0) |
| |
| |
| ------------------------------------- |
| Columns need for match is 0 |
| columns for width is 0 |
| other columns is 0 |
| reserved columns is 10 |
| reserved columns for tind 0 |
| reserved columns for stateful 0 |
| Ternary Indirection Rams Need is 0 |
| Depth sorted requested |
| Requesting to use 0 RAMs and have 32 available. |
| Result bus only needs (2): |
| egress_pkt |
| ingress_pkt |
| Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 0 |
| Allocating: Ram Data Bus MatchResult2R 0 left_and_right is 83 bits in stage 0 |
| |
| +========================================= |
| | Placing action/stats/meters/selection |
| +========================================= |
| |
| Requesting to use 0 RAMs and have 80 available. |
| Depth sorted idletime requests: |