blob: eb6cc14478739639f41a3e160ab7e9980615863c [file] [log] [blame]
Carmelo Cascone5db39682017-09-07 16:36:42 +02001+---------------------------------------------------------------------+
2| Log file: parde.log |
3| Compiler version: 5.1.0 (fca32d1) |
4| Created on: Thu Sep 7 13:56:08 2017 |
5+---------------------------------------------------------------------+
6
7># Begin digest init (pre-PHV)
8>## Gress 0
9>## Gress 1
10>## Rewrite CLONE_I2E_DIGEST_RCVR ids
11>## Rewrite CLONE_E2E_DIGEST_RCVR ids
12># End digest init (pre-PHV)
13># Begin digest PHV reservations
14># End digest PHV reservations
15># Begin digest init (post-PHV)
16># End digest init (post-PHV)
17Bridge-MF:ig_intr_md_for_tm.copy_to_cpu
18Bridge-MF:ig_intr_md.ingress_port
19Found parser entry point: start
20># Begin unroll of HLIR parse graph
21>## Create shadow parse graph and find loops
22>## Entrypoint 'p4_parse_state.start'
23Creating shadow state: 'p4_parse_state.start' -> 'shadow_state (start, 140040985456016)'
24Creating shadow state: 'p4_parse_state.parse_pkt_in' -> 'shadow_state (parse_pkt_in, 140040985455824)'
25Creating shadow state: 'p4_parse_state.parse_ethernet' -> 'shadow_state (parse_ethernet, 140040985455056)'
26Creating shadow state: 'p4_parse_state.parse_ipv4' -> 'shadow_state (parse_ipv4, 140040985455184)'
27Creating shadow state: 'p4_parse_state.parse_tcp' -> 'shadow_state (parse_tcp, 140040985454864)'
28Creating shadow state: 'p4_parse_state.parse_udp' -> 'shadow_state (parse_udp, 140040985454928)'
29Creating shadow state: 'p4_parse_state.default_parser' -> 'shadow_state (default_parser, 140040985454800)'
30Creating shadow state: 'p4_parse_state.parse_pkt_out' -> 'shadow_state (parse_pkt_out, 140040985454736)'
31># End unroll of HLIR parse graph
32># Begin deparser init
33>## Create records for gress 0
34Skipping metadata header 'p4_header_instance.standard_metadata'
35Skipping intrinsic header 'p4_header_instance.ig_intr_md'
36Skipping intrinsic header 'p4_header_instance.ig_intr_md_for_tm'
37Skipping intrinsic header 'p4_header_instance.ig_intr_md_for_mb'
38Skipping intrinsic header 'p4_header_instance.eg_intr_md'
39Skipping intrinsic header 'p4_header_instance.eg_intr_md_for_mb'
40Skipping intrinsic header 'p4_header_instance.eg_intr_md_for_oport'
41Created record for 'p4_header_instance.packet_in_hdr'
42Created record for 'p4_header_instance.packet_out_hdr'
43Created record for 'p4_header_instance.ethernet'
44Created record for 'p4_header_instance.ipv4'
45Created record for 'p4_header_instance.tcp'
46Created record for 'p4_header_instance.udp'
47>## Build record ordering for gress 0
48>## Build field ordering for record 'packet_out_hdr'
49>## Build field ordering for record 'packet_in_hdr'
50>## Build field ordering for record 'ethernet'
51>## Build field ordering for record 'ipv4'
52>## Build field ordering for record 'udp'
53>## Build field ordering for record 'tcp'
54>## Create records for gress 1
55Skipping metadata header 'p4_header_instance.standard_metadata'
56Skipping intrinsic header 'p4_header_instance.ig_intr_md'
57Skipping intrinsic header 'p4_header_instance.ig_intr_md_for_tm'
58Skipping intrinsic header 'p4_header_instance.ig_intr_md_for_mb'
59Skipping intrinsic header 'p4_header_instance.eg_intr_md'
60Skipping intrinsic header 'p4_header_instance.eg_intr_md_for_mb'
61Skipping intrinsic header 'p4_header_instance.eg_intr_md_for_oport'
62Created record for 'p4_header_instance.packet_in_hdr'
63Created record for 'p4_header_instance.packet_out_hdr'
64Created record for 'p4_header_instance.ethernet'
65Created record for 'p4_header_instance.ipv4'
66Created record for 'p4_header_instance.tcp'
67Created record for 'p4_header_instance.udp'
68>## Build record ordering for gress 1
69>## Build field ordering for record 'packet_out_hdr'
70>## Build field ordering for record 'packet_in_hdr'
71>## Build field ordering for record 'ethernet'
72>## Build field ordering for record 'ipv4'
73>## Build field ordering for record 'udp'
74>## Build field ordering for record 'tcp'
75Deparse bmeta_ig_intr_md header
76>## Create deparser bridge_ig_intr_md record
77Add container 128 for ig_intr_md.resubmit_flag to bmeta_ig_intr_md
78Add container 128 for ig_intr_md._pad1 to bmeta_ig_intr_md
79Add container 128 for ig_intr_md._pad2 to bmeta_ig_intr_md
80Add container 128 for ig_intr_md._pad3 to bmeta_ig_intr_md
81Add container 128 for ig_intr_md.ingress_port to bmeta_ig_intr_md
82>## Create deparser bridge record
83Bridge contains user-provided data
84># End deparser init
85Constructing parse graph for entry point start on ingress
86Constructing parse graph for entry point start on egress
87Adding special Egress state to access ingress intrisic metadata
88Egress intrinsic metadata unconditional extraction plan: ExtractionPlan { shift 24, extractions ['eg_intr_md.egress_port', 'eg_intr_md.egress_cos'] }
89Egress intrinsic metadata conditional extraction plan: ExtractionPlan { shift 0, extractions [] }
90Stretch extraction of ingress_port to state <Ingress intrinsic metadata> offset 7
91Stretch extraction of ig_intr_md.ingress_port to state <_parse_bridged_ingress_intrinsic_metadata> offset 7
92># Begin scraping deparser POV allocation from raw PHV allocation
93PHV layout: [0, 0, 0, 0, 67, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
94>## Scraping individual POV records
95POV 32 -> packet_in_hdr
96POV 33 -> packet_out_hdr
97POV 34 -> ethernet
98POV 35 -> ipv4
99POV 38 -> pov_bmeta
100POV 36 -> tcp
101POV 37 -> udp
102>## Setting up array bits
103># End scraping deparser POV allocation from raw PHV allocation
104># Begin parser POV rewrite
105>## Filling in POV init state
106>## Rewriting parser POV extractions
107POV for metadata_bridge -> PHV 67 |= 0x40
108POV for packet_in_hdr -> PHV 67 |= 0x1
109POV for ethernet -> PHV 67 |= 0x4
110POV for ipv4 -> PHV 67 |= 0x8
111POV for tcp -> PHV 67 |= 0x10
112POV for udp -> PHV 67 |= 0x20
113POV for packet_out_hdr -> PHV 67 |= 0x2
114POV for ig_intr_md -> dropped (no deparser record)
115POV for _bridged_intr_md_ -> PHV 0 |= 0x10000
116>## Sampling not detected, deparsing at least 1 POV byte
117>## Adding POV containers to metadata bridge: [0]
118>## Set POV skip state's shift amount to 32
119># Begin scraping deparser POV allocation from raw PHV allocation
120PHV layout: [82, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
121>## Scraping individual POV records
122POV 0 -> packet_in_hdr
123POV 1 -> packet_out_hdr
124POV 2 -> ethernet
125POV 3 -> ipv4
126POV 4 -> tcp
127POV 5 -> udp
128>## Setting up array bits
129># End scraping deparser POV allocation from raw PHV allocation
130># Begin parser POV rewrite
131>## Filling in POV init state
132>## Rewriting parser POV extractions
133POV for packet_in_hdr -> PHV 82 |= 0x1
134POV for ethernet -> PHV 82 |= 0x4
135POV for ipv4 -> PHV 82 |= 0x8
136POV for tcp -> PHV 82 |= 0x10
137POV for udp -> PHV 82 |= 0x20
138POV for packet_out_hdr -> PHV 82 |= 0x2
139Linear Chain parse_pkt_in -> parse_ethernet
140Try merge parse_pkt_in <- parse_ethernet
141Multiple paths to state S2 : parse_ethernet <- 3
142Linear Chain <POV initialization> -> start
143Try merge <POV initialization> <- <Ingress intrinsic metadata>
144merge output at offset 0
145Merge s2 constant extraction v=1 phv=0
146merge_offset = 16, complete_merge = True
147Before Merge ------
148S1: State : <POV initialization>
149shift: 0B
150match_reservations: []
151outputs[addr, width]: ()
152match_extractions: []
153next state <Ingress intrinsic metadata> val 0 mask [False]
154parent state <Shim start state>
155
156
157S2: State : <Ingress intrinsic metadata>
158shift: 8B
159match_reservations: []
160outputs[addr, width]: ([128, 16], [0, 32])
161branch on = None, offset = 0b, dst = <Ingress intrinsic metadata>
162branch promise on = ingress_port, offset = 7b, dst = default_parser
163match_extractions: []
164next state <Phase 0> val 0 mask [True]
165parent state <POV initialization>
166
167
168Full merge done <POV initialization> <- <Ingress intrinsic metadata>
169Try merge <POV initialization>_<Ingress intrinsic metadata> <- <Phase 0>
170merge_offset = 0, complete_merge = True
171Before Merge ------
172S1: State : <POV initialization>_<Ingress intrinsic metadata>
173shift: 8B
174match_reservations: []
175outputs[addr, width]: ([128, 16], [0, 32])
176branch on = None, offset = 0b, dst = <POV initialization>_<Ingress intrinsic metadata>
177branch promise on = ingress_port, offset = 7b, dst = default_parser
178match_extractions: []
179next state <Phase 0> val 0 mask [True]
180parent state <Shim start state>
181
182
183S2: State : <Phase 0>
184shift: 8B
185match_reservations: []
186outputs[addr, width]: ()
187branch on = None, offset = 0b, dst = <Phase 0>
188match_extractions: []
189next state start val 0 mask [False]
190parent state <POV initialization>_<Ingress intrinsic metadata>
191
192
193Full merge done <POV initialization>_<Ingress intrinsic metadata> <- <Phase 0>
194Try merge <POV initialization>_<Ingress intrinsic metadata>_<Phase 0> <- start
195Multiple paths to state S2 : start <- 2
196Remove state <Ingress intrinsic metadata>
197Remove state <Phase 0>
198assign ids to 10 states, dir = 0
199------
200State : <Shim start state>
201shift: 0B
202match_reservations: []
203outputs[addr, width]: ()
204match_extractions: []
205next state <POV initialization>_<Ingress intrinsic metadata>_<Phase 0> val 0 mask [False]
206
207------
208State : parse_pkt_in
209shift: 2B
210match_reservations: []
211outputs[addr, width]: ([67, 8], [129, 16])
212match_extractions: []
213next state parse_ethernet val 0 mask [False]
214parent state start
215
216------
217State : parse_ethernet
218shift: 14B
219match_reservations: []
220outputs[addr, width]: ([67, 8], [65, 8], [1, 32], [131, 16], [66, 8], [2, 32], [132, 16])
221branch on = etherType, offset = 96b, dst = parse_ethernet
222match_extractions: [match_window(hw_id=0, width=16)]
223match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
224next state parse_ipv4 val 2048 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
225parent state parse_pkt_in
226parent state parse_pkt_out
227parent state default_parser
228
229------
230State : parse_ipv4
231shift: 20B
232match_reservations: []
233outputs[addr, width]: ([67, 8], [288, 8], [289, 8], [320, 16], [321, 16], [322, 16], [256, 32], [257, 32], [258, 32])
234branch on = fragOffset, offset = 51b, dst = parse_ipv4
235branch on = protocol, offset = 72b, dst = parse_ipv4
236match_extractions: [match_window(hw_id=2, width=8), match_window(hw_id=0, width=16)]
237match key = [0, 1, 2, 3, 4, 5, 6, 7]
238match key = [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, None, None, None]
239next state parse_tcp val 6 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
240next state parse_udp val 17 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
241parent state parse_ethernet
242
243------
244State : parse_tcp
245shift: 20B
246match_reservations: []
247outputs[addr, width]: ([67, 8], [290, 8], [291, 8], [323, 16], [324, 16], [325, 16], [259, 32], [260, 32], [261, 32])
248match_extractions: []
249parent state parse_ipv4
250
251------
252State : parse_udp
253shift: 8B
254match_reservations: []
255outputs[addr, width]: ([67, 8], [290, 8], [291, 8], [323, 16], [259, 32])
256match_extractions: []
257parent state parse_ipv4
258
259------
260State : default_parser
261shift: 0B
262match_reservations: [match_window(hw_id=0, width=16)]
263outputs[addr, width]: ()
264branch on = ingress_port, offset = 7b, dst = default_parser
265match_extractions: [match_window(hw_id=0, width=16)]
266match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, None, None, None, None, None, None, None]
267next state parse_pkt_out val 320 mask [True, True, True, True, True, True, True, True, True]
268next state parse_ethernet val 0 mask [False]
269parent state start
270
271------
272State : parse_pkt_out
273shift: 2B
274match_reservations: []
275outputs[addr, width]: ([67, 8], [129, 16])
276match_extractions: []
277next state parse_ethernet val 0 mask [False]
278parent state default_parser
279
280------
281State : <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
282shift: 16B
283match_reservations: []
284outputs[addr, width]: ([128, 16], [0, 32])
285branch on = None, offset = 0b, dst = <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
286branch on = None, offset = 64b, dst = <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
287branch promise on = ingress_port, offset = 7b, dst = default_parser
288match_extractions: [match_window(hw_id=2, width=8), match_window(hw_id=0, width=16)]
289match key = [0, 1, 2, 3, 4, 5, 6, 7]
290match key = [None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, 8]
291next state start val 0 mask [False]
292parent state <Shim start state>
293
294------
295State : start
296shift: 0B
297match_reservations: [match_window(hw_id=0, width=16)]
298outputs[addr, width]: ([67, 8],)
299branch on = None, offset = 96b, dst = start
300match_extractions: [match_window(hw_id=2, width=8)]
301match key = [0, 1, 2, 3, 4, 5, 6, 7]
302next state parse_pkt_in val 0 mask [True, True, True, True, True, True, True, True]
303next state default_parser val 0 mask [False]
304parent state <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
305
306Linear Chain parse_pkt_in -> parse_ethernet
307Try merge parse_pkt_in <- parse_ethernet
308Multiple paths to state S2 : parse_ethernet <- 3
309Linear Chain <POV initialization> -> start
310Try merge <POV initialization> <- <Egress intrinsic metadata>
311merge output at offset 0
312merge output at offset 16
313merge_offset = 24, complete_merge = True
314Before Merge ------
315S1: State : <POV initialization>
316shift: 0B
317match_reservations: []
318outputs[addr, width]: ()
319match_extractions: []
320next state <Egress intrinsic metadata> val 0 mask [False]
321parent state <Shim start state>
322
323
324S2: State : <Egress intrinsic metadata>
325shift: 3B
326match_reservations: []
327outputs[addr, width]: ([146, 16], [81, 8])
328branch on = None, offset = 24b, dst = <Egress intrinsic metadata>
329match_extractions: []
330next state <POV skip> val 0 mask [False]
331parent state <POV initialization>
332
333
334Full merge done <POV initialization> <- <Egress intrinsic metadata>
335Try merge <POV initialization>_<Egress intrinsic metadata> <- <POV skip>
336merge_offset = 0, complete_merge = True
337Before Merge ------
338S1: State : <POV initialization>_<Egress intrinsic metadata>
339shift: 3B
340match_reservations: []
341outputs[addr, width]: ([146, 16], [81, 8])
342branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>
343match_extractions: []
344next state <POV skip> val 0 mask [False]
345parent state <Shim start state>
346
347
348S2: State : <POV skip>
349shift: 4B
350match_reservations: []
351outputs[addr, width]: ()
352match_extractions: []
353next state <Metadata bridge> val 0 mask [False]
354parent state <POV initialization>_<Egress intrinsic metadata>
355
356
357Full merge done <POV initialization>_<Egress intrinsic metadata> <- <POV skip>
358Try merge <POV initialization>_<Egress intrinsic metadata>_<POV skip> <- <Metadata bridge>
359merge output at offset 0
360merge output at offset 8
361merge_offset = 24, complete_merge = True
362Before Merge ------
363S1: State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>
364shift: 7B
365match_reservations: []
366outputs[addr, width]: ([146, 16], [81, 8])
367branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>
368match_extractions: []
369next state <Metadata bridge> val 0 mask [False]
370parent state <Shim start state>
371
372
373S2: State : <Metadata bridge>
374shift: 3B
375match_reservations: []
376outputs[addr, width]: ([80, 8], [144, 16])
377match_extractions: []
378next state <_parse_bridged_ingress_intrinsic_metadata> val 0 mask [False]
379parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>
380
381
382Full merge done <POV initialization>_<Egress intrinsic metadata>_<POV skip> <- <Metadata bridge>
383Try merge <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge> <- <_parse_bridged_ingress_intrinsic_metadata>
384merge_offset = 0, complete_merge = True
385Before Merge ------
386S1: State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>
387shift: 10B
388match_reservations: []
389outputs[addr, width]: ([146, 16], [81, 8], [80, 8], [144, 16])
390branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>
391match_extractions: []
392next state <_parse_bridged_ingress_intrinsic_metadata> val 0 mask [False]
393parent state <Shim start state>
394
395
396S2: State : <_parse_bridged_ingress_intrinsic_metadata>
397shift: 2B
398match_reservations: []
399outputs[addr, width]: ()
400branch promise on = ingress_port, offset = 7b, dst = default_parser
401match_extractions: []
402next state start val 0 mask [False]
403parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>
404
405
406Full merge done <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge> <- <_parse_bridged_ingress_intrinsic_metadata>
407Try merge <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata> <- start
408merge_offset = 0, complete_merge = True
409Before Merge ------
410S1: State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>
411shift: 12B
412match_reservations: []
413outputs[addr, width]: ([146, 16], [81, 8], [80, 8], [144, 16])
414branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>
415branch promise on = ingress_port, offset = 87b, dst = default_parser
416match_extractions: []
417next state start val 0 mask [False]
418parent state <Shim start state>
419
420
421S2: State : start
422shift: 0B
423match_reservations: []
424outputs[addr, width]: ()
425branch on = None, offset = 96b, dst = start
426match_extractions: []
427next state parse_pkt_in val 0 mask [True, True, True, True, True, True, True, True]
428next state default_parser val 0 mask [False]
429parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>
430
431
432Full merge done <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata> <- start
433Remove state <Egress intrinsic metadata>
434Remove state <POV skip>
435Remove state <Metadata bridge>
436Remove state <_parse_bridged_ingress_intrinsic_metadata>
437Remove state start
438assign ids to 9 states, dir = 1
439------
440State : <Shim start state>
441shift: 0B
442match_reservations: []
443outputs[addr, width]: ()
444match_extractions: []
445next state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start val 0 mask [False]
446
447------
448State : parse_ethernet
449shift: 14B
450match_reservations: []
451outputs[addr, width]: ([82, 8], [300, 8], [270, 32], [338, 16], [301, 8], [271, 32], [339, 16])
452branch on = etherType, offset = 96b, dst = parse_ethernet
453match_extractions: [match_window(hw_id=0, width=16)]
454match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
455next state parse_ipv4 val 2048 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
456parent state parse_pkt_in
457parent state parse_pkt_out
458parent state default_parser
459
460------
461State : parse_ipv4
462shift: 20B
463match_reservations: []
464outputs[addr, width]: ([82, 8], [296, 8], [297, 8], [332, 16], [333, 16], [334, 16], [264, 32], [265, 32], [266, 32])
465branch on = fragOffset, offset = 51b, dst = parse_ipv4
466branch on = protocol, offset = 72b, dst = parse_ipv4
467match_extractions: [match_window(hw_id=2, width=8), match_window(hw_id=0, width=16)]
468match key = [0, 1, 2, 3, 4, 5, 6, 7]
469match key = [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, None, None, None]
470next state parse_tcp val 6 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
471next state parse_udp val 17 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
472parent state parse_ethernet
473
474------
475State : parse_tcp
476shift: 20B
477match_reservations: []
478outputs[addr, width]: ([82, 8], [298, 8], [299, 8], [335, 16], [336, 16], [337, 16], [267, 32], [268, 32], [269, 32])
479match_extractions: []
480parent state parse_ipv4
481
482------
483State : parse_udp
484shift: 8B
485match_reservations: []
486outputs[addr, width]: ([82, 8], [298, 8], [299, 8], [336, 16], [267, 32])
487match_extractions: []
488parent state parse_ipv4
489
490------
491State : default_parser
492shift: 0B
493match_reservations: [match_window(hw_id=0, width=16)]
494outputs[addr, width]: ()
495branch on = ingress_port, offset = 87b, dst = default_parser
496match_extractions: [match_window(hw_id=0, width=16)]
497match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, None, None, None, None, None, None, None]
498next state parse_pkt_out val 320 mask [True, True, True, True, True, True, True, True, True]
499next state parse_ethernet val 0 mask [False]
500parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
501
502------
503State : parse_pkt_out
504shift: 2B
505match_reservations: []
506outputs[addr, width]: ([82, 8], [340, 16])
507match_extractions: []
508next state parse_ethernet val 0 mask [False]
509parent state default_parser
510
511------
512State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
513shift: 12B
514match_reservations: []
515outputs[addr, width]: ([146, 16], [81, 8], [80, 8], [144, 16])
516branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
517branch on = None, offset = 192b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
518branch promise on = ingress_port, offset = 87b, dst = default_parser
519match_extractions: [match_window(hw_id=2, width=8), match_window(hw_id=0, width=16), match_window(hw_id=3, width=8)]
520match key = [8, 9, 10, 11, 12, 13, 14, 15]
521match key = [None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
522match key = [0, 1, 2, 3, 4, 5, 6, 7]
523next state parse_pkt_in val 0 mask [True, True, True, True, True, True, True, True]
524next state default_parser val 0 mask [False]
525parent state <Shim start state>
526
527------
528State : parse_pkt_in
529shift: 2B
530match_reservations: []
531outputs[addr, width]: ([82, 8], [145, 16])
532match_extractions: []
533next state parse_ethernet val 0 mask [False]
534parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
535