Support for different tofino systems (mavericks and montara)
The tofino driver will now register two pipeconf, one for each system.
The right one should be injected via netcfg.
Change-Id: I0fc3e8afa6fedef13d1ab7067811707748e8e916
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/mavericks/logs/parde.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/mavericks/logs/parde.log
new file mode 100644
index 0000000..eb6cc14
--- /dev/null
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/mavericks/logs/parde.log
@@ -0,0 +1,535 @@
++---------------------------------------------------------------------+
+| Log file: parde.log |
+| Compiler version: 5.1.0 (fca32d1) |
+| Created on: Thu Sep 7 13:56:08 2017 |
++---------------------------------------------------------------------+
+
+># Begin digest init (pre-PHV)
+>## Gress 0
+>## Gress 1
+>## Rewrite CLONE_I2E_DIGEST_RCVR ids
+>## Rewrite CLONE_E2E_DIGEST_RCVR ids
+># End digest init (pre-PHV)
+># Begin digest PHV reservations
+># End digest PHV reservations
+># Begin digest init (post-PHV)
+># End digest init (post-PHV)
+Bridge-MF:ig_intr_md_for_tm.copy_to_cpu
+Bridge-MF:ig_intr_md.ingress_port
+Found parser entry point: start
+># Begin unroll of HLIR parse graph
+>## Create shadow parse graph and find loops
+>## Entrypoint 'p4_parse_state.start'
+Creating shadow state: 'p4_parse_state.start' -> 'shadow_state (start, 140040985456016)'
+Creating shadow state: 'p4_parse_state.parse_pkt_in' -> 'shadow_state (parse_pkt_in, 140040985455824)'
+Creating shadow state: 'p4_parse_state.parse_ethernet' -> 'shadow_state (parse_ethernet, 140040985455056)'
+Creating shadow state: 'p4_parse_state.parse_ipv4' -> 'shadow_state (parse_ipv4, 140040985455184)'
+Creating shadow state: 'p4_parse_state.parse_tcp' -> 'shadow_state (parse_tcp, 140040985454864)'
+Creating shadow state: 'p4_parse_state.parse_udp' -> 'shadow_state (parse_udp, 140040985454928)'
+Creating shadow state: 'p4_parse_state.default_parser' -> 'shadow_state (default_parser, 140040985454800)'
+Creating shadow state: 'p4_parse_state.parse_pkt_out' -> 'shadow_state (parse_pkt_out, 140040985454736)'
+># End unroll of HLIR parse graph
+># Begin deparser init
+>## Create records for gress 0
+Skipping metadata header 'p4_header_instance.standard_metadata'
+Skipping intrinsic header 'p4_header_instance.ig_intr_md'
+Skipping intrinsic header 'p4_header_instance.ig_intr_md_for_tm'
+Skipping intrinsic header 'p4_header_instance.ig_intr_md_for_mb'
+Skipping intrinsic header 'p4_header_instance.eg_intr_md'
+Skipping intrinsic header 'p4_header_instance.eg_intr_md_for_mb'
+Skipping intrinsic header 'p4_header_instance.eg_intr_md_for_oport'
+Created record for 'p4_header_instance.packet_in_hdr'
+Created record for 'p4_header_instance.packet_out_hdr'
+Created record for 'p4_header_instance.ethernet'
+Created record for 'p4_header_instance.ipv4'
+Created record for 'p4_header_instance.tcp'
+Created record for 'p4_header_instance.udp'
+>## Build record ordering for gress 0
+>## Build field ordering for record 'packet_out_hdr'
+>## Build field ordering for record 'packet_in_hdr'
+>## Build field ordering for record 'ethernet'
+>## Build field ordering for record 'ipv4'
+>## Build field ordering for record 'udp'
+>## Build field ordering for record 'tcp'
+>## Create records for gress 1
+Skipping metadata header 'p4_header_instance.standard_metadata'
+Skipping intrinsic header 'p4_header_instance.ig_intr_md'
+Skipping intrinsic header 'p4_header_instance.ig_intr_md_for_tm'
+Skipping intrinsic header 'p4_header_instance.ig_intr_md_for_mb'
+Skipping intrinsic header 'p4_header_instance.eg_intr_md'
+Skipping intrinsic header 'p4_header_instance.eg_intr_md_for_mb'
+Skipping intrinsic header 'p4_header_instance.eg_intr_md_for_oport'
+Created record for 'p4_header_instance.packet_in_hdr'
+Created record for 'p4_header_instance.packet_out_hdr'
+Created record for 'p4_header_instance.ethernet'
+Created record for 'p4_header_instance.ipv4'
+Created record for 'p4_header_instance.tcp'
+Created record for 'p4_header_instance.udp'
+>## Build record ordering for gress 1
+>## Build field ordering for record 'packet_out_hdr'
+>## Build field ordering for record 'packet_in_hdr'
+>## Build field ordering for record 'ethernet'
+>## Build field ordering for record 'ipv4'
+>## Build field ordering for record 'udp'
+>## Build field ordering for record 'tcp'
+Deparse bmeta_ig_intr_md header
+>## Create deparser bridge_ig_intr_md record
+Add container 128 for ig_intr_md.resubmit_flag to bmeta_ig_intr_md
+Add container 128 for ig_intr_md._pad1 to bmeta_ig_intr_md
+Add container 128 for ig_intr_md._pad2 to bmeta_ig_intr_md
+Add container 128 for ig_intr_md._pad3 to bmeta_ig_intr_md
+Add container 128 for ig_intr_md.ingress_port to bmeta_ig_intr_md
+>## Create deparser bridge record
+Bridge contains user-provided data
+># End deparser init
+Constructing parse graph for entry point start on ingress
+Constructing parse graph for entry point start on egress
+Adding special Egress state to access ingress intrisic metadata
+Egress intrinsic metadata unconditional extraction plan: ExtractionPlan { shift 24, extractions ['eg_intr_md.egress_port', 'eg_intr_md.egress_cos'] }
+Egress intrinsic metadata conditional extraction plan: ExtractionPlan { shift 0, extractions [] }
+Stretch extraction of ingress_port to state <Ingress intrinsic metadata> offset 7
+Stretch extraction of ig_intr_md.ingress_port to state <_parse_bridged_ingress_intrinsic_metadata> offset 7
+># Begin scraping deparser POV allocation from raw PHV allocation
+PHV layout: [0, 0, 0, 0, 67, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
+>## Scraping individual POV records
+POV 32 -> packet_in_hdr
+POV 33 -> packet_out_hdr
+POV 34 -> ethernet
+POV 35 -> ipv4
+POV 38 -> pov_bmeta
+POV 36 -> tcp
+POV 37 -> udp
+>## Setting up array bits
+># End scraping deparser POV allocation from raw PHV allocation
+># Begin parser POV rewrite
+>## Filling in POV init state
+>## Rewriting parser POV extractions
+POV for metadata_bridge -> PHV 67 |= 0x40
+POV for packet_in_hdr -> PHV 67 |= 0x1
+POV for ethernet -> PHV 67 |= 0x4
+POV for ipv4 -> PHV 67 |= 0x8
+POV for tcp -> PHV 67 |= 0x10
+POV for udp -> PHV 67 |= 0x20
+POV for packet_out_hdr -> PHV 67 |= 0x2
+POV for ig_intr_md -> dropped (no deparser record)
+POV for _bridged_intr_md_ -> PHV 0 |= 0x10000
+>## Sampling not detected, deparsing at least 1 POV byte
+>## Adding POV containers to metadata bridge: [0]
+>## Set POV skip state's shift amount to 32
+># Begin scraping deparser POV allocation from raw PHV allocation
+PHV layout: [82, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
+>## Scraping individual POV records
+POV 0 -> packet_in_hdr
+POV 1 -> packet_out_hdr
+POV 2 -> ethernet
+POV 3 -> ipv4
+POV 4 -> tcp
+POV 5 -> udp
+>## Setting up array bits
+># End scraping deparser POV allocation from raw PHV allocation
+># Begin parser POV rewrite
+>## Filling in POV init state
+>## Rewriting parser POV extractions
+POV for packet_in_hdr -> PHV 82 |= 0x1
+POV for ethernet -> PHV 82 |= 0x4
+POV for ipv4 -> PHV 82 |= 0x8
+POV for tcp -> PHV 82 |= 0x10
+POV for udp -> PHV 82 |= 0x20
+POV for packet_out_hdr -> PHV 82 |= 0x2
+Linear Chain parse_pkt_in -> parse_ethernet
+Try merge parse_pkt_in <- parse_ethernet
+Multiple paths to state S2 : parse_ethernet <- 3
+Linear Chain <POV initialization> -> start
+Try merge <POV initialization> <- <Ingress intrinsic metadata>
+merge output at offset 0
+Merge s2 constant extraction v=1 phv=0
+merge_offset = 16, complete_merge = True
+Before Merge ------
+S1: State : <POV initialization>
+shift: 0B
+match_reservations: []
+outputs[addr, width]: ()
+match_extractions: []
+next state <Ingress intrinsic metadata> val 0 mask [False]
+parent state <Shim start state>
+
+
+S2: State : <Ingress intrinsic metadata>
+shift: 8B
+match_reservations: []
+outputs[addr, width]: ([128, 16], [0, 32])
+branch on = None, offset = 0b, dst = <Ingress intrinsic metadata>
+branch promise on = ingress_port, offset = 7b, dst = default_parser
+match_extractions: []
+next state <Phase 0> val 0 mask [True]
+parent state <POV initialization>
+
+
+Full merge done <POV initialization> <- <Ingress intrinsic metadata>
+Try merge <POV initialization>_<Ingress intrinsic metadata> <- <Phase 0>
+merge_offset = 0, complete_merge = True
+Before Merge ------
+S1: State : <POV initialization>_<Ingress intrinsic metadata>
+shift: 8B
+match_reservations: []
+outputs[addr, width]: ([128, 16], [0, 32])
+branch on = None, offset = 0b, dst = <POV initialization>_<Ingress intrinsic metadata>
+branch promise on = ingress_port, offset = 7b, dst = default_parser
+match_extractions: []
+next state <Phase 0> val 0 mask [True]
+parent state <Shim start state>
+
+
+S2: State : <Phase 0>
+shift: 8B
+match_reservations: []
+outputs[addr, width]: ()
+branch on = None, offset = 0b, dst = <Phase 0>
+match_extractions: []
+next state start val 0 mask [False]
+parent state <POV initialization>_<Ingress intrinsic metadata>
+
+
+Full merge done <POV initialization>_<Ingress intrinsic metadata> <- <Phase 0>
+Try merge <POV initialization>_<Ingress intrinsic metadata>_<Phase 0> <- start
+Multiple paths to state S2 : start <- 2
+Remove state <Ingress intrinsic metadata>
+Remove state <Phase 0>
+assign ids to 10 states, dir = 0
+------
+State : <Shim start state>
+shift: 0B
+match_reservations: []
+outputs[addr, width]: ()
+match_extractions: []
+next state <POV initialization>_<Ingress intrinsic metadata>_<Phase 0> val 0 mask [False]
+
+------
+State : parse_pkt_in
+shift: 2B
+match_reservations: []
+outputs[addr, width]: ([67, 8], [129, 16])
+match_extractions: []
+next state parse_ethernet val 0 mask [False]
+parent state start
+
+------
+State : parse_ethernet
+shift: 14B
+match_reservations: []
+outputs[addr, width]: ([67, 8], [65, 8], [1, 32], [131, 16], [66, 8], [2, 32], [132, 16])
+branch on = etherType, offset = 96b, dst = parse_ethernet
+match_extractions: [match_window(hw_id=0, width=16)]
+match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
+next state parse_ipv4 val 2048 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
+parent state parse_pkt_in
+parent state parse_pkt_out
+parent state default_parser
+
+------
+State : parse_ipv4
+shift: 20B
+match_reservations: []
+outputs[addr, width]: ([67, 8], [288, 8], [289, 8], [320, 16], [321, 16], [322, 16], [256, 32], [257, 32], [258, 32])
+branch on = fragOffset, offset = 51b, dst = parse_ipv4
+branch on = protocol, offset = 72b, dst = parse_ipv4
+match_extractions: [match_window(hw_id=2, width=8), match_window(hw_id=0, width=16)]
+match key = [0, 1, 2, 3, 4, 5, 6, 7]
+match key = [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, None, None, None]
+next state parse_tcp val 6 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
+next state parse_udp val 17 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
+parent state parse_ethernet
+
+------
+State : parse_tcp
+shift: 20B
+match_reservations: []
+outputs[addr, width]: ([67, 8], [290, 8], [291, 8], [323, 16], [324, 16], [325, 16], [259, 32], [260, 32], [261, 32])
+match_extractions: []
+parent state parse_ipv4
+
+------
+State : parse_udp
+shift: 8B
+match_reservations: []
+outputs[addr, width]: ([67, 8], [290, 8], [291, 8], [323, 16], [259, 32])
+match_extractions: []
+parent state parse_ipv4
+
+------
+State : default_parser
+shift: 0B
+match_reservations: [match_window(hw_id=0, width=16)]
+outputs[addr, width]: ()
+branch on = ingress_port, offset = 7b, dst = default_parser
+match_extractions: [match_window(hw_id=0, width=16)]
+match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, None, None, None, None, None, None, None]
+next state parse_pkt_out val 320 mask [True, True, True, True, True, True, True, True, True]
+next state parse_ethernet val 0 mask [False]
+parent state start
+
+------
+State : parse_pkt_out
+shift: 2B
+match_reservations: []
+outputs[addr, width]: ([67, 8], [129, 16])
+match_extractions: []
+next state parse_ethernet val 0 mask [False]
+parent state default_parser
+
+------
+State : <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
+shift: 16B
+match_reservations: []
+outputs[addr, width]: ([128, 16], [0, 32])
+branch on = None, offset = 0b, dst = <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
+branch on = None, offset = 64b, dst = <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
+branch promise on = ingress_port, offset = 7b, dst = default_parser
+match_extractions: [match_window(hw_id=2, width=8), match_window(hw_id=0, width=16)]
+match key = [0, 1, 2, 3, 4, 5, 6, 7]
+match key = [None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, 8]
+next state start val 0 mask [False]
+parent state <Shim start state>
+
+------
+State : start
+shift: 0B
+match_reservations: [match_window(hw_id=0, width=16)]
+outputs[addr, width]: ([67, 8],)
+branch on = None, offset = 96b, dst = start
+match_extractions: [match_window(hw_id=2, width=8)]
+match key = [0, 1, 2, 3, 4, 5, 6, 7]
+next state parse_pkt_in val 0 mask [True, True, True, True, True, True, True, True]
+next state default_parser val 0 mask [False]
+parent state <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
+
+Linear Chain parse_pkt_in -> parse_ethernet
+Try merge parse_pkt_in <- parse_ethernet
+Multiple paths to state S2 : parse_ethernet <- 3
+Linear Chain <POV initialization> -> start
+Try merge <POV initialization> <- <Egress intrinsic metadata>
+merge output at offset 0
+merge output at offset 16
+merge_offset = 24, complete_merge = True
+Before Merge ------
+S1: State : <POV initialization>
+shift: 0B
+match_reservations: []
+outputs[addr, width]: ()
+match_extractions: []
+next state <Egress intrinsic metadata> val 0 mask [False]
+parent state <Shim start state>
+
+
+S2: State : <Egress intrinsic metadata>
+shift: 3B
+match_reservations: []
+outputs[addr, width]: ([146, 16], [81, 8])
+branch on = None, offset = 24b, dst = <Egress intrinsic metadata>
+match_extractions: []
+next state <POV skip> val 0 mask [False]
+parent state <POV initialization>
+
+
+Full merge done <POV initialization> <- <Egress intrinsic metadata>
+Try merge <POV initialization>_<Egress intrinsic metadata> <- <POV skip>
+merge_offset = 0, complete_merge = True
+Before Merge ------
+S1: State : <POV initialization>_<Egress intrinsic metadata>
+shift: 3B
+match_reservations: []
+outputs[addr, width]: ([146, 16], [81, 8])
+branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>
+match_extractions: []
+next state <POV skip> val 0 mask [False]
+parent state <Shim start state>
+
+
+S2: State : <POV skip>
+shift: 4B
+match_reservations: []
+outputs[addr, width]: ()
+match_extractions: []
+next state <Metadata bridge> val 0 mask [False]
+parent state <POV initialization>_<Egress intrinsic metadata>
+
+
+Full merge done <POV initialization>_<Egress intrinsic metadata> <- <POV skip>
+Try merge <POV initialization>_<Egress intrinsic metadata>_<POV skip> <- <Metadata bridge>
+merge output at offset 0
+merge output at offset 8
+merge_offset = 24, complete_merge = True
+Before Merge ------
+S1: State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>
+shift: 7B
+match_reservations: []
+outputs[addr, width]: ([146, 16], [81, 8])
+branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>
+match_extractions: []
+next state <Metadata bridge> val 0 mask [False]
+parent state <Shim start state>
+
+
+S2: State : <Metadata bridge>
+shift: 3B
+match_reservations: []
+outputs[addr, width]: ([80, 8], [144, 16])
+match_extractions: []
+next state <_parse_bridged_ingress_intrinsic_metadata> val 0 mask [False]
+parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>
+
+
+Full merge done <POV initialization>_<Egress intrinsic metadata>_<POV skip> <- <Metadata bridge>
+Try merge <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge> <- <_parse_bridged_ingress_intrinsic_metadata>
+merge_offset = 0, complete_merge = True
+Before Merge ------
+S1: State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>
+shift: 10B
+match_reservations: []
+outputs[addr, width]: ([146, 16], [81, 8], [80, 8], [144, 16])
+branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>
+match_extractions: []
+next state <_parse_bridged_ingress_intrinsic_metadata> val 0 mask [False]
+parent state <Shim start state>
+
+
+S2: State : <_parse_bridged_ingress_intrinsic_metadata>
+shift: 2B
+match_reservations: []
+outputs[addr, width]: ()
+branch promise on = ingress_port, offset = 7b, dst = default_parser
+match_extractions: []
+next state start val 0 mask [False]
+parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>
+
+
+Full merge done <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge> <- <_parse_bridged_ingress_intrinsic_metadata>
+Try merge <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata> <- start
+merge_offset = 0, complete_merge = True
+Before Merge ------
+S1: State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>
+shift: 12B
+match_reservations: []
+outputs[addr, width]: ([146, 16], [81, 8], [80, 8], [144, 16])
+branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>
+branch promise on = ingress_port, offset = 87b, dst = default_parser
+match_extractions: []
+next state start val 0 mask [False]
+parent state <Shim start state>
+
+
+S2: State : start
+shift: 0B
+match_reservations: []
+outputs[addr, width]: ()
+branch on = None, offset = 96b, dst = start
+match_extractions: []
+next state parse_pkt_in val 0 mask [True, True, True, True, True, True, True, True]
+next state default_parser val 0 mask [False]
+parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>
+
+
+Full merge done <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata> <- start
+Remove state <Egress intrinsic metadata>
+Remove state <POV skip>
+Remove state <Metadata bridge>
+Remove state <_parse_bridged_ingress_intrinsic_metadata>
+Remove state start
+assign ids to 9 states, dir = 1
+------
+State : <Shim start state>
+shift: 0B
+match_reservations: []
+outputs[addr, width]: ()
+match_extractions: []
+next state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start val 0 mask [False]
+
+------
+State : parse_ethernet
+shift: 14B
+match_reservations: []
+outputs[addr, width]: ([82, 8], [300, 8], [270, 32], [338, 16], [301, 8], [271, 32], [339, 16])
+branch on = etherType, offset = 96b, dst = parse_ethernet
+match_extractions: [match_window(hw_id=0, width=16)]
+match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
+next state parse_ipv4 val 2048 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
+parent state parse_pkt_in
+parent state parse_pkt_out
+parent state default_parser
+
+------
+State : parse_ipv4
+shift: 20B
+match_reservations: []
+outputs[addr, width]: ([82, 8], [296, 8], [297, 8], [332, 16], [333, 16], [334, 16], [264, 32], [265, 32], [266, 32])
+branch on = fragOffset, offset = 51b, dst = parse_ipv4
+branch on = protocol, offset = 72b, dst = parse_ipv4
+match_extractions: [match_window(hw_id=2, width=8), match_window(hw_id=0, width=16)]
+match key = [0, 1, 2, 3, 4, 5, 6, 7]
+match key = [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, None, None, None]
+next state parse_tcp val 6 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
+next state parse_udp val 17 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
+parent state parse_ethernet
+
+------
+State : parse_tcp
+shift: 20B
+match_reservations: []
+outputs[addr, width]: ([82, 8], [298, 8], [299, 8], [335, 16], [336, 16], [337, 16], [267, 32], [268, 32], [269, 32])
+match_extractions: []
+parent state parse_ipv4
+
+------
+State : parse_udp
+shift: 8B
+match_reservations: []
+outputs[addr, width]: ([82, 8], [298, 8], [299, 8], [336, 16], [267, 32])
+match_extractions: []
+parent state parse_ipv4
+
+------
+State : default_parser
+shift: 0B
+match_reservations: [match_window(hw_id=0, width=16)]
+outputs[addr, width]: ()
+branch on = ingress_port, offset = 87b, dst = default_parser
+match_extractions: [match_window(hw_id=0, width=16)]
+match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, None, None, None, None, None, None, None]
+next state parse_pkt_out val 320 mask [True, True, True, True, True, True, True, True, True]
+next state parse_ethernet val 0 mask [False]
+parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
+
+------
+State : parse_pkt_out
+shift: 2B
+match_reservations: []
+outputs[addr, width]: ([82, 8], [340, 16])
+match_extractions: []
+next state parse_ethernet val 0 mask [False]
+parent state default_parser
+
+------
+State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
+shift: 12B
+match_reservations: []
+outputs[addr, width]: ([146, 16], [81, 8], [80, 8], [144, 16])
+branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
+branch on = None, offset = 192b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
+branch promise on = ingress_port, offset = 87b, dst = default_parser
+match_extractions: [match_window(hw_id=2, width=8), match_window(hw_id=0, width=16), match_window(hw_id=3, width=8)]
+match key = [8, 9, 10, 11, 12, 13, 14, 15]
+match key = [None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
+match key = [0, 1, 2, 3, 4, 5, 6, 7]
+next state parse_pkt_in val 0 mask [True, True, True, True, True, True, True, True]
+next state default_parser val 0 mask [False]
+parent state <Shim start state>
+
+------
+State : parse_pkt_in
+shift: 2B
+match_reservations: []
+outputs[addr, width]: ([82, 8], [145, 16])
+match_extractions: []
+next state parse_ethernet val 0 mask [False]
+parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
+