| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1 | +---------------------------------------------------------------------+ |
| 2 | | Log file: mau.tcam.log | |
| 3 | | Compiler version: 5.1.0 (fca32d1) | |
| Carmelo Cascone | 133c7b1 | 2017-09-13 15:36:08 +0200 | [diff] [blame] | 4 | | Created on: Wed Sep 13 12:56:12 2017 | |
| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 5 | +---------------------------------------------------------------------+ |
| 6 | |
| 7 | |
| 8 | |
| 9 | ======================================================= |
| 10 | |
| 11 | calling allocate and add with TCAM Resource Request for table table0 wants 3 tcams. |
| 12 | ======================================================= |
| 13 | |
| 14 | Requesting to use 3 TCAMs and have 24 available. |
| 15 | |
| 16 | ======================================================== |
| 17 | Run Placement on Request List of size 1 |
| 18 | ======================================================== |
| 19 | |
| Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 20 | Allocating: TCAM: Row 11 Col 1 in stage 0 for table table0 for entries Entry bits [43:0] and word range Words 0 to 511. |
| 21 | Allocating: TCAM: Row 10 Col 1 in stage 0 for table table0 for entries Entry bits [87:44] and word range Words 0 to 511. |
| 22 | Allocating: TCAM: Row 9 Col 1 in stage 0 for table table0 for entries Entry bits [131:88] and word range Words 0 to 511. |
| 23 | Allocating: Ram Data Bus TcamMatchSearch2 11 left_and_right is 44 bits in stage 0 |
| 24 | Allocating: Ram Data Bus TcamMatchSearch2 10 left_and_right is 44 bits in stage 0 |
| 25 | Allocating: Ram Data Bus TcamMatchSearch2 9 left_and_right is 44 bits in stage 0 |