Fixing packet_io and regenerating default.p4 for tofino

Change-Id: I5c2c6565f71a13b375a8ec8da864e9157b8e56ed
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/mavericks/logs/mau.tcam.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/mavericks/logs/mau.tcam.log
index f1e6d64..601ac55 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/mavericks/logs/mau.tcam.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/mavericks/logs/mau.tcam.log
@@ -1,7 +1,7 @@
 +---------------------------------------------------------------------+
 |  Log file: mau.tcam.log                                             |
 |  Compiler version: 5.1.0 (fca32d1)                                  |
-|  Created on: Thu Sep  7 13:56:08 2017                               |
+|  Created on: Fri Sep  8 08:23:45 2017                               |
 +---------------------------------------------------------------------+
 
 
@@ -17,9 +17,9 @@
   Run Placement on Request List of size 1
 ========================================================
 
-Allocating: TCAM: Row 11 Col 1 in stage 1 for table table0 for entries Entry bits [43:0] and word range Words 0 to 511.
-Allocating: TCAM: Row 10 Col 1 in stage 1 for table table0 for entries Entry bits [87:44] and word range Words 0 to 511.
-Allocating: TCAM: Row 9 Col 1 in stage 1 for table table0 for entries Entry bits [131:88] and word range Words 0 to 511.
-Allocating: Ram Data Bus TcamMatchSearch2 11 left_and_right is 44 bits in stage 1
-Allocating: Ram Data Bus TcamMatchSearch2 10 left_and_right is 44 bits in stage 1
-Allocating: Ram Data Bus TcamMatchSearch2 9 left_and_right is 44 bits in stage 1
+Allocating: TCAM: Row 11 Col 1 in stage 0 for table table0 for entries Entry bits [43:0] and word range Words 0 to 511.
+Allocating: TCAM: Row 10 Col 1 in stage 0 for table table0 for entries Entry bits [87:44] and word range Words 0 to 511.
+Allocating: TCAM: Row 9 Col 1 in stage 0 for table table0 for entries Entry bits [131:88] and word range Words 0 to 511.
+Allocating: Ram Data Bus TcamMatchSearch2 11 left_and_right is 44 bits in stage 0
+Allocating: Ram Data Bus TcamMatchSearch2 10 left_and_right is 44 bits in stage 0
+Allocating: Ram Data Bus TcamMatchSearch2 9 left_and_right is 44 bits in stage 0