Workaround to counter-issue as suggested by Antonin
Manually modified via makefile context.json
Change-Id: Ibed9e0691bf1d552db28470da57955e8f3ca802a
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/asm.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/asm.log
index f641fdc..8d36d53 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/asm.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/asm.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: asm.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.characterize.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.characterize.log
index 40c8ad6..a096fd4 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.characterize.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.characterize.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.characterize.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
Match+Action Resource Usage
@@ -23,8 +23,8 @@
| ecmp_group_table | ingress | 1 | exact | sram | 5 (3/0/2/0/0) | 0 | 1024 / 3072 (2048) | 32 / 22 (-10) | 0 | 20 | 0/0/0/0/0/0/4/16 | 9 / 16 (7) | 0 / 0 (0) | 52 / 42 (-10) | 9 | 0 / 0 (0) | 3 in 1 (128) | 1 in 1 (128) | - / - | 96.1% / 29.7% | - / - |
| stage 1 totals | - | - | - | - | 5 (3/0/2/0/0) | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| | | | | | | | | | | | | | | | | | | | | | |
-| ingress_port_count_table | ingress | 2 | | - | 2 (0/0/2/0/0) | 0 | 1024 / 1 (-1023) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 1 in 0 (0) | - / - | - / - | - / - |
-| egress_port_count_table | ingress | 2 | | - | 2 (0/0/2/0/0) | 0 | 1024 / 1 (-1023) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 1 in 0 (0) | - / - | - / - | - / - |
+| ingress_port_count_table | ingress | 2 | | - | 2 (0/0/2/0/0) | 0 | 1024 / 1024 (0) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 0 in 0 (0) | - / - | - / - | - / - |
+| egress_port_count_table | ingress | 2 | | - | 2 (0/0/2/0/0) | 0 | 1024 / 1024 (0) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 0 in 0 (0) | - / - | - / - | - / - |
| stage 2 totals | - | - | - | - | 4 (0/0/4/0/0) | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| | | | | | | | | | | | | | | | | | | | | | |
| overall totals | - | - | - | - | 13 (3/1/8/0/1) | 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.config.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.config.log
index b0c43cd..0e6c149 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.config.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.config.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.config.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
Final Stage dependencies are:
@@ -50,11 +50,11 @@
Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x2. (old value = 0x0 OR new value = 0x2)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_address to be 4.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 12 to come from 8-bit PHV container 3.
+Configuring match input crossbar byte 12 to come from 8-bit PHV container 4.
That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=6][hash_bit_index=40].byte0 to be 0x2.
@@ -128,13 +128,13 @@
Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16])
Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
-Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=2].imem_subword8_instr to be 0x74d83.
-Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=2].imem_subword8_color to be 1.
-Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=2].imem_subword8_parity to be 1.
-Micro instruction added in VLIW 2 for 8-bit position 3 for table process_packet_out_table.
- Assembled as 0x74d83 (or decimal 478595)
- Micro Instruction deposit-field for PHV Container 67 has bit width 20
- Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_instr to be 0x74d84.
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_color to be 1.
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_parity to be 0.
+Micro instruction added in VLIW 2 for 8-bit position 4 for table process_packet_out_table.
+ Assembled as 0x74d84 (or decimal 478596)
+ Micro Instruction deposit-field for PHV Container 68 has bit width 20
+ Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -143,7 +143,7 @@
Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16])
Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
+Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10)
Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6)
--> Stage Gateway Table for condition process_packet_out_table_always_true_condition in stage 0
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
@@ -215,72 +215,71 @@
---- Hash Distribution Units for table table0__action__ ----
Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x2 OR new value = 0x3)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_address to be 5.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_address to be 2.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=0].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 0 to come from 32-bit PHV container 5.
- That PHV byte contains {udp.dstPort[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_address to be 5.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 1 to come from 32-bit PHV container 5.
- That PHV byte contains {udp.dstPort[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_address to be 5.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 2 to come from 32-bit PHV container 5.
- That PHV byte contains {udp.srcPort[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_address to be 5.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 3 to come from 32-bit PHV container 5.
- That PHV byte contains {udp.srcPort[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_address to be 2.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 4 to come from 32-bit PHV container 2.
+Configuring match input crossbar byte 0 to come from 32-bit PHV container 2.
That PHV byte contains {ipv4.dstAddr[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=5].match_input_xbar_32b_ctl_address to be 2.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=5].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 5 to come from 32-bit PHV container 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_address to be 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=1].match_input_xbar_32b_ctl_lo_enable to be 1.
+Configuring match input crossbar byte 1 to come from 32-bit PHV container 2.
That PHV byte contains {ipv4.dstAddr[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=6].match_input_xbar_32b_ctl_address to be 2.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=6].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 6 to come from 32-bit PHV container 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_address to be 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=2].match_input_xbar_32b_ctl_lo_enable to be 1.
+Configuring match input crossbar byte 2 to come from 32-bit PHV container 2.
That PHV byte contains {ipv4.dstAddr[23:16]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=3].match_input_xbar_32b_ctl_lo_enable to be 1.
+Configuring match input crossbar byte 3 to come from 32-bit PHV container 3.
+ That PHV byte contains {tcp.dstPort[7:0]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_address to be 1.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=4].match_input_xbar_32b_ctl_lo_enable to be 1.
+Configuring match input crossbar byte 4 to come from 32-bit PHV container 1.
+ That PHV byte contains {ipv4.srcAddr[31:24]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=5].match_input_xbar_816b_ctl_address to be 20.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=5].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 5 to come from 16-bit PHV container 4.
+ That PHV byte contains {tcp.srcPort[7:0]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=6].match_input_xbar_816b_ctl_address to be 20.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=6].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 6 to come from 16-bit PHV container 4.
+ That PHV byte contains {tcp.dstPort[15:8]}.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=7].match_input_xbar_32b_ctl_address to be 2.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=7].match_input_xbar_32b_ctl_lo_enable to be 1.
Configuring match input crossbar byte 7 to come from 32-bit PHV container 2.
That PHV byte contains {ipv4.dstAddr[31:24]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=8].match_input_xbar_32b_ctl_address to be 1.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=8].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 8 to come from 32-bit PHV container 1.
- That PHV byte contains {ipv4.srcAddr[31:24]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_address to be 19.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 8 to come from 16-bit PHV container 3.
+ That PHV byte contains {ipv4.srcAddr[7:0]}.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_address to be 19.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_enable to be 1.
Configuring match input crossbar byte 9 to come from 16-bit PHV container 3.
That PHV byte contains {ipv4.srcAddr[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_address to be 19.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_address to be 1.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 10 to come from 16-bit PHV container 3.
- That PHV byte contains {ipv4.srcAddr[7:0]}.
+Configuring match input crossbar byte 10 to come from 8-bit PHV container 1.
+ That PHV byte contains {tcp.srcPort[15:8]}.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_address to be 0.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_enable to be 1.
Configuring match input crossbar byte 11 to come from 8-bit PHV container 0.
That PHV byte contains {ipv4.srcAddr[23:16]}.
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x26. (previous value = 0x0 OR new value = 0x26)
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x9. (previous value = 0x8 OR new value = 0x1)
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
-Configuring dp.xbar_hash.hash.hash_seed[output_bit=0].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0xe. (previous value = 0x0 OR new value = 0xe)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x13. (previous value = 0x10 OR new value = 0x3)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x18. (previous value = 0x0 OR new value = 0x18)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x3. (previous value = 0x2 OR new value = 0x3)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x4.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte1 to be 0xd1.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte0 to be 0x1.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte1 to be 0xdf.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte0 to be 0x48.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte1 to be 0x1b.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte0 to be 0x4e.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte1 to be 0x5a.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0x7.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte1 to be 0x82.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte0 to be 0xf1.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte1 to be 0xfa.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0xff.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte1 to be 0xaf.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte0 to be 0xfe.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=0].byte1 to be 0xff.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte0 to be 0x7f.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=2][hash_bit_index=0].byte1 to be 0xff.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte0 to be 0xfb.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=3][hash_bit_index=0].byte1 to be 0x1f.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0xfb.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte1 to be 0xbf.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte0 to be 0xe7.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=5][hash_bit_index=0].byte1 to be 0xe6.
Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 1. (old value = 0 OR new value = 1).
Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 8. (old value = 0 OR new value = 8).
@@ -325,69 +324,69 @@
Configuring match input crossbar byte 133 to come from 16-bit PHV container 0.
That PHV byte contains version/valid
{unused[6:0], ig_intr_md.ingress_port[8:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_address to be 4.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_address to be 5.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 128 to come from 32-bit PHV container 4.
+Configuring match input crossbar byte 128 to come from 32-bit PHV container 5.
That PHV byte contains {ethernet.srcAddr[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_address to be 4.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_address to be 5.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 129 to come from 32-bit PHV container 4.
+Configuring match input crossbar byte 129 to come from 32-bit PHV container 5.
That PHV byte contains {ethernet.srcAddr[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_address to be 4.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_address to be 5.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 130 to come from 32-bit PHV container 4.
+Configuring match input crossbar byte 130 to come from 32-bit PHV container 5.
That PHV byte contains {ethernet.srcAddr[23:16]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_address to be 4.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_address to be 5.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 131 to come from 32-bit PHV container 4.
+Configuring match input crossbar byte 131 to come from 32-bit PHV container 5.
That PHV byte contains {ethernet.srcAddr[31:24]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_address to be 4.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 132 to come from 32-bit PHV container 3.
+Configuring match input crossbar byte 132 to come from 32-bit PHV container 4.
That PHV byte contains {ethernet.dstAddr[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_address to be 4.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 134 to come from 32-bit PHV container 3.
+Configuring match input crossbar byte 134 to come from 32-bit PHV container 4.
That PHV byte contains {ethernet.dstAddr[31:24]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_address to be 4.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 135 to come from 32-bit PHV container 3.
+Configuring match input crossbar byte 135 to come from 32-bit PHV container 4.
That PHV byte contains {ethernet.dstAddr[39:32]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_address to be 21.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_address to be 22.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 136 to come from 16-bit PHV container 5.
+Configuring match input crossbar byte 136 to come from 16-bit PHV container 6.
That PHV byte contains {ethernet.etherType[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_address to be 4.
Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_lo_enable to be 1.
-Configuring match input crossbar byte 137 to come from 32-bit PHV container 3.
+Configuring match input crossbar byte 137 to come from 32-bit PHV container 4.
That PHV byte contains {ethernet.dstAddr[23:16]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_address to be 20.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_address to be 21.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 138 to come from 16-bit PHV container 4.
+Configuring match input crossbar byte 138 to come from 16-bit PHV container 5.
That PHV byte contains {ethernet.srcAddr[47:40]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_address to be 21.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_address to be 22.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 139 to come from 16-bit PHV container 5.
+Configuring match input crossbar byte 139 to come from 16-bit PHV container 6.
That PHV byte contains {ethernet.etherType[15:8]}.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_address to be 16.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_enable to be 1.
Configuring match input crossbar byte 140 to come from 16-bit PHV container 0.
That PHV byte contains {ig_intr_md.ingress_port[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_address to be 20.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_address to be 21.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 141 to come from 16-bit PHV container 4.
+Configuring match input crossbar byte 141 to come from 16-bit PHV container 5.
That PHV byte contains {ethernet.dstAddr[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 3.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 142 to come from 8-bit PHV container 2.
+Configuring match input crossbar byte 142 to come from 8-bit PHV container 3.
That PHV byte contains {ethernet.srcAddr[39:32]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 1.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 2.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 143 to come from 8-bit PHV container 1.
+Configuring match input crossbar byte 143 to come from 8-bit PHV container 2.
That PHV byte contains {ethernet.dstAddr[47:40]}.
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x3e. (previous value = 0x26 OR new value = 0x18)
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0xf. (previous value = 0x9 OR new value = 0x6)
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x39. (previous value = 0x8 OR new value = 0x31)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x3e. (previous value = 0xe OR new value = 0x30)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x1f. (previous value = 0x13 OR new value = 0xc)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x79. (previous value = 0x18 OR new value = 0x61)
--> Idletime Table for match table table0 in stage 0
Looking at Map RAM: Row 7 Unit 0
@@ -447,25 +446,25 @@
Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x6 OR new value = 0x4)
-Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a06.
-Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_color to be 0.
-Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_parity to be 1.
-Micro instruction added in VLIW 1 for 16-bit position 6 for table table0.
- Assembled as 0xc7a06 (or decimal 817670)
- Micro Instruction alu_a for PHV Container 134 has bit width 23
- Field Src2 [3:0] : 0x6 (4 bits in instruction bits [3:0])
+Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a07.
+Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_color to be 0.
+Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_parity to be 0.
+Micro instruction added in VLIW 1 for 16-bit position 7 for table table0.
+ Assembled as 0xc7a07 (or decimal 817671)
+ Micro Instruction alu_a for PHV Container 135 has bit width 23
+ Field Src2 [3:0] : 0x7 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20])
-Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a27.
-Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_color to be 0.
-Configuring dp.imem.imem_subword16[unit_number=7][vliw_instruction_number=1].imem_subword16_parity to be 1.
-Micro instruction added in VLIW 1 for 16-bit position 7 for table table0.
- Assembled as 0xc7a27 (or decimal 817703)
- Micro Instruction alu_a for PHV Container 135 has bit width 23
- Field Src2 [3:0] : 0x7 (4 bits in instruction bits [3:0])
+Configuring dp.imem.imem_subword16[unit_number=8][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a28.
+Configuring dp.imem.imem_subword16[unit_number=8][vliw_instruction_number=1].imem_subword16_color to be 0.
+Configuring dp.imem.imem_subword16[unit_number=8][vliw_instruction_number=1].imem_subword16_parity to be 1.
+Micro instruction added in VLIW 1 for 16-bit position 8 for table table0.
+ Assembled as 0xc7a28 (or decimal 817704)
+ Micro Instruction alu_a for PHV Container 136 has bit width 23
+ Field Src2 [3:0] : 0x8 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x2 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
@@ -486,13 +485,13 @@
Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
-Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_instr to be 0x593.
-Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_color to be 1.
-Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_parity to be 1.
-Micro instruction added in VLIW 1 for 8-bit position 3 for table table0.
- Assembled as 0x593 (or decimal 1427)
- Micro Instruction deposit-field for PHV Container 67 has bit width 20
- Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_instr to be 0x594.
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_color to be 1.
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_parity to be 0.
+Micro instruction added in VLIW 1 for 8-bit position 4 for table table0.
+ Assembled as 0x594 (or decimal 1428)
+ Micro Instruction deposit-field for PHV Container 68 has bit width 20
+ Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -516,15 +515,15 @@
Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16])
Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20])
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x8. (previous value = 0x8 OR new value = 0x8)
+Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x10. (previous value = 0x10 OR new value = 0x10)
Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x7. (previous value = 0x6 OR new value = 0x7)
-Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_instr to be 0xb7d94.
-Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_color to be 0.
-Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_parity to be 0.
-Micro instruction added in VLIW 2 for 8-bit position 4 for table table0.
- Assembled as 0xb7d94 (or decimal 753044)
- Micro Instruction deposit-field for PHV Container 68 has bit width 20
- Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
+Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_instr to be 0xb7d95.
+Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_color to be 0.
+Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_parity to be 1.
+Micro instruction added in VLIW 2 for 8-bit position 5 for table table0.
+ Assembled as 0xb7d95 (or decimal 753045)
+ Micro Instruction deposit-field for PHV Container 69 has bit width 20
+ Field Src2 [3:0] : 0x5 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -533,7 +532,7 @@
Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16])
Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19])
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x18. (previous value = 0x8 OR new value = 0x10)
+Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x30. (previous value = 0x10 OR new value = 0x20)
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].idletime_adr_payload_shifter_en to be 1.
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].stats_adr_payload_shifter_en to be 1.
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].actiondata_adr_payload_shifter_en to be 1.
@@ -773,12 +772,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -853,23 +855,24 @@
Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=14].mau_stats_adr_default to be 0x80000.
Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 23.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 24.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 0 to come from 16-bit PHV container 7.
+Configuring match input crossbar byte 0 to come from 16-bit PHV container 8.
That PHV byte contains {ecmp_metadata.selector[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 23.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 24.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 1 to come from 16-bit PHV container 7.
+Configuring match input crossbar byte 1 to come from 16-bit PHV container 8.
That PHV byte contains {ecmp_metadata.selector[15:8]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 22.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 23.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 2 to come from 16-bit PHV container 6.
+Configuring match input crossbar byte 2 to come from 16-bit PHV container 7.
That PHV byte contains {ecmp_metadata.group_id[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 22.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 23.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 3 to come from 16-bit PHV container 6.
+Configuring match input crossbar byte 3 to come from 16-bit PHV container 7.
That PHV byte contains {ecmp_metadata.group_id[15:8]}.
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0xc0. (previous value = 0x0 OR new value = 0xc0)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x80. (previous value = 0x0 OR new value = 0x80)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=9].match_input_xbar_din_power_ctl to be 0x1. (previous value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.hash.hash_seed[output_bit=2].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.hash.hash_seed[output_bit=3].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.hash.hash_seed[output_bit=5].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
@@ -1765,12 +1768,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -1821,26 +1827,26 @@
Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 18.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 0 to come from 16-bit PHV container 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 18.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 2 to come from 16-bit PHV container 2.
That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 18.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 1 to come from 16-bit PHV container 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 18.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 3 to come from 16-bit PHV container 2.
That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte1 to be 0x1.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=41].byte0 to be 0x1.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=42].byte0 to be 0x2.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=43].byte0 to be 0x4.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=44].byte0 to be 0x8.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=45].byte0 to be 0x10.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=46].byte0 to be 0x20.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=47].byte0 to be 0x40.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=48].byte0 to be 0x80.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=40].byte1 to be 0x1.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=41].byte0 to be 0x1.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=42].byte0 to be 0x2.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=43].byte0 to be 0x4.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=44].byte0 to be 0x8.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=45].byte0 to be 0x10.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=46].byte0 to be 0x20.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=47].byte0 to be 0x40.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=48].byte0 to be 0x80.
Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
@@ -1858,23 +1864,23 @@
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_mode to be 0x2
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff3f
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffff00
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff00
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8
Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x21
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid0 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid1 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][0] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][1] to be 0xffffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff7fff
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xff00ff
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff00ff
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xc (previous value 0x8 OR new value 0x4)
Configuring rams.match.merge.gateway_next_table_lut[0][2] to be 0x21
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid0 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid1 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][0] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][1] to be 0xffffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0x1ffff
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0x3ffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][1] to be 0xffff
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xe (previous value 0xc OR new value 0x2)
Configuring rams.match.merge.gateway_next_table_lut[0][1] to be 0x21
@@ -1900,7 +1906,7 @@
+------------------------------------------------------------------------
| Working on table ingress_port_count_table in stage 2 ---
+------------------------------------------------------------------------
---> Match Table with no key ingress_port_count_table with logical_table_id 0
+--> Hash Action Table ingress_port_count_table with logical_table_id 0
allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
@@ -1920,6 +1926,37 @@
Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2000.
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
+
+---- Hash Distribution Units for table ingress_port_count_table ----
+Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x1)
+Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 16.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 0 to come from 16-bit PHV container 0.
+ That PHV byte contains {ig_intr_md.ingress_port[7:0]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 16.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 1 to come from 16-bit PHV container 0.
+ That PHV byte contains {unused[6:0], ig_intr_md.ingress_port[8:8]}.
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x5. (previous value = 0x4 OR new value = 0x1)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x1)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x1.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte0 to be 0x2.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte0 to be 0x4.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte0 to be 0x8.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte0 to be 0x10.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte0 to be 0x20.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte0 to be 0x40.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte0 to be 0x80.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=8].byte1 to be 0x1.
+Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
+Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 1. (old value = 0 OR new value = 1).
+Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 8. (old value = 0 OR new value = 8).
+Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 1. (old value = 0 OR new value = 1).
+Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x1. (old value = 0x0 OR new value = 0x1).
+Configuring rams.match.merge.mau_hash_group_mask[which_16=0].mau_hash_group_mask to be 0x3ff. (previous value = 0x0 OR new value = 0x3ff)
+Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=3][control_group_index=0].mau_hash_group_xbar_ctl to be 0x8 (old value = 0x0 OR new value = 0x8).
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].stats_adr_payload_shifter_en to be 1.
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
@@ -1931,7 +1968,7 @@
+------------------------------------------------------------------------
| Working on table egress_port_count_table in stage 2 ---
+------------------------------------------------------------------------
---> Match Table with no key egress_port_count_table with logical_table_id 1
+--> Hash Action Table egress_port_count_table with logical_table_id 1
allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
@@ -1951,6 +1988,37 @@
Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2).
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x40.
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
+
+---- Hash Distribution Units for table egress_port_count_table ----
+Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x1 OR new value = 0x2)
+Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_address to be 18.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 8 to come from 16-bit PHV container 2.
+ That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_address to be 18.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 9 to come from 16-bit PHV container 2.
+ That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x5. (previous value = 0x5 OR new value = 0x4)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=1][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=1][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0x1.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=1].byte0 to be 0x2.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=2].byte0 to be 0x4.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=3].byte0 to be 0x8.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=4].byte0 to be 0x10.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=5].byte0 to be 0x20.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=6].byte0 to be 0x40.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=7].byte0 to be 0x80.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=8].byte1 to be 0x1.
+Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x3. (previous value = 0x1 OR new value = 0x2)
+Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 9. (old value = 1 OR new value = 8).
+Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 152. (old value = 8 OR new value = 144).
+Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 65. (old value = 1 OR new value = 64).
+Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x201. (old value = 0x1 OR new value = 0x200).
+Configuring rams.match.merge.mau_hash_group_mask[which_16=3].mau_hash_group_mask to be 0x3ff. (previous value = 0x0 OR new value = 0x3ff)
+Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=3][control_group_index=0].mau_hash_group_xbar_ctl to be 0xb8 (old value = 0x8 OR new value = 0xb0).
--> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 2
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
@@ -1958,11 +2026,11 @@
Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
-Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x0)
+Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x3 OR new value = 0x0)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x0)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
-Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
+Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x3. (previous value = 0x3 OR new value = 0x1)
Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
@@ -2199,12 +2267,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2281,12 +2352,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2363,12 +2437,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2445,12 +2522,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2527,12 +2607,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2609,12 +2692,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2691,12 +2777,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2773,12 +2862,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2855,12 +2947,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2937,12 +3032,15 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=9].phv_ingress_thread to be 0x1.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=9].phv_ingress_thread_alu to be 0x1.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=9].phv_ingress_thread_imem to be 0x1.
Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
@@ -2978,7 +3076,7 @@
Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
+------------------------------------------------------------------------
-| Number of configuration field values set in Match-Action Stages: 2100
+| Number of configuration field values set in Match-Action Stages: 2186
+------------------------------------------------------------------------
+------------------------------------------------------------------------
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gateway.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gateway.log
index e48a0ef..88fe123 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gateway.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gateway.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.gateway.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
@@ -135,13 +135,13 @@
Call to _place_fields_for_constant_comparison
constant_match_key_partition is:
Byte Position 0
- (67, 0)
+ (68, 0)
Byte Position 1
- (67, 0)
+ (68, 0)
Byte Position 2
- (67, 0)
+ (68, 0)
Byte Position 3
- (67, 0)
+ (68, 0)
Available bytes in ram word is [0, 1, 2, 3, 4, 5, 6, 7]
Available data bytes for constants are [0, 1, 2, 3]
@@ -366,13 +366,13 @@
Call to _place_fields_for_constant_comparison
constant_match_key_partition is:
Byte Position 0
- (67, 0)
+ (68, 0)
Byte Position 1
- (67, 0)
+ (68, 0)
Byte Position 2
- (67, 0)
+ (68, 0)
Byte Position 3
- (67, 0)
+ (68, 0)
Available bytes in ram word is [0, 1, 2, 3, 4, 5, 6, 7]
Available data bytes for constants are [0, 1, 2, 3]
@@ -610,13 +610,13 @@
Call to _place_fields_for_constant_comparison
constant_match_key_partition is:
Byte Position 0
- (67, 0)
+ (68, 0)
Byte Position 1
- (67, 0)
+ (68, 0)
Byte Position 2
- (67, 0)
+ (68, 0)
Byte Position 3
- (67, 0)
+ (68, 0)
Available bytes in ram word is [0, 1, 2, 3, 4, 5, 6, 7]
Available data bytes for constants are [0, 1, 2, 3]
@@ -757,7 +757,7 @@
Gateway 14
------- Phase 0 -------------
Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (0, [1], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f5739d6e1d0>, 0)])), (1, (None, [], None, [], []))])
+match_groups_attached_to_gateway = OrderedDict([(0, (0, [1], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7faa2f2f0f10>, 0)])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
----------------------------
Trying to place Gateway Resource Request for table process_packet_out_table_always_true_condition needs access to 0 input bits in exact match group 0 (parity groups [1]) and hash group 0 for gateway 14.
@@ -979,13 +979,13 @@
Call to _place_fields_for_constant_comparison
constant_match_key_partition is:
Byte Position 0
- (67, 0)
+ (68, 0)
Byte Position 1
- (67, 0)
+ (68, 0)
Byte Position 2
- (67, 0)
+ (68, 0)
Byte Position 3
- (67, 0)
+ (68, 0)
Available bytes in ram word is [0, 1, 2, 3, 4, 5, 6, 7]
Available data bytes for constants are [0, 1, 2, 3]
@@ -1126,7 +1126,7 @@
Gateway 14
------- Phase 0 -------------
Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (0, [1], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f573a226b90>, 0)])), (1, (None, [], None, [], []))])
+match_groups_attached_to_gateway = OrderedDict([(0, (0, [1], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7faa2f2cc910>, 0)])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
----------------------------
Trying to place Gateway Resource Request for table process_packet_out_table_always_true_condition needs access to 0 input bits in exact match group 0 (parity groups [1]) and hash group 0 for gateway 14.
@@ -1510,15 +1510,15 @@
[42] = None
[43] = None
Hash Bit Mapping:
- (1, 0) --> 40
- (0, 0) --> 41
- (0, 1) --> 42
- (0, 2) --> 43
- (0, 3) --> 44
- (0, 4) --> 45
- (0, 5) --> 46
- (0, 6) --> 47
- (0, 7) --> 48
+ (3, 0) --> 40
+ (2, 0) --> 41
+ (2, 1) --> 42
+ (2, 2) --> 43
+ (2, 3) --> 44
+ (2, 4) --> 45
+ (2, 5) --> 46
+ (2, 6) --> 47
+ (2, 7) --> 48
Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 2 for gateway
Allocating: Gateway 15 in stage 2 for _condition_2.
@@ -1757,15 +1757,15 @@
[42] = None
[43] = None
Hash Bit Mapping:
- (1, 0) --> 40
- (0, 0) --> 41
- (0, 1) --> 42
- (0, 2) --> 43
- (0, 3) --> 44
- (0, 4) --> 45
- (0, 5) --> 46
- (0, 6) --> 47
- (0, 7) --> 48
+ (3, 0) --> 40
+ (2, 0) --> 41
+ (2, 1) --> 42
+ (2, 2) --> 43
+ (2, 3) --> 44
+ (2, 4) --> 45
+ (2, 5) --> 46
+ (2, 6) --> 47
+ (2, 7) --> 48
Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 2 for gateway
Allocating: Gateway 15 in stage 2 for _condition_2.
@@ -1861,7 +1861,7 @@
match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
- final_parity_group_ids = [(0, []), (1, [])]
+ final_parity_group_ids = [(0, [0]), (1, [])]
open_parity_group_ids = [0, 1]
----------------------------
@@ -2004,15 +2004,15 @@
[42] = None
[43] = None
Hash Bit Mapping:
- (1, 0) --> 40
- (0, 0) --> 41
- (0, 1) --> 42
- (0, 2) --> 43
- (0, 3) --> 44
- (0, 4) --> 45
- (0, 5) --> 46
- (0, 6) --> 47
- (0, 7) --> 48
+ (3, 0) --> 40
+ (2, 0) --> 41
+ (2, 1) --> 42
+ (2, 2) --> 43
+ (2, 3) --> 44
+ (2, 4) --> 45
+ (2, 5) --> 46
+ (2, 6) --> 47
+ (2, 7) --> 48
Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 2 for gateway
Allocating: Gateway 15 in stage 2 for _condition_2.
@@ -2121,7 +2121,7 @@
match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
- final_parity_group_ids = [(0, []), (1, [])]
+ final_parity_group_ids = [(0, [0]), (1, [])]
open_parity_group_ids = [0, 1]
----------------------------
@@ -2264,15 +2264,15 @@
[42] = None
[43] = None
Hash Bit Mapping:
- (1, 0) --> 40
- (0, 0) --> 41
- (0, 1) --> 42
- (0, 2) --> 43
- (0, 3) --> 44
- (0, 4) --> 45
- (0, 5) --> 46
- (0, 6) --> 47
- (0, 7) --> 48
+ (3, 0) --> 40
+ (2, 0) --> 41
+ (2, 1) --> 42
+ (2, 2) --> 43
+ (2, 3) --> 44
+ (2, 4) --> 45
+ (2, 5) --> 46
+ (2, 6) --> 47
+ (2, 7) --> 48
Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 2 for gateway
Allocating: Gateway 15 in stage 2 for _condition_2.
@@ -2294,7 +2294,7 @@
Gateway 14
------- Phase 0 -------------
Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f573df7c290>, 0)])), (1, (None, [], None, [], []))])
+match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7faa32fe2250>, 0)])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
----------------------------
Trying to place Gateway Resource Request for table egress_port_count_table_always_true_condition needs access to 0 input bits in exact match group 0 (parity groups [0]) and hash group 0 for gateway 14.
@@ -2506,7 +2506,7 @@
match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
- final_parity_group_ids = [(0, []), (1, [])]
+ final_parity_group_ids = [(0, [0]), (1, [])]
open_parity_group_ids = [0, 1]
----------------------------
@@ -2649,15 +2649,15 @@
[42] = None
[43] = None
Hash Bit Mapping:
- (1, 0) --> 40
- (0, 0) --> 41
- (0, 1) --> 42
- (0, 2) --> 43
- (0, 3) --> 44
- (0, 4) --> 45
- (0, 5) --> 46
- (0, 6) --> 47
- (0, 7) --> 48
+ (3, 0) --> 40
+ (2, 0) --> 41
+ (2, 1) --> 42
+ (2, 2) --> 43
+ (2, 3) --> 44
+ (2, 4) --> 45
+ (2, 5) --> 46
+ (2, 6) --> 47
+ (2, 7) --> 48
Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 2 for gateway
Allocating: Gateway 15 in stage 2 for _condition_2.
@@ -2679,7 +2679,7 @@
Gateway 14
------- Phase 0 -------------
Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f573a425a10>, 0)])), (1, (None, [], None, [], []))])
+match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7faa2f4d0790>, 0)])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
----------------------------
Trying to place Gateway Resource Request for table egress_port_count_table_always_true_condition needs access to 0 input bits in exact match group 0 (parity groups [0]) and hash group 0 for gateway 14.
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gw.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gw.log
index 97a672b..84d4242 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gw.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gw.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.gw.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
cond _condition_0: not valid packet_out_hdr
@@ -10,13 +10,13 @@
cond _condition_0 can be gateway (1+0)x1
cond !_condition_0 can be gateway (1+0)x1
_condition_0 is gateway for table0
-cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 510
- ig_intr_md_for_tm.ucast_egress_port < 510
- ! ig_intr_md_for_tm.ucast_egress_port >= 510
+cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 512
+ ig_intr_md_for_tm.ucast_egress_port < 512
+ ! ig_intr_md_for_tm.ucast_egress_port >= 512
cond _condition_2 can be gateway (9+0)x1
cond !_condition_2 can be gateway (9+0)x1
_condition_2 is gateway for ingress_port_count_table
-fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f573eab9c90>]) and and xor_fields is OrderedSet()
+fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7faa33b02c50>]) and and xor_fields is OrderedSet()
fields = OrderedSet() and and xor_fields is OrderedSet()
cond _condition_0: not valid packet_out_hdr
not valid packet_out_hdr
@@ -24,13 +24,13 @@
cond _condition_0 can be gateway (1+0)x1
cond !_condition_0 can be gateway (1+0)x1
_condition_0 is gateway for table0
-cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 510
- ig_intr_md_for_tm.ucast_egress_port < 510
- ! ig_intr_md_for_tm.ucast_egress_port >= 510
+cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 512
+ ig_intr_md_for_tm.ucast_egress_port < 512
+ ! ig_intr_md_for_tm.ucast_egress_port >= 512
cond _condition_2 can be gateway (9+0)x1
cond !_condition_2 can be gateway (9+0)x1
_condition_2 is gateway for ingress_port_count_table
-fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f573eab9c90>]) and and xor_fields is OrderedSet()
+fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7faa33b02c50>]) and and xor_fields is OrderedSet()
fields = OrderedSet() and and xor_fields is OrderedSet()
cond _condition_0: not valid packet_out_hdr
not valid packet_out_hdr
@@ -38,13 +38,13 @@
cond _condition_0 can be gateway (1+0)x1
cond !_condition_0 can be gateway (1+0)x1
_condition_0 is gateway for table0
-cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 510
- ig_intr_md_for_tm.ucast_egress_port < 510
- ! ig_intr_md_for_tm.ucast_egress_port >= 510
+cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 512
+ ig_intr_md_for_tm.ucast_egress_port < 512
+ ! ig_intr_md_for_tm.ucast_egress_port >= 512
cond _condition_2 can be gateway (9+0)x1
cond !_condition_2 can be gateway (9+0)x1
_condition_2 is gateway for ingress_port_count_table
-fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f573eab9c90>]) and and xor_fields is OrderedSet()
+fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7faa33b02c50>]) and and xor_fields is OrderedSet()
fields = OrderedSet() and and xor_fields is OrderedSet()
cond _always_true: True == True
True
@@ -66,12 +66,12 @@
final.tcam: [(match=0 mask=0 T)], miss=False
--> Stage Gateway Table for condition _condition_2 in stage 2
T -> ingress_port_count_table(32), F -> None(255)
-building tcam for GatewayTest('ig_intr_md_for_tm.ucast_egress_port < 510')
- adding line (range=[ffff ffff 3fff] match=0 mask=0 T)
- adding line (range=[ffff 7fff ffff] match=0 mask=0 T)
- adding line (range=[1 ffff ffff] match=0 mask=0 T)
-tcam data: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[1 ffff ffff] match=0 mask=0 T)]
-final.tcam: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[1 ffff ffff] match=0 mask=0 T)], miss=False
+building tcam for GatewayTest('ig_intr_md_for_tm.ucast_egress_port < 512')
+ adding line (range=[ffff ffff 0] match=0 mask=0 T)
+ adding line (range=[ffff 0 ffff] match=0 mask=0 T)
+ adding line (range=[3 ffff ffff] match=0 mask=0 T)
+tcam data: [(range=[ffff ffff 0] match=0 mask=0 T), (range=[ffff 0 ffff] match=0 mask=0 T), (range=[3 ffff ffff] match=0 mask=0 T)]
+final.tcam: [(range=[ffff ffff 0] match=0 mask=0 T), (range=[ffff 0 ffff] match=0 mask=0 T), (range=[3 ffff ffff] match=0 mask=0 T)], miss=False
--> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 2
T -> egress_port_count_table(33), F -> egress_port_count_table(33)
building tcam for GatewayTest('True')
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.log
index d04ab40..bf2704f 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
Match Table table0 did not specify the number of entries required. A default value (512) will be used.
@@ -21,129 +21,7 @@
Match Entry Table table0 has already been associated with stat Table table0_counter.
Match Entry Table ecmp_group_table has already been associated with stat Table ecmp_group_table_counter.
Match table ingress_port_count_table has no match key fields
-Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 510.
-
-##########################################
- Call to decide_action_data_placement(stage=0, table=ingress_port_count_table)
-##########################################
-
-
-Max immediate bits used in any action is 0 bits.
-Overhead bit width for table ingress_port_count_table is 22 bits.
-Bits available in overhead for non-essential immediate data is 32 bits.
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 0 bits in match overhead
-Overhead bit width for table ingress_port_count_table is 22 bits.
-Overhead SRAMs to use = 97
- Entries requested = 1024 and match entries get = 0
-ram_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-immediate_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-hash_to_phv_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action count_ingress has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action count_ingress has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action count_ingress has []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-Action Data SRAMs to use = 0
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 8 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 16 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 24 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 32 bits in match overhead
-
-##########################################
-
-Best Ram Usage is 97 rams
-Best Immediate placement is 0 bits
Match table egress_port_count_table has no match key fields
-Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 510.
-
-##########################################
- Call to decide_action_data_placement(stage=0, table=egress_port_count_table)
-##########################################
-
-
-Max immediate bits used in any action is 0 bits.
-Overhead bit width for table egress_port_count_table is 20 bits.
-Bits available in overhead for non-essential immediate data is 32 bits.
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 0 bits in match overhead
-Overhead bit width for table egress_port_count_table is 20 bits.
-Overhead SRAMs to use = 97
- Entries requested = 1024 and match entries get = 0
-ram_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-immediate_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-hash_to_phv_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action count_egress has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action count_egress has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action count_egress has []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-Action Data SRAMs to use = 0
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 8 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 16 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 24 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 32 bits in match overhead
-
-##########################################
-
-Best Ram Usage is 97 rams
-Best Immediate placement is 0 bits
##########################################
Call to decide_action_data_placement(stage=0, table=process_packet_out_table)
@@ -515,8 +393,8 @@
final packing is [(16, 0, False)]
----------------------------------------------
Call to allocate_hash_distribution_units with
- hash_algorithm = crc32
- hash_output_width = 32
+ hash_algorithm = crc16
+ hash_output_width = 16
hash_bits_need = 1
output_hash_bit_start = 0
immediate_bit_positions = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
@@ -525,17 +403,17 @@
available_tuples_sorted_by_parity_bytes_available = [(0, 3, 0), (1, 3, 0)]
available_tuples_split_sorted_by_parity_bytes_available = []
Allocate fresh exact match group / hash group
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {udp.dstPort[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {udp.dstPort[15:8]}.
-Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {udp.srcPort[7:0]}.
-Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {udp.srcPort[15:8]}.
-Allocating: Byte 4 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[7:0]}.
-Allocating: Byte 5 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[15:8]}.
-Allocating: Byte 6 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[23:16]}.
+Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[7:0]}.
+Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[15:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[23:16]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {tcp.dstPort[7:0]}.
+Allocating: Byte 4 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.srcAddr[31:24]}.
+Allocating: Byte 5 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {tcp.srcPort[7:0]}.
+Allocating: Byte 6 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {tcp.dstPort[15:8]}.
Allocating: Byte 7 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[31:24]}.
-Allocating: Byte 8 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ipv4.srcAddr[31:24]}.
+Allocating: Byte 8 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ipv4.srcAddr[7:0]}.
Allocating: Byte 9 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ipv4.srcAddr[15:8]}.
-Allocating: Byte 10 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ipv4.srcAddr[7:0]}.
+Allocating: Byte 10 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {tcp.srcPort[15:8]}.
Allocating: Byte 11 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ipv4.srcAddr[23:16]}.
-------------------
Call to _allocate_hash_distribution_and_hash_bits
@@ -548,10 +426,12 @@
-------------------
Allocating Hash Distribution Group 0/0 for table table0__action__ in stage 0.
Allocating Hash Bit 0 in hash match group 0 for table table0__action__ in stage 0.
-seed = 0x7bd5c66f
-set the seed to be [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+total_hash_result_bits = 16
+polynomial_as_hex_int = 0x18005
+seed = 0x0
+set the seed to be [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
Hash Function 0
-hash_bit_0 = udp.dstPort[2] ^ udp.dstPort[8] ^ udp.dstPort[12] ^ udp.dstPort[14] ^ udp.dstPort[15] ^ udp.srcPort[0] ^ udp.srcPort[8] ^ udp.srcPort[9] ^ udp.srcPort[10] ^ udp.srcPort[11] ^ udp.srcPort[12] ^ udp.srcPort[14] ^ udp.srcPort[15] ^ ipv4.dstAddr[3] ^ ipv4.dstAddr[6] ^ ipv4.dstAddr[8] ^ ipv4.dstAddr[9] ^ ipv4.dstAddr[11] ^ ipv4.dstAddr[12] ^ ipv4.dstAddr[17] ^ ipv4.dstAddr[18] ^ ipv4.dstAddr[19] ^ ipv4.dstAddr[22] ^ ipv4.dstAddr[25] ^ ipv4.dstAddr[27] ^ ipv4.dstAddr[28] ^ ipv4.dstAddr[30] ^ ipv4.srcAddr[24] ^ ipv4.srcAddr[25] ^ ipv4.srcAddr[26] ^ ipv4.srcAddr[9] ^ ipv4.srcAddr[15] ^ ipv4.srcAddr[0] ^ ipv4.srcAddr[4] ^ ipv4.srcAddr[5] ^ ipv4.srcAddr[6] ^ ipv4.srcAddr[7] ^ ipv4.srcAddr[17] ^ ipv4.srcAddr[19] ^ ipv4.srcAddr[20] ^ ipv4.srcAddr[21] ^ ipv4.srcAddr[22] ^ ipv4.srcAddr[23] ^ 1
+hash_bit_0 = ipv4.dstAddr[0] ^ ipv4.dstAddr[1] ^ ipv4.dstAddr[2] ^ ipv4.dstAddr[3] ^ ipv4.dstAddr[4] ^ ipv4.dstAddr[5] ^ ipv4.dstAddr[6] ^ ipv4.dstAddr[7] ^ ipv4.dstAddr[8] ^ ipv4.dstAddr[9] ^ ipv4.dstAddr[10] ^ ipv4.dstAddr[11] ^ ipv4.dstAddr[13] ^ ipv4.dstAddr[15] ^ ipv4.dstAddr[17] ^ ipv4.dstAddr[18] ^ ipv4.dstAddr[19] ^ ipv4.dstAddr[20] ^ ipv4.dstAddr[21] ^ ipv4.dstAddr[22] ^ ipv4.dstAddr[23] ^ tcp.dstPort[0] ^ tcp.dstPort[1] ^ tcp.dstPort[2] ^ tcp.dstPort[3] ^ tcp.dstPort[4] ^ tcp.dstPort[5] ^ tcp.dstPort[6] ^ tcp.dstPort[7] ^ ipv4.srcAddr[24] ^ ipv4.srcAddr[25] ^ ipv4.srcAddr[26] ^ ipv4.srcAddr[27] ^ ipv4.srcAddr[28] ^ ipv4.srcAddr[29] ^ ipv4.srcAddr[30] ^ tcp.srcPort[0] ^ tcp.srcPort[1] ^ tcp.srcPort[2] ^ tcp.srcPort[3] ^ tcp.srcPort[4] ^ tcp.srcPort[5] ^ tcp.srcPort[6] ^ tcp.srcPort[7] ^ tcp.dstPort[8] ^ tcp.dstPort[9] ^ tcp.dstPort[11] ^ tcp.dstPort[12] ^ tcp.dstPort[13] ^ tcp.dstPort[14] ^ tcp.dstPort[15] ^ ipv4.dstAddr[24] ^ ipv4.dstAddr[25] ^ ipv4.dstAddr[26] ^ ipv4.dstAddr[27] ^ ipv4.dstAddr[28] ^ ipv4.srcAddr[0] ^ ipv4.srcAddr[1] ^ ipv4.srcAddr[3] ^ ipv4.srcAddr[4] ^ ipv4.srcAddr[5] ^ ipv4.srcAddr[6] ^ ipv4.srcAddr[7] ^ ipv4.srcAddr[8] ^ ipv4.srcAddr[9] ^ ipv4.srcAddr[10] ^ ipv4.srcAddr[11] ^ ipv4.srcAddr[12] ^ ipv4.srcAddr[13] ^ ipv4.srcAddr[15] ^ tcp.srcPort[8] ^ tcp.srcPort[9] ^ tcp.srcPort[10] ^ tcp.srcPort[13] ^ tcp.srcPort[14] ^ tcp.srcPort[15] ^ ipv4.srcAddr[17] ^ ipv4.srcAddr[18] ^ ipv4.srcAddr[21] ^ ipv4.srcAddr[22] ^ ipv4.srcAddr[23] ^ 0
hash_bit_1 = 0
hash_bit_2 = 0
hash_bit_3 = 0
@@ -710,23 +590,23 @@
Allocating Action ALU 2 (16 bits) in stage 0 for match table table0's action set_egress_port
Allocating VLIW Instruction : 0 in stage 0 for match table table0's action set_egress_port
For action ecmp_group, formed micro_instruction:
-Micro Instruction alu_a for PHV Container 134 has bit width 23
- Field Src2 [3:0] : 0x6 (4 bits in instruction bits [3:0])
+Micro Instruction alu_a for PHV Container 135 has bit width 23
+ Field Src2 [3:0] : 0x7 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20])
For action ecmp_group, formed micro_instruction:
-Micro Instruction alu_a for PHV Container 135 has bit width 23
- Field Src2 [3:0] : 0x7 (4 bits in instruction bits [3:0])
+Micro Instruction alu_a for PHV Container 136 has bit width 23
+ Field Src2 [3:0] : 0x8 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x2 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20])
-Allocating Action ALU 6 (16 bits) in stage 0 for match table table0's action ecmp_group
Allocating Action ALU 7 (16 bits) in stage 0 for match table table0's action ecmp_group
+Allocating Action ALU 8 (16 bits) in stage 0 for match table table0's action ecmp_group
Allocating VLIW Instruction : 1 in stage 0 for match table table0's action ecmp_group
For action send_to_cpu, formed micro_instruction:
Micro Instruction deposit-field for PHV Container 130 has bit width 23
@@ -740,8 +620,8 @@
Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
For action send_to_cpu, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 67 has bit width 20
- Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
+Micro Instruction deposit-field for PHV Container 68 has bit width 20
+ Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -762,12 +642,12 @@
Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20])
Allocating Action ALU 2 (16 bits) in stage 0 for match table table0's action send_to_cpu
-Allocating Action ALU 3 (8 bits) in stage 0 for match table table0's action send_to_cpu
+Allocating Action ALU 4 (8 bits) in stage 0 for match table table0's action send_to_cpu
Allocating Action ALU 1 (16 bits) in stage 0 for match table table0's action send_to_cpu
Allocating VLIW Instruction : 1 in stage 0 for match table table0's action send_to_cpu
For action _drop, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 68 has bit width 20
- Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
+Micro Instruction deposit-field for PHV Container 69 has bit width 20
+ Field Src2 [3:0] : 0x5 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -776,7 +656,7 @@
Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16])
Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19])
-Allocating Action ALU 4 (8 bits) in stage 0 for match table table0's action _drop
+Allocating Action ALU 5 (8 bits) in stage 0 for match table table0's action _drop
Allocating VLIW Instruction : 2 in stage 0 for match table table0's action _drop
Ternary table Pack Format =
Pack Format:
@@ -880,8 +760,8 @@
Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
For action _process_packet_out, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 67 has bit width 20
- Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
+Micro Instruction deposit-field for PHV Container 68 has bit width 20
+ Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -891,7 +771,7 @@
Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
Allocating Action ALU 2 (16 bits) in stage 0 for match table process_packet_out_table's action _process_packet_out
-Allocating Action ALU 3 (8 bits) in stage 0 for match table process_packet_out_table's action _process_packet_out
+Allocating Action ALU 4 (8 bits) in stage 0 for match table process_packet_out_table's action _process_packet_out
Allocating VLIW Instruction : 2 in stage 0 for match table process_packet_out_table's action _process_packet_out
----------------------------------------------
@@ -1143,7 +1023,7 @@
Allocating Action Logical Table ID 0 in stage 2
----------------------------------------------
-Call to Allocate P4 Table with table ingress_port_counter, number_entries = 510, table id = None, and match type = exact
+Call to Allocate P4 Table with table ingress_port_counter, number_entries = 512, table id = None, and match type = exact
Allocating in stage 2
----------------------------------------------
@@ -1172,23 +1052,185 @@
Logical Table ID in stage 2 was not supplied by table placement for table ingress_port_count_table.
Allocating Logical Table ID 0 in stage 2
Allocating Table Type ID 0 of type exact in stage 2
-Match Overhead:
- Field --version_valid-- [3:0] (4 bits)
- Field --instruction_address-- [1:0] (2 bits)
- Field --statistics_pointer-- [19:0] (20 bits)
+Too few bits (9) specified to address ingress_port_counter from table ingress_port_count_table. 10 are needed.
+The most significant 1 bit will be padded with zeros.
+----------------------------------------------
+ Call to allocate_hash_distribution_units with
+ hash_algorithm = identity
+ hash_output_width = 10
+ hash_bits_need = 10
+ output_hash_bit_start = 0
+ immediate_bit_positions = None
+ used_for = Statistics Address
+----------------------------------------------
+available_tuples_sorted_by_parity_bytes_available = [(0, 3, 0), (1, 3, 0)]
+available_tuples_split_sorted_by_parity_bytes_available = []
+Allocate fresh exact match group / hash group
+Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md.ingress_port[7:0]}.
+Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md.ingress_port[8:8]}.
+-------------------
+Call to _allocate_hash_distribution_and_hash_bits
+ p4_table = ingress_port_count_table
+ used_for = Statistics Address
+ hash_distribution_hash_id = 0
+ hash_group_id = 0
+ hash_bits_in_units = OrderedDict([(0, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9])])
+ address_left_shift = 1
+-------------------
+Allocating Hash Distribution Group 0/0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 0 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 1 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 2 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 3 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 4 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 5 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 6 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 7 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 8 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 9 in hash match group 0 for table ingress_port_count_table in stage 2.
+seed = 0x0
+set the seed to be [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+Hash Function 0
+hash_bit_0 = ig_intr_md.ingress_port[0] ^ 0
+hash_bit_1 = ig_intr_md.ingress_port[1] ^ 0
+hash_bit_2 = ig_intr_md.ingress_port[2] ^ 0
+hash_bit_3 = ig_intr_md.ingress_port[3] ^ 0
+hash_bit_4 = ig_intr_md.ingress_port[4] ^ 0
+hash_bit_5 = ig_intr_md.ingress_port[5] ^ 0
+hash_bit_6 = ig_intr_md.ingress_port[6] ^ 0
+hash_bit_7 = ig_intr_md.ingress_port[7] ^ 0
+hash_bit_8 = ig_intr_md.ingress_port[8] ^ 0
+hash_bit_9 = 0
+hash_bit_10 = 0
+hash_bit_11 = 0
+hash_bit_12 = 0
+hash_bit_13 = 0
+hash_bit_14 = 0
+hash_bit_15 = 0
+hash_bit_16 = 0
+hash_bit_17 = 0
+hash_bit_18 = 0
+hash_bit_19 = 0
+hash_bit_20 = 0
+hash_bit_21 = 0
+hash_bit_22 = 0
+hash_bit_23 = 0
+hash_bit_24 = 0
+hash_bit_25 = 0
+hash_bit_26 = 0
+hash_bit_27 = 0
+hash_bit_28 = 0
+hash_bit_29 = 0
+hash_bit_30 = 0
+hash_bit_31 = 0
+hash_bit_32 = 0
+hash_bit_33 = 0
+hash_bit_34 = 0
+hash_bit_35 = 0
+hash_bit_36 = 0
+hash_bit_37 = 0
+hash_bit_38 = 0
+hash_bit_39 = 0
+hash_bit_40 = 0
+hash_bit_41 = 0
+hash_bit_42 = 0
+hash_bit_43 = 0
+hash_bit_44 = 0
+hash_bit_45 = 0
+hash_bit_46 = 0
+hash_bit_47 = 0
+hash_bit_48 = 0
+hash_bit_49 = 0
+hash_bit_50 = 0
+hash_bit_51 = 0
-Logical Table ID in stage 2 was not supplied by table placement for table ingress_port_count_table.
-Allocating Logical Table ID 0 in stage 2
-Allocating Table Type ID 0 of type exact in stage 2
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
Match Table Resource Request is:
SRAM Resource Request for table ingress_port_count_table (of type match), with 0 ways wants 0 rams.
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
No micro instructions needed for action count_ingress executed from table ingress_port_count_table.
Allocating Action ALU 0 (32 bits) in stage 2 for match table ingress_port_count_table's action count_ingress
Allocating VLIW Instruction : 0 in stage 2 for match table ingress_port_count_table's action count_ingress
+My hash-action stage table is
+StageHashActionTable
+ stage_number: 2
+ number_entries 1024
+ pack_format:
+ Pack Format:
+ table_word_width: 0
+ memory_word_width: 0
+ entries_per_table_word: 0
+ number_memory_units_per_table_word: 0
+ entry_list: [
+]
+
+ p4_table: 'ingress_port_count_table'
+ stage_table_handle: 0
+ stage_table_type_handle: 0
+ stage_gateway_table: StageGatewayTable
+ stage_number: 2
+ number_entries 0
+ memory_resource_allocation GatewayMemoryResourceAllocation:
+ memory_type: gateway
+ memory_units: [[15]]
+ home_row: -1
+ stateful_action_bus_output: None
+
+ p4_table: '_condition_2'
+
+ match_group_resource_allocation:
+ vliw_resource_allocation:
+ action handle 536870914 maps to:
+VliwResourceAllocation:
+ match_table_name: ingress_port_count_table
+ p4_action: count_ingress
+ address_to_use: 1
+ full_address: 64
+ vliw_instruction_number: 0
+ color: 0
+ direction: ingress
+ micro_instructions:
+
+ action_to_vliw_mapping:
+ action handle 536870914 maps to vliw instruction 0, color 0, and direction ingress and is found in instruction address 1
+ hash_distribution_usages:
+ MAU Hash Distribution Resource Usage for P4 table ingress_port_count_table
+ exact_match_group_resource_allocation : HashMatchGroupResourceAllocation:
+ match_groups: [(0, 16)]
+ match_group_key_bit_width: 9
+ match_group_phv_bit_scrambling: OrderedDict([(('ig_intr_md.ingress_port', 0), 0), (('ig_intr_md.ingress_port', 1), 1), (('ig_intr_md.ingress_port', 2), 2), (('ig_intr_md.ingress_port', 3), 3), (('ig_intr_md.ingress_port', 4), 4), (('ig_intr_md.ingress_port', 5), 5), (('ig_intr_md.ingress_port', 6), 6), (('ig_intr_md.ingress_port', 7), 7), (('ig_intr_md.ingress_port', 8), 8)])
+ ('ig_intr_md.ingress_port', 0) -> 0
+ ('ig_intr_md.ingress_port', 1) -> 1
+ ('ig_intr_md.ingress_port', 2) -> 2
+ ('ig_intr_md.ingress_port', 3) -> 3
+ ('ig_intr_md.ingress_port', 4) -> 4
+ ('ig_intr_md.ingress_port', 5) -> 5
+ ('ig_intr_md.ingress_port', 6) -> 6
+ ('ig_intr_md.ingress_port', 7) -> 7
+ ('ig_intr_md.ingress_port', 8) -> 8
+ hash_function_dictionary: OrderedDict([(0, <p4c_tofino.target.tofino.llir.mau.stage.resources.hash_function.HashFunction object at 0x7faa2f4d0750>)])
+ hash_group_id: 0
+ seed: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+ table_direction: ingress
+
+ hash_distribution_resource_allocations :
+Hash Distribution:
+ source_hash_group : 0
+ hash_distribution_hash_id : 0
+ hash_distribution_group_id : 0
+ hash_distribution_used_for : Statistics Address
+ table_direction : ingress
+ bits_to_use : [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]
+ left_shift : 1
+ expanded_lo : False
+ expanded_hi : False
+ expanded_bit_width : 0
+ immediate_position : unused
+
+
+
----------------------------------------------
Call to Allocate P4 Table with table egress_port_count_table__action__, number_entries = 1024, table id = None, and match type = exact
@@ -1228,7 +1270,7 @@
Allocating Action Logical Table ID 1 in stage 2
----------------------------------------------
-Call to Allocate P4 Table with table egress_port_counter, number_entries = 510, table id = None, and match type = exact
+Call to Allocate P4 Table with table egress_port_counter, number_entries = 512, table id = None, and match type = exact
Allocating in stage 2
----------------------------------------------
@@ -1248,8 +1290,8 @@
ram_word_select_bits : 0
ram_enable_select_bits : 0
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
----------------------------------------------
Call to Allocate P4 Table with table egress_port_count_table, number_entries = 1024, table id = None, and match type = exact
@@ -1259,22 +1301,185 @@
Logical Table ID in stage 2 was not supplied by table placement for table egress_port_count_table.
Allocating Logical Table ID 1 in stage 2
Allocating Table Type ID 1 of type exact in stage 2
-Match Overhead:
- Field --version_valid-- [3:0] (4 bits)
- Field --statistics_pointer-- [19:0] (20 bits)
+Too few bits (9) specified to address egress_port_counter from table egress_port_count_table. 10 are needed.
+The most significant 1 bit will be padded with zeros.
+----------------------------------------------
+ Call to allocate_hash_distribution_units with
+ hash_algorithm = identity
+ hash_output_width = 10
+ hash_bits_need = 10
+ output_hash_bit_start = 0
+ immediate_bit_positions = None
+ used_for = Statistics Address
+----------------------------------------------
+available_tuples_sorted_by_parity_bytes_available = [(1, 3, 0), (0, 2, 4)]
+available_tuples_split_sorted_by_parity_bytes_available = []
+Allocate fresh exact match group / hash group
+Allocating: Byte 8 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 9 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+-------------------
+Call to _allocate_hash_distribution_and_hash_bits
+ p4_table = egress_port_count_table
+ used_for = Statistics Address
+ hash_distribution_hash_id = 1
+ hash_group_id = 1
+ hash_bits_in_units = OrderedDict([(0, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9])])
+ address_left_shift = 1
+-------------------
+Allocating Hash Distribution Group 1/0 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 0 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 1 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 2 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 3 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 4 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 5 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 6 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 7 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 8 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 9 in hash match group 1 for table egress_port_count_table in stage 2.
+seed = 0x0
+set the seed to be [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+Hash Function 0
+hash_bit_0 = ig_intr_md_for_tm.ucast_egress_port[0] ^ 0
+hash_bit_1 = ig_intr_md_for_tm.ucast_egress_port[1] ^ 0
+hash_bit_2 = ig_intr_md_for_tm.ucast_egress_port[2] ^ 0
+hash_bit_3 = ig_intr_md_for_tm.ucast_egress_port[3] ^ 0
+hash_bit_4 = ig_intr_md_for_tm.ucast_egress_port[4] ^ 0
+hash_bit_5 = ig_intr_md_for_tm.ucast_egress_port[5] ^ 0
+hash_bit_6 = ig_intr_md_for_tm.ucast_egress_port[6] ^ 0
+hash_bit_7 = ig_intr_md_for_tm.ucast_egress_port[7] ^ 0
+hash_bit_8 = ig_intr_md_for_tm.ucast_egress_port[8] ^ 0
+hash_bit_9 = 0
+hash_bit_10 = 0
+hash_bit_11 = 0
+hash_bit_12 = 0
+hash_bit_13 = 0
+hash_bit_14 = 0
+hash_bit_15 = 0
+hash_bit_16 = 0
+hash_bit_17 = 0
+hash_bit_18 = 0
+hash_bit_19 = 0
+hash_bit_20 = 0
+hash_bit_21 = 0
+hash_bit_22 = 0
+hash_bit_23 = 0
+hash_bit_24 = 0
+hash_bit_25 = 0
+hash_bit_26 = 0
+hash_bit_27 = 0
+hash_bit_28 = 0
+hash_bit_29 = 0
+hash_bit_30 = 0
+hash_bit_31 = 0
+hash_bit_32 = 0
+hash_bit_33 = 0
+hash_bit_34 = 0
+hash_bit_35 = 0
+hash_bit_36 = 0
+hash_bit_37 = 0
+hash_bit_38 = 0
+hash_bit_39 = 0
+hash_bit_40 = 0
+hash_bit_41 = 0
+hash_bit_42 = 0
+hash_bit_43 = 0
+hash_bit_44 = 0
+hash_bit_45 = 0
+hash_bit_46 = 0
+hash_bit_47 = 0
+hash_bit_48 = 0
+hash_bit_49 = 0
+hash_bit_50 = 0
+hash_bit_51 = 0
-Logical Table ID in stage 2 was not supplied by table placement for table egress_port_count_table.
-Allocating Logical Table ID 1 in stage 2
-Allocating Table Type ID 1 of type exact in stage 2
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
Match Table Resource Request is:
SRAM Resource Request for table egress_port_count_table (of type match), with 0 ways wants 0 rams.
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
No micro instructions needed for action count_egress executed from table egress_port_count_table.
Allocating Action ALU 0 (32 bits) in stage 2 for match table egress_port_count_table's action count_egress
Allocating VLIW Instruction : 0 in stage 2 for match table egress_port_count_table's action count_egress
+My hash-action stage table is
+StageHashActionTable
+ stage_number: 2
+ number_entries 1024
+ pack_format:
+ Pack Format:
+ table_word_width: 0
+ memory_word_width: 0
+ entries_per_table_word: 0
+ number_memory_units_per_table_word: 0
+ entry_list: [
+]
+
+ p4_table: 'egress_port_count_table'
+ stage_table_handle: 1
+ stage_table_type_handle: 1
+ stage_gateway_table: StageGatewayTable
+ stage_number: 2
+ number_entries 0
+ memory_resource_allocation GatewayMemoryResourceAllocation:
+ memory_type: gateway
+ memory_units: [[14]]
+ home_row: -1
+ stateful_action_bus_output: None
+
+ p4_table: 'egress_port_count_table_always_true_condition'
+
+ match_group_resource_allocation:
+ vliw_resource_allocation:
+ action handle 536870916 maps to:
+VliwResourceAllocation:
+ match_table_name: egress_port_count_table
+ p4_action: count_egress
+ address_to_use: 0
+ full_address: 64
+ vliw_instruction_number: 0
+ color: 0
+ direction: ingress
+ micro_instructions:
+
+ action_to_vliw_mapping:
+ action handle 536870916 maps to vliw instruction 0, color 0, and direction ingress and is found in instruction address 0
+ hash_distribution_usages:
+ MAU Hash Distribution Resource Usage for P4 table egress_port_count_table
+ exact_match_group_resource_allocation : HashMatchGroupResourceAllocation:
+ match_groups: [(0, 16)]
+ match_group_key_bit_width: 73
+ match_group_phv_bit_scrambling: OrderedDict([(('ig_intr_md_for_tm.ucast_egress_port', 0), 64), (('ig_intr_md_for_tm.ucast_egress_port', 1), 65), (('ig_intr_md_for_tm.ucast_egress_port', 2), 66), (('ig_intr_md_for_tm.ucast_egress_port', 3), 67), (('ig_intr_md_for_tm.ucast_egress_port', 4), 68), (('ig_intr_md_for_tm.ucast_egress_port', 5), 69), (('ig_intr_md_for_tm.ucast_egress_port', 6), 70), (('ig_intr_md_for_tm.ucast_egress_port', 7), 71), (('ig_intr_md_for_tm.ucast_egress_port', 8), 72)])
+ ('ig_intr_md_for_tm.ucast_egress_port', 0) -> 64
+ ('ig_intr_md_for_tm.ucast_egress_port', 1) -> 65
+ ('ig_intr_md_for_tm.ucast_egress_port', 2) -> 66
+ ('ig_intr_md_for_tm.ucast_egress_port', 3) -> 67
+ ('ig_intr_md_for_tm.ucast_egress_port', 4) -> 68
+ ('ig_intr_md_for_tm.ucast_egress_port', 5) -> 69
+ ('ig_intr_md_for_tm.ucast_egress_port', 6) -> 70
+ ('ig_intr_md_for_tm.ucast_egress_port', 7) -> 71
+ ('ig_intr_md_for_tm.ucast_egress_port', 8) -> 72
+ hash_function_dictionary: OrderedDict([(0, <p4c_tofino.target.tofino.llir.mau.stage.resources.hash_function.HashFunction object at 0x7faa2f064690>)])
+ hash_group_id: 1
+ seed: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+ table_direction: ingress
+
+ hash_distribution_resource_allocations :
+Hash Distribution:
+ source_hash_group : 1
+ hash_distribution_hash_id : 1
+ hash_distribution_group_id : 0
+ hash_distribution_used_for : Statistics Address
+ table_direction : ingress
+ bits_to_use : [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]
+ left_shift : 1
+ expanded_lo : False
+ expanded_hi : False
+ expanded_bit_width : 0
+ immediate_position : unused
+
+
+
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.resources.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.resources.log
index 4c78d52..bc6238e 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.resources.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.resources.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.resources.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
@@ -10,7 +10,7 @@
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| 0 | 13 | 16 | 2 | 1 | 2 | 4 | 3 | 3 | 3 | 0 | 1 | 0 | 8 | 0 | 4 | 2 | 2 |
| 1 | 4 | 0 | 30 | 0 | 0 | 5 | 2 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 2 | 1 | 1 |
-| 2 | 2 | 0 | 9 | 0 | 2 | 4 | 4 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 |
+| 2 | 6 | 0 | 29 | 2 | 2 | 4 | 4 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 |
| 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
@@ -21,7 +21,7 @@
| 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| | | | | | | | | | | | | | | | | | |
-| Totals | 19 | 16 | 41 | 1 | 4 | 13 | 9 | 3 | 5 | 0 | 4 | 0 | 12 | 0 | 6 | 3 | 5 |
+| Totals | 23 | 16 | 61 | 3 | 4 | 13 | 9 | 3 | 5 | 0 | 4 | 0 | 12 | 0 | 6 | 3 | 5 |
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -30,7 +30,7 @@
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| 0 | 10.16% | 24.24% | 0.48% | 16.67% | 12.50% | 5.00% | 6.25% | 12.50% | 9.38% | 0.00% | 25.00% | 0.00% | 6.25% | 0.00% | 12.50% | 6.25% | 12.50% |
| 1 | 3.12% | 0.00% | 7.21% | 0.00% | 0.00% | 6.25% | 4.17% | 0.00% | 3.12% | 0.00% | 25.00% | 0.00% | 3.12% | 0.00% | 6.25% | 3.12% | 6.25% |
-| 2 | 1.56% | 0.00% | 2.16% | 0.00% | 12.50% | 5.00% | 8.33% | 0.00% | 3.12% | 0.00% | 50.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% |
+| 2 | 4.69% | 0.00% | 6.97% | 33.33% | 12.50% | 5.00% | 8.33% | 0.00% | 3.12% | 0.00% | 50.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% |
| 3 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| 4 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| 5 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
@@ -41,7 +41,7 @@
| 10 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| 11 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| | | | | | | | | | | | | | | | | | |
-| Average | 1.24% | 2.02% | 0.82% | 1.39% | 2.08% | 1.35% | 1.56% | 1.04% | 1.30% | 0.00% | 8.33% | 0.00% | 0.78% | 0.00% | 1.56% | 0.78% | 2.60% |
+| Average | 1.50% | 2.02% | 1.22% | 4.17% | 2.08% | 1.35% | 1.56% | 1.04% | 1.30% | 0.00% | 8.33% | 0.00% | 0.78% | 0.00% | 1.56% | 0.78% | 2.60% |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -63,9 +63,9 @@
| ecmp_group_table_counter | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
| _condition_2 | 2 | 2 | 9 | 1 | 0 | 0 | 0 | 0 | 0 |
| ingress_port_count_table__action__ | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| ingress_port_count_table | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
+| ingress_port_count_table | 2 | 2 | 10 | 0 | 0 | 0 | 0 | 0 | 1 |
| egress_port_count_table__action__ | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| egress_port_count_table | 2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
+| egress_port_count_table | 2 | 2 | 10 | 1 | 0 | 0 | 0 | 0 | 1 |
| ingress_port_counter | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
| egress_port_counter | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
--------------------------------------------------------------------------------------------------------------------
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.rf.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.rf.log
index e8e52eb..84b376e 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.rf.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.rf.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: mau.rf.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.sram.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.sram.log
index 304ac66..3f740f7 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.sram.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.sram.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.sram.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tcam.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tcam.log
index 748d34a..6f4718a 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tcam.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tcam.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.tcam.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tp.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tp.log
index 229af10..f83cb22 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tp.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tp.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.tp.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
----- Stage 0 ------
@@ -37,10 +37,10 @@
------------------------------------------
Running Table Placement 4
------------------------------------------
-Cannot use hash action for table ingress_port_count_table.
-Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 510.
-Cannot use hash action for table egress_port_count_table.
-Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 510.
+Can use hash action for table ingress_port_count_table??? True
+Decided that match table ingress_port_count_table is more efficiently allocated using hash-action to ingress_port_counter.
+Can use hash action for table egress_port_count_table??? True
+Decided that match table egress_port_count_table is more efficiently allocated using hash-action to egress_port_counter.
Cannot use hash action for table process_packet_out_table.
Table process_packet_out_table has no side effect tables.
User requested to not attempt to place action data parameters in the match overhead.
@@ -51,8 +51,8 @@
------------------------------------------
Table Groups
------------------------------------------
-Table Grouping (ingress) with match table ingress_port_count_table (1024) [ingress_port_count_table__action__ (1024), ingress_port_counter (510)]
-Table Grouping (ingress) with match table egress_port_count_table (1024) [egress_port_count_table__action__ (1024), egress_port_counter (510)]
+Table Grouping (ingress) with match table ingress_port_count_table (1024) [ingress_port_count_table__action__ (1024), ingress_port_counter (512)]
+Table Grouping (ingress) with match table egress_port_count_table (1024) [egress_port_count_table__action__ (1024), egress_port_counter (512)]
Table Grouping (ingress) with match table process_packet_out_table (1024) [process_packet_out_table__action__ (1024)]
Table Grouping (ingress) with match table table0 (512) [table0__action__ (512), table0_counter (512)]
Table Grouping (ingress) with match table ecmp_group_table (1024) [ecmp_group_table__action__ (1024), ecmp_group_table_counter (1024)]
@@ -108,13 +108,13 @@
Nodes could place:
_condition_2 (4)
->> choose Table Grouping (ingress) with match table ingress_port_count_table (1024) [ingress_port_count_table__action__ (1024), ingress_port_counter (510)]
+>> choose Table Grouping (ingress) with match table ingress_port_count_table (1024) [ingress_port_count_table__action__ (1024), ingress_port_counter (512)]
Earliest stage can place: 2
Placing table: ingress_port_count_table__action__ with 1024 entries
-Placing table: ingress_port_counter with 510 entries
+Placing table: ingress_port_counter with 512 entries
Table ingress_port_count_table__action__ with 0 entries is directly referenced
Table ingress_port_counter with 4096 entries is indirectly referenced
-Match Table ingress_port_count_table has a total of 1 entries in stage 2
+Match Table ingress_port_count_table has a total of 1024 entries in stage 2
Direct mapped table ingress_port_count_table__action__ has 0 entries
>> set ingress_port_count_table (5) to placed
>> set _condition_2 (4) to placed
@@ -123,15 +123,15 @@
egress_port_count_table (6)
egress_port_count_table and _condition_2 not mutually exclusive
egress_port_count_table and ingress_port_count_table not mutually exclusive
->> choose Table Grouping (ingress) with match table egress_port_count_table (1024) [egress_port_count_table__action__ (1024), egress_port_counter (510)]
+>> choose Table Grouping (ingress) with match table egress_port_count_table (1024) [egress_port_count_table__action__ (1024), egress_port_counter (512)]
Earliest stage can place: 2
egress_port_count_table and _condition_2 not mutually exclusive
egress_port_count_table and ingress_port_count_table not mutually exclusive
Placing table: egress_port_count_table__action__ with 1024 entries
-Placing table: egress_port_counter with 510 entries
+Placing table: egress_port_counter with 512 entries
Table egress_port_count_table__action__ with 0 entries is directly referenced
Table egress_port_counter with 4096 entries is indirectly referenced
-Match Table egress_port_count_table has a total of 1 entries in stage 2
+Match Table egress_port_count_table has a total of 1024 entries in stage 2
Direct mapped table egress_port_count_table__action__ has 0 entries
>> set egress_port_count_table (6) to placed
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.characterize.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.characterize.log
index 054eac9..bc61355 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.characterize.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.characterize.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: pa.characterize.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
Program: ecmp
@@ -17,13 +17,13 @@
| [7:0] | ingress | ipv4.srcAddr[31:24] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv2 | ingress | | | | | | | | | | | | | | | | | |
| [31:0] | ingress | ipv4.dstAddr[31:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv3 | ingress | | | | | | | | | | | | | | | | | |
-| [31:0] | ingress | ethernet.dstAddr[39:8] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv3 | ingress | | SH | | | | | | | | | | | | | | | |
+| [31:24] | ingress | tcp.dstPort[7:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [23:0] | ingress | tcp.seqNo[31:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv4 | ingress | | | | | | | | | | | | | | | | | |
+| [31:0] | ingress | ethernet.dstAddr[39:8] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv5 | ingress | | | | | | | | | | | | | | | | | |
| [31:0] | ingress | ethernet.srcAddr[31:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv5 | ingress | | SH | | | | | | | | | | | | | | | |
-| [31:16] | ingress | udp.srcPort[15:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [15:0] | ingress | udp.dstPort[15:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv6 | - | | | | | | | | | | | | | | | | | |
| phv7 | - | | | | | | | | | | | | | | | | | |
| phv8 | - | | | | | | | | | | | | | | | | | |
@@ -88,11 +88,14 @@
| | | | | | | | | | | | | | | | | | | |
| phv64 | ingress | | | | | | | | | | | | | | | | | |
| [7:0] | ingress | ipv4.srcAddr[23:16] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv65 | ingress | | | | | | | | | | | | | | | | | |
-| [7:0] | ingress | ethernet.dstAddr[47:40] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv65 | ingress | | OL,SH | | | | | | | | | | | | | | | |
+| [7:0] | ingress | tcp.srcPort[15:8] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [7:0] | ingress | udp.srcPort[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv66 | ingress | | | | | | | | | | | | | | | | | |
+| [7:0] | ingress | ethernet.dstAddr[47:40] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv67 | ingress | | | | | | | | | | | | | | | | | |
| [7:0] | ingress | ethernet.srcAddr[39:32] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv67 | ingress | | SH | | | | | | | | | | | | | | | |
+| phv68 | ingress | | SH | | | | | | | | | | | | | | | |
| [6:6] | ingress | --validity_check--metadata_bridge[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [5:5] | ingress | --validity_check--udp[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [4:4] | ingress | --validity_check--tcp[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
@@ -100,9 +103,8 @@
| [2:2] | ingress | --validity_check--ethernet[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [1:1] | ingress | --validity_check--packet_out_hdr[0:0] | pov | | W | RW | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [0:0] | ingress | --validity_check--packet_in_hdr[0:0] | pov | | W | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv68 | ingress | | | | | | | | | | | | | | | | | |
+| phv69 | ingress | | | | | | | | | | | | | | | | | |
| [7:5] | ingress | ig_intr_md_for_tm.drop_ctl[2:0] | imeta | | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv69 | - | | | | | | | | | | | | | | | | | |
| phv70 | - | | | | | | | | | | | | | | | | | |
| phv71 | - | | | | | | | | | | | | | | | | | |
| phv72 | - | | | | | | | | | | | | | | | | | |
@@ -189,15 +191,17 @@
| phv131 | ingress | | | | | | | | | | | | | | | | | |
| [15:0] | ingress | ipv4.srcAddr[15:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv132 | ingress | | SH | | | | | | | | | | | | | | | |
+| [15:8] | ingress | tcp.srcPort[7:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [7:0] | ingress | tcp.dstPort[15:8] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv133 | ingress | | SH | | | | | | | | | | | | | | | |
| [15:8] | ingress | ethernet.dstAddr[7:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [7:0] | ingress | ethernet.srcAddr[47:40] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv133 | ingress | | | | | | | | | | | | | | | | | |
-| [15:0] | ingress | ethernet.etherType[15:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv134 | ingress | | | | | | | | | | | | | | | | | |
-| [15:0] | ingress | ecmp_metadata.group_id[15:0] | meta | | | W | R | | | | | | | | | | | |
+| [15:0] | ingress | ethernet.etherType[15:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv135 | ingress | | | | | | | | | | | | | | | | | |
+| [15:0] | ingress | ecmp_metadata.group_id[15:0] | meta | | | W | R | | | | | | | | | | | |
+| phv136 | ingress | | | | | | | | | | | | | | | | | |
| [15:0] | ingress | ecmp_metadata.selector[15:0] | meta | | | W | R | | | | | | | | | | | |
-| phv136 | - | | | | | | | | | | | | | | | | | |
| phv137 | - | | | | | | | | | | | | | | | | | |
| phv138 | - | | | | | | | | | | | | | | | | | |
| phv139 | - | | | | | | | | | | | | | | | | | |
@@ -298,45 +302,47 @@
| [23:21] | ingress | ipv4.flags[2:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [20:8] | ingress | ipv4.fragOffset[12:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [7:0] | ingress | ipv4.ttl[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv257 | ingress | | SH | | | | | | | | | | | | | | | |
+| phv257 | ingress | | OL,SH | | | | | | | | | | | | | | | |
| [31:28] | ingress | tcp.dataOffset[3:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [27:25] | ingress | tcp.res[2:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [24:22] | ingress | tcp.ecn[2:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [21:16] | ingress | tcp.ctrl[5:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [31:16] | ingress | udp.length_[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | ingress | tcp.window[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [15:0] | ingress | udp.checksum[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv258 | ingress | | SH | | | | | | | | | | | | | | | |
| [31:16] | ingress | tcp.checksum[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | ingress | tcp.urgentPtr[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv259 | - | | | | | | | | | | | | | | | | | |
-| phv260 | - | | | | | | | | | | | | | | | | | |
-| phv261 | - | | | | | | | | | | | | | | | | | |
-| phv262 | - | | | | | | | | | | | | | | | | | |
-| phv263 | - | | | | | | | | | | | | | | | | | |
-| phv264 | egress | | SH | | | | | | | | | | | | | | | |
+| phv260 | egress | | SH | | | | | | | | | | | | | | | |
| [31:24] | egress | ipv4.ttl[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [23:16] | egress | ipv4.protocol[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | egress | ipv4.hdrChecksum[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv265 | egress | | | | | | | | | | | | | | | | | |
+| phv261 | egress | | | | | | | | | | | | | | | | | |
| [31:0] | egress | ipv4.srcAddr[31:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv266 | egress | | | | | | | | | | | | | | | | | |
+| phv262 | egress | | | | | | | | | | | | | | | | | |
| [31:0] | egress | ipv4.dstAddr[31:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv267 | egress | | OL,SH | | | | | | | | | | | | | | | |
+| phv263 | egress | | OL,SH | | | | | | | | | | | | | | | |
| [31:16] | egress | udp.length_[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [31:0] | egress | tcp.ackNo[31:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | egress | udp.checksum[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv268 | egress | | SH | | | | | | | | | | | | | | | |
+| phv264 | egress | | SH | | | | | | | | | | | | | | | |
| [31:28] | egress | tcp.dataOffset[3:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [27:25] | egress | tcp.res[2:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [24:22] | egress | tcp.ecn[2:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [21:16] | egress | tcp.ctrl[5:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | egress | tcp.window[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv269 | egress | | SH | | | | | | | | | | | | | | | |
+| phv265 | egress | | SH | | | | | | | | | | | | | | | |
| [31:16] | egress | tcp.checksum[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | egress | tcp.urgentPtr[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv270 | egress | | | | | | | | | | | | | | | | | |
+| phv266 | egress | | | | | | | | | | | | | | | | | |
| [31:0] | egress | ethernet.dstAddr[39:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv271 | egress | | | | | | | | | | | | | | | | | |
+| phv267 | egress | | | | | | | | | | | | | | | | | |
| [31:0] | egress | ethernet.srcAddr[31:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv268 | - | | | | | | | | | | | | | | | | | |
+| phv269 | - | | | | | | | | | | | | | | | | | |
+| phv270 | - | | | | | | | | | | | | | | | | | |
+| phv271 | - | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | |
| phv272 | - | | | | | | | | | | | | | | | | | |
| phv273 | - | | | | | | | | | | | | | | | | | |
@@ -359,33 +365,29 @@
| [7:4] | ingress | ipv4.version[3:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [3:0] | ingress | ipv4.ihl[3:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv289 | ingress | | OL,SH | | | | | | | | | | | | | | | |
-| [7:0] | ingress | tcp.srcPort[15:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [7:0] | ingress | udp.length_[15:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv290 | ingress | | OL,SH | | | | | | | | | | | | | | | |
-| [7:0] | ingress | tcp.srcPort[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [7:0] | ingress | udp.length_[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv291 | ingress | | | | | | | | | | | | | | | | | |
-| [7:0] | ingress | tcp.dstPort[15:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv292 | ingress | | | | | | | | | | | | | | | | | |
-| [7:0] | ingress | tcp.dstPort[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv293 | - | | | | | | | | | | | | | | | | | |
-| phv294 | - | | | | | | | | | | | | | | | | | |
-| phv295 | - | | | | | | | | | | | | | | | | | |
-| phv296 | egress | | SH | | | | | | | | | | | | | | | |
+| [7:0] | ingress | tcp.seqNo[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [7:0] | ingress | udp.srcPort[15:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv290 | - | | | | | | | | | | | | | | | | | |
+| phv291 | - | | | | | | | | | | | | | | | | | |
+| phv292 | egress | | SH | | | | | | | | | | | | | | | |
| [7:4] | egress | ipv4.version[3:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [3:0] | egress | ipv4.ihl[3:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv297 | egress | | | | | | | | | | | | | | | | | |
+| phv293 | egress | | | | | | | | | | | | | | | | | |
| [7:0] | egress | ipv4.diffserv[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv298 | egress | | OL,SH | | | | | | | | | | | | | | | |
+| phv294 | egress | | OL,SH | | | | | | | | | | | | | | | |
| [7:0] | egress | tcp.srcPort[15:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [7:0] | egress | udp.srcPort[15:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv299 | egress | | OL,SH | | | | | | | | | | | | | | | |
+| phv295 | egress | | OL,SH | | | | | | | | | | | | | | | |
| [7:0] | egress | tcp.srcPort[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [7:0] | egress | udp.srcPort[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv300 | egress | | | | | | | | | | | | | | | | | |
+| phv296 | egress | | | | | | | | | | | | | | | | | |
| [7:0] | egress | ethernet.dstAddr[47:40] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv301 | egress | | | | | | | | | | | | | | | | | |
+| phv297 | egress | | | | | | | | | | | | | | | | | |
| [7:0] | egress | ethernet.srcAddr[39:32] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv298 | - | | | | | | | | | | | | | | | | | |
+| phv299 | - | | | | | | | | | | | | | | | | | |
+| phv300 | - | | | | | | | | | | | | | | | | | |
+| phv301 | - | | | | | | | | | | | | | | | | | |
| phv302 | - | | | | | | | | | | | | | | | | | |
| phv303 | - | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | |
@@ -413,45 +415,43 @@
| [15:8] | ingress | ipv4.totalLen[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [7:0] | ingress | ipv4.identification[15:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv322 | ingress | | OL,SH | | | | | | | | | | | | | | | |
-| [15:0] | ingress | tcp.seqNo[31:16] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [15:0] | ingress | udp.checksum[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv323 | ingress | | | | | | | | | | | | | | | | | |
-| [15:0] | ingress | tcp.seqNo[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv324 | ingress | | | | | | | | | | | | | | | | | |
| [15:0] | ingress | tcp.ackNo[31:16] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv325 | ingress | | | | | | | | | | | | | | | | | |
+| [15:0] | ingress | udp.dstPort[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv323 | ingress | | | | | | | | | | | | | | | | | |
| [15:0] | ingress | tcp.ackNo[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv326 | - | | | | | | | | | | | | | | | | | |
-| phv327 | - | | | | | | | | | | | | | | | | | |
-| phv328 | - | | | | | | | | | | | | | | | | | |
-| phv329 | - | | | | | | | | | | | | | | | | | |
-| phv330 | - | | | | | | | | | | | | | | | | | |
-| phv331 | - | | | | | | | | | | | | | | | | | |
-| phv332 | egress | | | | | | | | | | | | | | | | | |
+| phv324 | - | | | | | | | | | | | | | | | | | |
+| phv325 | - | | | | | | | | | | | | | | | | | |
+| phv326 | egress | | | | | | | | | | | | | | | | | |
| [15:0] | egress | ipv4.totalLen[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv333 | egress | | | | | | | | | | | | | | | | | |
+| phv327 | egress | | | | | | | | | | | | | | | | | |
| [15:0] | egress | ipv4.identification[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv334 | egress | | SH | | | | | | | | | | | | | | | |
+| phv328 | egress | | SH | | | | | | | | | | | | | | | |
| [15:13] | egress | ipv4.flags[2:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [12:0] | egress | ipv4.fragOffset[12:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv335 | egress | | | | | | | | | | | | | | | | | |
+| phv329 | egress | | OL,SH | | | | | | | | | | | | | | | |
| [15:0] | egress | tcp.dstPort[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| | | | | | | | | | | | | | | | | | | |
-| phv336 | egress | | OL,SH | | | | | | | | | | | | | | | |
-| [15:0] | egress | tcp.seqNo[31:16] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | egress | udp.dstPort[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv337 | egress | | | | | | | | | | | | | | | | | |
+| phv330 | egress | | | | | | | | | | | | | | | | | |
+| [15:0] | egress | tcp.seqNo[31:16] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv331 | egress | | | | | | | | | | | | | | | | | |
| [15:0] | egress | tcp.seqNo[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv338 | egress | | SH | | | | | | | | | | | | | | | |
+| phv332 | egress | | SH | | | | | | | | | | | | | | | |
| [15:8] | egress | ethernet.dstAddr[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [7:0] | egress | ethernet.srcAddr[47:40] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv339 | egress | | | | | | | | | | | | | | | | | |
+| phv333 | egress | | | | | | | | | | | | | | | | | |
| [15:0] | egress | ethernet.etherType[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv340 | egress | | OL,SH | | | | | | | | | | | | | | | |
+| phv334 | egress | | OL,SH | | | | | | | | | | | | | | | |
| [15:7] | egress | packet_out_hdr.egress_port[8:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:7] | egress | packet_in_hdr.ingress_port[8:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [6:0] | egress | packet_out_hdr._padding[6:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [6:0] | egress | packet_in_hdr._padding[6:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv335 | - | | | | | | | | | | | | | | | | | |
+| | | | | | | | | | | | | | | | | | | |
+| phv336 | - | | | | | | | | | | | | | | | | | |
+| phv337 | - | | | | | | | | | | | | | | | | | |
+| phv338 | - | | | | | | | | | | | | | | | | | |
+| phv339 | - | | | | | | | | | | | | | | | | | |
+| phv340 | - | | | | | | | | | | | | | | | | | |
| phv341 | - | | | | | | | | | | | | | | | | | |
| phv342 | - | | | | | | | | | | | | | | | | | |
| phv343 | - | | | | | | | | | | | | | | | | | |
@@ -483,9 +483,9 @@
-----------------------------------------------------------------------------------------------------------------------------------------
-Containers used: 59
-Containers with data overlayed: 9 (15.25%)
-Containers shared: 29 (49.15%)
+Containers used: 56
+Containers with data overlayed: 10 (17.86%)
+Containers shared: 30 (53.57%)
------------------------
Legend:
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.constraints.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.constraints.log
index 5c79eac..6e4a8ae 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.constraints.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.constraints.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: pa.constraints.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
To populate this log file, include --print-pa-constraints as a compiler argument.
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.liveness.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.liveness.log
index 1209f55..cc28af3 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.liveness.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.liveness.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: pa.liveness.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.log
index 2a7aa5c..83138b1 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: pa.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
HLIR Version: 0.10.5
@@ -504,17 +504,17 @@
| tcp.checksum | 16 | ingress | x | x | | | |
| tcp.ctrl | 6 | ingress | x | x | | | |
| tcp.dataOffset | 4 | ingress | x | x | | | |
-| tcp.dstPort | 16 | ingress | x | x | | | |
+| tcp.dstPort | 16 | ingress | x | x | | x | |
| tcp.ecn | 3 | ingress | x | x | | | |
| tcp.res | 3 | ingress | x | x | | | |
| tcp.seqNo | 32 | ingress | x | x | | | |
-| tcp.srcPort | 16 | ingress | x | x | | | |
+| tcp.srcPort | 16 | ingress | x | x | | x | |
| tcp.urgentPtr | 16 | ingress | x | x | | | |
| tcp.window | 16 | ingress | x | x | | | |
| udp.checksum | 16 | ingress | x | x | | | |
-| udp.dstPort | 16 | ingress | x | x | | x | |
+| udp.dstPort | 16 | ingress | x | x | | | |
| udp.length_ | 16 | ingress | x | x | | | |
-| udp.srcPort | 16 | ingress | x | x | | x | |
+| udp.srcPort | 16 | ingress | x | x | | | |
---------------------------------------------------------------------------------------------------------------------------------
Performing PHV allocation...
@@ -553,7 +553,7 @@
parse_pkt_in and parse_pkt_out are exclusive parse states
parse_tcp and parse_udp are exclusive parse states
->>Event 'pa_init' at time 1505214955.36
+>>Event 'pa_init' at time 1505264383.13
Took 0.01 seconds
--------------------------------------------
PHV MAU Groups: 92
@@ -645,13 +645,13 @@
ipv4.dstAddr <32 bits ingress parsed R>
Phv Mau Group (ingress) -- 1 instance for total bit width of 16.
- tcp.srcPort <16 bits ingress parsed tagalong>
+ tcp.srcPort <16 bits ingress parsed R>
Phv Mau Group (ingress) -- 1 instance for total bit width of 1.
--validity_check--tcp <1 bits ingress parsed pov>
Phv Mau Group (ingress) -- 1 instance for total bit width of 16.
- tcp.dstPort <16 bits ingress parsed tagalong>
+ tcp.dstPort <16 bits ingress parsed R>
Phv Mau Group (ingress) -- 1 instance for total bit width of 32.
tcp.seqNo <32 bits ingress parsed tagalong>
@@ -681,13 +681,13 @@
tcp.urgentPtr <16 bits ingress parsed tagalong>
Phv Mau Group (ingress) -- 1 instance for total bit width of 16.
- udp.srcPort <16 bits ingress parsed R>
+ udp.srcPort <16 bits ingress parsed tagalong>
Phv Mau Group (ingress) -- 1 instance for total bit width of 1.
--validity_check--udp <1 bits ingress parsed pov>
Phv Mau Group (ingress) -- 1 instance for total bit width of 16.
- udp.dstPort <16 bits ingress parsed R>
+ udp.dstPort <16 bits ingress parsed tagalong>
Phv Mau Group (ingress) -- 1 instance for total bit width of 16.
udp.length_ <16 bits ingress parsed tagalong>
@@ -837,7 +837,7 @@
eg_intr_md.egress_cos <3 bits egress parsed imeta>
->>Event 'pa_resv' at time 1505214955.37
+>>Event 'pa_resv' at time 1505264383.13
Took 0.00 seconds
-----------------------------------------------
@@ -879,7 +879,7 @@
Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
Reserving 32-bit container for ingress: phv0
->>Event 'pa_bridge' at time 1505214955.40
+>>Event 'pa_bridge' at time 1505264383.17
Took 0.04 seconds
-----------------------------------------------
@@ -932,7 +932,7 @@
| Overall total | 1 (0.30%) | 32 (0.52%) | 6144 |
---------------------------------------------------------------------------
->>Event 'pa_phase0' at time 1505214955.41
+>>Event 'pa_phase0' at time 1505264383.17
Took 0.00 seconds
-----------------------------------------------
@@ -985,7 +985,7 @@
| Overall total | 1 (0.30%) | 32 (0.52%) | 6144 |
---------------------------------------------------------------------------
->>Event 'pa_critical' at time 1505214955.41
+>>Event 'pa_critical' at time 1505264383.17
Took 0.00 seconds
-----------------------------------------------
@@ -1334,8 +1334,8 @@
-------------------------------------------------------------------------------------
| Name | BW | Tagalong? | Req | Pref | Not Allow | MaxSplit | Group Size |
-------------------------------------------------------------------------------------
-| tcp.srcPort | 16 | True | - | - | - | 2 | 1 |
-| tcp.dstPort | 16 | True | - | - | - | 2 | 1 |
+| tcp.srcPort | 16 | False | - | - | - | 2 | 1 |
+| tcp.dstPort | 16 | False | - | - | - | 2 | 1 |
| tcp.seqNo | 32 | True | - | - | - | 4 | 1 |
| tcp.ackNo | 32 | True | - | - | - | 4 | 1 |
| tcp.dataOffset | 4 | True | - | - | - | 1 | 1 |
@@ -1361,23 +1361,21 @@
32-bit: 31
Initial packing options: 5196
-Packing option 0: [8, 8, 8, 8, 16, 16, 16, 16, 32, 32]
+Packing option 0: [8, 16, 32, 8, 16, 16, 32, 32]
MAU containers after:
- 8-bit: 47
- 16-bit: 76
- 32-bit: 45
+ 8-bit: 46
+ 16-bit: 75
+ 32-bit: 44
+-------------------------+
| tcp.srcPort [15:8] |
+-------------------------+
| tcp.srcPort [7:0] |
-+-------------------------+
| tcp.dstPort [15:8] |
+-------------------------+
| tcp.dstPort [7:0] |
+| tcp.seqNo [31:8] |
+-------------------------+
-| tcp.seqNo [31:16] |
-+-------------------------+
-| tcp.seqNo [15:0] |
+| tcp.seqNo [7:0] |
+-------------------------+
| tcp.ackNo [31:16] |
+-------------------------+
@@ -1395,28 +1393,43 @@
Looking at tcp.srcPort (ingress) [15:8], with test_alloc = True
----> tcp.srcPort (ingress) is allocated? False
-***Allocating phv289[7:0] for tcp.srcPort[15:8]
+
+MAU groups: 3
+ Group 4 8 bits -- avail 15 -- ingress avail 15 and remain 14 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv65
+ Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
+ Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
+***Allocating phv65[7:0] for tcp.srcPort[15:8]
Looking at tcp.srcPort (ingress) [7:0], with test_alloc = True
----> tcp.srcPort (ingress) is allocated? False
-***Allocating phv290[7:0] for tcp.srcPort[7:0]
Looking at tcp.dstPort (ingress) [15:8], with test_alloc = True
-----> tcp.dstPort (ingress) is allocated? False
-***Allocating phv291[7:0] for tcp.dstPort[15:8]
+
+MAU groups: 5
+ Group 8 16 bits -- avail 13 -- ingress avail 13 and remain 11 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv132
+ Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
+ Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
+ Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
+ Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
+***Allocating phv132[15:8] for tcp.srcPort[7:0]
+***Allocating phv132[7:0] for tcp.dstPort[15:8]
Looking at tcp.dstPort (ingress) [7:0], with test_alloc = True
----> tcp.dstPort (ingress) is allocated? False
-***Allocating phv292[7:0] for tcp.dstPort[7:0]
-Looking at tcp.seqNo (ingress) [31:16], with test_alloc = True
+Looking at tcp.seqNo (ingress) [31:8], with test_alloc = True
+
+MAU groups: 3
+ Group 0 32 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 12 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv3
+ Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
+ Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
+***Allocating phv3[31:24] for tcp.dstPort[7:0]
+***Allocating phv3[23:0] for tcp.seqNo[31:8]
+Looking at tcp.seqNo (ingress) [7:0], with test_alloc = True
----> tcp.seqNo (ingress) is allocated? False
-***Allocating phv322[15:0] for tcp.seqNo[31:16]
-Looking at tcp.seqNo (ingress) [15:0], with test_alloc = True
-----> tcp.seqNo (ingress) is allocated? False
-***Allocating phv323[15:0] for tcp.seqNo[15:0]
+***Allocating phv289[7:0] for tcp.seqNo[7:0]
Looking at tcp.ackNo (ingress) [31:16], with test_alloc = True
----> tcp.ackNo (ingress) is allocated? False
-***Allocating phv324[15:0] for tcp.ackNo[31:16]
+***Allocating phv322[15:0] for tcp.ackNo[31:16]
Looking at tcp.ackNo (ingress) [15:0], with test_alloc = True
----> tcp.ackNo (ingress) is allocated? False
-***Allocating phv325[15:0] for tcp.ackNo[15:0]
+***Allocating phv323[15:0] for tcp.ackNo[15:0]
Looking at tcp.dataOffset (ingress) [3:0], with test_alloc = True
----> tcp.dataOffset (ingress) is allocated? False
Looking at tcp.res (ingress) [2:0], with test_alloc = True
@@ -1487,9 +1500,9 @@
16-bit: 80
32-bit: 48
Tagalong containers available:
- 8-bit: 24
- 16-bit: 36
- 32-bit: 24
+ 8-bit: 28
+ 16-bit: 42
+ 32-bit: 28
Initial packing options: 5196
Packing option 0: [8, 8, 16, 16, 16, 32, 32, 32]
@@ -1522,35 +1535,35 @@
Looking at ipv4.version (egress) [3:0], with test_alloc = True
----> ipv4.version (egress) is allocated? False
Looking at ipv4.ihl (egress) [3:0], with test_alloc = True
-***Allocating phv296[7:4] for ipv4.version[3:0]
-***Allocating phv296[3:0] for ipv4.ihl[3:0]
+***Allocating phv292[7:4] for ipv4.version[3:0]
+***Allocating phv292[3:0] for ipv4.ihl[3:0]
Looking at ipv4.diffserv (egress) [7:0], with test_alloc = True
----> ipv4.diffserv (egress) is allocated? False
-***Allocating phv297[7:0] for ipv4.diffserv[7:0]
+***Allocating phv293[7:0] for ipv4.diffserv[7:0]
Looking at ipv4.totalLen (egress) [15:0], with test_alloc = True
----> ipv4.totalLen (egress) is allocated? False
-***Allocating phv332[15:0] for ipv4.totalLen[15:0]
+***Allocating phv326[15:0] for ipv4.totalLen[15:0]
Looking at ipv4.identification (egress) [15:0], with test_alloc = True
----> ipv4.identification (egress) is allocated? False
-***Allocating phv333[15:0] for ipv4.identification[15:0]
+***Allocating phv327[15:0] for ipv4.identification[15:0]
Looking at ipv4.flags (egress) [2:0], with test_alloc = True
----> ipv4.flags (egress) is allocated? False
Looking at ipv4.fragOffset (egress) [12:0], with test_alloc = True
-***Allocating phv334[15:13] for ipv4.flags[2:0]
-***Allocating phv334[12:0] for ipv4.fragOffset[12:0]
+***Allocating phv328[15:13] for ipv4.flags[2:0]
+***Allocating phv328[12:0] for ipv4.fragOffset[12:0]
Looking at ipv4.ttl (egress) [7:0], with test_alloc = True
----> ipv4.ttl (egress) is allocated? False
Looking at ipv4.protocol (egress) [7:0], with test_alloc = True
Looking at ipv4.hdrChecksum (egress) [15:0], with test_alloc = True
-***Allocating phv264[31:24] for ipv4.ttl[7:0]
-***Allocating phv264[23:16] for ipv4.protocol[7:0]
-***Allocating phv264[15:0] for ipv4.hdrChecksum[15:0]
+***Allocating phv260[31:24] for ipv4.ttl[7:0]
+***Allocating phv260[23:16] for ipv4.protocol[7:0]
+***Allocating phv260[15:0] for ipv4.hdrChecksum[15:0]
Looking at ipv4.srcAddr (egress) [31:0], with test_alloc = True
----> ipv4.srcAddr (egress) is allocated? False
-***Allocating phv265[31:0] for ipv4.srcAddr[31:0]
+***Allocating phv261[31:0] for ipv4.srcAddr[31:0]
Looking at ipv4.dstAddr (egress) [31:0], with test_alloc = True
----> ipv4.dstAddr (egress) is allocated? False
-***Allocating phv266[31:0] for ipv4.dstAddr[31:0]
+***Allocating phv262[31:0] for ipv4.dstAddr[31:0]
Packing options tried: 1
Packing options skipped: 0
@@ -1603,9 +1616,9 @@
16-bit: 80
32-bit: 48
Tagalong containers available:
- 8-bit: 22
- 16-bit: 33
- 32-bit: 21
+ 8-bit: 26
+ 16-bit: 39
+ 32-bit: 25
Initial packing options: 5196
Packing option 0: [8, 8, 16, 16, 16, 32, 32, 32]
@@ -1638,38 +1651,38 @@
Looking at tcp.srcPort (egress) [15:8], with test_alloc = True
----> tcp.srcPort (egress) is allocated? False
-***Allocating phv298[7:0] for tcp.srcPort[15:8]
+***Allocating phv294[7:0] for tcp.srcPort[15:8]
Looking at tcp.srcPort (egress) [7:0], with test_alloc = True
----> tcp.srcPort (egress) is allocated? False
-***Allocating phv299[7:0] for tcp.srcPort[7:0]
+***Allocating phv295[7:0] for tcp.srcPort[7:0]
Looking at tcp.dstPort (egress) [15:0], with test_alloc = True
----> tcp.dstPort (egress) is allocated? False
-***Allocating phv335[15:0] for tcp.dstPort[15:0]
+***Allocating phv329[15:0] for tcp.dstPort[15:0]
Looking at tcp.seqNo (egress) [31:16], with test_alloc = True
----> tcp.seqNo (egress) is allocated? False
-***Allocating phv336[15:0] for tcp.seqNo[31:16]
+***Allocating phv330[15:0] for tcp.seqNo[31:16]
Looking at tcp.seqNo (egress) [15:0], with test_alloc = True
----> tcp.seqNo (egress) is allocated? False
-***Allocating phv337[15:0] for tcp.seqNo[15:0]
+***Allocating phv331[15:0] for tcp.seqNo[15:0]
Looking at tcp.ackNo (egress) [31:0], with test_alloc = True
----> tcp.ackNo (egress) is allocated? False
-***Allocating phv267[31:0] for tcp.ackNo[31:0]
+***Allocating phv263[31:0] for tcp.ackNo[31:0]
Looking at tcp.dataOffset (egress) [3:0], with test_alloc = True
----> tcp.dataOffset (egress) is allocated? False
Looking at tcp.res (egress) [2:0], with test_alloc = True
Looking at tcp.ecn (egress) [2:0], with test_alloc = True
Looking at tcp.ctrl (egress) [5:0], with test_alloc = True
Looking at tcp.window (egress) [15:0], with test_alloc = True
-***Allocating phv268[31:28] for tcp.dataOffset[3:0]
-***Allocating phv268[27:25] for tcp.res[2:0]
-***Allocating phv268[24:22] for tcp.ecn[2:0]
-***Allocating phv268[21:16] for tcp.ctrl[5:0]
-***Allocating phv268[15:0] for tcp.window[15:0]
+***Allocating phv264[31:28] for tcp.dataOffset[3:0]
+***Allocating phv264[27:25] for tcp.res[2:0]
+***Allocating phv264[24:22] for tcp.ecn[2:0]
+***Allocating phv264[21:16] for tcp.ctrl[5:0]
+***Allocating phv264[15:0] for tcp.window[15:0]
Looking at tcp.checksum (egress) [15:0], with test_alloc = True
----> tcp.checksum (egress) is allocated? False
Looking at tcp.urgentPtr (egress) [15:0], with test_alloc = True
-***Allocating phv269[31:16] for tcp.checksum[15:0]
-***Allocating phv269[15:0] for tcp.urgentPtr[15:0]
+***Allocating phv265[31:16] for tcp.checksum[15:0]
+***Allocating phv265[15:0] for tcp.urgentPtr[15:0]
Packing options tried: 1
Packing options skipped: 0
@@ -1702,20 +1715,20 @@
min_extracts[32] = 1
Packing options: 604
MAU containers available:
- 8-bit: 47
- 16-bit: 76
- 32-bit: 45
+ 8-bit: 46
+ 16-bit: 75
+ 32-bit: 44
Tagalong containers available:
- 8-bit: 19
- 16-bit: 30
+ 8-bit: 22
+ 16-bit: 32
32-bit: 21
Initial packing options: 604
Packing option 0: [8, 32, 16, 8, 32, 16]
MAU containers after:
- 8-bit: 45
- 16-bit: 74
- 32-bit: 43
+ 8-bit: 44
+ 16-bit: 73
+ 32-bit: 42
+-----------------------------+
| ethernet.dstAddr [47:40] |
+-----------------------------+
@@ -1735,48 +1748,21 @@
----> ethernet.dstAddr (ingress) is allocated? False
MAU groups: 3
- Group 4 8 bits -- avail 15 -- ingress avail 15 and remain 14 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv65
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-***Allocating phv65[7:0] for ethernet.dstAddr[47:40]
-Looking at ethernet.dstAddr (ingress) [39:8], with test_alloc = True
-----> ethernet.dstAddr (ingress) is allocated? False
-
-MAU groups: 3
- Group 0 32 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 12 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv3
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
-***Allocating phv3[31:0] for ethernet.dstAddr[39:8]
-Looking at ethernet.dstAddr (ingress) [7:0], with test_alloc = True
-----> ethernet.dstAddr (ingress) is allocated? False
-Looking at ethernet.srcAddr (ingress) [47:40], with test_alloc = True
-
-MAU groups: 5
- Group 8 16 bits -- avail 13 -- ingress avail 13 and remain 11 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv132
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-***Allocating phv132[15:8] for ethernet.dstAddr[7:0]
-***Allocating phv132[7:0] for ethernet.srcAddr[47:40]
-Looking at ethernet.srcAddr (ingress) [39:32], with test_alloc = True
-----> ethernet.srcAddr (ingress) is allocated? False
-
-MAU groups: 3
Group 4 8 bits -- avail 14 -- ingress avail 14 and remain 13 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv66
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-***Allocating phv66[7:0] for ethernet.srcAddr[39:32]
-Looking at ethernet.srcAddr (ingress) [31:0], with test_alloc = True
-----> ethernet.srcAddr (ingress) is allocated? False
+***Allocating phv66[7:0] for ethernet.dstAddr[47:40]
+Looking at ethernet.dstAddr (ingress) [39:8], with test_alloc = True
+----> ethernet.dstAddr (ingress) is allocated? False
MAU groups: 3
Group 0 32 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 12 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv4
Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
-***Allocating phv4[31:0] for ethernet.srcAddr[31:0]
-Looking at ethernet.etherType (ingress) [15:0], with test_alloc = True
-----> ethernet.etherType (ingress) is allocated? False
+***Allocating phv4[31:0] for ethernet.dstAddr[39:8]
+Looking at ethernet.dstAddr (ingress) [7:0], with test_alloc = True
+----> ethernet.dstAddr (ingress) is allocated? False
+Looking at ethernet.srcAddr (ingress) [47:40], with test_alloc = True
MAU groups: 5
Group 8 16 bits -- avail 12 -- ingress avail 12 and remain 10 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv133
@@ -1784,7 +1770,34 @@
Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-***Allocating phv133[15:0] for ethernet.etherType[15:0]
+***Allocating phv133[15:8] for ethernet.dstAddr[7:0]
+***Allocating phv133[7:0] for ethernet.srcAddr[47:40]
+Looking at ethernet.srcAddr (ingress) [39:32], with test_alloc = True
+----> ethernet.srcAddr (ingress) is allocated? False
+
+MAU groups: 3
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
+ Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
+ Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
+***Allocating phv67[7:0] for ethernet.srcAddr[39:32]
+Looking at ethernet.srcAddr (ingress) [31:0], with test_alloc = True
+----> ethernet.srcAddr (ingress) is allocated? False
+
+MAU groups: 3
+ Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
+ Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
+ Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
+***Allocating phv5[31:0] for ethernet.srcAddr[31:0]
+Looking at ethernet.etherType (ingress) [15:0], with test_alloc = True
+----> ethernet.etherType (ingress) is allocated? False
+
+MAU groups: 5
+ Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
+ Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
+ Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
+ Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
+ Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
+***Allocating phv134[15:0] for ethernet.etherType[15:0]
Packing options tried: 1
Packing options skipped: 0
@@ -1821,9 +1834,9 @@
16-bit: 80
32-bit: 48
Tagalong containers available:
- 8-bit: 20
- 16-bit: 30
- 32-bit: 18
+ 8-bit: 24
+ 16-bit: 36
+ 32-bit: 22
Initial packing options: 604
Packing option 0: [8, 32, 16, 8, 32, 16]
@@ -1848,24 +1861,24 @@
Looking at ethernet.dstAddr (egress) [47:40], with test_alloc = True
----> ethernet.dstAddr (egress) is allocated? False
-***Allocating phv300[7:0] for ethernet.dstAddr[47:40]
+***Allocating phv296[7:0] for ethernet.dstAddr[47:40]
Looking at ethernet.dstAddr (egress) [39:8], with test_alloc = True
----> ethernet.dstAddr (egress) is allocated? False
-***Allocating phv270[31:0] for ethernet.dstAddr[39:8]
+***Allocating phv266[31:0] for ethernet.dstAddr[39:8]
Looking at ethernet.dstAddr (egress) [7:0], with test_alloc = True
----> ethernet.dstAddr (egress) is allocated? False
Looking at ethernet.srcAddr (egress) [47:40], with test_alloc = True
-***Allocating phv338[15:8] for ethernet.dstAddr[7:0]
-***Allocating phv338[7:0] for ethernet.srcAddr[47:40]
+***Allocating phv332[15:8] for ethernet.dstAddr[7:0]
+***Allocating phv332[7:0] for ethernet.srcAddr[47:40]
Looking at ethernet.srcAddr (egress) [39:32], with test_alloc = True
----> ethernet.srcAddr (egress) is allocated? False
-***Allocating phv301[7:0] for ethernet.srcAddr[39:32]
+***Allocating phv297[7:0] for ethernet.srcAddr[39:32]
Looking at ethernet.srcAddr (egress) [31:0], with test_alloc = True
----> ethernet.srcAddr (egress) is allocated? False
-***Allocating phv271[31:0] for ethernet.srcAddr[31:0]
+***Allocating phv267[31:0] for ethernet.srcAddr[31:0]
Looking at ethernet.etherType (egress) [15:0], with test_alloc = True
----> ethernet.etherType (egress) is allocated? False
-***Allocating phv339[15:0] for ethernet.etherType[15:0]
+***Allocating phv333[15:0] for ethernet.etherType[15:0]
Packing options tried: 1
Packing options skipped: 0
@@ -1904,9 +1917,9 @@
16-bit: 80
32-bit: 48
Tagalong containers available:
- 8-bit: 18
- 16-bit: 28
- 32-bit: 16
+ 8-bit: 22
+ 16-bit: 34
+ 32-bit: 20
Initial packing options: 3
Packing option 1: [16, 8]
@@ -1993,9 +2006,9 @@
16-bit: 79
32-bit: 48
Tagalong containers available:
- 8-bit: 18
- 16-bit: 28
- 32-bit: 16
+ 8-bit: 22
+ 16-bit: 34
+ 32-bit: 20
Initial packing options: 2
Packing option 0: [16]
@@ -2011,8 +2024,8 @@
Looking at packet_out_hdr.egress_port (egress) [8:0], with test_alloc = True
----> packet_out_hdr.egress_port (egress) is allocated? False
Looking at packet_out_hdr._padding (egress) [6:0], with test_alloc = True
-***Allocating phv340[15:7] for packet_out_hdr.egress_port[8:0]
-***Allocating phv340[6:0] for packet_out_hdr._padding[6:0]
+***Allocating phv334[15:7] for packet_out_hdr.egress_port[8:0]
+***Allocating phv334[6:0] for packet_out_hdr._padding[6:0]
Packing options tried: 1
Packing options skipped: 0
@@ -2030,46 +2043,46 @@
| PHV Group | Containers Used | Bits Used | Bits Available |
| (container bit widths) | (% used) | (% used) | |
-----------------------------------------------------------------------------
-| 0 (32) | 5 (31.25%) | 160 (31.25%) | 512 |
+| 0 (32) | 6 (37.50%) | 192 (37.50%) | 512 |
| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 5 (7.81%) | 160 (7.81%) | 2048 |
+| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
| | | | |
-| 4 (8) | 3 (18.75%) | 24 (18.75%) | 128 |
+| 4 (8) | 4 (25.00%) | 32 (25.00%) | 128 |
| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 4 (6.25%) | 32 (6.25%) | 512 |
+| Total for 8 bit | 5 (7.81%) | 40 (7.81%) | 512 |
| | | | |
-| 8 (16) | 5 (31.25%) | 80 (31.25%) | 256 |
+| 8 (16) | 6 (37.50%) | 96 (37.50%) | 256 |
| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 6 (6.25%) | 96 (6.25%) | 1536 |
+| Total for 16 bit | 7 (7.29%) | 112 (7.29%) | 1536 |
| | | | |
| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
| | | | |
-| 16 (8) T | 11 (68.75%) | 88 (68.75%) | 128 |
+| 16 (8) T | 8 (50.00%) | 64 (50.00%) | 128 |
| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 11 (34.38%) | 88 (34.38%) | 256 |
+| Total for 8 bit | 8 (25.00%) | 64 (25.00%) | 256 |
| | | | |
-| 18 (16) T | 10 (62.50%) | 160 (62.50%) | 256 |
-| 19 (16) T | 5 (31.25%) | 80 (31.25%) | 256 |
+| 18 (16) T | 13 (81.25%) | 208 (81.25%) | 256 |
+| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 15 (31.25%) | 240 (31.25%) | 768 |
+| Total for 16 bit | 13 (27.08%) | 208 (27.08%) | 768 |
| | | | |
-| MAU total | 15 (6.70%) | 288 (7.03%) | 4096 |
-| Tagalong total | 37 (33.04%) | 680 (33.20%) | 2048 |
-| Overall total | 52 (15.48%) | 968 (15.76%) | 6144 |
+| MAU total | 18 (8.04%) | 344 (8.40%) | 4096 |
+| Tagalong total | 32 (28.57%) | 624 (30.47%) | 2048 |
+| Overall total | 50 (14.88%) | 968 (15.76%) | 6144 |
-----------------------------------------------------------------------------
->>Event 'pa_overlay' at time 1505214964.48
- Took 9.07 seconds
+>>Event 'pa_overlay' at time 1505264392.23
+ Took 9.06 seconds
-----------------------------------------------
Allocating remaining parsed fields
@@ -2107,9 +2120,9 @@
-------------------------------------------------------------------------------------------------------
MAU containers available:
- 8-bit: 45
- 16-bit: 74
- 32-bit: 43
+ 8-bit: 44
+ 16-bit: 73
+ 32-bit: 42
Packing options: 2
Initial packing options: 2
@@ -2140,381 +2153,29 @@
-----------------------------------------------------------------------------------
| Name | BW | Tagalong? | Req | Pref | Not Allow | MaxSplit | Group Size |
-----------------------------------------------------------------------------------
-| udp.srcPort | 16 | False | - | - | - | 2 | 1 |
-| udp.dstPort | 16 | False | - | - | - | 2 | 1 |
+| udp.srcPort | 16 | True | - | - | - | 2 | 1 |
+| udp.dstPort | 16 | True | - | - | - | 2 | 1 |
| udp.length_ | 16 | True | - | - | - | 2 | 1 |
| udp.checksum | 16 | True | - | - | - | 2 | 1 |
-----------------------------------------------------------------------------------
MAU containers available:
- 8-bit: 45
- 16-bit: 74
- 32-bit: 43
+ 8-bit: 44
+ 16-bit: 73
+ 32-bit: 42
Packing options: 47
Initial packing options: 47
Packing option 0: [8, 8, 16, 32]
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
->>Can pack using [8, 8, 16, 32] if open up 3 new containers.
-
-Packing option 1: [8, 8, 32, 16]
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 3
- Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
->>Can pack using [8, 8, 32, 16] if open up 3 new containers.
-
-Packing option 2: [8, 16, 8, 32]
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-
-MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
->>Can pack using [8, 16, 8, 32] if open up 3 new containers.
-
-Packing option 3: [8, 16, 32, 8]
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-
-MAU groups: 3
- Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
->>Can pack using [8, 16, 32, 8] if open up 3 new containers.
-
-Packing option 4: [8, 32, 8, 16]
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 3
- Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
->>Can pack using [8, 32, 8, 16] if open up 2 new containers.
-
-Packing option 5: [8, 32, 16, 8]
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 3
- Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
->>Can pack using [8, 32, 16, 8] if open up 2 new containers.
-
-Packing option 6: [16, 8, 8, 32]
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
->>Can pack using [16, 8, 8, 32] if open up 3 new containers.
-
-Packing option 7: [16, 8, 32, 8]
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 3
- Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
->>Can pack using [16, 8, 32, 8] if open up 3 new containers.
-
-Packing option 8: [16, 32, 8, 8]
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-
-MAU groups: 3
- Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
->>Can pack using [16, 32, 8, 8] if open up 2 new containers.
-
-Packing option 9: [32, 8, 8, 16]
-
-MAU groups: 3
- Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
->>Can pack using [32, 8, 8, 16] if open up 1 new containers.
-
-Packing option 10: [32, 8, 16, 8]
-
-MAU groups: 3
- Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
->>Can pack using [32, 8, 16, 8] if open up 1 new containers.
-
-Packing option 11: [32, 16, 8, 8]
-
-MAU groups: 3
- Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
->>Can pack using [32, 16, 8, 8] if open up 1 new containers.
-
-Packing option 12: [16, 16, 32]
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-
-MAU groups: 5
- Group 8 16 bits -- avail 10 -- ingress avail 10 and remain 8 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv135
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
->>Can pack using [16, 16, 32] if open up 2 new containers.
-
-Packing option 13: [16, 32, 16]
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-
-MAU groups: 3
- Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
->>Can pack using [16, 32, 16] if open up 2 new containers.
-
-Packing option 14: [32, 16, 16]
-
-MAU groups: 3
- Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
->>Can pack using [32, 16, 16] if open up 1 new containers.
-
-Packing option 15: [8, 8, 16, 16, 16]
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
->>Can pack using [8, 8, 16, 16, 16] if open up 3 new containers.
-
-Packing option 16: [8, 16, 8, 16, 16]
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-
-MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
->>Can pack using [8, 16, 8, 16, 16] if open up 3 new containers.
-
-Packing option 17: [8, 16, 16, 8, 16]
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-
-MAU groups: 5
- Group 8 16 bits -- avail 10 -- ingress avail 10 and remain 8 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv135
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
->>Can pack using [8, 16, 16, 8, 16] if open up 3 new containers.
-
-Packing option 18: [8, 16, 16, 16, 8]
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-
-MAU groups: 5
- Group 8 16 bits -- avail 10 -- ingress avail 10 and remain 8 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv135
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
->>Can pack using [8, 16, 16, 16, 8] if open up 3 new containers.
-
-Packing option 19: [16, 8, 8, 16, 16]
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
->>Can pack using [16, 8, 8, 16, 16] if open up 3 new containers.
-
-Packing option 20: [16, 8, 16, 8, 16]
-
-MAU groups: 5
- Group 8 16 bits -- avail 11 -- ingress avail 11 and remain 9 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv134
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-
-MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-
-MAU groups: 5
- Group 8 16 bits -- avail 10 -- ingress avail 10 and remain 8 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv135
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
->>Can pack using [16, 8, 16, 8, 16] if open up 3 new containers.
-Terminate search for time purposes...
-Packing options tried: 21
+>>Can pack using [8, 8, 16, 32] if open up 0 new containers.
+Packing options tried: 1
Packing options skipped: 0
-Trying to place using best packing [32, 8, 8, 16]
-
-MAU groups: 3
- Group 0 32 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv5
- Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
- Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
-***Allocating phv5[31:16] for udp.srcPort[15:0]
-***Allocating phv5[15:0] for udp.dstPort[15:0]
-***Allocating phv289[7:0] for udp.length_[15:8]
-***Allocating phv290[7:0] for udp.length_[7:0]
-***Allocating phv322[15:0] for udp.checksum[15:0]
+Trying to place using best packing [8, 8, 16, 32]
+***Allocating phv289[7:0] for udp.srcPort[15:8]
+***Allocating phv65[7:0] for udp.srcPort[7:0]
+***Allocating phv322[15:0] for udp.dstPort[15:0]
+***Allocating phv257[31:16] for udp.length_[15:0]
+***Allocating phv257[15:0] for udp.checksum[15:0]
Working on parse node parse_udp (8) (egress)
-------------------------------------------
@@ -2553,11 +2214,11 @@
Packing options tried: 1
Packing options skipped: 0
Trying to place using best packing [8, 8, 16, 32]
-***Allocating phv298[7:0] for udp.srcPort[15:8]
-***Allocating phv299[7:0] for udp.srcPort[7:0]
-***Allocating phv336[15:0] for udp.dstPort[15:0]
-***Allocating phv267[31:16] for udp.length_[15:0]
-***Allocating phv267[15:0] for udp.checksum[15:0]
+***Allocating phv294[7:0] for udp.srcPort[15:8]
+***Allocating phv295[7:0] for udp.srcPort[7:0]
+***Allocating phv329[15:0] for udp.dstPort[15:0]
+***Allocating phv263[31:16] for udp.length_[15:0]
+***Allocating phv263[15:0] for udp.checksum[15:0]
Working on parse node parse_pkt_in (2) (egress)
-------------------------------------------
@@ -2592,101 +2253,101 @@
Packing options tried: 1
Packing options skipped: 0
Trying to place using best packing [16]
-***Allocating phv340[15:7] for packet_in_hdr.ingress_port[8:0]
-***Allocating phv340[6:0] for packet_in_hdr._padding[6:0]
+***Allocating phv334[15:7] for packet_in_hdr.ingress_port[8:0]
+***Allocating phv334[6:0] for packet_in_hdr._padding[6:0]
After allocating remaining parse nodes:
Allocation state: Final Allocation
-------------------------------------------------------------------------------
-| PHV Group | Containers Used | Bits Used | Bits Available |
-| (container bit widths) | (% used) | (% used) | |
-------------------------------------------------------------------------------
-| 0 (32) | 6 (37.50%) | 192 (37.50%) | 512 |
-| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
-| | | | |
-| 4 (8) | 3 (18.75%) | 24 (18.75%) | 128 |
-| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
-| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 4 (6.25%) | 32 (6.25%) | 512 |
-| | | | |
-| 8 (16) | 5 (31.25%) | 80 (31.25%) | 256 |
-| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
-| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 6 (6.25%) | 96 (6.25%) | 1536 |
-| | | | |
-| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
-| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
-| | | | |
-| 16 (8) T | 11 (68.75%) | 88 (68.75%) | 128 |
-| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 11 (34.38%) | 88 (34.38%) | 256 |
-| | | | |
-| 18 (16) T | 10 (62.50%) | 160 (62.50%) | 256 |
-| 19 (16) T | 5 (31.25%) | 80 (31.25%) | 256 |
-| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 15 (31.25%) | 240 (31.25%) | 768 |
-| | | | |
-| MAU total | 16 (7.14%) | 320 (7.81%) | 4096 |
-| Tagalong total | 37 (33.04%) | 680 (33.20%) | 2048 |
-| Overall total | 53 (15.77%) | 1000 (16.28%) | 6144 |
-------------------------------------------------------------------------------
+-----------------------------------------------------------------------------
+| PHV Group | Containers Used | Bits Used | Bits Available |
+| (container bit widths) | (% used) | (% used) | |
+-----------------------------------------------------------------------------
+| 0 (32) | 6 (37.50%) | 192 (37.50%) | 512 |
+| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
+| | | | |
+| 4 (8) | 4 (25.00%) | 32 (25.00%) | 128 |
+| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
+| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| Total for 8 bit | 5 (7.81%) | 40 (7.81%) | 512 |
+| | | | |
+| 8 (16) | 6 (37.50%) | 96 (37.50%) | 256 |
+| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
+| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| Total for 16 bit | 7 (7.29%) | 112 (7.29%) | 1536 |
+| | | | |
+| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
+| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
+| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
+| | | | |
+| 16 (8) T | 8 (50.00%) | 64 (50.00%) | 128 |
+| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
+| Total for 8 bit | 8 (25.00%) | 64 (25.00%) | 256 |
+| | | | |
+| 18 (16) T | 13 (81.25%) | 208 (81.25%) | 256 |
+| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| Total for 16 bit | 13 (27.08%) | 208 (27.08%) | 768 |
+| | | | |
+| MAU total | 18 (8.04%) | 344 (8.40%) | 4096 |
+| Tagalong total | 32 (28.57%) | 624 (30.47%) | 2048 |
+| Overall total | 50 (14.88%) | 968 (15.76%) | 6144 |
+-----------------------------------------------------------------------------
Difference in allocation between critical parse path and overlaying headers:
Allocation state: Diff
----------------------------------------------------------------------------
-| PHV Group | Containers Used | Bits Used | Bits Available |
-| (container bit widths) | (% used) | (% used) | |
----------------------------------------------------------------------------
-| 0 (32) | 1 (6.25%) | 32 (6.25%) | 512 |
-| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 1 (1.56%) | 32 (1.56%) | 2048 |
-| | | | |
-| 4 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| 5 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 0 (0.00%) | 0 (0.00%) | 512 |
-| | | | |
-| 8 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 9 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 0 (0.00%) | 0 (0.00%) | 1536 |
-| | | | |
-| 14 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
-| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 0 (0.00%) | 0 (0.00%) | 1024 |
-| | | | |
-| 16 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 0 (0.00%) | 0 (0.00%) | 256 |
-| | | | |
-| 18 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 0 (0.00%) | 0 (0.00%) | 768 |
-| | | | |
-| MAU total | 1 (0.45%) | 32 (0.78%) | 4096 |
-| Tagalong total | 0 (0.00%) | 0 (0.00%) | 2048 |
-| Overall total | 1 (0.30%) | 32 (0.52%) | 6144 |
----------------------------------------------------------------------------
+--------------------------------------------------------------------------
+| PHV Group | Containers Used | Bits Used | Bits Available |
+| (container bit widths) | (% used) | (% used) | |
+--------------------------------------------------------------------------
+| 0 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| Total for 32 bit | 0 (0.00%) | 0 (0.00%) | 2048 |
+| | | | |
+| 4 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| 5 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| Total for 8 bit | 0 (0.00%) | 0 (0.00%) | 512 |
+| | | | |
+| 8 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 9 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| Total for 16 bit | 0 (0.00%) | 0 (0.00%) | 1536 |
+| | | | |
+| 14 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
+| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
+| Total for 32 bit | 0 (0.00%) | 0 (0.00%) | 1024 |
+| | | | |
+| 16 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
+| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
+| Total for 8 bit | 0 (0.00%) | 0 (0.00%) | 256 |
+| | | | |
+| 18 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| Total for 16 bit | 0 (0.00%) | 0 (0.00%) | 768 |
+| | | | |
+| MAU total | 0 (0.00%) | 0 (0.00%) | 4096 |
+| Tagalong total | 0 (0.00%) | 0 (0.00%) | 2048 |
+| Overall total | 0 (0.00%) | 0 (0.00%) | 6144 |
+--------------------------------------------------------------------------
->>Event 'pa_meta1' at time 1505214968.21
- Took 3.72 seconds
+>>Event 'pa_meta1' at time 1505264392.74
+ Took 0.51 seconds
-----------------------------------------------
Allocating metadata (pass 1)
@@ -2754,47 +2415,47 @@
***Allocating phv130[8:0] for ig_intr_md_for_tm.ucast_egress_port[8:0]
Allocation state after promised meta allocated:
Allocation state: Final Allocation
-------------------------------------------------------------------------------
-| PHV Group | Containers Used | Bits Used | Bits Available |
-| (container bit widths) | (% used) | (% used) | |
-------------------------------------------------------------------------------
-| 0 (32) | 6 (37.50%) | 192 (37.50%) | 512 |
-| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
-| | | | |
-| 4 (8) | 3 (18.75%) | 24 (18.75%) | 128 |
-| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
-| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 4 (6.25%) | 32 (6.25%) | 512 |
-| | | | |
-| 8 (16) | 6 (37.50%) | 89 (34.77%) | 256 |
-| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
-| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 7 (7.29%) | 105 (6.84%) | 1536 |
-| | | | |
-| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
-| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
-| | | | |
-| 16 (8) T | 11 (68.75%) | 88 (68.75%) | 128 |
-| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 11 (34.38%) | 88 (34.38%) | 256 |
-| | | | |
-| 18 (16) T | 10 (62.50%) | 160 (62.50%) | 256 |
-| 19 (16) T | 5 (31.25%) | 80 (31.25%) | 256 |
-| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 15 (31.25%) | 240 (31.25%) | 768 |
-| | | | |
-| MAU total | 17 (7.59%) | 329 (8.03%) | 4096 |
-| Tagalong total | 37 (33.04%) | 680 (33.20%) | 2048 |
-| Overall total | 54 (16.07%) | 1009 (16.42%) | 6144 |
-------------------------------------------------------------------------------
+-----------------------------------------------------------------------------
+| PHV Group | Containers Used | Bits Used | Bits Available |
+| (container bit widths) | (% used) | (% used) | |
+-----------------------------------------------------------------------------
+| 0 (32) | 6 (37.50%) | 192 (37.50%) | 512 |
+| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
+| | | | |
+| 4 (8) | 4 (25.00%) | 32 (25.00%) | 128 |
+| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
+| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| Total for 8 bit | 5 (7.81%) | 40 (7.81%) | 512 |
+| | | | |
+| 8 (16) | 7 (43.75%) | 105 (41.02%) | 256 |
+| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
+| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| Total for 16 bit | 8 (8.33%) | 121 (7.88%) | 1536 |
+| | | | |
+| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
+| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
+| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
+| | | | |
+| 16 (8) T | 8 (50.00%) | 64 (50.00%) | 128 |
+| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
+| Total for 8 bit | 8 (25.00%) | 64 (25.00%) | 256 |
+| | | | |
+| 18 (16) T | 13 (81.25%) | 208 (81.25%) | 256 |
+| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| Total for 16 bit | 13 (27.08%) | 208 (27.08%) | 768 |
+| | | | |
+| MAU total | 19 (8.48%) | 353 (8.62%) | 4096 |
+| Tagalong total | 32 (28.57%) | 624 (30.47%) | 2048 |
+| Overall total | 51 (15.18%) | 977 (15.90%) | 6144 |
+-----------------------------------------------------------------------------
Allocation state difference after promised meta allocated:
Allocation state: Diff
@@ -2841,55 +2502,55 @@
--------------------------------------------------------------------------
Sorted metadata field instances to allocate: 0 / 0 bits (0 ingress bits and 0 egress bits)
->>Event 'pa_pov' at time 1505214968.31
- Took 0.10 seconds
+>>Event 'pa_pov' at time 1505264392.84
+ Took 0.11 seconds
-----------------------------------------------
Allocating POV
-----------------------------------------------
Allocation Step
Allocation state: Final Allocation
-------------------------------------------------------------------------------
-| PHV Group | Containers Used | Bits Used | Bits Available |
-| (container bit widths) | (% used) | (% used) | |
-------------------------------------------------------------------------------
-| 0 (32) | 6 (37.50%) | 192 (37.50%) | 512 |
-| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
-| | | | |
-| 4 (8) | 3 (18.75%) | 24 (18.75%) | 128 |
-| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
-| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 4 (6.25%) | 32 (6.25%) | 512 |
-| | | | |
-| 8 (16) | 6 (37.50%) | 89 (34.77%) | 256 |
-| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
-| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 7 (7.29%) | 105 (6.84%) | 1536 |
-| | | | |
-| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
-| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
-| | | | |
-| 16 (8) T | 11 (68.75%) | 88 (68.75%) | 128 |
-| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 11 (34.38%) | 88 (34.38%) | 256 |
-| | | | |
-| 18 (16) T | 10 (62.50%) | 160 (62.50%) | 256 |
-| 19 (16) T | 5 (31.25%) | 80 (31.25%) | 256 |
-| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 15 (31.25%) | 240 (31.25%) | 768 |
-| | | | |
-| MAU total | 17 (7.59%) | 329 (8.03%) | 4096 |
-| Tagalong total | 37 (33.04%) | 680 (33.20%) | 2048 |
-| Overall total | 54 (16.07%) | 1009 (16.42%) | 6144 |
-------------------------------------------------------------------------------
+-----------------------------------------------------------------------------
+| PHV Group | Containers Used | Bits Used | Bits Available |
+| (container bit widths) | (% used) | (% used) | |
+-----------------------------------------------------------------------------
+| 0 (32) | 6 (37.50%) | 192 (37.50%) | 512 |
+| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
+| | | | |
+| 4 (8) | 4 (25.00%) | 32 (25.00%) | 128 |
+| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
+| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| Total for 8 bit | 5 (7.81%) | 40 (7.81%) | 512 |
+| | | | |
+| 8 (16) | 7 (43.75%) | 105 (41.02%) | 256 |
+| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
+| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| Total for 16 bit | 8 (8.33%) | 121 (7.88%) | 1536 |
+| | | | |
+| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
+| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
+| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
+| | | | |
+| 16 (8) T | 8 (50.00%) | 64 (50.00%) | 128 |
+| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
+| Total for 8 bit | 8 (25.00%) | 64 (25.00%) | 256 |
+| | | | |
+| 18 (16) T | 13 (81.25%) | 208 (81.25%) | 256 |
+| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| Total for 16 bit | 13 (27.08%) | 208 (27.08%) | 768 |
+| | | | |
+| MAU total | 19 (8.48%) | 353 (8.62%) | 4096 |
+| Tagalong total | 32 (28.57%) | 624 (30.47%) | 2048 |
+| Overall total | 51 (15.18%) | 977 (15.90%) | 6144 |
+-----------------------------------------------------------------------------
Sorted POV field instances to allocate (with best pack): 13
0: --validity_check--packet_in_hdr (ingress) -- max pov share 6 / best pack 5
@@ -2913,19 +2574,19 @@
Best pack group: (6)
Looking for container to share POV bit in from already allocated containers for POV.
-Container availability (not used yet for POV): total 193 / partial 1
+Container availability (not used yet for POV): total 191 / partial 1
Looking for container to share POV bit in from already allocated containers that have not been used for POV.
->>Choose container phv67, starting at container bit 0, which results in 7 bits still available (unused = 8 and could fit = 7).
+>>Choose container phv68, starting at container bit 0, which results in 7 bits still available (unused = 8 and could fit = 7).
>> Decided to allocate new container
-Required container phv67
-***Allocating phv67[0:0] for --validity_check--packet_in_hdr[0:0]
-***Allocating phv67[1:1] for --validity_check--packet_out_hdr[0:0]
-***Allocating phv67[2:2] for --validity_check--ethernet[0:0]
-***Allocating phv67[3:3] for --validity_check--ipv4[0:0]
-***Allocating phv67[4:4] for --validity_check--tcp[0:0]
-***Allocating phv67[5:5] for --validity_check--udp[0:0]
-***Allocating phv67[6:6] for --validity_check--metadata_bridge[0:0]
+Required container phv68
+***Allocating phv68[0:0] for --validity_check--packet_in_hdr[0:0]
+***Allocating phv68[1:1] for --validity_check--packet_out_hdr[0:0]
+***Allocating phv68[2:2] for --validity_check--ethernet[0:0]
+***Allocating phv68[3:3] for --validity_check--ipv4[0:0]
+***Allocating phv68[4:4] for --validity_check--tcp[0:0]
+***Allocating phv68[5:5] for --validity_check--udp[0:0]
+***Allocating phv68[6:6] for --validity_check--metadata_bridge[0:0]
Working on
--validity_check--packet_out_hdr <1 bits ingress parsed pov R W>
@@ -2993,12 +2654,12 @@
Sum of container bit widths POVs found in: 16
ingress
- phv67 (8 bits)
+ phv68 (8 bits)
>> 8 total bits
egress
phv81 (8 bits)
>> 8 total bits
->>Event 'pa_meta2' at time 1505214968.43
+>>Event 'pa_meta2' at time 1505264392.97
Took 0.12 seconds
-----------------------------------------------
@@ -3009,47 +2670,47 @@
Promised metadata field instances to allocate: 0 / 0 bits (0 ingress bits and 0 egress bits)
Allocation state after promised meta allocated:
Allocation state: Final Allocation
-------------------------------------------------------------------------------
-| PHV Group | Containers Used | Bits Used | Bits Available |
-| (container bit widths) | (% used) | (% used) | |
-------------------------------------------------------------------------------
-| 0 (32) | 6 (37.50%) | 192 (37.50%) | 512 |
-| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
-| | | | |
-| 4 (8) | 4 (25.00%) | 31 (24.22%) | 128 |
-| 5 (8) | 2 (12.50%) | 14 (10.94%) | 128 |
-| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 6 (9.38%) | 45 (8.79%) | 512 |
-| | | | |
-| 8 (16) | 6 (37.50%) | 89 (34.77%) | 256 |
-| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
-| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 7 (7.29%) | 105 (6.84%) | 1536 |
-| | | | |
-| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
-| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
-| | | | |
-| 16 (8) T | 11 (68.75%) | 88 (68.75%) | 128 |
-| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 11 (34.38%) | 88 (34.38%) | 256 |
-| | | | |
-| 18 (16) T | 10 (62.50%) | 160 (62.50%) | 256 |
-| 19 (16) T | 5 (31.25%) | 80 (31.25%) | 256 |
-| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 15 (31.25%) | 240 (31.25%) | 768 |
-| | | | |
-| MAU total | 19 (8.48%) | 342 (8.35%) | 4096 |
-| Tagalong total | 37 (33.04%) | 680 (33.20%) | 2048 |
-| Overall total | 56 (16.67%) | 1022 (16.63%) | 6144 |
-------------------------------------------------------------------------------
+-----------------------------------------------------------------------------
+| PHV Group | Containers Used | Bits Used | Bits Available |
+| (container bit widths) | (% used) | (% used) | |
+-----------------------------------------------------------------------------
+| 0 (32) | 6 (37.50%) | 192 (37.50%) | 512 |
+| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
+| | | | |
+| 4 (8) | 5 (31.25%) | 39 (30.47%) | 128 |
+| 5 (8) | 2 (12.50%) | 14 (10.94%) | 128 |
+| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| Total for 8 bit | 7 (10.94%) | 53 (10.35%) | 512 |
+| | | | |
+| 8 (16) | 7 (43.75%) | 105 (41.02%) | 256 |
+| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
+| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| Total for 16 bit | 8 (8.33%) | 121 (7.88%) | 1536 |
+| | | | |
+| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
+| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
+| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
+| | | | |
+| 16 (8) T | 8 (50.00%) | 64 (50.00%) | 128 |
+| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
+| Total for 8 bit | 8 (25.00%) | 64 (25.00%) | 256 |
+| | | | |
+| 18 (16) T | 13 (81.25%) | 208 (81.25%) | 256 |
+| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| Total for 16 bit | 13 (27.08%) | 208 (27.08%) | 768 |
+| | | | |
+| MAU total | 21 (9.38%) | 366 (8.94%) | 4096 |
+| Tagalong total | 32 (28.57%) | 624 (30.47%) | 2048 |
+| Overall total | 53 (15.77%) | 990 (16.11%) | 6144 |
+-----------------------------------------------------------------------------
Allocation state difference after promised meta allocated:
Allocation state: Diff
@@ -3125,11 +2786,11 @@
Group 1 32 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 2 32 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv32 -- fails False
Group 3 32 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv48 -- fails False
- Group 4 8 bits -- avail 12 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
+ Group 4 8 bits -- avail 11 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 5 8 bits -- avail 14 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 6 8 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 7 8 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
- Group 8 16 bits -- avail 10 and promised 1 -- ingress promised 1 and remain 9 and req 0 -- egress promised 0 and remain 8 and req 0 -- as if deparsed False -- container_to_use phv134 -- fails False
+ Group 8 16 bits -- avail 9 and promised 1 -- ingress promised 1 and remain 8 and req 0 -- egress promised 0 and remain 8 and req 0 -- as if deparsed False -- container_to_use phv135 -- fails False
Group 9 16 bits -- avail 15 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 10 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv160 -- fails False
Group 11 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv176 -- fails False
@@ -3139,7 +2800,7 @@
>>req_alignment = None
>>allowed_container_start_bits = None
>>req_container = None
-***Allocating phv134[15:0] for ecmp_metadata.group_id[15:0]
+***Allocating phv135[15:0] for ecmp_metadata.group_id[15:0]
---------------------------------------
Working on:
@@ -3166,11 +2827,11 @@
Group 1 32 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 2 32 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv32 -- fails False
Group 3 32 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv48 -- fails False
- Group 4 8 bits -- avail 12 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
+ Group 4 8 bits -- avail 11 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 5 8 bits -- avail 14 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 6 8 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 7 8 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
- Group 8 16 bits -- avail 9 and promised 1 -- ingress promised 1 and remain 8 and req 0 -- egress promised 0 and remain 8 and req 0 -- as if deparsed False -- container_to_use phv135 -- fails False
+ Group 8 16 bits -- avail 8 and promised 1 -- ingress promised 1 and remain 7 and req 0 -- egress promised 0 and remain 7 and req 0 -- as if deparsed False -- container_to_use phv136 -- fails False
Group 9 16 bits -- avail 15 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 10 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv160 -- fails False
Group 11 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv176 -- fails False
@@ -3180,7 +2841,7 @@
>>req_alignment = None
>>allowed_container_start_bits = None
>>req_container = None
-***Allocating phv135[15:0] for ecmp_metadata.selector[15:0]
+***Allocating phv136[15:0] for ecmp_metadata.selector[15:0]
---------------------------------------
Working on:
@@ -3207,11 +2868,11 @@
Group 1 32 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 2 32 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 12 and req 0 -- as if deparsed True -- container_to_use phv32 -- fails False
Group 3 32 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 12 and req 0 -- as if deparsed True -- container_to_use phv48 -- fails False
- Group 4 8 bits -- avail 12 and promised 1 -- ingress promised 1 and remain 11 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv68 -- fails False
+ Group 4 8 bits -- avail 11 and promised 1 -- ingress promised 1 and remain 10 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv69 -- fails False
Group 5 8 bits -- avail 14 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 6 8 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv96 -- fails False
Group 7 8 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv112 -- fails False
- Group 8 16 bits -- avail 8 and promised 1 -- ingress promised 1 and remain 7 and req 1 -- egress promised 0 and remain 0 and req 0 -- as if deparsed True -- container_to_use phv136 -- fails False
+ Group 8 16 bits -- avail 7 and promised 1 -- ingress promised 1 and remain 6 and req 1 -- egress promised 0 and remain 0 and req 0 -- as if deparsed True -- container_to_use phv137 -- fails False
Group 9 16 bits -- avail 15 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 10 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv160 -- fails False
Group 11 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv176 -- fails False
@@ -3224,8 +2885,8 @@
case 2: looking at allowed start bits [0, 1, 2, 3, 4, 5, 6, 7]
final start_bit = 5
(1) msb_offset = 8
-***Allocating phv68[7:5] for ig_intr_md_for_tm.drop_ctl[2:0]
->>Event 'pa_meta_init' at time 1505214968.59
+***Allocating phv69[7:5] for ig_intr_md_for_tm.drop_ctl[2:0]
+>>Event 'pa_meta_init' at time 1505264393.13
Took 0.16 seconds
-----------------------------------------------
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.results.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.results.log
index f790718..5d2349e 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.results.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.results.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: pa.results.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
Program: ecmp
@@ -17,36 +17,36 @@
| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
| | | | |
-| 4 (8) | 5 (31.25%) | 34 (26.56%) | 128 |
+| 4 (8) | 6 (37.50%) | 42 (32.81%) | 128 |
| 5 (8) | 2 (12.50%) | 14 (10.94%) | 128 |
| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 7 (10.94%) | 48 (9.38%) | 512 |
+| Total for 8 bit | 8 (12.50%) | 56 (10.94%) | 512 |
| | | | |
-| 8 (16) | 8 (50.00%) | 121 (47.27%) | 256 |
+| 8 (16) | 9 (56.25%) | 137 (53.52%) | 256 |
| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 9 (9.38%) | 137 (8.92%) | 1536 |
+| Total for 16 bit | 10 (10.42%) | 153 (9.96%) | 1536 |
| | | | |
| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
| | | | |
-| 16 (8) T | 11 (68.75%) | 88 (68.75%) | 128 |
+| 16 (8) T | 8 (50.00%) | 64 (50.00%) | 128 |
| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 11 (34.38%) | 88 (34.38%) | 256 |
+| Total for 8 bit | 8 (25.00%) | 64 (25.00%) | 256 |
| | | | |
-| 18 (16) T | 10 (62.50%) | 160 (62.50%) | 256 |
-| 19 (16) T | 5 (31.25%) | 80 (31.25%) | 256 |
+| 18 (16) T | 13 (81.25%) | 208 (81.25%) | 256 |
+| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 15 (31.25%) | 240 (31.25%) | 768 |
+| Total for 16 bit | 13 (27.08%) | 208 (27.08%) | 768 |
| | | | |
-| MAU total | 22 (9.82%) | 377 (9.20%) | 4096 |
-| Tagalong total | 37 (33.04%) | 680 (33.20%) | 2048 |
-| Overall total | 59 (17.56%) | 1057 (17.20%) | 6144 |
+| MAU total | 24 (10.71%) | 401 (9.79%) | 4096 |
+| Tagalong total | 32 (28.57%) | 624 (30.47%) | 2048 |
+| Overall total | 56 (16.67%) | 1025 (16.68%) | 6144 |
------------------------------------------------------------------------------
--------------------------------------------
@@ -59,25 +59,27 @@
32-bit PHV 1 (ingress): phv1[23:8] = ipv4.hdrChecksum[15:0] (tagalong capable) (deparsed)
32-bit PHV 1 (ingress): phv1[7:0] = ipv4.srcAddr[31:24] (deparsed)
32-bit PHV 2 (ingress): phv2[31:0] = ipv4.dstAddr[31:0] (deparsed)
- 32-bit PHV 3 (ingress): phv3[31:0] = ethernet.dstAddr[39:8] (deparsed)
- 32-bit PHV 4 (ingress): phv4[31:0] = ethernet.srcAddr[31:0] (deparsed)
- 32-bit PHV 5 (ingress): phv5[31:16] = udp.srcPort[15:0] (deparsed)
- 32-bit PHV 5 (ingress): phv5[15:0] = udp.dstPort[15:0] (deparsed)
+ 32-bit PHV 3 (ingress): phv3[31:24] = tcp.dstPort[7:0] (deparsed)
+ 32-bit PHV 3 (ingress): phv3[23:0] = tcp.seqNo[31:8] (tagalong capable) (deparsed)
+ 32-bit PHV 4 (ingress): phv4[31:0] = ethernet.dstAddr[39:8] (deparsed)
+ 32-bit PHV 5 (ingress): phv5[31:0] = ethernet.srcAddr[31:0] (deparsed)
>> 6 in ingress and 0 in egress
Allocations in Group 4 8 bits
8-bit PHV 64 (ingress): phv64[7:0] = ipv4.srcAddr[23:16] (deparsed)
- 8-bit PHV 65 (ingress): phv65[7:0] = ethernet.dstAddr[47:40] (deparsed)
- 8-bit PHV 66 (ingress): phv66[7:0] = ethernet.srcAddr[39:32] (deparsed)
- 8-bit PHV 67 (ingress): phv67[6:6] = --validity_check--metadata_bridge[0:0] (deparsed)
- 8-bit PHV 67 (ingress): phv67[5:5] = --validity_check--udp[0:0] (deparsed)
- 8-bit PHV 67 (ingress): phv67[4:4] = --validity_check--tcp[0:0] (deparsed)
- 8-bit PHV 67 (ingress): phv67[3:3] = --validity_check--ipv4[0:0] (deparsed)
- 8-bit PHV 67 (ingress): phv67[2:2] = --validity_check--ethernet[0:0] (deparsed)
- 8-bit PHV 67 (ingress): phv67[1:1] = --validity_check--packet_out_hdr[0:0] (deparsed)
- 8-bit PHV 67 (ingress): phv67[0:0] = --validity_check--packet_in_hdr[0:0] (deparsed)
- 8-bit PHV 68 (ingress): phv68[7:5] = ig_intr_md_for_tm.drop_ctl[2:0] (deparsed)
- >> 5 in ingress and 0 in egress
+ 8-bit PHV 65 (ingress): phv65[7:0] = tcp.srcPort[15:8] (deparsed)
+ 8-bit PHV 65 (ingress): phv65[7:0] = udp.srcPort[7:0] (tagalong capable) (deparsed)
+ 8-bit PHV 66 (ingress): phv66[7:0] = ethernet.dstAddr[47:40] (deparsed)
+ 8-bit PHV 67 (ingress): phv67[7:0] = ethernet.srcAddr[39:32] (deparsed)
+ 8-bit PHV 68 (ingress): phv68[6:6] = --validity_check--metadata_bridge[0:0] (deparsed)
+ 8-bit PHV 68 (ingress): phv68[5:5] = --validity_check--udp[0:0] (deparsed)
+ 8-bit PHV 68 (ingress): phv68[4:4] = --validity_check--tcp[0:0] (deparsed)
+ 8-bit PHV 68 (ingress): phv68[3:3] = --validity_check--ipv4[0:0] (deparsed)
+ 8-bit PHV 68 (ingress): phv68[2:2] = --validity_check--ethernet[0:0] (deparsed)
+ 8-bit PHV 68 (ingress): phv68[1:1] = --validity_check--packet_out_hdr[0:0] (deparsed)
+ 8-bit PHV 68 (ingress): phv68[0:0] = --validity_check--packet_in_hdr[0:0] (deparsed)
+ 8-bit PHV 69 (ingress): phv69[7:5] = ig_intr_md_for_tm.drop_ctl[2:0] (deparsed)
+ >> 6 in ingress and 0 in egress
Allocations in Group 5 8 bits
8-bit PHV 80 (egress): phv80[7:3] = eg_intr_md._pad7[4:0]
@@ -102,12 +104,14 @@
16-bit PHV 129 (ingress): phv129[6:0] = packet_in_hdr._padding[6:0] (tagalong capable) (deparsed)
16-bit PHV 130 (ingress): phv130[8:0] = ig_intr_md_for_tm.ucast_egress_port[8:0] (deparsed)
16-bit PHV 131 (ingress): phv131[15:0] = ipv4.srcAddr[15:0] (deparsed)
- 16-bit PHV 132 (ingress): phv132[15:8] = ethernet.dstAddr[7:0] (deparsed)
- 16-bit PHV 132 (ingress): phv132[7:0] = ethernet.srcAddr[47:40] (deparsed)
- 16-bit PHV 133 (ingress): phv133[15:0] = ethernet.etherType[15:0] (deparsed)
- 16-bit PHV 134 (ingress): phv134[15:0] = ecmp_metadata.group_id[15:0]
- 16-bit PHV 135 (ingress): phv135[15:0] = ecmp_metadata.selector[15:0]
- >> 8 in ingress and 0 in egress
+ 16-bit PHV 132 (ingress): phv132[15:8] = tcp.srcPort[7:0] (deparsed)
+ 16-bit PHV 132 (ingress): phv132[7:0] = tcp.dstPort[15:8] (deparsed)
+ 16-bit PHV 133 (ingress): phv133[15:8] = ethernet.dstAddr[7:0] (deparsed)
+ 16-bit PHV 133 (ingress): phv133[7:0] = ethernet.srcAddr[47:40] (deparsed)
+ 16-bit PHV 134 (ingress): phv134[15:0] = ethernet.etherType[15:0] (deparsed)
+ 16-bit PHV 135 (ingress): phv135[15:0] = ecmp_metadata.group_id[15:0]
+ 16-bit PHV 136 (ingress): phv136[15:0] = ecmp_metadata.selector[15:0]
+ >> 9 in ingress and 0 in egress
Allocations in Group 9 16 bits
16-bit PHV 144 (egress): phv144[15:9] = eg_intr_md._pad0[6:0]
@@ -120,90 +124,83 @@
32-bit PHV 256 (ingress): phv256[20:8] = ipv4.fragOffset[12:0] (tagalong capable) (deparsed)
32-bit PHV 256 (ingress): phv256[7:0] = ipv4.ttl[7:0] (tagalong capable) (deparsed)
32-bit PHV 257 (ingress): phv257[31:28] = tcp.dataOffset[3:0] (tagalong capable) (deparsed)
+ 32-bit PHV 257 (ingress): phv257[31:16] = udp.length_[15:0] (tagalong capable) (deparsed)
32-bit PHV 257 (ingress): phv257[27:25] = tcp.res[2:0] (tagalong capable) (deparsed)
32-bit PHV 257 (ingress): phv257[24:22] = tcp.ecn[2:0] (tagalong capable) (deparsed)
32-bit PHV 257 (ingress): phv257[21:16] = tcp.ctrl[5:0] (tagalong capable) (deparsed)
32-bit PHV 257 (ingress): phv257[15:0] = tcp.window[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 257 (ingress): phv257[15:0] = udp.checksum[15:0] (tagalong capable) (deparsed)
32-bit PHV 258 (ingress): phv258[31:16] = tcp.checksum[15:0] (tagalong capable) (deparsed)
32-bit PHV 258 (ingress): phv258[15:0] = tcp.urgentPtr[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 264 (egress): phv264[31:24] = ipv4.ttl[7:0] (tagalong capable) (deparsed)
- 32-bit PHV 264 (egress): phv264[23:16] = ipv4.protocol[7:0] (tagalong capable) (deparsed)
- 32-bit PHV 264 (egress): phv264[15:0] = ipv4.hdrChecksum[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 265 (egress): phv265[31:0] = ipv4.srcAddr[31:0] (tagalong capable) (deparsed)
- 32-bit PHV 266 (egress): phv266[31:0] = ipv4.dstAddr[31:0] (tagalong capable) (deparsed)
- 32-bit PHV 267 (egress): phv267[31:0] = tcp.ackNo[31:0] (tagalong capable) (deparsed)
- 32-bit PHV 267 (egress): phv267[31:16] = udp.length_[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 267 (egress): phv267[15:0] = udp.checksum[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 268 (egress): phv268[31:28] = tcp.dataOffset[3:0] (tagalong capable) (deparsed)
- 32-bit PHV 268 (egress): phv268[27:25] = tcp.res[2:0] (tagalong capable) (deparsed)
- 32-bit PHV 268 (egress): phv268[24:22] = tcp.ecn[2:0] (tagalong capable) (deparsed)
- 32-bit PHV 268 (egress): phv268[21:16] = tcp.ctrl[5:0] (tagalong capable) (deparsed)
- 32-bit PHV 268 (egress): phv268[15:0] = tcp.window[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 269 (egress): phv269[31:16] = tcp.checksum[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 269 (egress): phv269[15:0] = tcp.urgentPtr[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 270 (egress): phv270[31:0] = ethernet.dstAddr[39:8] (tagalong capable) (deparsed)
- 32-bit PHV 271 (egress): phv271[31:0] = ethernet.srcAddr[31:0] (tagalong capable) (deparsed)
+ 32-bit PHV 260 (egress): phv260[31:24] = ipv4.ttl[7:0] (tagalong capable) (deparsed)
+ 32-bit PHV 260 (egress): phv260[23:16] = ipv4.protocol[7:0] (tagalong capable) (deparsed)
+ 32-bit PHV 260 (egress): phv260[15:0] = ipv4.hdrChecksum[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 261 (egress): phv261[31:0] = ipv4.srcAddr[31:0] (tagalong capable) (deparsed)
+ 32-bit PHV 262 (egress): phv262[31:0] = ipv4.dstAddr[31:0] (tagalong capable) (deparsed)
+ 32-bit PHV 263 (egress): phv263[31:0] = tcp.ackNo[31:0] (tagalong capable) (deparsed)
+ 32-bit PHV 263 (egress): phv263[31:16] = udp.length_[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 263 (egress): phv263[15:0] = udp.checksum[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 264 (egress): phv264[31:28] = tcp.dataOffset[3:0] (tagalong capable) (deparsed)
+ 32-bit PHV 264 (egress): phv264[27:25] = tcp.res[2:0] (tagalong capable) (deparsed)
+ 32-bit PHV 264 (egress): phv264[24:22] = tcp.ecn[2:0] (tagalong capable) (deparsed)
+ 32-bit PHV 264 (egress): phv264[21:16] = tcp.ctrl[5:0] (tagalong capable) (deparsed)
+ 32-bit PHV 264 (egress): phv264[15:0] = tcp.window[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 265 (egress): phv265[31:16] = tcp.checksum[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 265 (egress): phv265[15:0] = tcp.urgentPtr[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 266 (egress): phv266[31:0] = ethernet.dstAddr[39:8] (tagalong capable) (deparsed)
+ 32-bit PHV 267 (egress): phv267[31:0] = ethernet.srcAddr[31:0] (tagalong capable) (deparsed)
>> 3 in ingress and 8 in egress
Allocations in Group 16 8 bits (tagalong)
8-bit PHV 288 (ingress): phv288[7:4] = ipv4.version[3:0] (tagalong capable) (deparsed)
8-bit PHV 288 (ingress): phv288[3:0] = ipv4.ihl[3:0] (tagalong capable) (deparsed)
- 8-bit PHV 289 (ingress): phv289[7:0] = tcp.srcPort[15:8] (tagalong capable) (deparsed)
- 8-bit PHV 289 (ingress): phv289[7:0] = udp.length_[15:8] (tagalong capable) (deparsed)
- 8-bit PHV 290 (ingress): phv290[7:0] = tcp.srcPort[7:0] (tagalong capable) (deparsed)
- 8-bit PHV 290 (ingress): phv290[7:0] = udp.length_[7:0] (tagalong capable) (deparsed)
- 8-bit PHV 291 (ingress): phv291[7:0] = tcp.dstPort[15:8] (tagalong capable) (deparsed)
- 8-bit PHV 292 (ingress): phv292[7:0] = tcp.dstPort[7:0] (tagalong capable) (deparsed)
- 8-bit PHV 296 (egress): phv296[7:4] = ipv4.version[3:0] (tagalong capable) (deparsed)
- 8-bit PHV 296 (egress): phv296[3:0] = ipv4.ihl[3:0] (tagalong capable) (deparsed)
- 8-bit PHV 297 (egress): phv297[7:0] = ipv4.diffserv[7:0] (tagalong capable) (deparsed)
- 8-bit PHV 298 (egress): phv298[7:0] = tcp.srcPort[15:8] (tagalong capable) (deparsed)
- 8-bit PHV 298 (egress): phv298[7:0] = udp.srcPort[15:8] (tagalong capable) (deparsed)
- 8-bit PHV 299 (egress): phv299[7:0] = tcp.srcPort[7:0] (tagalong capable) (deparsed)
- 8-bit PHV 299 (egress): phv299[7:0] = udp.srcPort[7:0] (tagalong capable) (deparsed)
- 8-bit PHV 300 (egress): phv300[7:0] = ethernet.dstAddr[47:40] (tagalong capable) (deparsed)
- 8-bit PHV 301 (egress): phv301[7:0] = ethernet.srcAddr[39:32] (tagalong capable) (deparsed)
- >> 5 in ingress and 6 in egress
+ 8-bit PHV 289 (ingress): phv289[7:0] = tcp.seqNo[7:0] (tagalong capable) (deparsed)
+ 8-bit PHV 289 (ingress): phv289[7:0] = udp.srcPort[15:8] (tagalong capable) (deparsed)
+ 8-bit PHV 292 (egress): phv292[7:4] = ipv4.version[3:0] (tagalong capable) (deparsed)
+ 8-bit PHV 292 (egress): phv292[3:0] = ipv4.ihl[3:0] (tagalong capable) (deparsed)
+ 8-bit PHV 293 (egress): phv293[7:0] = ipv4.diffserv[7:0] (tagalong capable) (deparsed)
+ 8-bit PHV 294 (egress): phv294[7:0] = tcp.srcPort[15:8] (tagalong capable) (deparsed)
+ 8-bit PHV 294 (egress): phv294[7:0] = udp.srcPort[15:8] (tagalong capable) (deparsed)
+ 8-bit PHV 295 (egress): phv295[7:0] = tcp.srcPort[7:0] (tagalong capable) (deparsed)
+ 8-bit PHV 295 (egress): phv295[7:0] = udp.srcPort[7:0] (tagalong capable) (deparsed)
+ 8-bit PHV 296 (egress): phv296[7:0] = ethernet.dstAddr[47:40] (tagalong capable) (deparsed)
+ 8-bit PHV 297 (egress): phv297[7:0] = ethernet.srcAddr[39:32] (tagalong capable) (deparsed)
+ >> 2 in ingress and 6 in egress
Allocations in Group 18 16 bits (tagalong)
16-bit PHV 320 (ingress): phv320[15:8] = ipv4.diffserv[7:0] (tagalong capable) (deparsed)
16-bit PHV 320 (ingress): phv320[7:0] = ipv4.totalLen[15:8] (tagalong capable) (deparsed)
16-bit PHV 321 (ingress): phv321[15:8] = ipv4.totalLen[7:0] (tagalong capable) (deparsed)
16-bit PHV 321 (ingress): phv321[7:0] = ipv4.identification[15:8] (tagalong capable) (deparsed)
- 16-bit PHV 322 (ingress): phv322[15:0] = tcp.seqNo[31:16] (tagalong capable) (deparsed)
- 16-bit PHV 322 (ingress): phv322[15:0] = udp.checksum[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 323 (ingress): phv323[15:0] = tcp.seqNo[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 324 (ingress): phv324[15:0] = tcp.ackNo[31:16] (tagalong capable) (deparsed)
- 16-bit PHV 325 (ingress): phv325[15:0] = tcp.ackNo[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 332 (egress): phv332[15:0] = ipv4.totalLen[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 333 (egress): phv333[15:0] = ipv4.identification[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 334 (egress): phv334[15:13] = ipv4.flags[2:0] (tagalong capable) (deparsed)
- 16-bit PHV 334 (egress): phv334[12:0] = ipv4.fragOffset[12:0] (tagalong capable) (deparsed)
- 16-bit PHV 335 (egress): phv335[15:0] = tcp.dstPort[15:0] (tagalong capable) (deparsed)
- >> 6 in ingress and 4 in egress
-
-Allocations in Group 19 16 bits (tagalong)
- 16-bit PHV 336 (egress): phv336[15:0] = tcp.seqNo[31:16] (tagalong capable) (deparsed)
- 16-bit PHV 336 (egress): phv336[15:0] = udp.dstPort[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 337 (egress): phv337[15:0] = tcp.seqNo[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 338 (egress): phv338[15:8] = ethernet.dstAddr[7:0] (tagalong capable) (deparsed)
- 16-bit PHV 338 (egress): phv338[7:0] = ethernet.srcAddr[47:40] (tagalong capable) (deparsed)
- 16-bit PHV 339 (egress): phv339[15:0] = ethernet.etherType[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 340 (egress): phv340[15:7] = packet_out_hdr.egress_port[8:0] (tagalong capable) (deparsed)
- 16-bit PHV 340 (egress): phv340[15:7] = packet_in_hdr.ingress_port[8:0] (tagalong capable) (deparsed)
- 16-bit PHV 340 (egress): phv340[6:0] = packet_out_hdr._padding[6:0] (tagalong capable) (deparsed)
- 16-bit PHV 340 (egress): phv340[6:0] = packet_in_hdr._padding[6:0] (tagalong capable) (deparsed)
- >> 0 in ingress and 5 in egress
+ 16-bit PHV 322 (ingress): phv322[15:0] = tcp.ackNo[31:16] (tagalong capable) (deparsed)
+ 16-bit PHV 322 (ingress): phv322[15:0] = udp.dstPort[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 323 (ingress): phv323[15:0] = tcp.ackNo[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 326 (egress): phv326[15:0] = ipv4.totalLen[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 327 (egress): phv327[15:0] = ipv4.identification[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 328 (egress): phv328[15:13] = ipv4.flags[2:0] (tagalong capable) (deparsed)
+ 16-bit PHV 328 (egress): phv328[12:0] = ipv4.fragOffset[12:0] (tagalong capable) (deparsed)
+ 16-bit PHV 329 (egress): phv329[15:0] = tcp.dstPort[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 329 (egress): phv329[15:0] = udp.dstPort[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 330 (egress): phv330[15:0] = tcp.seqNo[31:16] (tagalong capable) (deparsed)
+ 16-bit PHV 331 (egress): phv331[15:0] = tcp.seqNo[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 332 (egress): phv332[15:8] = ethernet.dstAddr[7:0] (tagalong capable) (deparsed)
+ 16-bit PHV 332 (egress): phv332[7:0] = ethernet.srcAddr[47:40] (tagalong capable) (deparsed)
+ 16-bit PHV 333 (egress): phv333[15:0] = ethernet.etherType[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 334 (egress): phv334[15:7] = packet_out_hdr.egress_port[8:0] (tagalong capable) (deparsed)
+ 16-bit PHV 334 (egress): phv334[15:7] = packet_in_hdr.ingress_port[8:0] (tagalong capable) (deparsed)
+ 16-bit PHV 334 (egress): phv334[6:0] = packet_out_hdr._padding[6:0] (tagalong capable) (deparsed)
+ 16-bit PHV 334 (egress): phv334[6:0] = packet_in_hdr._padding[6:0] (tagalong capable) (deparsed)
+ >> 4 in ingress and 9 in egress
Final POV layout (ingress):
- 32: --validity_check--packet_in_hdr (ingress) in container 67
- 33: --validity_check--packet_out_hdr (ingress) in container 67
- 34: --validity_check--ethernet (ingress) in container 67
- 35: --validity_check--ipv4 (ingress) in container 67
- 36: --validity_check--tcp (ingress) in container 67
- 37: --validity_check--udp (ingress) in container 67
- 38: --validity_check--metadata_bridge (ingress) in container 67
+ 32: --validity_check--packet_in_hdr (ingress) in container 68
+ 33: --validity_check--packet_out_hdr (ingress) in container 68
+ 34: --validity_check--ethernet (ingress) in container 68
+ 35: --validity_check--ipv4 (ingress) in container 68
+ 36: --validity_check--tcp (ingress) in container 68
+ 37: --validity_check--udp (ingress) in container 68
+ 38: --validity_check--metadata_bridge (ingress) in container 68
Final POV layout (egress):
0: --validity_check--packet_in_hdr (egress) in container 81
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.calcfields.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.calcfields.log
index 3096df6..2aec839 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.calcfields.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.calcfields.log
@@ -1,37 +1,35 @@
+---------------------------------------------------------------------+
| Log file: parde.calcfields.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
Reserving 0 16-bit ingress tphvs for residual checksums
Reserving 0 16-bit egress tphvs for residual checksums
Need 0 POV bits for checksum update control
-Number of reachable states from state parse_tcp//spilled : 1
-Number of reachable states from state parse_tcp : 2
+Number of reachable states from state parse_tcp : 1
Number of reachable states from state parse_udp : 1
-Number of reachable states from state parse_ipv4 : 4
-Number of reachable states from state parse_ethernet : 5
-Number of reachable states from state parse_pkt_in : 6
-Number of reachable states from state parse_pkt_out : 6
-Number of reachable states from state default_parser : 7
-Number of reachable states from state start : 9
-Number of reachable states from state <POV initialization>_<Ingress intrinsic metadata>_<Phase 0> : 10
-Number of reachable states from state <Shim start state> : 11
+Number of reachable states from state parse_ipv4 : 3
+Number of reachable states from state parse_ethernet : 4
+Number of reachable states from state parse_pkt_in : 5
+Number of reachable states from state parse_pkt_out : 5
+Number of reachable states from state default_parser : 6
+Number of reachable states from state start : 8
+Number of reachable states from state <POV initialization>_<Ingress intrinsic metadata>_<Phase 0> : 9
+Number of reachable states from state <Shim start state> : 10
parser_state_calculations:[
- parse_tcp_140012620391248
- parse_tcp_140012609531792
- parse_udp_140012609530832
- parse_ipv4_140012609453328
- parse_ethernet_140012609450128
- parse_pkt_in_140012609453264
- parse_pkt_out_140012609529744
- default_parser_140012609529936
- start_140012609453008
- <Phase 0>_140012616925840
- <Ingress intrinsic metadata>_140012616925520
- <POV initialization>_140012616926224
- <Shim start state>_140012616926544
+ parse_tcp_140368914071184
+ parse_udp_140368914018832
+ parse_ipv4_140368914067984
+ parse_ethernet_140368916524560
+ parse_pkt_in_140368914070288
+ parse_pkt_out_140368914019920
+ default_parser_140368914019728
+ start_140368914069328
+ <Phase 0>_140368913928272
+ <Ingress intrinsic metadata>_140368913952464
+ <POV initialization>_140368913928656
+ <Shim start state>_140368913928976
]
parser_calculations: [
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.config.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.config.log
index f6b4359..e6fce26 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.config.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.config.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: parde.config.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
Configuring deparser.inp.iim.ii_phv_csum.csum_cfg[0].csum_cfg_entry[0].zero_m_s_b = 1
@@ -15994,9 +15994,9 @@
0 | I g0w0: [POV[31:0]]
1 | I g0w1: [ipv4.protocol, ipv4.hdrChecksum, ipv4.srcAddr[31:24]]
2 | I g0w2: [ipv4.dstAddr]
- 3 | I g0w3: [ethernet.dstAddr[39:8]]
- 4 | I g0w4: [ethernet.srcAddr[31:0]]
- 5 | I g0w5: [udp.srcPort, udp.dstPort]
+ 3 | I g0w3: [tcp.dstPort[7:0], tcp.seqNo[31:8]]
+ 4 | I g0w4: [ethernet.dstAddr[39:8]]
+ 5 | I g0w5: [ethernet.srcAddr[31:0]]
6 | g0w6:
7 | g0w7:
8 | g0w8:
@@ -16060,11 +16060,11 @@
|
8 bits
64 | I g2w0: [ipv4.srcAddr[23:16]]
- 65 | I g2w1: [ethernet.dstAddr[47:40]]
- 66 | I g2w2: [ethernet.srcAddr[39:32]]
- 67 | I g2w3: [POV[39:32]]
- 68 | I g2w4: [ig_intr_md_for_tm.drop_ctl]
- 69 | g2w5:
+ 65 | I g2w1: [tcp.srcPort[15:8], udp.srcPort[7:0]]
+ 66 | I g2w2: [ethernet.dstAddr[47:40]]
+ 67 | I g2w3: [ethernet.srcAddr[39:32]]
+ 68 | I g2w4: [POV[39:32]]
+ 69 | I g2w5: [ig_intr_md_for_tm.drop_ctl]
70 | g2w6:
71 | g2w7:
72 | g2w8:
@@ -16131,11 +16131,11 @@
129 | I g4w1: [packet_out_hdr.egress_port, packet_out_hdr._padding, packet_in_hdr.ingress_port, packet_in_hdr._padding]
130 | I g4w2: [ig_intr_md_for_tm.ucast_egress_port]
131 | I g4w3: [ipv4.srcAddr[15:0]]
- 132 | I g4w4: [ethernet.dstAddr[7:0], ethernet.srcAddr[47:40]]
- 133 | I g4w5: [ethernet.etherType]
- 134 | I g4w6: [ecmp_metadata.group_id]
- 135 | I g4w7: [ecmp_metadata.selector]
- 136 | g4w8:
+ 132 | I g4w4: [tcp.srcPort[7:0], tcp.dstPort[15:8]]
+ 133 | I g4w5: [ethernet.dstAddr[7:0], ethernet.srcAddr[47:40]]
+ 134 | I g4w6: [ethernet.etherType]
+ 135 | I g4w7: [ecmp_metadata.group_id]
+ 136 | I g4w8: [ecmp_metadata.selector]
137 | g4w9:
138 | g4w10:
139 | g4w11:
@@ -16232,21 +16232,21 @@
|
32 bits
256 | I g8w0: [ipv4.identification[7:0], ipv4.flags, ipv4.fragOffset, ipv4.ttl]
- 257 | I g8w1: [tcp.dataOffset, tcp.res, tcp.ecn, tcp.ctrl, tcp.window]
+ 257 | I g8w1: [tcp.dataOffset, tcp.res, tcp.ecn, tcp.ctrl, tcp.window, udp.length_, udp.checksum]
258 | I g8w2: [tcp.checksum, tcp.urgentPtr]
259 | g8w3:
- 260 | g8w4:
- 261 | g8w5:
- 262 | g8w6:
- 263 | g8w7:
- 264 | E g8w8: [ipv4.ttl, ipv4.protocol, ipv4.hdrChecksum]
- 265 | E g8w9: [ipv4.srcAddr]
- 266 | E g8w10: [ipv4.dstAddr]
- 267 | E g8w11: [tcp.ackNo, udp.length_, udp.checksum]
- 268 | E g8w12: [tcp.dataOffset, tcp.res, tcp.ecn, tcp.ctrl, tcp.window]
- 269 | E g8w13: [tcp.checksum, tcp.urgentPtr]
- 270 | E g8w14: [ethernet.dstAddr[39:8]]
- 271 | E g8w15: [ethernet.srcAddr[31:0]]
+ 260 | E g8w4: [ipv4.ttl, ipv4.protocol, ipv4.hdrChecksum]
+ 261 | E g8w5: [ipv4.srcAddr]
+ 262 | E g8w6: [ipv4.dstAddr]
+ 263 | E g8w7: [tcp.ackNo, udp.length_, udp.checksum]
+ 264 | E g8w8: [tcp.dataOffset, tcp.res, tcp.ecn, tcp.ctrl, tcp.window]
+ 265 | E g8w9: [tcp.checksum, tcp.urgentPtr]
+ 266 | E g8w10: [ethernet.dstAddr[39:8]]
+ 267 | E g8w11: [ethernet.srcAddr[31:0]]
+ 268 | g8w12:
+ 269 | g8w13:
+ 270 | g8w14:
+ 271 | g8w15:
272 | g8w16:
273 | g8w17:
274 | g8w18:
@@ -16266,19 +16266,19 @@
|
8 bits
288 | I g9w0: [ipv4.version, ipv4.ihl]
- 289 | I g9w1: [tcp.srcPort[15:8], udp.length_[15:8]]
- 290 | I g9w2: [tcp.srcPort[7:0], udp.length_[7:0]]
- 291 | I g9w3: [tcp.dstPort[15:8]]
- 292 | I g9w4: [tcp.dstPort[7:0]]
- 293 | g9w5:
- 294 | g9w6:
- 295 | g9w7:
- 296 | E g9w8: [ipv4.version, ipv4.ihl]
- 297 | E g9w9: [ipv4.diffserv]
- 298 | E g9w10: [tcp.srcPort[15:8], udp.srcPort[15:8]]
- 299 | E g9w11: [tcp.srcPort[7:0], udp.srcPort[7:0]]
- 300 | E g9w12: [ethernet.dstAddr[47:40]]
- 301 | E g9w13: [ethernet.srcAddr[39:32]]
+ 289 | I g9w1: [tcp.seqNo[7:0], udp.srcPort[15:8]]
+ 290 | g9w2:
+ 291 | g9w3:
+ 292 | E g9w4: [ipv4.version, ipv4.ihl]
+ 293 | E g9w5: [ipv4.diffserv]
+ 294 | E g9w6: [tcp.srcPort[15:8], udp.srcPort[15:8]]
+ 295 | E g9w7: [tcp.srcPort[7:0], udp.srcPort[7:0]]
+ 296 | E g9w8: [ethernet.dstAddr[47:40]]
+ 297 | E g9w9: [ethernet.srcAddr[39:32]]
+ 298 | g9w10:
+ 299 | g9w11:
+ 300 | g9w12:
+ 301 | g9w13:
302 | g9w14:
303 | g9w15:
304 | g9w16:
@@ -16301,25 +16301,25 @@
16 bits
320 | I g10w0: [ipv4.diffserv, ipv4.totalLen[15:8]]
321 | I g10w1: [ipv4.totalLen[7:0], ipv4.identification[15:8]]
- 322 | I g10w2: [tcp.seqNo[31:16], udp.checksum]
- 323 | I g10w3: [tcp.seqNo[15:0]]
- 324 | I g10w4: [tcp.ackNo[31:16]]
- 325 | I g10w5: [tcp.ackNo[15:0]]
- 326 | g10w6:
- 327 | g10w7:
- 328 | g10w8:
- 329 | g10w9:
- 330 | g10w10:
- 331 | g10w11:
- 332 | E g10w12: [ipv4.totalLen]
- 333 | E g10w13: [ipv4.identification]
- 334 | E g10w14: [ipv4.flags, ipv4.fragOffset]
- 335 | E g10w15: [tcp.dstPort]
- 336 | E g10w16: [tcp.seqNo[31:16], udp.dstPort]
- 337 | E g10w17: [tcp.seqNo[15:0]]
- 338 | E g10w18: [ethernet.dstAddr[7:0], ethernet.srcAddr[47:40]]
- 339 | E g10w19: [ethernet.etherType]
- 340 | E g10w20: [packet_out_hdr.egress_port, packet_out_hdr._padding, packet_in_hdr.ingress_port, packet_in_hdr._padding]
+ 322 | I g10w2: [tcp.ackNo[31:16], udp.dstPort]
+ 323 | I g10w3: [tcp.ackNo[15:0]]
+ 324 | g10w4:
+ 325 | g10w5:
+ 326 | E g10w6: [ipv4.totalLen]
+ 327 | E g10w7: [ipv4.identification]
+ 328 | E g10w8: [ipv4.flags, ipv4.fragOffset]
+ 329 | E g10w9: [tcp.dstPort, udp.dstPort]
+ 330 | E g10w10: [tcp.seqNo[31:16]]
+ 331 | E g10w11: [tcp.seqNo[15:0]]
+ 332 | E g10w12: [ethernet.dstAddr[7:0], ethernet.srcAddr[47:40]]
+ 333 | E g10w13: [ethernet.etherType]
+ 334 | E g10w14: [packet_out_hdr.egress_port, packet_out_hdr._padding, packet_in_hdr.ingress_port, packet_in_hdr._padding]
+ 335 | g10w15:
+ 336 | g10w16:
+ 337 | g10w17:
+ 338 | g10w18:
+ 339 | g10w19:
+ 340 | g10w20:
341 | g10w21:
342 | g10w22:
343 | g10w23:
@@ -16363,7 +16363,6 @@
7: parse_pkt_out
8: <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
9: start
- 10: parse_tcp//spilled
Egress:
0: <Shim start state>
1: parse_ethernet
@@ -16399,5 +16398,5 @@
[None]
---------------
Deparse order:
-Ingress: ['metadata_bridge', '_bridged_intr_md_', 'packet_out_hdr', 'packet_in_hdr', 'ethernet', 'ipv4', 'udp', 'tcp']
-Egress: ['packet_out_hdr', 'packet_in_hdr', 'ethernet', 'ipv4', 'udp', 'tcp']
+Ingress: ['metadata_bridge', '_bridged_intr_md_', 'packet_in_hdr', 'packet_out_hdr', 'ethernet', 'ipv4', 'udp', 'tcp']
+Egress: ['packet_in_hdr', 'packet_out_hdr', 'ethernet', 'ipv4', 'udp', 'tcp']
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.error.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.error.log
index 7353702..f633e91 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.error.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.error.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: parde.error.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.log
index d2894f8..9eca7bc 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: parde.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
># Begin digest init (pre-PHV)
@@ -18,14 +18,14 @@
># Begin unroll of HLIR parse graph
>## Create shadow parse graph and find loops
>## Entrypoint 'p4_parse_state.start'
-Creating shadow state: 'p4_parse_state.start' -> 'shadow_state (start, 140012609633872)'
-Creating shadow state: 'p4_parse_state.parse_pkt_in' -> 'shadow_state (parse_pkt_in, 140012609450640)'
-Creating shadow state: 'p4_parse_state.parse_ethernet' -> 'shadow_state (parse_ethernet, 140012609451216)'
-Creating shadow state: 'p4_parse_state.parse_ipv4' -> 'shadow_state (parse_ipv4, 140012609450448)'
-Creating shadow state: 'p4_parse_state.parse_tcp' -> 'shadow_state (parse_tcp, 140012609451280)'
-Creating shadow state: 'p4_parse_state.parse_udp' -> 'shadow_state (parse_udp, 140012609450064)'
-Creating shadow state: 'p4_parse_state.default_parser' -> 'shadow_state (default_parser, 140012609451344)'
-Creating shadow state: 'p4_parse_state.parse_pkt_out' -> 'shadow_state (parse_pkt_out, 140012609451408)'
+Creating shadow state: 'p4_parse_state.start' -> 'shadow_state (start, 140368916524624)'
+Creating shadow state: 'p4_parse_state.parse_pkt_in' -> 'shadow_state (parse_pkt_in, 140368916524176)'
+Creating shadow state: 'p4_parse_state.parse_ethernet' -> 'shadow_state (parse_ethernet, 140368914068240)'
+Creating shadow state: 'p4_parse_state.parse_ipv4' -> 'shadow_state (parse_ipv4, 140368914067920)'
+Creating shadow state: 'p4_parse_state.parse_tcp' -> 'shadow_state (parse_tcp, 140368914068304)'
+Creating shadow state: 'p4_parse_state.parse_udp' -> 'shadow_state (parse_udp, 140368914067536)'
+Creating shadow state: 'p4_parse_state.default_parser' -> 'shadow_state (default_parser, 140368914068368)'
+Creating shadow state: 'p4_parse_state.parse_pkt_out' -> 'shadow_state (parse_pkt_out, 140368914068432)'
># End unroll of HLIR parse graph
># Begin deparser init
>## Create records for gress 0
@@ -44,8 +44,8 @@
Created record for 'p4_header_instance.udp'
Skipping metadata header 'p4_header_instance.ecmp_metadata'
>## Build record ordering for gress 0
->## Build field ordering for record 'packet_out_hdr'
>## Build field ordering for record 'packet_in_hdr'
+>## Build field ordering for record 'packet_out_hdr'
>## Build field ordering for record 'ethernet'
>## Build field ordering for record 'ipv4'
>## Build field ordering for record 'udp'
@@ -66,8 +66,8 @@
Created record for 'p4_header_instance.udp'
Skipping metadata header 'p4_header_instance.ecmp_metadata'
>## Build record ordering for gress 1
->## Build field ordering for record 'packet_out_hdr'
>## Build field ordering for record 'packet_in_hdr'
+>## Build field ordering for record 'packet_out_hdr'
>## Build field ordering for record 'ethernet'
>## Build field ordering for record 'ipv4'
>## Build field ordering for record 'udp'
@@ -89,27 +89,27 @@
Stretch extraction of ingress_port to state <Ingress intrinsic metadata> offset 7
Stretch extraction of ig_intr_md.ingress_port to state <_parse_bridged_ingress_intrinsic_metadata> offset 7
># Begin scraping deparser POV allocation from raw PHV allocation
-PHV layout: [0, 0, 0, 0, 67, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
+PHV layout: [0, 0, 0, 0, 68, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
>## Scraping individual POV records
-POV 32 -> packet_in_hdr
POV 33 -> packet_out_hdr
POV 34 -> ethernet
POV 35 -> ipv4
POV 36 -> tcp
POV 37 -> udp
POV 38 -> pov_bmeta
+POV 32 -> packet_in_hdr
>## Setting up array bits
># End scraping deparser POV allocation from raw PHV allocation
># Begin parser POV rewrite
>## Filling in POV init state
>## Rewriting parser POV extractions
-POV for metadata_bridge -> PHV 67 |= 0x40
-POV for packet_in_hdr -> PHV 67 |= 0x1
-POV for ethernet -> PHV 67 |= 0x4
-POV for ipv4 -> PHV 67 |= 0x8
-POV for tcp -> PHV 67 |= 0x10
-POV for udp -> PHV 67 |= 0x20
-POV for packet_out_hdr -> PHV 67 |= 0x2
+POV for metadata_bridge -> PHV 68 |= 0x40
+POV for packet_in_hdr -> PHV 68 |= 0x1
+POV for ethernet -> PHV 68 |= 0x4
+POV for ipv4 -> PHV 68 |= 0x8
+POV for tcp -> PHV 68 |= 0x10
+POV for udp -> PHV 68 |= 0x20
+POV for packet_out_hdr -> PHV 68 |= 0x2
POV for ig_intr_md -> dropped (no deparser record)
POV for _bridged_intr_md_ -> PHV 0 |= 0x10000
>## Sampling not detected, deparsing at least 1 POV byte
@@ -118,12 +118,12 @@
># Begin scraping deparser POV allocation from raw PHV allocation
PHV layout: [81, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
>## Scraping individual POV records
-POV 0 -> packet_in_hdr
POV 1 -> packet_out_hdr
POV 2 -> ethernet
POV 3 -> ipv4
POV 4 -> tcp
POV 5 -> udp
+POV 0 -> packet_in_hdr
>## Setting up array bits
># End scraping deparser POV allocation from raw PHV allocation
># Begin parser POV rewrite
@@ -135,11 +135,6 @@
POV for tcp -> PHV 81 |= 0x10
POV for udp -> PHV 81 |= 0x20
POV for packet_out_hdr -> PHV 81 |= 0x2
-Linear Chain parse_tcp -> parse_tcp//spilled
-Try merge parse_tcp <- parse_tcp//spilled
-merge output at offset 24
-Ran out of 8b extractors
-states will not be partially merged since S2 is end of chain
Linear Chain parse_pkt_in -> parse_ethernet
Try merge parse_pkt_in <- parse_ethernet
Multiple paths to state S2 : parse_ethernet <- 3
@@ -199,7 +194,7 @@
Multiple paths to state S2 : start <- 2
Remove state <Ingress intrinsic metadata>
Remove state <Phase 0>
-assign ids to 11 states, dir = 0
+assign ids to 10 states, dir = 0
------
State : <Shim start state>
shift: 0B
@@ -212,7 +207,7 @@
State : parse_pkt_in
shift: 2B
match_reservations: []
-outputs[addr, width]: ([67, 8], [129, 16])
+outputs[addr, width]: ([68, 8], [129, 16])
match_extractions: []
next state parse_ethernet val 0 mask [False]
parent state start
@@ -221,7 +216,7 @@
State : parse_ethernet
shift: 14B
match_reservations: []
-outputs[addr, width]: ([67, 8], [65, 8], [3, 32], [132, 16], [66, 8], [4, 32], [133, 16])
+outputs[addr, width]: ([68, 8], [66, 8], [4, 32], [133, 16], [67, 8], [5, 32], [134, 16])
branch on = etherType, offset = 96b, dst = parse_ethernet
match_extractions: [match_window(hw_id=0, width=16)]
match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
@@ -234,30 +229,29 @@
State : parse_ipv4
shift: 20B
match_reservations: []
-outputs[addr, width]: ([67, 8], [288, 8], [320, 16], [321, 16], [256, 32], [1, 32], [64, 8], [131, 16], [2, 32])
+outputs[addr, width]: ([68, 8], [288, 8], [320, 16], [321, 16], [256, 32], [1, 32], [64, 8], [131, 16], [2, 32])
branch on = fragOffset, offset = 51b, dst = parse_ipv4
branch on = protocol, offset = 72b, dst = parse_ipv4
-match_extractions: [match_window(hw_id=2, width=8), match_window(hw_id=0, width=16)]
-match key = [0, 1, 2, 3, 4, 5, 6, 7]
+match_extractions: [match_window(hw_id=0, width=16), match_window(hw_id=2, width=8)]
match key = [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, None, None, None]
+match key = [0, 1, 2, 3, 4, 5, 6, 7]
next state parse_tcp val 6 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
next state parse_udp val 17 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
parent state parse_ethernet
------
State : parse_tcp
-shift: 0B
+shift: 20B
match_reservations: []
-outputs[addr, width]: ([67, 8], [289, 8], [290, 8], [291, 8], [322, 16], [323, 16], [324, 16], [325, 16], [257, 32], [258, 32])
+outputs[addr, width]: ([68, 8], [65, 8], [132, 16], [3, 32], [289, 8], [322, 16], [323, 16], [257, 32], [258, 32])
match_extractions: []
-next state parse_tcp//spilled val 0 mask [False]
parent state parse_ipv4
------
State : parse_udp
shift: 8B
match_reservations: []
-outputs[addr, width]: ([67, 8], [5, 32], [289, 8], [290, 8], [322, 16])
+outputs[addr, width]: ([68, 8], [289, 8], [65, 8], [322, 16], [257, 32])
match_extractions: []
parent state parse_ipv4
@@ -277,7 +271,7 @@
State : parse_pkt_out
shift: 2B
match_reservations: []
-outputs[addr, width]: ([67, 8], [129, 16])
+outputs[addr, width]: ([68, 8], [129, 16])
match_extractions: []
next state parse_ethernet val 0 mask [False]
parent state default_parser
@@ -290,9 +284,9 @@
branch on = None, offset = 0b, dst = <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
branch on = None, offset = 64b, dst = <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
branch promise on = ingress_port, offset = 7b, dst = default_parser
-match_extractions: [match_window(hw_id=2, width=8), match_window(hw_id=0, width=16)]
-match key = [0, 1, 2, 3, 4, 5, 6, 7]
+match_extractions: [match_window(hw_id=0, width=16), match_window(hw_id=2, width=8)]
match key = [None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, 8]
+match key = [0, 1, 2, 3, 4, 5, 6, 7]
next state start val 0 mask [False]
parent state <Shim start state>
@@ -300,7 +294,7 @@
State : start
shift: 0B
match_reservations: [match_window(hw_id=0, width=16)]
-outputs[addr, width]: ([67, 8],)
+outputs[addr, width]: ([68, 8],)
branch on = None, offset = 96b, dst = start
match_extractions: [match_window(hw_id=2, width=8)]
match key = [0, 1, 2, 3, 4, 5, 6, 7]
@@ -308,14 +302,6 @@
next state default_parser val 0 mask [False]
parent state <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
-------
-State : parse_tcp//spilled
-shift: 20B
-match_reservations: []
-outputs[addr, width]: ([292, 8],)
-match_extractions: []
-parent state parse_tcp
-
Linear Chain parse_pkt_in -> parse_ethernet
Try merge parse_pkt_in <- parse_ethernet
Multiple paths to state S2 : parse_ethernet <- 3
@@ -435,7 +421,7 @@
State : parse_ethernet
shift: 14B
match_reservations: []
-outputs[addr, width]: ([81, 8], [300, 8], [270, 32], [338, 16], [301, 8], [271, 32], [339, 16])
+outputs[addr, width]: ([81, 8], [296, 8], [266, 32], [332, 16], [297, 8], [267, 32], [333, 16])
branch on = etherType, offset = 96b, dst = parse_ethernet
match_extractions: [match_window(hw_id=0, width=16)]
match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
@@ -448,12 +434,12 @@
State : parse_ipv4
shift: 20B
match_reservations: []
-outputs[addr, width]: ([81, 8], [296, 8], [297, 8], [332, 16], [333, 16], [334, 16], [264, 32], [265, 32], [266, 32])
+outputs[addr, width]: ([81, 8], [292, 8], [293, 8], [326, 16], [327, 16], [328, 16], [260, 32], [261, 32], [262, 32])
branch on = fragOffset, offset = 51b, dst = parse_ipv4
branch on = protocol, offset = 72b, dst = parse_ipv4
-match_extractions: [match_window(hw_id=2, width=8), match_window(hw_id=0, width=16)]
-match key = [0, 1, 2, 3, 4, 5, 6, 7]
+match_extractions: [match_window(hw_id=0, width=16), match_window(hw_id=2, width=8)]
match key = [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, None, None, None]
+match key = [0, 1, 2, 3, 4, 5, 6, 7]
next state parse_tcp val 6 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
next state parse_udp val 17 mask [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True]
parent state parse_ethernet
@@ -462,7 +448,7 @@
State : parse_tcp
shift: 20B
match_reservations: []
-outputs[addr, width]: ([81, 8], [298, 8], [299, 8], [335, 16], [336, 16], [337, 16], [267, 32], [268, 32], [269, 32])
+outputs[addr, width]: ([81, 8], [294, 8], [295, 8], [329, 16], [330, 16], [331, 16], [263, 32], [264, 32], [265, 32])
match_extractions: []
parent state parse_ipv4
@@ -470,7 +456,7 @@
State : parse_udp
shift: 8B
match_reservations: []
-outputs[addr, width]: ([81, 8], [298, 8], [299, 8], [336, 16], [267, 32])
+outputs[addr, width]: ([81, 8], [294, 8], [295, 8], [329, 16], [263, 32])
match_extractions: []
parent state parse_ipv4
@@ -490,7 +476,7 @@
State : parse_pkt_out
shift: 2B
match_reservations: []
-outputs[addr, width]: ([81, 8], [340, 16])
+outputs[addr, width]: ([81, 8], [334, 16])
match_extractions: []
next state parse_ethernet val 0 mask [False]
parent state default_parser
@@ -503,9 +489,9 @@
branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>_start
branch on = None, offset = 168b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>_start
branch promise on = ingress_port, offset = 63b, dst = default_parser
-match_extractions: [match_window(hw_id=2, width=8), match_window(hw_id=0, width=16), match_window(hw_id=3, width=8)]
-match key = [8, 9, 10, 11, 12, 13, 14, 15]
+match_extractions: [match_window(hw_id=0, width=16), match_window(hw_id=2, width=8), match_window(hw_id=3, width=8)]
match key = [None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
+match key = [8, 9, 10, 11, 12, 13, 14, 15]
match key = [0, 1, 2, 3, 4, 5, 6, 7]
next state parse_pkt_in val 0 mask [True, True, True, True, True, True, True, True]
next state default_parser val 0 mask [False]
@@ -515,7 +501,7 @@
State : parse_pkt_in
shift: 2B
match_reservations: []
-outputs[addr, width]: ([81, 8], [340, 16])
+outputs[addr, width]: ([81, 8], [334, 16])
match_extractions: []
next state parse_ethernet val 0 mask [False]
parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>_start
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parser.characterize.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parser.characterize.log
index 8fd7a5a..c48a218 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parser.characterize.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parser.characterize.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: parser.characterize.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/transform.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/transform.log
index 7a7ed25..d50b7f3 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/transform.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/transform.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: transform.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Tue Sep 12 11:15:53 2017 |
+| Created on: Wed Sep 13 00:59:40 2017 |
+---------------------------------------------------------------------+
-------------------------------