Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 2 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
Wilson Ng | d72013d | 2013-09-29 10:21:48 -0700 | [diff] [blame] | 38 | OFP_TCP_PORT = 6653, |
| 39 | OFP_SSL_PORT = 6653, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFPFW_ICMP_TYPE = 0x40, |
| 46 | OFPFW_ICMP_CODE = 0x80, |
| 47 | |
| 48 | OFP_DL_TYPE_ETH2_CUTOFF = 0x600, |
| 49 | OFP_DL_TYPE_NOT_ETH_TYPE = 0x5ff, |
| 50 | |
| 51 | OFP_VLAN_NONE = 0, |
| 52 | |
| 53 | OFPMT_STANDARD_LENGTH = 88, |
| 54 | |
| 55 | OFP_FLOW_PERMANENT = 0, |
| 56 | |
| 57 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 58 | |
| 59 | DESC_STR_LEN = 256, |
| 60 | SERIAL_NUM_LEN = 32, |
| 61 | |
| 62 | OFPQ_ALL = 0xffffffff, |
| 63 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 64 | }; |
| 65 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 66 | enum ofp_port(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 67 | OFPP_MAX = 0xffffff00, |
| 68 | OFPP_IN_PORT = 0xfffffff8, |
| 69 | OFPP_TABLE = 0xfffffff9, |
| 70 | OFPP_NORMAL = 0xfffffffa, |
| 71 | OFPP_FLOOD = 0xfffffffb, |
| 72 | OFPP_ALL = 0xfffffffc, |
| 73 | OFPP_CONTROLLER = 0xfffffffd, |
| 74 | OFPP_LOCAL = 0xfffffffe, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 75 | OFPP_ANY = 0xffffffff, |
| 76 | }; |
| 77 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 78 | enum ofp_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 79 | OFPT_HELLO = 0, |
| 80 | OFPT_ERROR = 1, |
| 81 | OFPT_ECHO_REQUEST = 2, |
| 82 | OFPT_ECHO_REPLY = 3, |
| 83 | OFPT_EXPERIMENTER = 4, |
| 84 | OFPT_FEATURES_REQUEST = 5, |
| 85 | OFPT_FEATURES_REPLY = 6, |
| 86 | OFPT_GET_CONFIG_REQUEST = 7, |
| 87 | OFPT_GET_CONFIG_REPLY = 8, |
| 88 | OFPT_SET_CONFIG = 9, |
| 89 | OFPT_PACKET_IN = 10, |
| 90 | OFPT_FLOW_REMOVED = 11, |
| 91 | OFPT_PORT_STATUS = 12, |
| 92 | OFPT_PACKET_OUT = 13, |
| 93 | OFPT_FLOW_MOD = 14, |
| 94 | OFPT_GROUP_MOD = 15, |
| 95 | OFPT_PORT_MOD = 16, |
| 96 | OFPT_TABLE_MOD = 17, |
| 97 | OFPT_STATS_REQUEST = 18, |
| 98 | OFPT_STATS_REPLY = 19, |
| 99 | OFPT_BARRIER_REQUEST = 20, |
| 100 | OFPT_BARRIER_REPLY = 21, |
| 101 | OFPT_QUEUE_GET_CONFIG_REQUEST = 22, |
| 102 | OFPT_QUEUE_GET_CONFIG_REPLY = 23, |
| 103 | }; |
| 104 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 105 | enum ofp_config_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 106 | OFPC_FRAG_NORMAL = 0, |
| 107 | OFPC_FRAG_DROP = 1, |
| 108 | OFPC_FRAG_REASM = 2, |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 109 | OFPC_FRAG_MASK(virtual=True) = 3, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 110 | OFPC_INVALID_TTL_TO_CONTROLLER = 4, |
| 111 | }; |
| 112 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 113 | enum ofp_table_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 114 | OFPTC_TABLE_MISS_CONTROLLER = 0, |
| 115 | OFPTC_TABLE_MISS_CONTINUE = 1, |
| 116 | OFPTC_TABLE_MISS_DROP = 2, |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 117 | OFPTC_TABLE_MISS_MASK(virtual=True) = 3, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 118 | }; |
| 119 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 120 | enum ofp_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 121 | OFPC_FLOW_STATS = 0x1, |
| 122 | OFPC_TABLE_STATS = 0x2, |
| 123 | OFPC_PORT_STATS = 0x4, |
| 124 | OFPC_GROUP_STATS = 0x8, |
| 125 | OFPC_IP_REASM = 0x20, |
| 126 | OFPC_QUEUE_STATS = 0x40, |
| 127 | OFPC_ARP_MATCH_IP = 0x80, |
| 128 | }; |
| 129 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 130 | enum ofp_port_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 131 | OFPPC_PORT_DOWN = 0x1, |
| 132 | OFPPC_NO_RECV = 0x4, |
| 133 | OFPPC_NO_FWD = 0x20, |
| 134 | OFPPC_NO_PACKET_IN = 0x40, |
Rob Vaterlaus | 0a8ec14 | 2013-10-10 13:27:14 -0700 | [diff] [blame] | 135 | OFPPC_BSN_MIRROR_DEST = 0x80000000, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 136 | }; |
| 137 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 138 | enum ofp_port_state(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 139 | OFPPS_LINK_DOWN = 0x1, |
| 140 | OFPPS_BLOCKED = 0x2, |
| 141 | OFPPS_LIVE = 0x4, |
| 142 | }; |
| 143 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 144 | enum ofp_port_features(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 145 | OFPPF_10MB_HD = 0x1, |
| 146 | OFPPF_10MB_FD = 0x2, |
| 147 | OFPPF_100MB_HD = 0x4, |
| 148 | OFPPF_100MB_FD = 0x8, |
| 149 | OFPPF_1GB_HD = 0x10, |
| 150 | OFPPF_1GB_FD = 0x20, |
| 151 | OFPPF_10GB_FD = 0x40, |
| 152 | OFPPF_40GB_FD = 0x80, |
| 153 | OFPPF_100GB_FD = 0x100, |
| 154 | OFPPF_1TB_FD = 0x200, |
| 155 | OFPPF_OTHER = 0x400, |
| 156 | OFPPF_COPPER = 0x800, |
| 157 | OFPPF_FIBER = 0x1000, |
| 158 | OFPPF_AUTONEG = 0x2000, |
| 159 | OFPPF_PAUSE = 0x4000, |
| 160 | OFPPF_PAUSE_ASYM = 0x8000, |
| 161 | }; |
| 162 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 163 | enum ofp_port_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 164 | OFPPR_ADD = 0, |
| 165 | OFPPR_DELETE = 1, |
| 166 | OFPPR_MODIFY = 2, |
| 167 | }; |
| 168 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 169 | enum ofp_packet_in_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 170 | OFPR_NO_MATCH = 0, |
| 171 | OFPR_ACTION = 1, |
| 172 | }; |
| 173 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 174 | enum ofp_action_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 175 | OFPAT_OUTPUT = 0, |
| 176 | OFPAT_SET_VLAN_VID = 1, |
| 177 | OFPAT_SET_VLAN_PCP = 2, |
| 178 | OFPAT_SET_DL_SRC = 3, |
| 179 | OFPAT_SET_DL_DST = 4, |
| 180 | OFPAT_SET_NW_SRC = 5, |
| 181 | OFPAT_SET_NW_DST = 6, |
| 182 | OFPAT_SET_NW_TOS = 7, |
| 183 | OFPAT_SET_NW_ECN = 8, |
| 184 | OFPAT_SET_TP_SRC = 9, |
| 185 | OFPAT_SET_TP_DST = 10, |
| 186 | OFPAT_COPY_TTL_OUT = 11, |
| 187 | OFPAT_COPY_TTL_IN = 12, |
| 188 | OFPAT_SET_MPLS_LABEL = 13, |
| 189 | OFPAT_SET_MPLS_TC = 14, |
| 190 | OFPAT_SET_MPLS_TTL = 15, |
| 191 | OFPAT_DEC_MPLS_TTL = 16, |
| 192 | OFPAT_PUSH_VLAN = 17, |
| 193 | OFPAT_POP_VLAN = 18, |
| 194 | OFPAT_PUSH_MPLS = 19, |
| 195 | OFPAT_POP_MPLS = 20, |
| 196 | OFPAT_SET_QUEUE = 21, |
| 197 | OFPAT_GROUP = 22, |
| 198 | OFPAT_SET_NW_TTL = 23, |
| 199 | OFPAT_DEC_NW_TTL = 24, |
| 200 | OFPAT_EXPERIMENTER = 0xffff, |
| 201 | }; |
| 202 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 203 | enum ofp_flow_mod_command(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 204 | OFPFC_ADD = 0, |
| 205 | OFPFC_MODIFY = 1, |
| 206 | OFPFC_MODIFY_STRICT = 2, |
| 207 | OFPFC_DELETE = 3, |
| 208 | OFPFC_DELETE_STRICT = 4, |
| 209 | }; |
| 210 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 211 | enum ofp_group_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 212 | OFPGC_ADD = 0, |
| 213 | OFPGC_MODIFY = 1, |
| 214 | OFPGC_DELETE = 2, |
| 215 | }; |
| 216 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 217 | enum ofp_flow_wildcards(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 218 | OFPFW_IN_PORT = 0x1, |
| 219 | OFPFW_DL_VLAN = 0x2, |
| 220 | OFPFW_DL_VLAN_PCP = 0x4, |
| 221 | OFPFW_DL_TYPE = 0x8, |
| 222 | OFPFW_NW_TOS = 0x10, |
| 223 | OFPFW_NW_PROTO = 0x20, |
| 224 | OFPFW_TP_SRC = 0x40, |
| 225 | OFPFW_TP_DST = 0x80, |
| 226 | OFPFW_MPLS_LABEL = 0x100, |
| 227 | OFPFW_MPLS_TC = 0x200, |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 228 | OFPFW_ALL(virtual=True) = 0x3ff, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 229 | }; |
| 230 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 231 | enum ofp_vlan_id(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 232 | OFPVID_ANY = 0xfffe, |
| 233 | OFPVID_NONE = 0xffff, |
| 234 | }; |
| 235 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 236 | enum ofp_match_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 237 | OFPMT_STANDARD = 0, |
| 238 | }; |
| 239 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 240 | enum ofp_instruction_type(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 241 | OFPIT_GOTO_TABLE = 0x1, |
| 242 | OFPIT_WRITE_METADATA = 0x2, |
| 243 | OFPIT_WRITE_ACTIONS = 0x3, |
| 244 | OFPIT_APPLY_ACTIONS = 0x4, |
| 245 | OFPIT_CLEAR_ACTIONS = 0x5, |
| 246 | OFPIT_EXPERIMENTER = 0xffff, |
| 247 | }; |
| 248 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 249 | enum ofp_flow_mod_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 250 | OFPFF_SEND_FLOW_REM = 0x1, |
| 251 | OFPFF_CHECK_OVERLAP = 0x2, |
| 252 | }; |
| 253 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 254 | enum ofp_group(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 255 | OFPG_MAX = 0xffffff00, |
| 256 | OFPG_ALL = 0xfffffffc, |
| 257 | OFPG_ANY = 0xffffffff, |
| 258 | }; |
| 259 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 260 | enum ofp_group_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 261 | OFPGT_ALL = 0, |
| 262 | OFPGT_SELECT = 1, |
| 263 | OFPGT_INDIRECT = 2, |
| 264 | OFPGT_FF = 3, |
| 265 | }; |
| 266 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 267 | enum ofp_flow_removed_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 268 | OFPRR_IDLE_TIMEOUT = 0, |
| 269 | OFPRR_HARD_TIMEOUT = 1, |
| 270 | OFPRR_DELETE = 2, |
| 271 | OFPRR_GROUP_DELETE = 3, |
| 272 | }; |
| 273 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 274 | enum ofp_error_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 275 | OFPET_HELLO_FAILED = 0, |
| 276 | OFPET_BAD_REQUEST = 1, |
| 277 | OFPET_BAD_ACTION = 2, |
| 278 | OFPET_BAD_INSTRUCTION = 3, |
| 279 | OFPET_BAD_MATCH = 4, |
| 280 | OFPET_FLOW_MOD_FAILED = 5, |
| 281 | OFPET_GROUP_MOD_FAILED = 6, |
| 282 | OFPET_PORT_MOD_FAILED = 7, |
| 283 | OFPET_TABLE_MOD_FAILED = 8, |
| 284 | OFPET_QUEUE_OP_FAILED = 9, |
| 285 | OFPET_SWITCH_CONFIG_FAILED = 10, |
| 286 | }; |
| 287 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 288 | enum ofp_hello_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 289 | OFPHFC_INCOMPATIBLE = 0, |
| 290 | OFPHFC_EPERM = 1, |
| 291 | }; |
| 292 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 293 | enum ofp_bad_request_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 294 | OFPBRC_BAD_VERSION = 0, |
| 295 | OFPBRC_BAD_TYPE = 1, |
| 296 | OFPBRC_BAD_STAT = 2, |
| 297 | OFPBRC_BAD_EXPERIMENTER = 3, |
| 298 | OFPBRC_BAD_SUBTYPE = 4, |
| 299 | OFPBRC_EPERM = 5, |
| 300 | OFPBRC_BAD_LEN = 6, |
| 301 | OFPBRC_BUFFER_EMPTY = 7, |
| 302 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 303 | OFPBRC_BAD_TABLE_ID = 9, |
| 304 | }; |
| 305 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 306 | enum ofp_bad_action_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 307 | OFPBAC_BAD_TYPE = 0, |
| 308 | OFPBAC_BAD_LEN = 1, |
| 309 | OFPBAC_BAD_EXPERIMENTER = 2, |
| 310 | OFPBAC_BAD_EXPERIMENTER_TYPE = 3, |
| 311 | OFPBAC_BAD_OUT_PORT = 4, |
| 312 | OFPBAC_BAD_ARGUMENT = 5, |
| 313 | OFPBAC_EPERM = 6, |
| 314 | OFPBAC_TOO_MANY = 7, |
| 315 | OFPBAC_BAD_QUEUE = 8, |
| 316 | OFPBAC_BAD_OUT_GROUP = 9, |
| 317 | OFPBAC_MATCH_INCONSISTENT = 10, |
| 318 | OFPBAC_UNSUPPORTED_ORDER = 11, |
| 319 | OFPBAC_BAD_TAG = 12, |
| 320 | }; |
| 321 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 322 | enum ofp_bad_instruction_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 323 | OFPBIC_UNKNOWN_INST = 0, |
| 324 | OFPBIC_UNSUP_INST = 1, |
| 325 | OFPBIC_BAD_TABLE_ID = 2, |
| 326 | OFPBIC_UNSUP_METADATA = 3, |
| 327 | OFPBIC_UNSUP_METADATA_MASK = 4, |
| 328 | OFPBIC_UNSUP_EXP_INST = 5, |
| 329 | }; |
| 330 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 331 | enum ofp_bad_match_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 332 | OFPBMC_BAD_TYPE = 0, |
| 333 | OFPBMC_BAD_LEN = 1, |
| 334 | OFPBMC_BAD_TAG = 2, |
| 335 | OFPBMC_BAD_DL_ADDR_MASK = 3, |
| 336 | OFPBMC_BAD_NW_ADDR_MASK = 4, |
| 337 | OFPBMC_BAD_WILDCARDS = 5, |
| 338 | OFPBMC_BAD_FIELD = 6, |
| 339 | OFPBMC_BAD_VALUE = 7, |
| 340 | }; |
| 341 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 342 | enum ofp_flow_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 343 | OFPFMFC_UNKNOWN = 0, |
| 344 | OFPFMFC_TABLE_FULL = 1, |
| 345 | OFPFMFC_BAD_TABLE_ID = 2, |
| 346 | OFPFMFC_OVERLAP = 3, |
| 347 | OFPFMFC_EPERM = 4, |
| 348 | OFPFMFC_BAD_TIMEOUT = 5, |
| 349 | OFPFMFC_BAD_COMMAND = 6, |
| 350 | }; |
| 351 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 352 | enum ofp_group_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 353 | OFPGMFC_GROUP_EXISTS = 0, |
| 354 | OFPGMFC_INVALID_GROUP = 1, |
| 355 | OFPGMFC_WEIGHT_UNSUPPORTED = 2, |
| 356 | OFPGMFC_OUT_OF_GROUPS = 3, |
| 357 | OFPGMFC_OUT_OF_BUCKETS = 4, |
| 358 | OFPGMFC_CHAINING_UNSUPPORTED = 5, |
| 359 | OFPGMFC_WATCH_UNSUPPORTED = 6, |
| 360 | OFPGMFC_LOOP = 7, |
| 361 | OFPGMFC_UNKNOWN_GROUP = 8, |
| 362 | }; |
| 363 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 364 | enum ofp_port_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 365 | OFPPMFC_BAD_PORT = 0, |
| 366 | OFPPMFC_BAD_HW_ADDR = 1, |
| 367 | OFPPMFC_BAD_CONFIG = 2, |
| 368 | OFPPMFC_BAD_ADVERTISE = 3, |
| 369 | }; |
| 370 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 371 | enum ofp_table_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 372 | OFPTMFC_BAD_TABLE = 0, |
| 373 | OFPTMFC_BAD_CONFIG = 1, |
| 374 | }; |
| 375 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 376 | enum ofp_queue_op_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 377 | OFPQOFC_BAD_PORT = 0, |
| 378 | OFPQOFC_BAD_QUEUE = 1, |
| 379 | OFPQOFC_EPERM = 2, |
| 380 | }; |
| 381 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 382 | enum ofp_switch_config_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 383 | OFPSCFC_BAD_FLAGS = 0, |
| 384 | OFPSCFC_BAD_LEN = 1, |
| 385 | }; |
| 386 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 387 | enum ofp_stats_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 388 | OFPST_DESC = 0, |
| 389 | OFPST_FLOW = 1, |
| 390 | OFPST_AGGREGATE = 2, |
| 391 | OFPST_TABLE = 3, |
| 392 | OFPST_PORT = 4, |
| 393 | OFPST_QUEUE = 5, |
| 394 | OFPST_GROUP = 6, |
| 395 | OFPST_GROUP_DESC = 7, |
| 396 | OFPST_EXPERIMENTER = 0xffff, |
| 397 | }; |
| 398 | |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 399 | // none defined |
| 400 | enum ofp_stats_request_flags(wire_type=uint16_t, bitmask=True) { |
| 401 | }; |
| 402 | |
| 403 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 404 | enum ofp_stats_reply_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 405 | OFPSF_REPLY_MORE = 0x1, |
| 406 | }; |
| 407 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 408 | enum ofp_queue_properties(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 409 | OFPQT_NONE = 0, |
| 410 | OFPQT_MIN_RATE = 1, |
| 411 | }; |
| 412 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 413 | /* XXX rename to of_message */ |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 414 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 415 | uint8_t version; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 416 | uint8_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 417 | uint16_t length; |
| 418 | uint32_t xid; |
| 419 | }; |
| 420 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 421 | struct of_hello : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 422 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 423 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 424 | uint16_t length; |
| 425 | uint32_t xid; |
| 426 | }; |
| 427 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 428 | struct of_echo_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 429 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 430 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 431 | uint16_t length; |
| 432 | uint32_t xid; |
| 433 | of_octets_t data; |
| 434 | }; |
| 435 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 436 | struct of_echo_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 437 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 438 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 439 | uint16_t length; |
| 440 | uint32_t xid; |
| 441 | of_octets_t data; |
| 442 | }; |
| 443 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 444 | struct of_experimenter : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 445 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 446 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 447 | uint16_t length; |
| 448 | uint32_t xid; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 449 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 450 | uint32_t subtype; |
| 451 | of_octets_t data; |
| 452 | }; |
| 453 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 454 | struct of_barrier_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 455 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 456 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 457 | uint16_t length; |
| 458 | uint32_t xid; |
| 459 | }; |
| 460 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 461 | struct of_barrier_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 462 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 463 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 464 | uint16_t length; |
| 465 | uint32_t xid; |
| 466 | }; |
| 467 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 468 | struct of_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 469 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 470 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 471 | uint16_t length; |
| 472 | uint32_t xid; |
| 473 | }; |
| 474 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 475 | struct of_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 476 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 477 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 478 | uint16_t length; |
| 479 | uint32_t xid; |
Andreas Wundsam | 057540b | 2013-11-19 16:51:36 -0800 | [diff] [blame] | 480 | enum ofp_config_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 481 | uint16_t miss_send_len; |
| 482 | }; |
| 483 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 484 | struct of_set_config : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 485 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 486 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 487 | uint16_t length; |
| 488 | uint32_t xid; |
Andreas Wundsam | 057540b | 2013-11-19 16:51:36 -0800 | [diff] [blame] | 489 | enum ofp_config_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 490 | uint16_t miss_send_len; |
| 491 | }; |
| 492 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 493 | struct of_table_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 494 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 495 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 496 | uint16_t length; |
| 497 | uint32_t xid; |
| 498 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 499 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 500 | uint32_t config; |
| 501 | }; |
| 502 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 503 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 504 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 505 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 506 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 507 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 508 | of_port_name_t name; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 509 | enum ofp_port_config config; |
| 510 | enum ofp_port_state state; |
| 511 | enum ofp_port_features curr; |
| 512 | enum ofp_port_features advertised; |
| 513 | enum ofp_port_features supported; |
| 514 | enum ofp_port_features peer; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 515 | uint32_t curr_speed; |
| 516 | uint32_t max_speed; |
| 517 | }; |
| 518 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 519 | struct of_features_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 520 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 521 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 522 | uint16_t length; |
| 523 | uint32_t xid; |
| 524 | }; |
| 525 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 526 | struct of_features_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 527 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 528 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 529 | uint16_t length; |
| 530 | uint32_t xid; |
| 531 | uint64_t datapath_id; |
| 532 | uint32_t n_buffers; |
| 533 | uint8_t n_tables; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 534 | pad(3); |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 535 | enum ofp_capabilities capabilities; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 536 | uint32_t reserved; |
| 537 | list(of_port_desc_t) ports; |
| 538 | }; |
| 539 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 540 | struct of_port_status : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 541 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 542 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 543 | uint16_t length; |
| 544 | uint32_t xid; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 545 | enum ofp_port_reason reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 546 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 547 | of_port_desc_t desc; |
| 548 | }; |
| 549 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 550 | struct of_port_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 551 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 552 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 553 | uint16_t length; |
| 554 | uint32_t xid; |
| 555 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 556 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 557 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 558 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 559 | uint32_t config; |
| 560 | uint32_t mask; |
| 561 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 562 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 563 | }; |
| 564 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 565 | struct of_packet_in : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 566 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 567 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 568 | uint16_t length; |
| 569 | uint32_t xid; |
| 570 | uint32_t buffer_id; |
| 571 | of_port_no_t in_port; |
| 572 | of_port_no_t in_phy_port; |
| 573 | uint16_t total_len; |
| 574 | uint8_t reason; |
| 575 | uint8_t table_id; |
| 576 | of_octets_t data; |
| 577 | }; |
| 578 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 579 | struct of_action_output : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 580 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 581 | uint16_t len; |
| 582 | of_port_no_t port; |
| 583 | uint16_t max_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 584 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 585 | }; |
| 586 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 587 | struct of_action_set_vlan_vid : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 588 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 589 | uint16_t len; |
| 590 | uint16_t vlan_vid; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 591 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 592 | }; |
| 593 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 594 | struct of_action_set_vlan_pcp : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 595 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 596 | uint16_t len; |
| 597 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 598 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 599 | }; |
| 600 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 601 | struct of_action_set_dl_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 602 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 603 | uint16_t len; |
| 604 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 605 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 606 | }; |
| 607 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 608 | struct of_action_set_dl_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 609 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 610 | uint16_t len; |
| 611 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 612 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 613 | }; |
| 614 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 615 | struct of_action_set_nw_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 616 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 617 | uint16_t len; |
| 618 | uint32_t nw_addr; |
| 619 | }; |
| 620 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 621 | struct of_action_set_nw_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 622 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 623 | uint16_t len; |
| 624 | uint32_t nw_addr; |
| 625 | }; |
| 626 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 627 | struct of_action_set_nw_tos : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 628 | uint16_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 629 | uint16_t len; |
| 630 | uint8_t nw_tos; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 631 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 632 | }; |
| 633 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 634 | struct of_action_set_nw_ecn : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 635 | uint16_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 636 | uint16_t len; |
| 637 | uint8_t nw_ecn; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 638 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 639 | }; |
| 640 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 641 | struct of_action_set_tp_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 642 | uint16_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 643 | uint16_t len; |
| 644 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 645 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 646 | }; |
| 647 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 648 | struct of_action_set_tp_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 649 | uint16_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 650 | uint16_t len; |
| 651 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 652 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 653 | }; |
| 654 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 655 | struct of_action_copy_ttl_out : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 656 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 657 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 658 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 659 | }; |
| 660 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 661 | struct of_action_copy_ttl_in : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 662 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 663 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 664 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 665 | }; |
| 666 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 667 | struct of_action_set_mpls_label : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 668 | uint16_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 669 | uint16_t len; |
| 670 | uint32_t mpls_label; |
| 671 | }; |
| 672 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 673 | struct of_action_set_mpls_tc : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 674 | uint16_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 675 | uint16_t len; |
| 676 | uint8_t mpls_tc; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 677 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 678 | }; |
| 679 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 680 | struct of_action_set_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 681 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 682 | uint16_t len; |
| 683 | uint8_t mpls_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 684 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 685 | }; |
| 686 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 687 | struct of_action_dec_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 688 | uint16_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 689 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 690 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 691 | }; |
| 692 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 693 | struct of_action_push_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 694 | uint16_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 695 | uint16_t len; |
| 696 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 697 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 698 | }; |
| 699 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 700 | struct of_action_pop_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 701 | uint16_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 702 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 703 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 704 | }; |
| 705 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 706 | struct of_action_push_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 707 | uint16_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 708 | uint16_t len; |
| 709 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 710 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 711 | }; |
| 712 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 713 | struct of_action_pop_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 714 | uint16_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 715 | uint16_t len; |
| 716 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 717 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 718 | }; |
| 719 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 720 | struct of_action_set_queue : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 721 | uint16_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 722 | uint16_t len; |
| 723 | uint32_t queue_id; |
| 724 | }; |
| 725 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 726 | struct of_action_group : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 727 | uint16_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 728 | uint16_t len; |
| 729 | uint32_t group_id; |
| 730 | }; |
| 731 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 732 | struct of_action_set_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 733 | uint16_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 734 | uint16_t len; |
| 735 | uint8_t nw_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 736 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 737 | }; |
| 738 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 739 | struct of_action_dec_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 740 | uint16_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 741 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 742 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 743 | }; |
| 744 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 745 | struct of_action_experimenter : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 746 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 747 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 748 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 749 | of_octets_t data; |
| 750 | }; |
| 751 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 752 | struct of_action { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 753 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 754 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 755 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 756 | }; |
| 757 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 758 | struct of_packet_out : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 759 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 760 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 761 | uint16_t length; |
| 762 | uint32_t xid; |
| 763 | uint32_t buffer_id; |
| 764 | of_port_no_t in_port; |
| 765 | uint16_t actions_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 766 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 767 | list(of_action_t) actions; |
| 768 | of_octets_t data; |
| 769 | }; |
| 770 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 771 | struct of_match_v2 { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 772 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 773 | uint16_t length; |
| 774 | of_port_no_t in_port; |
| 775 | of_wc_bmap_t wildcards; |
| 776 | of_mac_addr_t eth_src; |
| 777 | of_mac_addr_t eth_src_mask; |
| 778 | of_mac_addr_t eth_dst; |
| 779 | of_mac_addr_t eth_dst_mask; |
| 780 | uint16_t vlan_vid; |
| 781 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 782 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 783 | uint16_t eth_type; |
| 784 | uint8_t ip_dscp; |
| 785 | uint8_t ip_proto; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 786 | of_ipv4_t ipv4_src; |
| 787 | of_ipv4_t ipv4_src_mask; |
| 788 | of_ipv4_t ipv4_dst; |
| 789 | of_ipv4_t ipv4_dst_mask; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 790 | uint16_t tcp_src; |
| 791 | uint16_t tcp_dst; |
| 792 | uint32_t mpls_label; |
| 793 | uint8_t mpls_tc; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 794 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 795 | uint64_t metadata; |
| 796 | uint64_t metadata_mask; |
| 797 | }; |
| 798 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 799 | struct of_instruction { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 800 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 801 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 802 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 803 | }; |
| 804 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 805 | struct of_instruction_goto_table : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 806 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 807 | uint16_t len; |
| 808 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 809 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 810 | }; |
| 811 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 812 | struct of_instruction_write_metadata : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 813 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 814 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 815 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 816 | uint64_t metadata; |
| 817 | uint64_t metadata_mask; |
| 818 | }; |
| 819 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 820 | struct of_instruction_write_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 821 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 822 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 823 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 824 | list(of_action_t) actions; |
| 825 | }; |
| 826 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 827 | struct of_instruction_apply_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 828 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 829 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 830 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 831 | list(of_action_t) actions; |
| 832 | }; |
| 833 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 834 | struct of_instruction_clear_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 835 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 836 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 837 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 838 | }; |
| 839 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 840 | struct of_instruction_experimenter : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 841 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 842 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 843 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 844 | of_octets_t data; |
| 845 | }; |
| 846 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 847 | struct of_flow_mod : of_header { |
| 848 | uint8_t version; |
| 849 | uint8_t type == 14; |
| 850 | uint16_t length; |
| 851 | uint32_t xid; |
| 852 | uint64_t cookie; |
| 853 | uint64_t cookie_mask; |
| 854 | uint8_t table_id; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 855 | of_fm_cmd_t _command == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 856 | uint16_t idle_timeout; |
| 857 | uint16_t hard_timeout; |
| 858 | uint16_t priority; |
| 859 | uint32_t buffer_id; |
| 860 | of_port_no_t out_port; |
| 861 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 862 | enum ofp_flow_mod_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 863 | pad(2); |
| 864 | of_match_t match; |
| 865 | list(of_instruction_t) instructions; |
| 866 | }; |
| 867 | |
| 868 | struct of_flow_add : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 869 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 870 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 871 | uint16_t length; |
| 872 | uint32_t xid; |
| 873 | uint64_t cookie; |
| 874 | uint64_t cookie_mask; |
| 875 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 876 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 877 | uint16_t idle_timeout; |
| 878 | uint16_t hard_timeout; |
| 879 | uint16_t priority; |
| 880 | uint32_t buffer_id; |
| 881 | of_port_no_t out_port; |
| 882 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 883 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 884 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 885 | of_match_t match; |
| 886 | list(of_instruction_t) instructions; |
| 887 | }; |
| 888 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 889 | struct of_flow_modify : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 890 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 891 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 892 | uint16_t length; |
| 893 | uint32_t xid; |
| 894 | uint64_t cookie; |
| 895 | uint64_t cookie_mask; |
| 896 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 897 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 898 | uint16_t idle_timeout; |
| 899 | uint16_t hard_timeout; |
| 900 | uint16_t priority; |
| 901 | uint32_t buffer_id; |
| 902 | of_port_no_t out_port; |
| 903 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 904 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 905 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 906 | of_match_t match; |
| 907 | list(of_instruction_t) instructions; |
| 908 | }; |
| 909 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 910 | struct of_flow_modify_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 911 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 912 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 913 | uint16_t length; |
| 914 | uint32_t xid; |
| 915 | uint64_t cookie; |
| 916 | uint64_t cookie_mask; |
| 917 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 918 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 919 | uint16_t idle_timeout; |
| 920 | uint16_t hard_timeout; |
| 921 | uint16_t priority; |
| 922 | uint32_t buffer_id; |
| 923 | of_port_no_t out_port; |
| 924 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 925 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 926 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 927 | of_match_t match; |
| 928 | list(of_instruction_t) instructions; |
| 929 | }; |
| 930 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 931 | struct of_flow_delete : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 932 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 933 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 934 | uint16_t length; |
| 935 | uint32_t xid; |
| 936 | uint64_t cookie; |
| 937 | uint64_t cookie_mask; |
| 938 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 939 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 940 | uint16_t idle_timeout; |
| 941 | uint16_t hard_timeout; |
| 942 | uint16_t priority; |
| 943 | uint32_t buffer_id; |
| 944 | of_port_no_t out_port; |
| 945 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 946 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 947 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 948 | of_match_t match; |
| 949 | list(of_instruction_t) instructions; |
| 950 | }; |
| 951 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 952 | struct of_flow_delete_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 953 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 954 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 955 | uint16_t length; |
| 956 | uint32_t xid; |
| 957 | uint64_t cookie; |
| 958 | uint64_t cookie_mask; |
| 959 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 960 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 961 | uint16_t idle_timeout; |
| 962 | uint16_t hard_timeout; |
| 963 | uint16_t priority; |
| 964 | uint32_t buffer_id; |
| 965 | of_port_no_t out_port; |
| 966 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 967 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 968 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 969 | of_match_t match; |
| 970 | list(of_instruction_t) instructions; |
| 971 | }; |
| 972 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 973 | struct of_bucket { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 974 | uint16_t len; |
| 975 | uint16_t weight; |
| 976 | of_port_no_t watch_port; |
| 977 | uint32_t watch_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 978 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 979 | list(of_action_t) actions; |
| 980 | }; |
| 981 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 982 | struct of_group_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 983 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 984 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 985 | uint16_t length; |
| 986 | uint32_t xid; |
Andreas Wundsam | 5812cf3 | 2013-11-15 13:51:24 -0800 | [diff] [blame] | 987 | enum ofp_group_mod_command command == ?; |
| 988 | enum ofp_group_type group_type; |
| 989 | pad(1); |
| 990 | uint32_t group_id; |
| 991 | list(of_bucket_t) buckets; |
| 992 | }; |
| 993 | |
| 994 | struct of_group_add : of_group_mod { |
| 995 | uint8_t version; |
| 996 | uint8_t type == 15; |
| 997 | uint16_t length; |
| 998 | uint32_t xid; |
| 999 | enum ofp_group_mod_command command == 0; |
| 1000 | enum ofp_group_type group_type; |
| 1001 | pad(1); |
| 1002 | uint32_t group_id; |
| 1003 | list(of_bucket_t) buckets; |
| 1004 | }; |
| 1005 | |
| 1006 | struct of_group_modify : of_group_mod { |
| 1007 | uint8_t version; |
| 1008 | uint8_t type == 15; |
| 1009 | uint16_t length; |
| 1010 | uint32_t xid; |
| 1011 | enum ofp_group_mod_command command == 1; |
| 1012 | enum ofp_group_type group_type; |
| 1013 | pad(1); |
| 1014 | uint32_t group_id; |
| 1015 | list(of_bucket_t) buckets; |
| 1016 | }; |
| 1017 | |
| 1018 | struct of_group_delete : of_group_mod { |
| 1019 | uint8_t version; |
| 1020 | uint8_t type == 15; |
| 1021 | uint16_t length; |
| 1022 | uint32_t xid; |
| 1023 | enum ofp_group_mod_command command == 2; |
| 1024 | enum ofp_group_type group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1025 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1026 | uint32_t group_id; |
| 1027 | list(of_bucket_t) buckets; |
| 1028 | }; |
| 1029 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1030 | struct of_flow_removed : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1031 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1032 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1033 | uint16_t length; |
| 1034 | uint32_t xid; |
| 1035 | uint64_t cookie; |
| 1036 | uint16_t priority; |
| 1037 | uint8_t reason; |
| 1038 | uint8_t table_id; |
| 1039 | uint32_t duration_sec; |
| 1040 | uint32_t duration_nsec; |
| 1041 | uint16_t idle_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1042 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1043 | uint64_t packet_count; |
| 1044 | uint64_t byte_count; |
| 1045 | of_match_t match; |
| 1046 | }; |
| 1047 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1048 | struct of_error_msg : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1049 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1050 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1051 | uint16_t length; |
| 1052 | uint32_t xid; |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 1053 | uint16_t err_type == ?; |
| 1054 | }; |
| 1055 | |
| 1056 | struct of_hello_failed_error_msg : of_error_msg { |
| 1057 | uint8_t version; |
| 1058 | uint8_t type == 1; |
| 1059 | uint16_t length; |
| 1060 | uint32_t xid; |
| 1061 | uint16_t err_type == 0; |
| 1062 | enum ofp_hello_failed_code code; |
| 1063 | of_octets_t data; |
| 1064 | }; |
| 1065 | |
| 1066 | struct of_bad_request_error_msg : of_error_msg { |
| 1067 | uint8_t version; |
| 1068 | uint8_t type == 1; |
| 1069 | uint16_t length; |
| 1070 | uint32_t xid; |
| 1071 | uint16_t err_type == 1; |
| 1072 | enum ofp_bad_request_code code; |
| 1073 | of_octets_t data; |
| 1074 | }; |
| 1075 | |
| 1076 | struct of_bad_action_error_msg : of_error_msg { |
| 1077 | uint8_t version; |
| 1078 | uint8_t type == 1; |
| 1079 | uint16_t length; |
| 1080 | uint32_t xid; |
| 1081 | uint16_t err_type == 2; |
| 1082 | enum ofp_bad_action_code code; |
| 1083 | of_octets_t data; |
| 1084 | }; |
| 1085 | |
| 1086 | struct of_bad_instruction_error_msg : of_error_msg { |
| 1087 | uint8_t version; |
| 1088 | uint8_t type == 1; |
| 1089 | uint16_t length; |
| 1090 | uint32_t xid; |
| 1091 | uint16_t err_type == 3; |
| 1092 | enum ofp_bad_instruction_code code; |
| 1093 | of_octets_t data; |
| 1094 | }; |
| 1095 | |
| 1096 | struct of_bad_match_error_msg : of_error_msg { |
| 1097 | uint8_t version; |
| 1098 | uint8_t type == 1; |
| 1099 | uint16_t length; |
| 1100 | uint32_t xid; |
| 1101 | uint16_t err_type == 4; |
| 1102 | enum ofp_bad_match_code code; |
| 1103 | of_octets_t data; |
| 1104 | }; |
| 1105 | |
| 1106 | struct of_flow_mod_failed_error_msg : of_error_msg { |
| 1107 | uint8_t version; |
| 1108 | uint8_t type == 1; |
| 1109 | uint16_t length; |
| 1110 | uint32_t xid; |
| 1111 | uint16_t err_type == 5; |
| 1112 | enum ofp_flow_mod_failed_code code; |
| 1113 | of_octets_t data; |
| 1114 | }; |
| 1115 | |
| 1116 | struct of_group_mod_failed_error_msg : of_error_msg { |
| 1117 | uint8_t version; |
| 1118 | uint8_t type == 1; |
| 1119 | uint16_t length; |
| 1120 | uint32_t xid; |
| 1121 | uint16_t err_type == 6; |
| 1122 | enum ofp_group_mod_failed_code code; |
| 1123 | of_octets_t data; |
| 1124 | }; |
| 1125 | |
| 1126 | struct of_port_mod_failed_error_msg : of_error_msg { |
| 1127 | uint8_t version; |
| 1128 | uint8_t type == 1; |
| 1129 | uint16_t length; |
| 1130 | uint32_t xid; |
| 1131 | uint16_t err_type == 7; |
| 1132 | enum ofp_port_mod_failed_code code; |
| 1133 | of_octets_t data; |
| 1134 | }; |
| 1135 | |
| 1136 | struct of_table_mod_failed_error_msg : of_error_msg { |
| 1137 | uint8_t version; |
| 1138 | uint8_t type == 1; |
| 1139 | uint16_t length; |
| 1140 | uint32_t xid; |
| 1141 | uint16_t err_type == 8; |
| 1142 | enum ofp_table_mod_failed_code code; |
| 1143 | of_octets_t data; |
| 1144 | }; |
| 1145 | |
| 1146 | struct of_queue_op_failed_error_msg : of_error_msg { |
| 1147 | uint8_t version; |
| 1148 | uint8_t type == 1; |
| 1149 | uint16_t length; |
| 1150 | uint32_t xid; |
| 1151 | uint16_t err_type == 9; |
| 1152 | enum ofp_queue_op_failed_code code; |
| 1153 | of_octets_t data; |
| 1154 | }; |
| 1155 | |
| 1156 | struct of_switch_config_failed_error_msg : of_error_msg { |
| 1157 | uint8_t version; |
| 1158 | uint8_t type == 1; |
| 1159 | uint16_t length; |
| 1160 | uint32_t xid; |
| 1161 | uint16_t err_type == 10; |
| 1162 | enum ofp_switch_config_failed_code code; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1163 | of_octets_t data; |
| 1164 | }; |
| 1165 | |
| 1166 | // STATS ENTRIES: flow, table, port, group, group_desc |
| 1167 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1168 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1169 | uint16_t length; |
| 1170 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1171 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1172 | uint32_t duration_sec; |
| 1173 | uint32_t duration_nsec; |
| 1174 | uint16_t priority; |
| 1175 | uint16_t idle_timeout; |
| 1176 | uint16_t hard_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1177 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1178 | uint64_t cookie; |
| 1179 | uint64_t packet_count; |
| 1180 | uint64_t byte_count; |
| 1181 | of_match_t match; |
| 1182 | list(of_instruction_t) instructions; |
| 1183 | }; |
| 1184 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1185 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1186 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1187 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1188 | of_table_name_t name; |
| 1189 | of_wc_bmap_t wildcards; |
| 1190 | of_match_bmap_t match; |
| 1191 | uint32_t instructions; |
| 1192 | uint32_t write_actions; |
| 1193 | uint32_t apply_actions; |
| 1194 | uint32_t config; |
| 1195 | uint32_t max_entries; |
| 1196 | uint32_t active_count; |
| 1197 | uint64_t lookup_count; |
| 1198 | uint64_t matched_count; |
| 1199 | }; |
| 1200 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1201 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1202 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1203 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1204 | uint64_t rx_packets; |
| 1205 | uint64_t tx_packets; |
| 1206 | uint64_t rx_bytes; |
| 1207 | uint64_t tx_bytes; |
| 1208 | uint64_t rx_dropped; |
| 1209 | uint64_t tx_dropped; |
| 1210 | uint64_t rx_errors; |
| 1211 | uint64_t tx_errors; |
| 1212 | uint64_t rx_frame_err; |
| 1213 | uint64_t rx_over_err; |
| 1214 | uint64_t rx_crc_err; |
| 1215 | uint64_t collisions; |
| 1216 | }; |
| 1217 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1218 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1219 | of_port_no_t port_no; |
| 1220 | uint32_t queue_id; |
| 1221 | uint64_t tx_bytes; |
| 1222 | uint64_t tx_packets; |
| 1223 | uint64_t tx_errors; |
| 1224 | }; |
| 1225 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1226 | struct of_bucket_counter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1227 | uint64_t packet_count; |
| 1228 | uint64_t byte_count; |
| 1229 | }; |
| 1230 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1231 | struct of_group_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1232 | uint16_t length; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1233 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1234 | uint32_t group_id; |
| 1235 | uint32_t ref_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1236 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1237 | uint64_t packet_count; |
| 1238 | uint64_t byte_count; |
| 1239 | list(of_bucket_counter_t) bucket_stats; |
| 1240 | }; |
| 1241 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1242 | struct of_group_desc_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1243 | uint16_t length; |
Andreas Wundsam | 84603f0 | 2013-11-18 18:45:30 -0800 | [diff] [blame] | 1244 | enum ofp_group_type group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1245 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1246 | uint32_t group_id; |
| 1247 | list(of_bucket_t) buckets; |
| 1248 | }; |
| 1249 | |
| 1250 | // STATS: Desc, flow, agg, table, port, queue, group, group_desc, experi |
| 1251 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1252 | struct of_stats_request : of_header { |
| 1253 | uint8_t version; |
| 1254 | uint8_t type == 18; |
| 1255 | uint16_t length; |
| 1256 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1257 | uint16_t stats_type == ?; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1258 | enum ofp_stats_request_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1259 | pad(4); |
| 1260 | }; |
| 1261 | |
| 1262 | struct of_stats_reply : of_header { |
| 1263 | uint8_t version; |
| 1264 | uint8_t type == 19; |
| 1265 | uint16_t length; |
| 1266 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1267 | uint16_t stats_type == ?; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1268 | enum ofp_stats_reply_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1269 | pad(4); |
| 1270 | }; |
| 1271 | |
| 1272 | struct of_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1273 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1274 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1275 | uint16_t length; |
| 1276 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1277 | uint16_t stats_type == 0; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1278 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1279 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1280 | }; |
| 1281 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1282 | struct of_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1283 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1284 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1285 | uint16_t length; |
| 1286 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1287 | uint16_t stats_type == 0; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1288 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1289 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1290 | of_desc_str_t mfr_desc; |
| 1291 | of_desc_str_t hw_desc; |
| 1292 | of_desc_str_t sw_desc; |
| 1293 | of_serial_num_t serial_num; |
| 1294 | of_desc_str_t dp_desc; |
| 1295 | }; |
| 1296 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1297 | struct of_flow_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1298 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1299 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1300 | uint16_t length; |
| 1301 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1302 | uint16_t stats_type == 1; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1303 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1304 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1305 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1306 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1307 | of_port_no_t out_port; |
| 1308 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1309 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1310 | uint64_t cookie; |
| 1311 | uint64_t cookie_mask; |
| 1312 | of_match_t match; |
| 1313 | }; |
| 1314 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1315 | struct of_flow_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1316 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1317 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1318 | uint16_t length; |
| 1319 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1320 | uint16_t stats_type == 1; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1321 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1322 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1323 | list(of_flow_stats_entry_t) entries; |
| 1324 | }; |
| 1325 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1326 | struct of_aggregate_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1327 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1328 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1329 | uint16_t length; |
| 1330 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1331 | uint16_t stats_type == 2; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1332 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1333 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1334 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1335 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1336 | of_port_no_t out_port; |
| 1337 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1338 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1339 | uint64_t cookie; |
| 1340 | uint64_t cookie_mask; |
| 1341 | of_match_t match; |
| 1342 | }; |
| 1343 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1344 | struct of_aggregate_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1345 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1346 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1347 | uint16_t length; |
| 1348 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1349 | uint16_t stats_type == 2; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1350 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1351 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1352 | uint64_t packet_count; |
| 1353 | uint64_t byte_count; |
| 1354 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1355 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1356 | }; |
| 1357 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1358 | struct of_table_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1359 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1360 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1361 | uint16_t length; |
| 1362 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1363 | uint16_t stats_type == 3; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1364 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1365 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1366 | }; |
| 1367 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1368 | struct of_table_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1369 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1370 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1371 | uint16_t length; |
| 1372 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1373 | uint16_t stats_type == 3; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1374 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1375 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1376 | list(of_table_stats_entry_t) entries; |
| 1377 | }; |
| 1378 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1379 | struct of_port_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1380 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1381 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1382 | uint16_t length; |
| 1383 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1384 | uint16_t stats_type == 4; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1385 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1386 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1387 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1388 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1389 | }; |
| 1390 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1391 | struct of_port_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1392 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1393 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1394 | uint16_t length; |
| 1395 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1396 | uint16_t stats_type == 4; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1397 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1398 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1399 | list(of_port_stats_entry_t) entries; |
| 1400 | }; |
| 1401 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1402 | struct of_queue_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1403 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1404 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1405 | uint16_t length; |
| 1406 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1407 | uint16_t stats_type == 5; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1408 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1409 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1410 | of_port_no_t port_no; |
| 1411 | uint32_t queue_id; |
| 1412 | }; |
| 1413 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1414 | struct of_queue_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1415 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1416 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1417 | uint16_t length; |
| 1418 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1419 | uint16_t stats_type == 5; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1420 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1421 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1422 | list(of_queue_stats_entry_t) entries; |
| 1423 | }; |
| 1424 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1425 | struct of_group_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1426 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1427 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1428 | uint16_t length; |
| 1429 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1430 | uint16_t stats_type == 6; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1431 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1432 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1433 | uint32_t group_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1434 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1435 | }; |
| 1436 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1437 | struct of_group_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1438 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1439 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1440 | uint16_t length; |
| 1441 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1442 | uint16_t stats_type == 6; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1443 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1444 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1445 | list(of_group_stats_entry_t) entries; |
| 1446 | }; |
| 1447 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1448 | struct of_group_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1449 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1450 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1451 | uint16_t length; |
| 1452 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1453 | uint16_t stats_type == 7; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1454 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1455 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1456 | }; |
| 1457 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1458 | struct of_group_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1459 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1460 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1461 | uint16_t length; |
| 1462 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1463 | uint16_t stats_type == 7; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1464 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1465 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1466 | list(of_group_desc_stats_entry_t) entries; |
| 1467 | }; |
| 1468 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1469 | struct of_experimenter_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1470 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1471 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1472 | uint16_t length; |
| 1473 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1474 | uint16_t stats_type == 0xffff; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1475 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1476 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1477 | uint32_t experimenter == ?; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1478 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1479 | of_octets_t data; |
| 1480 | }; |
| 1481 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1482 | struct of_experimenter_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1483 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1484 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1485 | uint16_t length; |
| 1486 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1487 | uint16_t stats_type == 0xffff; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1488 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1489 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1490 | uint32_t experimenter == ?; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1491 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1492 | of_octets_t data; |
| 1493 | }; |
| 1494 | |
| 1495 | // END OF STATS OBJECTS |
| 1496 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1497 | struct of_queue_prop { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1498 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1499 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1500 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1501 | }; |
| 1502 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1503 | struct of_queue_prop_min_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1504 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1505 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1506 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1507 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1508 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1509 | }; |
| 1510 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1511 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1512 | uint32_t queue_id; |
| 1513 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1514 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1515 | list(of_queue_prop_t) properties; |
| 1516 | }; |
| 1517 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1518 | struct of_queue_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1519 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1520 | uint8_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1521 | uint16_t length; |
| 1522 | uint32_t xid; |
| 1523 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1524 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1525 | }; |
| 1526 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1527 | struct of_queue_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1528 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1529 | uint8_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1530 | uint16_t length; |
| 1531 | uint32_t xid; |
| 1532 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1533 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1534 | list(of_packet_queue_t) queues; |
| 1535 | }; |