Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 2 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
Wilson Ng | d72013d | 2013-09-29 10:21:48 -0700 | [diff] [blame] | 38 | OFP_TCP_PORT = 6653, |
| 39 | OFP_SSL_PORT = 6653, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFPFW_ICMP_TYPE = 0x40, |
| 46 | OFPFW_ICMP_CODE = 0x80, |
| 47 | |
| 48 | OFP_DL_TYPE_ETH2_CUTOFF = 0x600, |
| 49 | OFP_DL_TYPE_NOT_ETH_TYPE = 0x5ff, |
| 50 | |
| 51 | OFP_VLAN_NONE = 0, |
| 52 | |
| 53 | OFPMT_STANDARD_LENGTH = 88, |
| 54 | |
| 55 | OFP_FLOW_PERMANENT = 0, |
| 56 | |
| 57 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 58 | |
| 59 | DESC_STR_LEN = 256, |
| 60 | SERIAL_NUM_LEN = 32, |
| 61 | |
| 62 | OFPQ_ALL = 0xffffffff, |
| 63 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 64 | }; |
| 65 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 66 | enum ofp_port(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 67 | OFPP_MAX = 0xffffff00, |
| 68 | OFPP_IN_PORT = 0xfffffff8, |
| 69 | OFPP_TABLE = 0xfffffff9, |
| 70 | OFPP_NORMAL = 0xfffffffa, |
| 71 | OFPP_FLOOD = 0xfffffffb, |
| 72 | OFPP_ALL = 0xfffffffc, |
| 73 | OFPP_CONTROLLER = 0xfffffffd, |
| 74 | OFPP_LOCAL = 0xfffffffe, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 75 | OFPP_ANY = 0xffffffff, |
| 76 | }; |
| 77 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 78 | enum ofp_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 79 | OFPT_HELLO = 0, |
| 80 | OFPT_ERROR = 1, |
| 81 | OFPT_ECHO_REQUEST = 2, |
| 82 | OFPT_ECHO_REPLY = 3, |
| 83 | OFPT_EXPERIMENTER = 4, |
| 84 | OFPT_FEATURES_REQUEST = 5, |
| 85 | OFPT_FEATURES_REPLY = 6, |
| 86 | OFPT_GET_CONFIG_REQUEST = 7, |
| 87 | OFPT_GET_CONFIG_REPLY = 8, |
| 88 | OFPT_SET_CONFIG = 9, |
| 89 | OFPT_PACKET_IN = 10, |
| 90 | OFPT_FLOW_REMOVED = 11, |
| 91 | OFPT_PORT_STATUS = 12, |
| 92 | OFPT_PACKET_OUT = 13, |
| 93 | OFPT_FLOW_MOD = 14, |
| 94 | OFPT_GROUP_MOD = 15, |
| 95 | OFPT_PORT_MOD = 16, |
| 96 | OFPT_TABLE_MOD = 17, |
| 97 | OFPT_STATS_REQUEST = 18, |
| 98 | OFPT_STATS_REPLY = 19, |
| 99 | OFPT_BARRIER_REQUEST = 20, |
| 100 | OFPT_BARRIER_REPLY = 21, |
| 101 | OFPT_QUEUE_GET_CONFIG_REQUEST = 22, |
| 102 | OFPT_QUEUE_GET_CONFIG_REPLY = 23, |
| 103 | }; |
| 104 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 105 | enum ofp_config_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 106 | OFPC_FRAG_NORMAL = 0, |
| 107 | OFPC_FRAG_DROP = 1, |
| 108 | OFPC_FRAG_REASM = 2, |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 109 | OFPC_FRAG_MASK(virtual=True) = 3, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 110 | OFPC_INVALID_TTL_TO_CONTROLLER = 4, |
| 111 | }; |
| 112 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 113 | enum ofp_table_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 114 | OFPTC_TABLE_MISS_CONTROLLER = 0, |
| 115 | OFPTC_TABLE_MISS_CONTINUE = 1, |
| 116 | OFPTC_TABLE_MISS_DROP = 2, |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 117 | OFPTC_TABLE_MISS_MASK(virtual=True) = 3, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 118 | }; |
| 119 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 120 | enum ofp_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 121 | OFPC_FLOW_STATS = 0x1, |
| 122 | OFPC_TABLE_STATS = 0x2, |
| 123 | OFPC_PORT_STATS = 0x4, |
| 124 | OFPC_GROUP_STATS = 0x8, |
| 125 | OFPC_IP_REASM = 0x20, |
| 126 | OFPC_QUEUE_STATS = 0x40, |
| 127 | OFPC_ARP_MATCH_IP = 0x80, |
| 128 | }; |
| 129 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 130 | enum ofp_port_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 131 | OFPPC_PORT_DOWN = 0x1, |
| 132 | OFPPC_NO_RECV = 0x4, |
| 133 | OFPPC_NO_FWD = 0x20, |
| 134 | OFPPC_NO_PACKET_IN = 0x40, |
| 135 | }; |
| 136 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 137 | enum ofp_port_state(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 138 | OFPPS_LINK_DOWN = 0x1, |
| 139 | OFPPS_BLOCKED = 0x2, |
| 140 | OFPPS_LIVE = 0x4, |
| 141 | }; |
| 142 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 143 | enum ofp_port_features(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 144 | OFPPF_10MB_HD = 0x1, |
| 145 | OFPPF_10MB_FD = 0x2, |
| 146 | OFPPF_100MB_HD = 0x4, |
| 147 | OFPPF_100MB_FD = 0x8, |
| 148 | OFPPF_1GB_HD = 0x10, |
| 149 | OFPPF_1GB_FD = 0x20, |
| 150 | OFPPF_10GB_FD = 0x40, |
| 151 | OFPPF_40GB_FD = 0x80, |
| 152 | OFPPF_100GB_FD = 0x100, |
| 153 | OFPPF_1TB_FD = 0x200, |
| 154 | OFPPF_OTHER = 0x400, |
| 155 | OFPPF_COPPER = 0x800, |
| 156 | OFPPF_FIBER = 0x1000, |
| 157 | OFPPF_AUTONEG = 0x2000, |
| 158 | OFPPF_PAUSE = 0x4000, |
| 159 | OFPPF_PAUSE_ASYM = 0x8000, |
| 160 | }; |
| 161 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 162 | enum ofp_port_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 163 | OFPPR_ADD = 0, |
| 164 | OFPPR_DELETE = 1, |
| 165 | OFPPR_MODIFY = 2, |
| 166 | }; |
| 167 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 168 | enum ofp_packet_in_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 169 | OFPR_NO_MATCH = 0, |
| 170 | OFPR_ACTION = 1, |
| 171 | }; |
| 172 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 173 | enum ofp_action_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 174 | OFPAT_OUTPUT = 0, |
| 175 | OFPAT_SET_VLAN_VID = 1, |
| 176 | OFPAT_SET_VLAN_PCP = 2, |
| 177 | OFPAT_SET_DL_SRC = 3, |
| 178 | OFPAT_SET_DL_DST = 4, |
| 179 | OFPAT_SET_NW_SRC = 5, |
| 180 | OFPAT_SET_NW_DST = 6, |
| 181 | OFPAT_SET_NW_TOS = 7, |
| 182 | OFPAT_SET_NW_ECN = 8, |
| 183 | OFPAT_SET_TP_SRC = 9, |
| 184 | OFPAT_SET_TP_DST = 10, |
| 185 | OFPAT_COPY_TTL_OUT = 11, |
| 186 | OFPAT_COPY_TTL_IN = 12, |
| 187 | OFPAT_SET_MPLS_LABEL = 13, |
| 188 | OFPAT_SET_MPLS_TC = 14, |
| 189 | OFPAT_SET_MPLS_TTL = 15, |
| 190 | OFPAT_DEC_MPLS_TTL = 16, |
| 191 | OFPAT_PUSH_VLAN = 17, |
| 192 | OFPAT_POP_VLAN = 18, |
| 193 | OFPAT_PUSH_MPLS = 19, |
| 194 | OFPAT_POP_MPLS = 20, |
| 195 | OFPAT_SET_QUEUE = 21, |
| 196 | OFPAT_GROUP = 22, |
| 197 | OFPAT_SET_NW_TTL = 23, |
| 198 | OFPAT_DEC_NW_TTL = 24, |
| 199 | OFPAT_EXPERIMENTER = 0xffff, |
| 200 | }; |
| 201 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 202 | enum ofp_flow_mod_command(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 203 | OFPFC_ADD = 0, |
| 204 | OFPFC_MODIFY = 1, |
| 205 | OFPFC_MODIFY_STRICT = 2, |
| 206 | OFPFC_DELETE = 3, |
| 207 | OFPFC_DELETE_STRICT = 4, |
| 208 | }; |
| 209 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 210 | enum ofp_group_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 211 | OFPGC_ADD = 0, |
| 212 | OFPGC_MODIFY = 1, |
| 213 | OFPGC_DELETE = 2, |
| 214 | }; |
| 215 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 216 | enum ofp_flow_wildcards(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 217 | OFPFW_IN_PORT = 0x1, |
| 218 | OFPFW_DL_VLAN = 0x2, |
| 219 | OFPFW_DL_VLAN_PCP = 0x4, |
| 220 | OFPFW_DL_TYPE = 0x8, |
| 221 | OFPFW_NW_TOS = 0x10, |
| 222 | OFPFW_NW_PROTO = 0x20, |
| 223 | OFPFW_TP_SRC = 0x40, |
| 224 | OFPFW_TP_DST = 0x80, |
| 225 | OFPFW_MPLS_LABEL = 0x100, |
| 226 | OFPFW_MPLS_TC = 0x200, |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 227 | OFPFW_ALL(virtual=True) = 0x3ff, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 228 | }; |
| 229 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 230 | enum ofp_vlan_id(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 231 | OFPVID_ANY = 0xfffe, |
| 232 | OFPVID_NONE = 0xffff, |
| 233 | }; |
| 234 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 235 | enum ofp_match_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 236 | OFPMT_STANDARD = 0, |
| 237 | }; |
| 238 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 239 | enum ofp_instruction_type(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 240 | OFPIT_GOTO_TABLE = 0x1, |
| 241 | OFPIT_WRITE_METADATA = 0x2, |
| 242 | OFPIT_WRITE_ACTIONS = 0x3, |
| 243 | OFPIT_APPLY_ACTIONS = 0x4, |
| 244 | OFPIT_CLEAR_ACTIONS = 0x5, |
| 245 | OFPIT_EXPERIMENTER = 0xffff, |
| 246 | }; |
| 247 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 248 | enum ofp_flow_mod_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 249 | OFPFF_SEND_FLOW_REM = 0x1, |
| 250 | OFPFF_CHECK_OVERLAP = 0x2, |
| 251 | }; |
| 252 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 253 | enum ofp_group(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 254 | OFPG_MAX = 0xffffff00, |
| 255 | OFPG_ALL = 0xfffffffc, |
| 256 | OFPG_ANY = 0xffffffff, |
| 257 | }; |
| 258 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 259 | enum ofp_group_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 260 | OFPGT_ALL = 0, |
| 261 | OFPGT_SELECT = 1, |
| 262 | OFPGT_INDIRECT = 2, |
| 263 | OFPGT_FF = 3, |
| 264 | }; |
| 265 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 266 | enum ofp_flow_removed_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 267 | OFPRR_IDLE_TIMEOUT = 0, |
| 268 | OFPRR_HARD_TIMEOUT = 1, |
| 269 | OFPRR_DELETE = 2, |
| 270 | OFPRR_GROUP_DELETE = 3, |
| 271 | }; |
| 272 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 273 | enum ofp_error_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 274 | OFPET_HELLO_FAILED = 0, |
| 275 | OFPET_BAD_REQUEST = 1, |
| 276 | OFPET_BAD_ACTION = 2, |
| 277 | OFPET_BAD_INSTRUCTION = 3, |
| 278 | OFPET_BAD_MATCH = 4, |
| 279 | OFPET_FLOW_MOD_FAILED = 5, |
| 280 | OFPET_GROUP_MOD_FAILED = 6, |
| 281 | OFPET_PORT_MOD_FAILED = 7, |
| 282 | OFPET_TABLE_MOD_FAILED = 8, |
| 283 | OFPET_QUEUE_OP_FAILED = 9, |
| 284 | OFPET_SWITCH_CONFIG_FAILED = 10, |
| 285 | }; |
| 286 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 287 | enum ofp_hello_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 288 | OFPHFC_INCOMPATIBLE = 0, |
| 289 | OFPHFC_EPERM = 1, |
| 290 | }; |
| 291 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 292 | enum ofp_bad_request_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 293 | OFPBRC_BAD_VERSION = 0, |
| 294 | OFPBRC_BAD_TYPE = 1, |
| 295 | OFPBRC_BAD_STAT = 2, |
| 296 | OFPBRC_BAD_EXPERIMENTER = 3, |
| 297 | OFPBRC_BAD_SUBTYPE = 4, |
| 298 | OFPBRC_EPERM = 5, |
| 299 | OFPBRC_BAD_LEN = 6, |
| 300 | OFPBRC_BUFFER_EMPTY = 7, |
| 301 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 302 | OFPBRC_BAD_TABLE_ID = 9, |
| 303 | }; |
| 304 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 305 | enum ofp_bad_action_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 306 | OFPBAC_BAD_TYPE = 0, |
| 307 | OFPBAC_BAD_LEN = 1, |
| 308 | OFPBAC_BAD_EXPERIMENTER = 2, |
| 309 | OFPBAC_BAD_EXPERIMENTER_TYPE = 3, |
| 310 | OFPBAC_BAD_OUT_PORT = 4, |
| 311 | OFPBAC_BAD_ARGUMENT = 5, |
| 312 | OFPBAC_EPERM = 6, |
| 313 | OFPBAC_TOO_MANY = 7, |
| 314 | OFPBAC_BAD_QUEUE = 8, |
| 315 | OFPBAC_BAD_OUT_GROUP = 9, |
| 316 | OFPBAC_MATCH_INCONSISTENT = 10, |
| 317 | OFPBAC_UNSUPPORTED_ORDER = 11, |
| 318 | OFPBAC_BAD_TAG = 12, |
| 319 | }; |
| 320 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 321 | enum ofp_bad_instruction_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 322 | OFPBIC_UNKNOWN_INST = 0, |
| 323 | OFPBIC_UNSUP_INST = 1, |
| 324 | OFPBIC_BAD_TABLE_ID = 2, |
| 325 | OFPBIC_UNSUP_METADATA = 3, |
| 326 | OFPBIC_UNSUP_METADATA_MASK = 4, |
| 327 | OFPBIC_UNSUP_EXP_INST = 5, |
| 328 | }; |
| 329 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 330 | enum ofp_bad_match_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 331 | OFPBMC_BAD_TYPE = 0, |
| 332 | OFPBMC_BAD_LEN = 1, |
| 333 | OFPBMC_BAD_TAG = 2, |
| 334 | OFPBMC_BAD_DL_ADDR_MASK = 3, |
| 335 | OFPBMC_BAD_NW_ADDR_MASK = 4, |
| 336 | OFPBMC_BAD_WILDCARDS = 5, |
| 337 | OFPBMC_BAD_FIELD = 6, |
| 338 | OFPBMC_BAD_VALUE = 7, |
| 339 | }; |
| 340 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 341 | enum ofp_flow_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 342 | OFPFMFC_UNKNOWN = 0, |
| 343 | OFPFMFC_TABLE_FULL = 1, |
| 344 | OFPFMFC_BAD_TABLE_ID = 2, |
| 345 | OFPFMFC_OVERLAP = 3, |
| 346 | OFPFMFC_EPERM = 4, |
| 347 | OFPFMFC_BAD_TIMEOUT = 5, |
| 348 | OFPFMFC_BAD_COMMAND = 6, |
| 349 | }; |
| 350 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 351 | enum ofp_group_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 352 | OFPGMFC_GROUP_EXISTS = 0, |
| 353 | OFPGMFC_INVALID_GROUP = 1, |
| 354 | OFPGMFC_WEIGHT_UNSUPPORTED = 2, |
| 355 | OFPGMFC_OUT_OF_GROUPS = 3, |
| 356 | OFPGMFC_OUT_OF_BUCKETS = 4, |
| 357 | OFPGMFC_CHAINING_UNSUPPORTED = 5, |
| 358 | OFPGMFC_WATCH_UNSUPPORTED = 6, |
| 359 | OFPGMFC_LOOP = 7, |
| 360 | OFPGMFC_UNKNOWN_GROUP = 8, |
| 361 | }; |
| 362 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 363 | enum ofp_port_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 364 | OFPPMFC_BAD_PORT = 0, |
| 365 | OFPPMFC_BAD_HW_ADDR = 1, |
| 366 | OFPPMFC_BAD_CONFIG = 2, |
| 367 | OFPPMFC_BAD_ADVERTISE = 3, |
| 368 | }; |
| 369 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 370 | enum ofp_table_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 371 | OFPTMFC_BAD_TABLE = 0, |
| 372 | OFPTMFC_BAD_CONFIG = 1, |
| 373 | }; |
| 374 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 375 | enum ofp_queue_op_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 376 | OFPQOFC_BAD_PORT = 0, |
| 377 | OFPQOFC_BAD_QUEUE = 1, |
| 378 | OFPQOFC_EPERM = 2, |
| 379 | }; |
| 380 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 381 | enum ofp_switch_config_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 382 | OFPSCFC_BAD_FLAGS = 0, |
| 383 | OFPSCFC_BAD_LEN = 1, |
| 384 | }; |
| 385 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 386 | enum ofp_stats_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 387 | OFPST_DESC = 0, |
| 388 | OFPST_FLOW = 1, |
| 389 | OFPST_AGGREGATE = 2, |
| 390 | OFPST_TABLE = 3, |
| 391 | OFPST_PORT = 4, |
| 392 | OFPST_QUEUE = 5, |
| 393 | OFPST_GROUP = 6, |
| 394 | OFPST_GROUP_DESC = 7, |
| 395 | OFPST_EXPERIMENTER = 0xffff, |
| 396 | }; |
| 397 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 398 | enum ofp_stats_reply_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 399 | OFPSF_REPLY_MORE = 0x1, |
| 400 | }; |
| 401 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 402 | enum ofp_queue_properties(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 403 | OFPQT_NONE = 0, |
| 404 | OFPQT_MIN_RATE = 1, |
| 405 | }; |
| 406 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 407 | /* XXX rename to of_message */ |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 408 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 409 | uint8_t version; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 410 | uint8_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 411 | uint16_t length; |
| 412 | uint32_t xid; |
| 413 | }; |
| 414 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 415 | struct of_hello : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 416 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 417 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 418 | uint16_t length; |
| 419 | uint32_t xid; |
| 420 | }; |
| 421 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 422 | struct of_echo_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 423 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 424 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 425 | uint16_t length; |
| 426 | uint32_t xid; |
| 427 | of_octets_t data; |
| 428 | }; |
| 429 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 430 | struct of_echo_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 431 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 432 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 433 | uint16_t length; |
| 434 | uint32_t xid; |
| 435 | of_octets_t data; |
| 436 | }; |
| 437 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 438 | struct of_experimenter : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 439 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 440 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 441 | uint16_t length; |
| 442 | uint32_t xid; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 443 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 444 | uint32_t subtype; |
| 445 | of_octets_t data; |
| 446 | }; |
| 447 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 448 | struct of_barrier_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 449 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 450 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 451 | uint16_t length; |
| 452 | uint32_t xid; |
| 453 | }; |
| 454 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 455 | struct of_barrier_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 456 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 457 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 458 | uint16_t length; |
| 459 | uint32_t xid; |
| 460 | }; |
| 461 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 462 | struct of_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 463 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 464 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 465 | uint16_t length; |
| 466 | uint32_t xid; |
| 467 | }; |
| 468 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 469 | struct of_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 470 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 471 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 472 | uint16_t length; |
| 473 | uint32_t xid; |
| 474 | uint16_t flags; |
| 475 | uint16_t miss_send_len; |
| 476 | }; |
| 477 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 478 | struct of_set_config : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 479 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 480 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 481 | uint16_t length; |
| 482 | uint32_t xid; |
| 483 | uint16_t flags; |
| 484 | uint16_t miss_send_len; |
| 485 | }; |
| 486 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 487 | struct of_table_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 488 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 489 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 490 | uint16_t length; |
| 491 | uint32_t xid; |
| 492 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 493 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 494 | uint32_t config; |
| 495 | }; |
| 496 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 497 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 498 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 499 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 500 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 501 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 502 | of_port_name_t name; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 503 | enum ofp_port_config config; |
| 504 | enum ofp_port_state state; |
| 505 | enum ofp_port_features curr; |
| 506 | enum ofp_port_features advertised; |
| 507 | enum ofp_port_features supported; |
| 508 | enum ofp_port_features peer; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 509 | uint32_t curr_speed; |
| 510 | uint32_t max_speed; |
| 511 | }; |
| 512 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 513 | struct of_features_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 514 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 515 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 516 | uint16_t length; |
| 517 | uint32_t xid; |
| 518 | }; |
| 519 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 520 | struct of_features_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 521 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 522 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 523 | uint16_t length; |
| 524 | uint32_t xid; |
| 525 | uint64_t datapath_id; |
| 526 | uint32_t n_buffers; |
| 527 | uint8_t n_tables; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 528 | pad(3); |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 529 | enum ofp_capabilities capabilities; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 530 | uint32_t reserved; |
| 531 | list(of_port_desc_t) ports; |
| 532 | }; |
| 533 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 534 | struct of_port_status : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 535 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 536 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 537 | uint16_t length; |
| 538 | uint32_t xid; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 539 | enum ofp_port_reason reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 540 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 541 | of_port_desc_t desc; |
| 542 | }; |
| 543 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 544 | struct of_port_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 545 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 546 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 547 | uint16_t length; |
| 548 | uint32_t xid; |
| 549 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 550 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 551 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 552 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 553 | uint32_t config; |
| 554 | uint32_t mask; |
| 555 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 556 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 557 | }; |
| 558 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 559 | struct of_packet_in : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 560 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 561 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 562 | uint16_t length; |
| 563 | uint32_t xid; |
| 564 | uint32_t buffer_id; |
| 565 | of_port_no_t in_port; |
| 566 | of_port_no_t in_phy_port; |
| 567 | uint16_t total_len; |
| 568 | uint8_t reason; |
| 569 | uint8_t table_id; |
| 570 | of_octets_t data; |
| 571 | }; |
| 572 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 573 | struct of_action_output : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 574 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 575 | uint16_t len; |
| 576 | of_port_no_t port; |
| 577 | uint16_t max_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 578 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 579 | }; |
| 580 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 581 | struct of_action_set_vlan_vid : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 582 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 583 | uint16_t len; |
| 584 | uint16_t vlan_vid; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 585 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 586 | }; |
| 587 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 588 | struct of_action_set_vlan_pcp : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 589 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 590 | uint16_t len; |
| 591 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 592 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 593 | }; |
| 594 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 595 | struct of_action_set_dl_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 596 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 597 | uint16_t len; |
| 598 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 599 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 600 | }; |
| 601 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 602 | struct of_action_set_dl_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 603 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 604 | uint16_t len; |
| 605 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 606 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 607 | }; |
| 608 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 609 | struct of_action_set_nw_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 610 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 611 | uint16_t len; |
| 612 | uint32_t nw_addr; |
| 613 | }; |
| 614 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 615 | struct of_action_set_nw_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 616 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 617 | uint16_t len; |
| 618 | uint32_t nw_addr; |
| 619 | }; |
| 620 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 621 | struct of_action_set_nw_tos : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 622 | uint16_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 623 | uint16_t len; |
| 624 | uint8_t nw_tos; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 625 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 626 | }; |
| 627 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 628 | struct of_action_set_nw_ecn : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 629 | uint16_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 630 | uint16_t len; |
| 631 | uint8_t nw_ecn; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 632 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 633 | }; |
| 634 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 635 | struct of_action_set_tp_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 636 | uint16_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 637 | uint16_t len; |
| 638 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 639 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 640 | }; |
| 641 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 642 | struct of_action_set_tp_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 643 | uint16_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 644 | uint16_t len; |
| 645 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 646 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 647 | }; |
| 648 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 649 | struct of_action_copy_ttl_out : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 650 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 651 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 652 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 653 | }; |
| 654 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 655 | struct of_action_copy_ttl_in : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 656 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 657 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 658 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 659 | }; |
| 660 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 661 | struct of_action_set_mpls_label : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 662 | uint16_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 663 | uint16_t len; |
| 664 | uint32_t mpls_label; |
| 665 | }; |
| 666 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 667 | struct of_action_set_mpls_tc : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 668 | uint16_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 669 | uint16_t len; |
| 670 | uint8_t mpls_tc; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 671 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 672 | }; |
| 673 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 674 | struct of_action_set_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 675 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 676 | uint16_t len; |
| 677 | uint8_t mpls_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 678 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 679 | }; |
| 680 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 681 | struct of_action_dec_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 682 | uint16_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 683 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 684 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 685 | }; |
| 686 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 687 | struct of_action_push_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 688 | uint16_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 689 | uint16_t len; |
| 690 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 691 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 692 | }; |
| 693 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 694 | struct of_action_pop_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 695 | uint16_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 696 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 697 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 698 | }; |
| 699 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 700 | struct of_action_push_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 701 | uint16_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 702 | uint16_t len; |
| 703 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 704 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 705 | }; |
| 706 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 707 | struct of_action_pop_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 708 | uint16_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 709 | uint16_t len; |
| 710 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 711 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 712 | }; |
| 713 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 714 | struct of_action_set_queue : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 715 | uint16_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 716 | uint16_t len; |
| 717 | uint32_t queue_id; |
| 718 | }; |
| 719 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 720 | struct of_action_group : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 721 | uint16_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 722 | uint16_t len; |
| 723 | uint32_t group_id; |
| 724 | }; |
| 725 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 726 | struct of_action_set_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 727 | uint16_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 728 | uint16_t len; |
| 729 | uint8_t nw_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 730 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 731 | }; |
| 732 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 733 | struct of_action_dec_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 734 | uint16_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 735 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 736 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 737 | }; |
| 738 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 739 | struct of_action_experimenter : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 740 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 741 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 742 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 743 | of_octets_t data; |
| 744 | }; |
| 745 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 746 | struct of_action { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 747 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 748 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 749 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 750 | }; |
| 751 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 752 | struct of_packet_out : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 753 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 754 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 755 | uint16_t length; |
| 756 | uint32_t xid; |
| 757 | uint32_t buffer_id; |
| 758 | of_port_no_t in_port; |
| 759 | uint16_t actions_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 760 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 761 | list(of_action_t) actions; |
| 762 | of_octets_t data; |
| 763 | }; |
| 764 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 765 | struct of_match_v2 { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 766 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 767 | uint16_t length; |
| 768 | of_port_no_t in_port; |
| 769 | of_wc_bmap_t wildcards; |
| 770 | of_mac_addr_t eth_src; |
| 771 | of_mac_addr_t eth_src_mask; |
| 772 | of_mac_addr_t eth_dst; |
| 773 | of_mac_addr_t eth_dst_mask; |
| 774 | uint16_t vlan_vid; |
| 775 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 776 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 777 | uint16_t eth_type; |
| 778 | uint8_t ip_dscp; |
| 779 | uint8_t ip_proto; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 780 | of_ipv4_t ipv4_src; |
| 781 | of_ipv4_t ipv4_src_mask; |
| 782 | of_ipv4_t ipv4_dst; |
| 783 | of_ipv4_t ipv4_dst_mask; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 784 | uint16_t tcp_src; |
| 785 | uint16_t tcp_dst; |
| 786 | uint32_t mpls_label; |
| 787 | uint8_t mpls_tc; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 788 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 789 | uint64_t metadata; |
| 790 | uint64_t metadata_mask; |
| 791 | }; |
| 792 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 793 | struct of_instruction { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 794 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 795 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 796 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 797 | }; |
| 798 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 799 | struct of_instruction_goto_table : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 800 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 801 | uint16_t len; |
| 802 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 803 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 804 | }; |
| 805 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 806 | struct of_instruction_write_metadata : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 807 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 808 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 809 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 810 | uint64_t metadata; |
| 811 | uint64_t metadata_mask; |
| 812 | }; |
| 813 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 814 | struct of_instruction_write_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 815 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 816 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 817 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 818 | list(of_action_t) actions; |
| 819 | }; |
| 820 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 821 | struct of_instruction_apply_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 822 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 823 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 824 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 825 | list(of_action_t) actions; |
| 826 | }; |
| 827 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 828 | struct of_instruction_clear_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 829 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 830 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 831 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 832 | }; |
| 833 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 834 | struct of_instruction_experimenter : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 835 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 836 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 837 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 838 | of_octets_t data; |
| 839 | }; |
| 840 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 841 | struct of_flow_mod : of_header { |
| 842 | uint8_t version; |
| 843 | uint8_t type == 14; |
| 844 | uint16_t length; |
| 845 | uint32_t xid; |
| 846 | uint64_t cookie; |
| 847 | uint64_t cookie_mask; |
| 848 | uint8_t table_id; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 849 | of_fm_cmd_t _command == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 850 | uint16_t idle_timeout; |
| 851 | uint16_t hard_timeout; |
| 852 | uint16_t priority; |
| 853 | uint32_t buffer_id; |
| 854 | of_port_no_t out_port; |
| 855 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 856 | enum ofp_flow_mod_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 857 | pad(2); |
| 858 | of_match_t match; |
| 859 | list(of_instruction_t) instructions; |
| 860 | }; |
| 861 | |
| 862 | struct of_flow_add : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 863 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 864 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 865 | uint16_t length; |
| 866 | uint32_t xid; |
| 867 | uint64_t cookie; |
| 868 | uint64_t cookie_mask; |
| 869 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 870 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 871 | uint16_t idle_timeout; |
| 872 | uint16_t hard_timeout; |
| 873 | uint16_t priority; |
| 874 | uint32_t buffer_id; |
| 875 | of_port_no_t out_port; |
| 876 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 877 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 878 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 879 | of_match_t match; |
| 880 | list(of_instruction_t) instructions; |
| 881 | }; |
| 882 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 883 | struct of_flow_modify : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 884 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 885 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 886 | uint16_t length; |
| 887 | uint32_t xid; |
| 888 | uint64_t cookie; |
| 889 | uint64_t cookie_mask; |
| 890 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 891 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 892 | uint16_t idle_timeout; |
| 893 | uint16_t hard_timeout; |
| 894 | uint16_t priority; |
| 895 | uint32_t buffer_id; |
| 896 | of_port_no_t out_port; |
| 897 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 898 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 899 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 900 | of_match_t match; |
| 901 | list(of_instruction_t) instructions; |
| 902 | }; |
| 903 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 904 | struct of_flow_modify_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 905 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 906 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 907 | uint16_t length; |
| 908 | uint32_t xid; |
| 909 | uint64_t cookie; |
| 910 | uint64_t cookie_mask; |
| 911 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 912 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 913 | uint16_t idle_timeout; |
| 914 | uint16_t hard_timeout; |
| 915 | uint16_t priority; |
| 916 | uint32_t buffer_id; |
| 917 | of_port_no_t out_port; |
| 918 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 919 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 920 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 921 | of_match_t match; |
| 922 | list(of_instruction_t) instructions; |
| 923 | }; |
| 924 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 925 | struct of_flow_delete : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 926 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 927 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 928 | uint16_t length; |
| 929 | uint32_t xid; |
| 930 | uint64_t cookie; |
| 931 | uint64_t cookie_mask; |
| 932 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 933 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 934 | uint16_t idle_timeout; |
| 935 | uint16_t hard_timeout; |
| 936 | uint16_t priority; |
| 937 | uint32_t buffer_id; |
| 938 | of_port_no_t out_port; |
| 939 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 940 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 941 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 942 | of_match_t match; |
| 943 | list(of_instruction_t) instructions; |
| 944 | }; |
| 945 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 946 | struct of_flow_delete_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 947 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 948 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 949 | uint16_t length; |
| 950 | uint32_t xid; |
| 951 | uint64_t cookie; |
| 952 | uint64_t cookie_mask; |
| 953 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 954 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 955 | uint16_t idle_timeout; |
| 956 | uint16_t hard_timeout; |
| 957 | uint16_t priority; |
| 958 | uint32_t buffer_id; |
| 959 | of_port_no_t out_port; |
| 960 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 961 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 962 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 963 | of_match_t match; |
| 964 | list(of_instruction_t) instructions; |
| 965 | }; |
| 966 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 967 | struct of_bucket { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 968 | uint16_t len; |
| 969 | uint16_t weight; |
| 970 | of_port_no_t watch_port; |
| 971 | uint32_t watch_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 972 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 973 | list(of_action_t) actions; |
| 974 | }; |
| 975 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 976 | struct of_group_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 977 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 978 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 979 | uint16_t length; |
| 980 | uint32_t xid; |
| 981 | uint16_t command; |
| 982 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 983 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 984 | uint32_t group_id; |
| 985 | list(of_bucket_t) buckets; |
| 986 | }; |
| 987 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 988 | struct of_flow_removed : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 989 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 990 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 991 | uint16_t length; |
| 992 | uint32_t xid; |
| 993 | uint64_t cookie; |
| 994 | uint16_t priority; |
| 995 | uint8_t reason; |
| 996 | uint8_t table_id; |
| 997 | uint32_t duration_sec; |
| 998 | uint32_t duration_nsec; |
| 999 | uint16_t idle_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1000 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1001 | uint64_t packet_count; |
| 1002 | uint64_t byte_count; |
| 1003 | of_match_t match; |
| 1004 | }; |
| 1005 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1006 | struct of_error_msg : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1007 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1008 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1009 | uint16_t length; |
| 1010 | uint32_t xid; |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 1011 | uint16_t err_type == ?; |
| 1012 | }; |
| 1013 | |
| 1014 | struct of_hello_failed_error_msg : of_error_msg { |
| 1015 | uint8_t version; |
| 1016 | uint8_t type == 1; |
| 1017 | uint16_t length; |
| 1018 | uint32_t xid; |
| 1019 | uint16_t err_type == 0; |
| 1020 | enum ofp_hello_failed_code code; |
| 1021 | of_octets_t data; |
| 1022 | }; |
| 1023 | |
| 1024 | struct of_bad_request_error_msg : of_error_msg { |
| 1025 | uint8_t version; |
| 1026 | uint8_t type == 1; |
| 1027 | uint16_t length; |
| 1028 | uint32_t xid; |
| 1029 | uint16_t err_type == 1; |
| 1030 | enum ofp_bad_request_code code; |
| 1031 | of_octets_t data; |
| 1032 | }; |
| 1033 | |
| 1034 | struct of_bad_action_error_msg : of_error_msg { |
| 1035 | uint8_t version; |
| 1036 | uint8_t type == 1; |
| 1037 | uint16_t length; |
| 1038 | uint32_t xid; |
| 1039 | uint16_t err_type == 2; |
| 1040 | enum ofp_bad_action_code code; |
| 1041 | of_octets_t data; |
| 1042 | }; |
| 1043 | |
| 1044 | struct of_bad_instruction_error_msg : of_error_msg { |
| 1045 | uint8_t version; |
| 1046 | uint8_t type == 1; |
| 1047 | uint16_t length; |
| 1048 | uint32_t xid; |
| 1049 | uint16_t err_type == 3; |
| 1050 | enum ofp_bad_instruction_code code; |
| 1051 | of_octets_t data; |
| 1052 | }; |
| 1053 | |
| 1054 | struct of_bad_match_error_msg : of_error_msg { |
| 1055 | uint8_t version; |
| 1056 | uint8_t type == 1; |
| 1057 | uint16_t length; |
| 1058 | uint32_t xid; |
| 1059 | uint16_t err_type == 4; |
| 1060 | enum ofp_bad_match_code code; |
| 1061 | of_octets_t data; |
| 1062 | }; |
| 1063 | |
| 1064 | struct of_flow_mod_failed_error_msg : of_error_msg { |
| 1065 | uint8_t version; |
| 1066 | uint8_t type == 1; |
| 1067 | uint16_t length; |
| 1068 | uint32_t xid; |
| 1069 | uint16_t err_type == 5; |
| 1070 | enum ofp_flow_mod_failed_code code; |
| 1071 | of_octets_t data; |
| 1072 | }; |
| 1073 | |
| 1074 | struct of_group_mod_failed_error_msg : of_error_msg { |
| 1075 | uint8_t version; |
| 1076 | uint8_t type == 1; |
| 1077 | uint16_t length; |
| 1078 | uint32_t xid; |
| 1079 | uint16_t err_type == 6; |
| 1080 | enum ofp_group_mod_failed_code code; |
| 1081 | of_octets_t data; |
| 1082 | }; |
| 1083 | |
| 1084 | struct of_port_mod_failed_error_msg : of_error_msg { |
| 1085 | uint8_t version; |
| 1086 | uint8_t type == 1; |
| 1087 | uint16_t length; |
| 1088 | uint32_t xid; |
| 1089 | uint16_t err_type == 7; |
| 1090 | enum ofp_port_mod_failed_code code; |
| 1091 | of_octets_t data; |
| 1092 | }; |
| 1093 | |
| 1094 | struct of_table_mod_failed_error_msg : of_error_msg { |
| 1095 | uint8_t version; |
| 1096 | uint8_t type == 1; |
| 1097 | uint16_t length; |
| 1098 | uint32_t xid; |
| 1099 | uint16_t err_type == 8; |
| 1100 | enum ofp_table_mod_failed_code code; |
| 1101 | of_octets_t data; |
| 1102 | }; |
| 1103 | |
| 1104 | struct of_queue_op_failed_error_msg : of_error_msg { |
| 1105 | uint8_t version; |
| 1106 | uint8_t type == 1; |
| 1107 | uint16_t length; |
| 1108 | uint32_t xid; |
| 1109 | uint16_t err_type == 9; |
| 1110 | enum ofp_queue_op_failed_code code; |
| 1111 | of_octets_t data; |
| 1112 | }; |
| 1113 | |
| 1114 | struct of_switch_config_failed_error_msg : of_error_msg { |
| 1115 | uint8_t version; |
| 1116 | uint8_t type == 1; |
| 1117 | uint16_t length; |
| 1118 | uint32_t xid; |
| 1119 | uint16_t err_type == 10; |
| 1120 | enum ofp_switch_config_failed_code code; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1121 | of_octets_t data; |
| 1122 | }; |
| 1123 | |
| 1124 | // STATS ENTRIES: flow, table, port, group, group_desc |
| 1125 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1126 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1127 | uint16_t length; |
| 1128 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1129 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1130 | uint32_t duration_sec; |
| 1131 | uint32_t duration_nsec; |
| 1132 | uint16_t priority; |
| 1133 | uint16_t idle_timeout; |
| 1134 | uint16_t hard_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1135 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1136 | uint64_t cookie; |
| 1137 | uint64_t packet_count; |
| 1138 | uint64_t byte_count; |
| 1139 | of_match_t match; |
| 1140 | list(of_instruction_t) instructions; |
| 1141 | }; |
| 1142 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1143 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1144 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1145 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1146 | of_table_name_t name; |
| 1147 | of_wc_bmap_t wildcards; |
| 1148 | of_match_bmap_t match; |
| 1149 | uint32_t instructions; |
| 1150 | uint32_t write_actions; |
| 1151 | uint32_t apply_actions; |
| 1152 | uint32_t config; |
| 1153 | uint32_t max_entries; |
| 1154 | uint32_t active_count; |
| 1155 | uint64_t lookup_count; |
| 1156 | uint64_t matched_count; |
| 1157 | }; |
| 1158 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1159 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1160 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1161 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1162 | uint64_t rx_packets; |
| 1163 | uint64_t tx_packets; |
| 1164 | uint64_t rx_bytes; |
| 1165 | uint64_t tx_bytes; |
| 1166 | uint64_t rx_dropped; |
| 1167 | uint64_t tx_dropped; |
| 1168 | uint64_t rx_errors; |
| 1169 | uint64_t tx_errors; |
| 1170 | uint64_t rx_frame_err; |
| 1171 | uint64_t rx_over_err; |
| 1172 | uint64_t rx_crc_err; |
| 1173 | uint64_t collisions; |
| 1174 | }; |
| 1175 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1176 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1177 | of_port_no_t port_no; |
| 1178 | uint32_t queue_id; |
| 1179 | uint64_t tx_bytes; |
| 1180 | uint64_t tx_packets; |
| 1181 | uint64_t tx_errors; |
| 1182 | }; |
| 1183 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1184 | struct of_bucket_counter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1185 | uint64_t packet_count; |
| 1186 | uint64_t byte_count; |
| 1187 | }; |
| 1188 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1189 | struct of_group_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1190 | uint16_t length; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1191 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1192 | uint32_t group_id; |
| 1193 | uint32_t ref_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1194 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1195 | uint64_t packet_count; |
| 1196 | uint64_t byte_count; |
| 1197 | list(of_bucket_counter_t) bucket_stats; |
| 1198 | }; |
| 1199 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1200 | struct of_group_desc_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1201 | uint16_t length; |
Rich Lane | 35e7ac7 | 2013-10-15 10:36:10 -0700 | [diff] [blame] | 1202 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1203 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1204 | uint32_t group_id; |
| 1205 | list(of_bucket_t) buckets; |
| 1206 | }; |
| 1207 | |
| 1208 | // STATS: Desc, flow, agg, table, port, queue, group, group_desc, experi |
| 1209 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1210 | struct of_stats_request : of_header { |
| 1211 | uint8_t version; |
| 1212 | uint8_t type == 18; |
| 1213 | uint16_t length; |
| 1214 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1215 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1216 | uint16_t flags; |
| 1217 | pad(4); |
| 1218 | }; |
| 1219 | |
| 1220 | struct of_stats_reply : of_header { |
| 1221 | uint8_t version; |
| 1222 | uint8_t type == 19; |
| 1223 | uint16_t length; |
| 1224 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1225 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1226 | uint16_t flags; |
| 1227 | pad(4); |
| 1228 | }; |
| 1229 | |
| 1230 | struct of_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1231 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1232 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1233 | uint16_t length; |
| 1234 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1235 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1236 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1237 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1238 | }; |
| 1239 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1240 | struct of_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1241 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1242 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1243 | uint16_t length; |
| 1244 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1245 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1246 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1247 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1248 | of_desc_str_t mfr_desc; |
| 1249 | of_desc_str_t hw_desc; |
| 1250 | of_desc_str_t sw_desc; |
| 1251 | of_serial_num_t serial_num; |
| 1252 | of_desc_str_t dp_desc; |
| 1253 | }; |
| 1254 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1255 | struct of_flow_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1256 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1257 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1258 | uint16_t length; |
| 1259 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1260 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1261 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1262 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1263 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1264 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1265 | of_port_no_t out_port; |
| 1266 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1267 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1268 | uint64_t cookie; |
| 1269 | uint64_t cookie_mask; |
| 1270 | of_match_t match; |
| 1271 | }; |
| 1272 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1273 | struct of_flow_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1274 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1275 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1276 | uint16_t length; |
| 1277 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1278 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1279 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1280 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1281 | list(of_flow_stats_entry_t) entries; |
| 1282 | }; |
| 1283 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1284 | struct of_aggregate_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1285 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1286 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1287 | uint16_t length; |
| 1288 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1289 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1290 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1291 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1292 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1293 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1294 | of_port_no_t out_port; |
| 1295 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1296 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1297 | uint64_t cookie; |
| 1298 | uint64_t cookie_mask; |
| 1299 | of_match_t match; |
| 1300 | }; |
| 1301 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1302 | struct of_aggregate_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1303 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1304 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1305 | uint16_t length; |
| 1306 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1307 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1308 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1309 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1310 | uint64_t packet_count; |
| 1311 | uint64_t byte_count; |
| 1312 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1313 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1314 | }; |
| 1315 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1316 | struct of_table_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1317 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1318 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1319 | uint16_t length; |
| 1320 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1321 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1322 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1323 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1324 | }; |
| 1325 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1326 | struct of_table_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1327 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1328 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1329 | uint16_t length; |
| 1330 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1331 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1332 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1333 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1334 | list(of_table_stats_entry_t) entries; |
| 1335 | }; |
| 1336 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1337 | struct of_port_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1338 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1339 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1340 | uint16_t length; |
| 1341 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1342 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1343 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1344 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1345 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1346 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1347 | }; |
| 1348 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1349 | struct of_port_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1350 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1351 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1352 | uint16_t length; |
| 1353 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1354 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1355 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1356 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1357 | list(of_port_stats_entry_t) entries; |
| 1358 | }; |
| 1359 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1360 | struct of_queue_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1361 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1362 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1363 | uint16_t length; |
| 1364 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1365 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1366 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1367 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1368 | of_port_no_t port_no; |
| 1369 | uint32_t queue_id; |
| 1370 | }; |
| 1371 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1372 | struct of_queue_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1373 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1374 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1375 | uint16_t length; |
| 1376 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1377 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1378 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1379 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1380 | list(of_queue_stats_entry_t) entries; |
| 1381 | }; |
| 1382 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1383 | struct of_group_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1384 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1385 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1386 | uint16_t length; |
| 1387 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1388 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1389 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1390 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1391 | uint32_t group_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1392 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1393 | }; |
| 1394 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1395 | struct of_group_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1396 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1397 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1398 | uint16_t length; |
| 1399 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1400 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1401 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1402 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1403 | list(of_group_stats_entry_t) entries; |
| 1404 | }; |
| 1405 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1406 | struct of_group_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1407 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1408 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1409 | uint16_t length; |
| 1410 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1411 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1412 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1413 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1414 | }; |
| 1415 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1416 | struct of_group_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1417 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1418 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1419 | uint16_t length; |
| 1420 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1421 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1422 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1423 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1424 | list(of_group_desc_stats_entry_t) entries; |
| 1425 | }; |
| 1426 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1427 | struct of_experimenter_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1428 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1429 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1430 | uint16_t length; |
| 1431 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1432 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1433 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1434 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1435 | uint32_t experimenter == ?; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1436 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1437 | of_octets_t data; |
| 1438 | }; |
| 1439 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1440 | struct of_experimenter_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1441 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1442 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1443 | uint16_t length; |
| 1444 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1445 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1446 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1447 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1448 | uint32_t experimenter == ?; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1449 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1450 | of_octets_t data; |
| 1451 | }; |
| 1452 | |
| 1453 | // END OF STATS OBJECTS |
| 1454 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1455 | struct of_queue_prop { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1456 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1457 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1458 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1459 | }; |
| 1460 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1461 | struct of_queue_prop_min_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1462 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1463 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1464 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1465 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1466 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1467 | }; |
| 1468 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1469 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1470 | uint32_t queue_id; |
| 1471 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1472 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1473 | list(of_queue_prop_t) properties; |
| 1474 | }; |
| 1475 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1476 | struct of_queue_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1477 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1478 | uint8_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1479 | uint16_t length; |
| 1480 | uint32_t xid; |
| 1481 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1482 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1483 | }; |
| 1484 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1485 | struct of_queue_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1486 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1487 | uint8_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1488 | uint16_t length; |
| 1489 | uint32_t xid; |
| 1490 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1491 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1492 | list(of_packet_queue_t) queues; |
| 1493 | }; |