Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 2 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
| 38 | OFP_TCP_PORT = 6633, |
| 39 | OFP_SSL_PORT = 6633, |
| 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFPFW_ICMP_TYPE = 0x40, |
| 46 | OFPFW_ICMP_CODE = 0x80, |
| 47 | |
| 48 | OFP_DL_TYPE_ETH2_CUTOFF = 0x600, |
| 49 | OFP_DL_TYPE_NOT_ETH_TYPE = 0x5ff, |
| 50 | |
| 51 | OFP_VLAN_NONE = 0, |
| 52 | |
| 53 | OFPMT_STANDARD_LENGTH = 88, |
| 54 | |
| 55 | OFP_FLOW_PERMANENT = 0, |
| 56 | |
| 57 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 58 | |
| 59 | DESC_STR_LEN = 256, |
| 60 | SERIAL_NUM_LEN = 32, |
| 61 | |
| 62 | OFPQ_ALL = 0xffffffff, |
| 63 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 64 | }; |
| 65 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 66 | enum ofp_port(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 67 | OFPP_MAX = 0xffffff00, |
| 68 | OFPP_IN_PORT = 0xfffffff8, |
| 69 | OFPP_TABLE = 0xfffffff9, |
| 70 | OFPP_NORMAL = 0xfffffffa, |
| 71 | OFPP_FLOOD = 0xfffffffb, |
| 72 | OFPP_ALL = 0xfffffffc, |
| 73 | OFPP_CONTROLLER = 0xfffffffd, |
| 74 | OFPP_LOCAL = 0xfffffffe, |
| 75 | }; |
| 76 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 77 | enum ofp_port_no(wire_type=uint32_t, complete=no) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 78 | OFPP_ANY = 0xffffffff, |
| 79 | }; |
| 80 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 81 | enum ofp_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 82 | OFPT_HELLO = 0, |
| 83 | OFPT_ERROR = 1, |
| 84 | OFPT_ECHO_REQUEST = 2, |
| 85 | OFPT_ECHO_REPLY = 3, |
| 86 | OFPT_EXPERIMENTER = 4, |
| 87 | OFPT_FEATURES_REQUEST = 5, |
| 88 | OFPT_FEATURES_REPLY = 6, |
| 89 | OFPT_GET_CONFIG_REQUEST = 7, |
| 90 | OFPT_GET_CONFIG_REPLY = 8, |
| 91 | OFPT_SET_CONFIG = 9, |
| 92 | OFPT_PACKET_IN = 10, |
| 93 | OFPT_FLOW_REMOVED = 11, |
| 94 | OFPT_PORT_STATUS = 12, |
| 95 | OFPT_PACKET_OUT = 13, |
| 96 | OFPT_FLOW_MOD = 14, |
| 97 | OFPT_GROUP_MOD = 15, |
| 98 | OFPT_PORT_MOD = 16, |
| 99 | OFPT_TABLE_MOD = 17, |
| 100 | OFPT_STATS_REQUEST = 18, |
| 101 | OFPT_STATS_REPLY = 19, |
| 102 | OFPT_BARRIER_REQUEST = 20, |
| 103 | OFPT_BARRIER_REPLY = 21, |
| 104 | OFPT_QUEUE_GET_CONFIG_REQUEST = 22, |
| 105 | OFPT_QUEUE_GET_CONFIG_REPLY = 23, |
| 106 | }; |
| 107 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 108 | enum ofp_config_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 109 | OFPC_FRAG_NORMAL = 0, |
| 110 | OFPC_FRAG_DROP = 1, |
| 111 | OFPC_FRAG_REASM = 2, |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 112 | OFPC_FRAG_MASK(virtual=True) = 3, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 113 | OFPC_INVALID_TTL_TO_CONTROLLER = 4, |
| 114 | }; |
| 115 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 116 | enum ofp_table_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 117 | OFPTC_TABLE_MISS_CONTROLLER = 0, |
| 118 | OFPTC_TABLE_MISS_CONTINUE = 1, |
| 119 | OFPTC_TABLE_MISS_DROP = 2, |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 120 | OFPTC_TABLE_MISS_MASK(virtual=True) = 3, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 121 | }; |
| 122 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 123 | enum ofp_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 124 | OFPC_FLOW_STATS = 0x1, |
| 125 | OFPC_TABLE_STATS = 0x2, |
| 126 | OFPC_PORT_STATS = 0x4, |
| 127 | OFPC_GROUP_STATS = 0x8, |
| 128 | OFPC_IP_REASM = 0x20, |
| 129 | OFPC_QUEUE_STATS = 0x40, |
| 130 | OFPC_ARP_MATCH_IP = 0x80, |
| 131 | }; |
| 132 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 133 | enum ofp_port_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 134 | OFPPC_PORT_DOWN = 0x1, |
| 135 | OFPPC_NO_RECV = 0x4, |
| 136 | OFPPC_NO_FWD = 0x20, |
| 137 | OFPPC_NO_PACKET_IN = 0x40, |
| 138 | }; |
| 139 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 140 | enum ofp_port_state(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 141 | OFPPS_LINK_DOWN = 0x1, |
| 142 | OFPPS_BLOCKED = 0x2, |
| 143 | OFPPS_LIVE = 0x4, |
| 144 | }; |
| 145 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 146 | enum ofp_port_features(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 147 | OFPPF_10MB_HD = 0x1, |
| 148 | OFPPF_10MB_FD = 0x2, |
| 149 | OFPPF_100MB_HD = 0x4, |
| 150 | OFPPF_100MB_FD = 0x8, |
| 151 | OFPPF_1GB_HD = 0x10, |
| 152 | OFPPF_1GB_FD = 0x20, |
| 153 | OFPPF_10GB_FD = 0x40, |
| 154 | OFPPF_40GB_FD = 0x80, |
| 155 | OFPPF_100GB_FD = 0x100, |
| 156 | OFPPF_1TB_FD = 0x200, |
| 157 | OFPPF_OTHER = 0x400, |
| 158 | OFPPF_COPPER = 0x800, |
| 159 | OFPPF_FIBER = 0x1000, |
| 160 | OFPPF_AUTONEG = 0x2000, |
| 161 | OFPPF_PAUSE = 0x4000, |
| 162 | OFPPF_PAUSE_ASYM = 0x8000, |
| 163 | }; |
| 164 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 165 | enum ofp_port_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 166 | OFPPR_ADD = 0, |
| 167 | OFPPR_DELETE = 1, |
| 168 | OFPPR_MODIFY = 2, |
| 169 | }; |
| 170 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 171 | enum ofp_packet_in_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 172 | OFPR_NO_MATCH = 0, |
| 173 | OFPR_ACTION = 1, |
| 174 | }; |
| 175 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 176 | enum ofp_action_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 177 | OFPAT_OUTPUT = 0, |
| 178 | OFPAT_SET_VLAN_VID = 1, |
| 179 | OFPAT_SET_VLAN_PCP = 2, |
| 180 | OFPAT_SET_DL_SRC = 3, |
| 181 | OFPAT_SET_DL_DST = 4, |
| 182 | OFPAT_SET_NW_SRC = 5, |
| 183 | OFPAT_SET_NW_DST = 6, |
| 184 | OFPAT_SET_NW_TOS = 7, |
| 185 | OFPAT_SET_NW_ECN = 8, |
| 186 | OFPAT_SET_TP_SRC = 9, |
| 187 | OFPAT_SET_TP_DST = 10, |
| 188 | OFPAT_COPY_TTL_OUT = 11, |
| 189 | OFPAT_COPY_TTL_IN = 12, |
| 190 | OFPAT_SET_MPLS_LABEL = 13, |
| 191 | OFPAT_SET_MPLS_TC = 14, |
| 192 | OFPAT_SET_MPLS_TTL = 15, |
| 193 | OFPAT_DEC_MPLS_TTL = 16, |
| 194 | OFPAT_PUSH_VLAN = 17, |
| 195 | OFPAT_POP_VLAN = 18, |
| 196 | OFPAT_PUSH_MPLS = 19, |
| 197 | OFPAT_POP_MPLS = 20, |
| 198 | OFPAT_SET_QUEUE = 21, |
| 199 | OFPAT_GROUP = 22, |
| 200 | OFPAT_SET_NW_TTL = 23, |
| 201 | OFPAT_DEC_NW_TTL = 24, |
| 202 | OFPAT_EXPERIMENTER = 0xffff, |
| 203 | }; |
| 204 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 205 | enum ofp_flow_mod_command(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 206 | OFPFC_ADD = 0, |
| 207 | OFPFC_MODIFY = 1, |
| 208 | OFPFC_MODIFY_STRICT = 2, |
| 209 | OFPFC_DELETE = 3, |
| 210 | OFPFC_DELETE_STRICT = 4, |
| 211 | }; |
| 212 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 213 | enum ofp_group_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 214 | OFPGC_ADD = 0, |
| 215 | OFPGC_MODIFY = 1, |
| 216 | OFPGC_DELETE = 2, |
| 217 | }; |
| 218 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 219 | enum ofp_flow_wildcards(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 220 | OFPFW_IN_PORT = 0x1, |
| 221 | OFPFW_DL_VLAN = 0x2, |
| 222 | OFPFW_DL_VLAN_PCP = 0x4, |
| 223 | OFPFW_DL_TYPE = 0x8, |
| 224 | OFPFW_NW_TOS = 0x10, |
| 225 | OFPFW_NW_PROTO = 0x20, |
| 226 | OFPFW_TP_SRC = 0x40, |
| 227 | OFPFW_TP_DST = 0x80, |
| 228 | OFPFW_MPLS_LABEL = 0x100, |
| 229 | OFPFW_MPLS_TC = 0x200, |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 230 | OFPFW_ALL(virtual=True) = 0x3ff, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 231 | }; |
| 232 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 233 | enum ofp_vlan_id(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 234 | OFPVID_ANY = 0xfffe, |
| 235 | OFPVID_NONE = 0xffff, |
| 236 | }; |
| 237 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 238 | enum ofp_match_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 239 | OFPMT_STANDARD = 0, |
| 240 | }; |
| 241 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 242 | enum ofp_instruction_type(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 243 | OFPIT_GOTO_TABLE = 0x1, |
| 244 | OFPIT_WRITE_METADATA = 0x2, |
| 245 | OFPIT_WRITE_ACTIONS = 0x3, |
| 246 | OFPIT_APPLY_ACTIONS = 0x4, |
| 247 | OFPIT_CLEAR_ACTIONS = 0x5, |
| 248 | OFPIT_EXPERIMENTER = 0xffff, |
| 249 | }; |
| 250 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 251 | enum ofp_flow_mod_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 252 | OFPFF_SEND_FLOW_REM = 0x1, |
| 253 | OFPFF_CHECK_OVERLAP = 0x2, |
| 254 | }; |
| 255 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 256 | enum ofp_group(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 257 | OFPG_MAX = 0xffffff00, |
| 258 | OFPG_ALL = 0xfffffffc, |
| 259 | OFPG_ANY = 0xffffffff, |
| 260 | }; |
| 261 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 262 | enum ofp_group_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 263 | OFPGT_ALL = 0, |
| 264 | OFPGT_SELECT = 1, |
| 265 | OFPGT_INDIRECT = 2, |
| 266 | OFPGT_FF = 3, |
| 267 | }; |
| 268 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 269 | enum ofp_flow_removed_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 270 | OFPRR_IDLE_TIMEOUT = 0, |
| 271 | OFPRR_HARD_TIMEOUT = 1, |
| 272 | OFPRR_DELETE = 2, |
| 273 | OFPRR_GROUP_DELETE = 3, |
| 274 | }; |
| 275 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 276 | enum ofp_error_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 277 | OFPET_HELLO_FAILED = 0, |
| 278 | OFPET_BAD_REQUEST = 1, |
| 279 | OFPET_BAD_ACTION = 2, |
| 280 | OFPET_BAD_INSTRUCTION = 3, |
| 281 | OFPET_BAD_MATCH = 4, |
| 282 | OFPET_FLOW_MOD_FAILED = 5, |
| 283 | OFPET_GROUP_MOD_FAILED = 6, |
| 284 | OFPET_PORT_MOD_FAILED = 7, |
| 285 | OFPET_TABLE_MOD_FAILED = 8, |
| 286 | OFPET_QUEUE_OP_FAILED = 9, |
| 287 | OFPET_SWITCH_CONFIG_FAILED = 10, |
| 288 | }; |
| 289 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 290 | enum ofp_hello_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 291 | OFPHFC_INCOMPATIBLE = 0, |
| 292 | OFPHFC_EPERM = 1, |
| 293 | }; |
| 294 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 295 | enum ofp_bad_request_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 296 | OFPBRC_BAD_VERSION = 0, |
| 297 | OFPBRC_BAD_TYPE = 1, |
| 298 | OFPBRC_BAD_STAT = 2, |
| 299 | OFPBRC_BAD_EXPERIMENTER = 3, |
| 300 | OFPBRC_BAD_SUBTYPE = 4, |
| 301 | OFPBRC_EPERM = 5, |
| 302 | OFPBRC_BAD_LEN = 6, |
| 303 | OFPBRC_BUFFER_EMPTY = 7, |
| 304 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 305 | OFPBRC_BAD_TABLE_ID = 9, |
| 306 | }; |
| 307 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 308 | enum ofp_bad_action_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 309 | OFPBAC_BAD_TYPE = 0, |
| 310 | OFPBAC_BAD_LEN = 1, |
| 311 | OFPBAC_BAD_EXPERIMENTER = 2, |
| 312 | OFPBAC_BAD_EXPERIMENTER_TYPE = 3, |
| 313 | OFPBAC_BAD_OUT_PORT = 4, |
| 314 | OFPBAC_BAD_ARGUMENT = 5, |
| 315 | OFPBAC_EPERM = 6, |
| 316 | OFPBAC_TOO_MANY = 7, |
| 317 | OFPBAC_BAD_QUEUE = 8, |
| 318 | OFPBAC_BAD_OUT_GROUP = 9, |
| 319 | OFPBAC_MATCH_INCONSISTENT = 10, |
| 320 | OFPBAC_UNSUPPORTED_ORDER = 11, |
| 321 | OFPBAC_BAD_TAG = 12, |
| 322 | }; |
| 323 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 324 | enum ofp_bad_instruction_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 325 | OFPBIC_UNKNOWN_INST = 0, |
| 326 | OFPBIC_UNSUP_INST = 1, |
| 327 | OFPBIC_BAD_TABLE_ID = 2, |
| 328 | OFPBIC_UNSUP_METADATA = 3, |
| 329 | OFPBIC_UNSUP_METADATA_MASK = 4, |
| 330 | OFPBIC_UNSUP_EXP_INST = 5, |
| 331 | }; |
| 332 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 333 | enum ofp_bad_match_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 334 | OFPBMC_BAD_TYPE = 0, |
| 335 | OFPBMC_BAD_LEN = 1, |
| 336 | OFPBMC_BAD_TAG = 2, |
| 337 | OFPBMC_BAD_DL_ADDR_MASK = 3, |
| 338 | OFPBMC_BAD_NW_ADDR_MASK = 4, |
| 339 | OFPBMC_BAD_WILDCARDS = 5, |
| 340 | OFPBMC_BAD_FIELD = 6, |
| 341 | OFPBMC_BAD_VALUE = 7, |
| 342 | }; |
| 343 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 344 | enum ofp_flow_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 345 | OFPFMFC_UNKNOWN = 0, |
| 346 | OFPFMFC_TABLE_FULL = 1, |
| 347 | OFPFMFC_BAD_TABLE_ID = 2, |
| 348 | OFPFMFC_OVERLAP = 3, |
| 349 | OFPFMFC_EPERM = 4, |
| 350 | OFPFMFC_BAD_TIMEOUT = 5, |
| 351 | OFPFMFC_BAD_COMMAND = 6, |
| 352 | }; |
| 353 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 354 | enum ofp_group_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 355 | OFPGMFC_GROUP_EXISTS = 0, |
| 356 | OFPGMFC_INVALID_GROUP = 1, |
| 357 | OFPGMFC_WEIGHT_UNSUPPORTED = 2, |
| 358 | OFPGMFC_OUT_OF_GROUPS = 3, |
| 359 | OFPGMFC_OUT_OF_BUCKETS = 4, |
| 360 | OFPGMFC_CHAINING_UNSUPPORTED = 5, |
| 361 | OFPGMFC_WATCH_UNSUPPORTED = 6, |
| 362 | OFPGMFC_LOOP = 7, |
| 363 | OFPGMFC_UNKNOWN_GROUP = 8, |
| 364 | }; |
| 365 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 366 | enum ofp_port_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 367 | OFPPMFC_BAD_PORT = 0, |
| 368 | OFPPMFC_BAD_HW_ADDR = 1, |
| 369 | OFPPMFC_BAD_CONFIG = 2, |
| 370 | OFPPMFC_BAD_ADVERTISE = 3, |
| 371 | }; |
| 372 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 373 | enum ofp_table_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 374 | OFPTMFC_BAD_TABLE = 0, |
| 375 | OFPTMFC_BAD_CONFIG = 1, |
| 376 | }; |
| 377 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 378 | enum ofp_queue_op_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 379 | OFPQOFC_BAD_PORT = 0, |
| 380 | OFPQOFC_BAD_QUEUE = 1, |
| 381 | OFPQOFC_EPERM = 2, |
| 382 | }; |
| 383 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 384 | enum ofp_switch_config_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 385 | OFPSCFC_BAD_FLAGS = 0, |
| 386 | OFPSCFC_BAD_LEN = 1, |
| 387 | }; |
| 388 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 389 | enum ofp_stats_types(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 390 | OFPST_DESC = 0, |
| 391 | OFPST_FLOW = 1, |
| 392 | OFPST_AGGREGATE = 2, |
| 393 | OFPST_TABLE = 3, |
| 394 | OFPST_PORT = 4, |
| 395 | OFPST_QUEUE = 5, |
| 396 | OFPST_GROUP = 6, |
| 397 | OFPST_GROUP_DESC = 7, |
| 398 | OFPST_EXPERIMENTER = 0xffff, |
| 399 | }; |
| 400 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 401 | enum ofp_stats_reply_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 402 | OFPSF_REPLY_MORE = 0x1, |
| 403 | }; |
| 404 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 405 | enum ofp_queue_properties(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 406 | OFPQT_NONE = 0, |
| 407 | OFPQT_MIN_RATE = 1, |
| 408 | }; |
| 409 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 410 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 411 | uint8_t version; |
| 412 | uint8_t type; |
| 413 | uint16_t length; |
| 414 | uint32_t xid; |
| 415 | }; |
| 416 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 417 | struct of_hello { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 418 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 419 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 420 | uint16_t length; |
| 421 | uint32_t xid; |
| 422 | }; |
| 423 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 424 | struct of_echo_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 425 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 426 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 427 | uint16_t length; |
| 428 | uint32_t xid; |
| 429 | of_octets_t data; |
| 430 | }; |
| 431 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 432 | struct of_echo_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 433 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 434 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 435 | uint16_t length; |
| 436 | uint32_t xid; |
| 437 | of_octets_t data; |
| 438 | }; |
| 439 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 440 | struct of_experimenter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 441 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 442 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 443 | uint16_t length; |
| 444 | uint32_t xid; |
| 445 | uint32_t experimenter; |
| 446 | uint32_t subtype; |
| 447 | of_octets_t data; |
| 448 | }; |
| 449 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 450 | struct of_barrier_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 451 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 452 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 453 | uint16_t length; |
| 454 | uint32_t xid; |
| 455 | }; |
| 456 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 457 | struct of_barrier_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 458 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 459 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 460 | uint16_t length; |
| 461 | uint32_t xid; |
| 462 | }; |
| 463 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 464 | struct of_get_config_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 465 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 466 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 467 | uint16_t length; |
| 468 | uint32_t xid; |
| 469 | }; |
| 470 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 471 | struct of_get_config_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 472 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 473 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 474 | uint16_t length; |
| 475 | uint32_t xid; |
| 476 | uint16_t flags; |
| 477 | uint16_t miss_send_len; |
| 478 | }; |
| 479 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 480 | struct of_set_config { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 481 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 482 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 483 | uint16_t length; |
| 484 | uint32_t xid; |
| 485 | uint16_t flags; |
| 486 | uint16_t miss_send_len; |
| 487 | }; |
| 488 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 489 | struct of_table_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 490 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 491 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 492 | uint16_t length; |
| 493 | uint32_t xid; |
| 494 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 495 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 496 | uint32_t config; |
| 497 | }; |
| 498 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 499 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 500 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 501 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 502 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 503 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 504 | of_port_name_t name; |
| 505 | uint32_t config; |
| 506 | uint32_t state; |
| 507 | uint32_t curr; |
| 508 | uint32_t advertised; |
| 509 | uint32_t supported; |
| 510 | uint32_t peer; |
| 511 | uint32_t curr_speed; |
| 512 | uint32_t max_speed; |
| 513 | }; |
| 514 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 515 | struct of_features_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 516 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 517 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 518 | uint16_t length; |
| 519 | uint32_t xid; |
| 520 | }; |
| 521 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 522 | struct of_features_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 523 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 524 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 525 | uint16_t length; |
| 526 | uint32_t xid; |
| 527 | uint64_t datapath_id; |
| 528 | uint32_t n_buffers; |
| 529 | uint8_t n_tables; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 530 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 531 | uint32_t capabilities; |
| 532 | uint32_t reserved; |
| 533 | list(of_port_desc_t) ports; |
| 534 | }; |
| 535 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 536 | struct of_port_status { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 537 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 538 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 539 | uint16_t length; |
| 540 | uint32_t xid; |
| 541 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 542 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 543 | of_port_desc_t desc; |
| 544 | }; |
| 545 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 546 | struct of_port_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 547 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 548 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 549 | uint16_t length; |
| 550 | uint32_t xid; |
| 551 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 552 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 553 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 554 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 555 | uint32_t config; |
| 556 | uint32_t mask; |
| 557 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 558 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 559 | }; |
| 560 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 561 | struct of_packet_in { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 562 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 563 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 564 | uint16_t length; |
| 565 | uint32_t xid; |
| 566 | uint32_t buffer_id; |
| 567 | of_port_no_t in_port; |
| 568 | of_port_no_t in_phy_port; |
| 569 | uint16_t total_len; |
| 570 | uint8_t reason; |
| 571 | uint8_t table_id; |
| 572 | of_octets_t data; |
| 573 | }; |
| 574 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 575 | struct of_action_output { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 576 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 577 | uint16_t len; |
| 578 | of_port_no_t port; |
| 579 | uint16_t max_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 580 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 581 | }; |
| 582 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 583 | struct of_action_set_vlan_vid { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 584 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 585 | uint16_t len; |
| 586 | uint16_t vlan_vid; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 587 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 588 | }; |
| 589 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 590 | struct of_action_set_vlan_pcp { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 591 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 592 | uint16_t len; |
| 593 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 594 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 595 | }; |
| 596 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 597 | struct of_action_set_dl_src { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 598 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 599 | uint16_t len; |
| 600 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 601 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 602 | }; |
| 603 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 604 | struct of_action_set_dl_dst { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 605 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 606 | uint16_t len; |
| 607 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 608 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 609 | }; |
| 610 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 611 | struct of_action_set_nw_src { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 612 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 613 | uint16_t len; |
| 614 | uint32_t nw_addr; |
| 615 | }; |
| 616 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 617 | struct of_action_set_nw_dst { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 618 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 619 | uint16_t len; |
| 620 | uint32_t nw_addr; |
| 621 | }; |
| 622 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 623 | struct of_action_set_nw_tos { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 624 | uint16_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 625 | uint16_t len; |
| 626 | uint8_t nw_tos; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 627 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 628 | }; |
| 629 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 630 | struct of_action_set_nw_ecn { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 631 | uint16_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 632 | uint16_t len; |
| 633 | uint8_t nw_ecn; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 634 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 635 | }; |
| 636 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 637 | struct of_action_set_tp_src { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 638 | uint16_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 639 | uint16_t len; |
| 640 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 641 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 642 | }; |
| 643 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 644 | struct of_action_set_tp_dst { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 645 | uint16_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 646 | uint16_t len; |
| 647 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 648 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 649 | }; |
| 650 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 651 | struct of_action_copy_ttl_out { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 652 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 653 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 654 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 655 | }; |
| 656 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 657 | struct of_action_copy_ttl_in { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 658 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 659 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 660 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 661 | }; |
| 662 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 663 | struct of_action_set_mpls_label { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 664 | uint16_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 665 | uint16_t len; |
| 666 | uint32_t mpls_label; |
| 667 | }; |
| 668 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 669 | struct of_action_set_mpls_tc { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 670 | uint16_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 671 | uint16_t len; |
| 672 | uint8_t mpls_tc; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 673 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 674 | }; |
| 675 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 676 | struct of_action_set_mpls_ttl { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 677 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 678 | uint16_t len; |
| 679 | uint8_t mpls_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 680 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 681 | }; |
| 682 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 683 | struct of_action_dec_mpls_ttl { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 684 | uint16_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 685 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 686 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 687 | }; |
| 688 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 689 | struct of_action_push_vlan { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 690 | uint16_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 691 | uint16_t len; |
| 692 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 693 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 694 | }; |
| 695 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 696 | struct of_action_pop_vlan { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 697 | uint16_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 698 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 699 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 700 | }; |
| 701 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 702 | struct of_action_push_mpls { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 703 | uint16_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 704 | uint16_t len; |
| 705 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 706 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 707 | }; |
| 708 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 709 | struct of_action_pop_mpls { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 710 | uint16_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 711 | uint16_t len; |
| 712 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 713 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 714 | }; |
| 715 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 716 | struct of_action_set_queue { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 717 | uint16_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 718 | uint16_t len; |
| 719 | uint32_t queue_id; |
| 720 | }; |
| 721 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 722 | struct of_action_group { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 723 | uint16_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 724 | uint16_t len; |
| 725 | uint32_t group_id; |
| 726 | }; |
| 727 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 728 | struct of_action_set_nw_ttl { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 729 | uint16_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 730 | uint16_t len; |
| 731 | uint8_t nw_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 732 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 733 | }; |
| 734 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 735 | struct of_action_dec_nw_ttl { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 736 | uint16_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 737 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 738 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 739 | }; |
| 740 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 741 | struct of_action_experimenter { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 742 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 743 | uint16_t len; |
| 744 | uint32_t experimenter; |
| 745 | of_octets_t data; |
| 746 | }; |
| 747 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 748 | struct of_action { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 749 | uint16_t type; |
| 750 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 751 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 752 | }; |
| 753 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 754 | struct of_packet_out { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 755 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 756 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 757 | uint16_t length; |
| 758 | uint32_t xid; |
| 759 | uint32_t buffer_id; |
| 760 | of_port_no_t in_port; |
| 761 | uint16_t actions_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 762 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 763 | list(of_action_t) actions; |
| 764 | of_octets_t data; |
| 765 | }; |
| 766 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 767 | struct of_match_v2 { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 768 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 769 | uint16_t length; |
| 770 | of_port_no_t in_port; |
| 771 | of_wc_bmap_t wildcards; |
| 772 | of_mac_addr_t eth_src; |
| 773 | of_mac_addr_t eth_src_mask; |
| 774 | of_mac_addr_t eth_dst; |
| 775 | of_mac_addr_t eth_dst_mask; |
| 776 | uint16_t vlan_vid; |
| 777 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 778 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 779 | uint16_t eth_type; |
| 780 | uint8_t ip_dscp; |
| 781 | uint8_t ip_proto; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 782 | of_ipv4_t ipv4_src; |
| 783 | of_ipv4_t ipv4_src_mask; |
| 784 | of_ipv4_t ipv4_dst; |
| 785 | of_ipv4_t ipv4_dst_mask; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 786 | uint16_t tcp_src; |
| 787 | uint16_t tcp_dst; |
| 788 | uint32_t mpls_label; |
| 789 | uint8_t mpls_tc; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 790 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 791 | uint64_t metadata; |
| 792 | uint64_t metadata_mask; |
| 793 | }; |
| 794 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 795 | struct of_instruction { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 796 | uint16_t type; |
| 797 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 798 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 799 | }; |
| 800 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 801 | struct of_instruction_goto_table { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 802 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 803 | uint16_t len; |
| 804 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 805 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 806 | }; |
| 807 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 808 | struct of_instruction_write_metadata { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 809 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 810 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 811 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 812 | uint64_t metadata; |
| 813 | uint64_t metadata_mask; |
| 814 | }; |
| 815 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 816 | struct of_instruction_write_actions { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 817 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 818 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 819 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 820 | list(of_action_t) actions; |
| 821 | }; |
| 822 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 823 | struct of_instruction_apply_actions { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 824 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 825 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 826 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 827 | list(of_action_t) actions; |
| 828 | }; |
| 829 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 830 | struct of_instruction_clear_actions { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 831 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 832 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 833 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 834 | }; |
| 835 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 836 | struct of_instruction_experimenter { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 837 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 838 | uint16_t len; |
| 839 | uint32_t experimenter; |
| 840 | of_octets_t data; |
| 841 | }; |
| 842 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 843 | struct of_flow_add { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 844 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 845 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 846 | uint16_t length; |
| 847 | uint32_t xid; |
| 848 | uint64_t cookie; |
| 849 | uint64_t cookie_mask; |
| 850 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 851 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 852 | uint16_t idle_timeout; |
| 853 | uint16_t hard_timeout; |
| 854 | uint16_t priority; |
| 855 | uint32_t buffer_id; |
| 856 | of_port_no_t out_port; |
| 857 | uint32_t out_group; |
| 858 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 859 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 860 | of_match_t match; |
| 861 | list(of_instruction_t) instructions; |
| 862 | }; |
| 863 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 864 | struct of_flow_modify { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 865 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 866 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 867 | uint16_t length; |
| 868 | uint32_t xid; |
| 869 | uint64_t cookie; |
| 870 | uint64_t cookie_mask; |
| 871 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 872 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 873 | uint16_t idle_timeout; |
| 874 | uint16_t hard_timeout; |
| 875 | uint16_t priority; |
| 876 | uint32_t buffer_id; |
| 877 | of_port_no_t out_port; |
| 878 | uint32_t out_group; |
| 879 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 880 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 881 | of_match_t match; |
| 882 | list(of_instruction_t) instructions; |
| 883 | }; |
| 884 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 885 | struct of_flow_modify_strict { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 886 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 887 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 888 | uint16_t length; |
| 889 | uint32_t xid; |
| 890 | uint64_t cookie; |
| 891 | uint64_t cookie_mask; |
| 892 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 893 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 894 | uint16_t idle_timeout; |
| 895 | uint16_t hard_timeout; |
| 896 | uint16_t priority; |
| 897 | uint32_t buffer_id; |
| 898 | of_port_no_t out_port; |
| 899 | uint32_t out_group; |
| 900 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 901 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 902 | of_match_t match; |
| 903 | list(of_instruction_t) instructions; |
| 904 | }; |
| 905 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 906 | struct of_flow_delete { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 907 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 908 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 909 | uint16_t length; |
| 910 | uint32_t xid; |
| 911 | uint64_t cookie; |
| 912 | uint64_t cookie_mask; |
| 913 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 914 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 915 | uint16_t idle_timeout; |
| 916 | uint16_t hard_timeout; |
| 917 | uint16_t priority; |
| 918 | uint32_t buffer_id; |
| 919 | of_port_no_t out_port; |
| 920 | uint32_t out_group; |
| 921 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 922 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 923 | of_match_t match; |
| 924 | list(of_instruction_t) instructions; |
| 925 | }; |
| 926 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 927 | struct of_flow_delete_strict { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 928 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 929 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 930 | uint16_t length; |
| 931 | uint32_t xid; |
| 932 | uint64_t cookie; |
| 933 | uint64_t cookie_mask; |
| 934 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 935 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 936 | uint16_t idle_timeout; |
| 937 | uint16_t hard_timeout; |
| 938 | uint16_t priority; |
| 939 | uint32_t buffer_id; |
| 940 | of_port_no_t out_port; |
| 941 | uint32_t out_group; |
| 942 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 943 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 944 | of_match_t match; |
| 945 | list(of_instruction_t) instructions; |
| 946 | }; |
| 947 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 948 | struct of_bucket { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 949 | uint16_t len; |
| 950 | uint16_t weight; |
| 951 | of_port_no_t watch_port; |
| 952 | uint32_t watch_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 953 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 954 | list(of_action_t) actions; |
| 955 | }; |
| 956 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 957 | struct of_group_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 958 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 959 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 960 | uint16_t length; |
| 961 | uint32_t xid; |
| 962 | uint16_t command; |
| 963 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 964 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 965 | uint32_t group_id; |
| 966 | list(of_bucket_t) buckets; |
| 967 | }; |
| 968 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 969 | struct of_flow_removed { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 970 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 971 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 972 | uint16_t length; |
| 973 | uint32_t xid; |
| 974 | uint64_t cookie; |
| 975 | uint16_t priority; |
| 976 | uint8_t reason; |
| 977 | uint8_t table_id; |
| 978 | uint32_t duration_sec; |
| 979 | uint32_t duration_nsec; |
| 980 | uint16_t idle_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 981 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 982 | uint64_t packet_count; |
| 983 | uint64_t byte_count; |
| 984 | of_match_t match; |
| 985 | }; |
| 986 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 987 | struct of_error_msg { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 988 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 989 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 990 | uint16_t length; |
| 991 | uint32_t xid; |
| 992 | uint16_t err_type; |
| 993 | uint16_t code; |
| 994 | of_octets_t data; |
| 995 | }; |
| 996 | |
| 997 | // STATS ENTRIES: flow, table, port, group, group_desc |
| 998 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 999 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1000 | uint16_t length; |
| 1001 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1002 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1003 | uint32_t duration_sec; |
| 1004 | uint32_t duration_nsec; |
| 1005 | uint16_t priority; |
| 1006 | uint16_t idle_timeout; |
| 1007 | uint16_t hard_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1008 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1009 | uint64_t cookie; |
| 1010 | uint64_t packet_count; |
| 1011 | uint64_t byte_count; |
| 1012 | of_match_t match; |
| 1013 | list(of_instruction_t) instructions; |
| 1014 | }; |
| 1015 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1016 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1017 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1018 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1019 | of_table_name_t name; |
| 1020 | of_wc_bmap_t wildcards; |
| 1021 | of_match_bmap_t match; |
| 1022 | uint32_t instructions; |
| 1023 | uint32_t write_actions; |
| 1024 | uint32_t apply_actions; |
| 1025 | uint32_t config; |
| 1026 | uint32_t max_entries; |
| 1027 | uint32_t active_count; |
| 1028 | uint64_t lookup_count; |
| 1029 | uint64_t matched_count; |
| 1030 | }; |
| 1031 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1032 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1033 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1034 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1035 | uint64_t rx_packets; |
| 1036 | uint64_t tx_packets; |
| 1037 | uint64_t rx_bytes; |
| 1038 | uint64_t tx_bytes; |
| 1039 | uint64_t rx_dropped; |
| 1040 | uint64_t tx_dropped; |
| 1041 | uint64_t rx_errors; |
| 1042 | uint64_t tx_errors; |
| 1043 | uint64_t rx_frame_err; |
| 1044 | uint64_t rx_over_err; |
| 1045 | uint64_t rx_crc_err; |
| 1046 | uint64_t collisions; |
| 1047 | }; |
| 1048 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1049 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1050 | of_port_no_t port_no; |
| 1051 | uint32_t queue_id; |
| 1052 | uint64_t tx_bytes; |
| 1053 | uint64_t tx_packets; |
| 1054 | uint64_t tx_errors; |
| 1055 | }; |
| 1056 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1057 | struct of_bucket_counter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1058 | uint64_t packet_count; |
| 1059 | uint64_t byte_count; |
| 1060 | }; |
| 1061 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1062 | struct of_group_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1063 | uint16_t length; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1064 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1065 | uint32_t group_id; |
| 1066 | uint32_t ref_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1067 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1068 | uint64_t packet_count; |
| 1069 | uint64_t byte_count; |
| 1070 | list(of_bucket_counter_t) bucket_stats; |
| 1071 | }; |
| 1072 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1073 | struct of_group_desc_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1074 | uint16_t length; |
| 1075 | uint8_t type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1076 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1077 | uint32_t group_id; |
| 1078 | list(of_bucket_t) buckets; |
| 1079 | }; |
| 1080 | |
| 1081 | // STATS: Desc, flow, agg, table, port, queue, group, group_desc, experi |
| 1082 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1083 | struct of_desc_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1084 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1085 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1086 | uint16_t length; |
| 1087 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1088 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1089 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1090 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1091 | }; |
| 1092 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1093 | struct of_desc_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1094 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1095 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1096 | uint16_t length; |
| 1097 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1098 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1099 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1100 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1101 | of_desc_str_t mfr_desc; |
| 1102 | of_desc_str_t hw_desc; |
| 1103 | of_desc_str_t sw_desc; |
| 1104 | of_serial_num_t serial_num; |
| 1105 | of_desc_str_t dp_desc; |
| 1106 | }; |
| 1107 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1108 | struct of_flow_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1109 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1110 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1111 | uint16_t length; |
| 1112 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1113 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1114 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1115 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1116 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1117 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1118 | of_port_no_t out_port; |
| 1119 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1120 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1121 | uint64_t cookie; |
| 1122 | uint64_t cookie_mask; |
| 1123 | of_match_t match; |
| 1124 | }; |
| 1125 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1126 | struct of_flow_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1127 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1128 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1129 | uint16_t length; |
| 1130 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1131 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1132 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1133 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1134 | list(of_flow_stats_entry_t) entries; |
| 1135 | }; |
| 1136 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1137 | struct of_aggregate_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1138 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1139 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1140 | uint16_t length; |
| 1141 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1142 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1143 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1144 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1145 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1146 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1147 | of_port_no_t out_port; |
| 1148 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1149 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1150 | uint64_t cookie; |
| 1151 | uint64_t cookie_mask; |
| 1152 | of_match_t match; |
| 1153 | }; |
| 1154 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1155 | struct of_aggregate_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1156 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1157 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1158 | uint16_t length; |
| 1159 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1160 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1161 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1162 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1163 | uint64_t packet_count; |
| 1164 | uint64_t byte_count; |
| 1165 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1166 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1167 | }; |
| 1168 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1169 | struct of_table_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1170 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1171 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1172 | uint16_t length; |
| 1173 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1174 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1175 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1176 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1177 | }; |
| 1178 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1179 | struct of_table_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1180 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1181 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1182 | uint16_t length; |
| 1183 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1184 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1185 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1186 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1187 | list(of_table_stats_entry_t) entries; |
| 1188 | }; |
| 1189 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1190 | struct of_port_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1191 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1192 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1193 | uint16_t length; |
| 1194 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1195 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1196 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1197 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1198 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1199 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1200 | }; |
| 1201 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1202 | struct of_port_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1203 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1204 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1205 | uint16_t length; |
| 1206 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1207 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1208 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1209 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1210 | list(of_port_stats_entry_t) entries; |
| 1211 | }; |
| 1212 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1213 | struct of_queue_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1214 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1215 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1216 | uint16_t length; |
| 1217 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1218 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1219 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1220 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1221 | of_port_no_t port_no; |
| 1222 | uint32_t queue_id; |
| 1223 | }; |
| 1224 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1225 | struct of_queue_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1226 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1227 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1228 | uint16_t length; |
| 1229 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1230 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1231 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1232 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1233 | list(of_queue_stats_entry_t) entries; |
| 1234 | }; |
| 1235 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1236 | struct of_group_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1237 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1238 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1239 | uint16_t length; |
| 1240 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1241 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1242 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1243 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1244 | uint32_t group_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1245 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1246 | }; |
| 1247 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1248 | struct of_group_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1249 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1250 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1251 | uint16_t length; |
| 1252 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1253 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1254 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1255 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1256 | list(of_group_stats_entry_t) entries; |
| 1257 | }; |
| 1258 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1259 | struct of_group_desc_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1260 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1261 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1262 | uint16_t length; |
| 1263 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1264 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1265 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1266 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1267 | }; |
| 1268 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1269 | struct of_group_desc_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1270 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1271 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1272 | uint16_t length; |
| 1273 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1274 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1275 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1276 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1277 | list(of_group_desc_stats_entry_t) entries; |
| 1278 | }; |
| 1279 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1280 | struct of_experimenter_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1281 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1282 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1283 | uint16_t length; |
| 1284 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1285 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1286 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1287 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1288 | uint32_t experimenter; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1289 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1290 | of_octets_t data; |
| 1291 | }; |
| 1292 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1293 | struct of_experimenter_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1294 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1295 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1296 | uint16_t length; |
| 1297 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1298 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1299 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1300 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1301 | uint32_t experimenter; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1302 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1303 | of_octets_t data; |
| 1304 | }; |
| 1305 | |
| 1306 | // END OF STATS OBJECTS |
| 1307 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1308 | struct of_queue_prop { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1309 | uint16_t type; |
| 1310 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1311 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1312 | }; |
| 1313 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1314 | struct of_queue_prop_min_rate { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1315 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1316 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1317 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1318 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1319 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1320 | }; |
| 1321 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1322 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1323 | uint32_t queue_id; |
| 1324 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1325 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1326 | list(of_queue_prop_t) properties; |
| 1327 | }; |
| 1328 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1329 | struct of_queue_get_config_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1330 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1331 | uint8_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1332 | uint16_t length; |
| 1333 | uint32_t xid; |
| 1334 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1335 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1336 | }; |
| 1337 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1338 | struct of_queue_get_config_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1339 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1340 | uint8_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1341 | uint16_t length; |
| 1342 | uint32_t xid; |
| 1343 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1344 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1345 | list(of_packet_queue_t) queues; |
| 1346 | }; |