blob: 36e6279d8c253676346075d453b0006d2eccb6a7 [file] [log] [blame]
Yi Tseng21629932017-06-06 11:17:43 -07001#include <core.p4>
2#include <v1model.p4>
3#include "include/defines.p4"
4#include "include/headers.p4"
5#include "include/parsers.p4"
6#include "include/port_counters.p4"
7#include "include/checksums.p4"
8#include "include/actions.p4"
9
10control ingress(inout headers hdr, inout metadata meta, inout standard_metadata_t standard_metadata) {
11 direct_counter(CounterType.packets) table0_counter;
12
13 table table0 {
14 support_timeout = true;
15 actions = {
16 set_egress_port(standard_metadata);
17 send_to_cpu(standard_metadata);
18 drop(standard_metadata);
19 }
20 key = {
21 standard_metadata.ingress_port: ternary;
22 hdr.ethernet.dstAddr : ternary;
23 hdr.ethernet.srcAddr : ternary;
24 hdr.ethernet.etherType : ternary;
25 }
26 counters = table0_counter;
27 }
28 PortCountersControl() port_counters_control;
29 apply {
30 table0.apply();
31 port_counters_control.apply(hdr, meta, standard_metadata);
32 }
33
34}
35
36control egress(inout headers hdr, inout metadata meta, inout standard_metadata_t standard_metadata) {
37 apply {
38 // Nothing to do
39 }
40}
41
Andrea Campanellafc1d34c2017-07-18 17:01:41 +020042@controller_header("packet_in")
43header packet_in_header_t {
44 bit<9> ingress_port;
45 bit<32> other1;
46}
47
48@controller_header("packet_out")
49header packet_out_header_t {
50 bit<9> egress_port;
51 bit<32> other2;
52}
53
Yi Tseng21629932017-06-06 11:17:43 -070054V1Switch(ParserImpl(), verifyChecksum(), ingress(), egress(), computeChecksum(), DeparserImpl()) main;