Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1 | +---------------------------------------------------------------------+ |
| 2 | | Log file: mau.gw.log | |
| 3 | | Compiler version: 5.1.0 (fca32d1) | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 4 | | Created on: Fri Sep 8 08:24:30 2017 | |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 5 | +---------------------------------------------------------------------+ |
| 6 | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 7 | cond _condition_0: not valid packet_out_hdr |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 8 | not valid packet_out_hdr |
| 9 | ! not not valid packet_out_hdr |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 10 | cond _condition_0 can be gateway (1+0)x1 |
| 11 | cond !_condition_0 can be gateway (1+0)x1 |
| 12 | _condition_0 is gateway for table0 |
| 13 | cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 510 |
| 14 | ig_intr_md_for_tm.ucast_egress_port < 510 |
| 15 | ! ig_intr_md_for_tm.ucast_egress_port >= 510 |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 16 | cond _condition_2 can be gateway (9+0)x1 |
| 17 | cond !_condition_2 can be gateway (9+0)x1 |
| 18 | _condition_2 is gateway for ingress_port_count_table |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 19 | fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f555fea6d90>]) and and xor_fields is OrderedSet() |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 20 | fields = OrderedSet() and and xor_fields is OrderedSet() |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 21 | cond _condition_0: not valid packet_out_hdr |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 22 | not valid packet_out_hdr |
| 23 | ! not not valid packet_out_hdr |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 24 | cond _condition_0 can be gateway (1+0)x1 |
| 25 | cond !_condition_0 can be gateway (1+0)x1 |
| 26 | _condition_0 is gateway for table0 |
| 27 | cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 510 |
| 28 | ig_intr_md_for_tm.ucast_egress_port < 510 |
| 29 | ! ig_intr_md_for_tm.ucast_egress_port >= 510 |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 30 | cond _condition_2 can be gateway (9+0)x1 |
| 31 | cond !_condition_2 can be gateway (9+0)x1 |
| 32 | _condition_2 is gateway for ingress_port_count_table |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 33 | fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f555fea6d90>]) and and xor_fields is OrderedSet() |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 34 | fields = OrderedSet() and and xor_fields is OrderedSet() |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 35 | cond _condition_0: not valid packet_out_hdr |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 36 | not valid packet_out_hdr |
| 37 | ! not not valid packet_out_hdr |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 38 | cond _condition_0 can be gateway (1+0)x1 |
| 39 | cond !_condition_0 can be gateway (1+0)x1 |
| 40 | _condition_0 is gateway for table0 |
| 41 | cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 510 |
| 42 | ig_intr_md_for_tm.ucast_egress_port < 510 |
| 43 | ! ig_intr_md_for_tm.ucast_egress_port >= 510 |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 44 | cond _condition_2 can be gateway (9+0)x1 |
| 45 | cond !_condition_2 can be gateway (9+0)x1 |
| 46 | _condition_2 is gateway for ingress_port_count_table |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 47 | fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f555fea6d90>]) and and xor_fields is OrderedSet() |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 48 | fields = OrderedSet() and and xor_fields is OrderedSet() |
| 49 | cond _always_true: True == True |
| 50 | True |
| 51 | ! False |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 52 | cond _always_true: True == True |
| 53 | True |
| 54 | ! False |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 55 | --> Stage Gateway Table for condition _condition_0 in stage 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 56 | T -> table0(0), F -> process_packet_out_table(1) |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 57 | building tcam for GatewayTest('not valid packet_out_hdr') |
| 58 | adding line (match=0 mask=100000000 T) |
| 59 | tcam data: [(match=0 mask=100000000 T)] |
| 60 | final.tcam: [(match=0 mask=100000000 T)], miss=False |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 61 | --> Stage Gateway Table for condition process_packet_out_table_always_true_condition in stage 0 |
| 62 | T -> process_packet_out_table(1), F -> process_packet_out_table(1) |
| 63 | building tcam for GatewayTest('True') |
| 64 | adding line (match=0 mask=0 T) |
| 65 | tcam data: [(match=0 mask=0 T)] |
| 66 | final.tcam: [(match=0 mask=0 T)], miss=False |
| 67 | --> Stage Gateway Table for condition _condition_2 in stage 1 |
| 68 | T -> ingress_port_count_table(16), F -> None(255) |
| 69 | building tcam for GatewayTest('ig_intr_md_for_tm.ucast_egress_port < 510') |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 70 | adding line (range=[ffff ffff 3fff] match=0 mask=0 T) |
| 71 | adding line (range=[ffff 7fff ffff] match=0 mask=0 T) |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 72 | adding line (range=[1 ffff ffff] match=0 mask=0 T) |
| 73 | tcam data: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[1 ffff ffff] match=0 mask=0 T)] |
| 74 | final.tcam: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[1 ffff ffff] match=0 mask=0 T)], miss=False |
| 75 | --> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 1 |
| 76 | T -> egress_port_count_table(17), F -> egress_port_count_table(17) |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 77 | building tcam for GatewayTest('True') |
| 78 | adding line (match=0 mask=0 T) |
| 79 | tcam data: [(match=0 mask=0 T)] |
| 80 | final.tcam: [(match=0 mask=0 T)], miss=False |