| Daniele Moro | f178b0a | 2020-12-15 14:13:51 +0100 | [diff] [blame] | 1 | pkg_info { |
| 2 | arch: "v1model" |
| 3 | } |
| 4 | tables { |
| 5 | preamble { |
| 6 | id: 36960149 |
| 7 | name: "table0" |
| 8 | alias: "table0" |
| 9 | } |
| 10 | match_fields { |
| 11 | id: 1 |
| 12 | name: "local_metadata.ingress_port" |
| 13 | bitwidth: 32 |
| 14 | match_type: EXACT |
| 15 | type_name { |
| 16 | name: "port_id_bit_t" |
| 17 | } |
| 18 | } |
| 19 | match_fields { |
| 20 | id: 2 |
| 21 | name: "hdr.ethernet.srcAddr" |
| 22 | match_type: EXACT |
| 23 | type_name { |
| 24 | name: "mac_addr_t" |
| 25 | } |
| 26 | } |
| 27 | match_fields { |
| 28 | id: 3 |
| 29 | name: "hdr.ethernet.dstAddr" |
| 30 | match_type: EXACT |
| 31 | type_name { |
| 32 | name: "mac_addr_t" |
| 33 | } |
| 34 | } |
| 35 | match_fields { |
| 36 | id: 4 |
| 37 | name: "hdr.ethernet.etherType" |
| 38 | bitwidth: 16 |
| Daniele Moro | c6f2f7f | 2020-12-18 10:55:57 +0100 | [diff] [blame^] | 39 | match_type: OPTIONAL |
| Daniele Moro | f178b0a | 2020-12-15 14:13:51 +0100 | [diff] [blame] | 40 | } |
| 41 | action_refs { |
| 42 | id: 27607748 |
| 43 | } |
| 44 | action_refs { |
| 45 | id: 32872817 |
| 46 | } |
| 47 | action_refs { |
| 48 | id: 24562328 |
| 49 | } |
| 50 | action_refs { |
| 51 | id: 18759588 |
| 52 | } |
| 53 | const_default_action_id: 18759588 |
| 54 | size: 1024 |
| 55 | } |
| 56 | actions { |
| 57 | preamble { |
| 58 | id: 24562328 |
| 59 | name: "send_to_cpu" |
| 60 | alias: "send_to_cpu" |
| 61 | } |
| 62 | } |
| 63 | actions { |
| 64 | preamble { |
| 65 | id: 27607748 |
| 66 | name: "set_egress_port" |
| 67 | alias: "set_egress_port" |
| 68 | } |
| 69 | params { |
| 70 | id: 1 |
| 71 | name: "port" |
| 72 | type_name { |
| 73 | name: "port_id_str_t" |
| 74 | } |
| 75 | } |
| 76 | } |
| 77 | actions { |
| 78 | preamble { |
| 79 | id: 32872817 |
| 80 | name: "set_egress_port2" |
| 81 | alias: "set_egress_port2" |
| 82 | } |
| 83 | params { |
| 84 | id: 1 |
| 85 | name: "port" |
| 86 | bitwidth: 32 |
| 87 | type_name { |
| 88 | name: "port_id_bit_t" |
| 89 | } |
| 90 | } |
| 91 | } |
| 92 | actions { |
| 93 | preamble { |
| 94 | id: 18759588 |
| 95 | name: "drop" |
| 96 | alias: "drop" |
| 97 | } |
| 98 | } |
| 99 | controller_packet_metadata { |
| 100 | preamble { |
| 101 | id: 81826293 |
| 102 | name: "packet_in" |
| 103 | alias: "packet_in" |
| 104 | annotations: "@controller_header(\"packet_in\")" |
| 105 | } |
| 106 | metadata { |
| 107 | id: 1 |
| 108 | name: "ingress_port" |
| 109 | bitwidth: 9 |
| 110 | } |
| 111 | metadata { |
| 112 | id: 2 |
| 113 | name: "_padding" |
| 114 | bitwidth: 7 |
| 115 | } |
| 116 | } |
| 117 | controller_packet_metadata { |
| 118 | preamble { |
| 119 | id: 76689799 |
| 120 | name: "packet_out" |
| 121 | alias: "packet_out" |
| 122 | annotations: "@controller_header(\"packet_out\")" |
| 123 | } |
| 124 | metadata { |
| 125 | id: 1 |
| 126 | name: "egress_port" |
| 127 | bitwidth: 9 |
| 128 | } |
| 129 | metadata { |
| 130 | id: 2 |
| 131 | name: "_padding" |
| 132 | bitwidth: 7 |
| 133 | } |
| 134 | } |
| 135 | type_info { |
| 136 | new_types { |
| 137 | key: "mac_addr_t" |
| 138 | value { |
| 139 | translated_type { |
| 140 | sdn_string { |
| 141 | } |
| 142 | } |
| 143 | } |
| 144 | } |
| 145 | new_types { |
| 146 | key: "port_id_bit_t" |
| 147 | value { |
| 148 | translated_type { |
| 149 | sdn_bitwidth: 32 |
| 150 | } |
| 151 | } |
| 152 | } |
| 153 | new_types { |
| 154 | key: "port_id_str_t" |
| 155 | value { |
| 156 | translated_type { |
| 157 | sdn_string { |
| 158 | } |
| 159 | } |
| 160 | } |
| 161 | } |
| 162 | } |