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Carmelo Cascone79a3a312018-08-16 17:14:43 -07001/*
2 * Copyright 2017-present Open Networking Foundation
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17/* -*- P4_16 -*- */
18#ifndef __INT_TRANSIT__
19#define __INT_TRANSIT__
20control process_int_transit (
21 inout parsed_headers_t hdr,
22 inout fabric_metadata_t fmeta,
23 inout standard_metadata_t smeta) {
24
25 action init_metadata(bit<32> switch_id) {
26 fmeta.int_meta.transit = _TRUE;
27#ifdef _INT_INIT_METADATA
28 // Allow other targets to initialize INT metadata in their own way.
29 _INT_INIT_METADATA
30#else
31 fmeta.int_meta.switch_id = switch_id;
32#endif // _INT_INIT_METADATA
33 }
34
35#ifdef _INT_METADATA_ACTIONS
36 _INT_METADATA_ACTIONS
37#else
38 // Switch ID.
39 action int_set_header_0() {
40 hdr.int_switch_id.setValid();
41 hdr.int_switch_id.switch_id = fmeta.int_meta.switch_id;
42 }
43 // Port IDs.
44 action int_set_header_1() {
45 hdr.int_port_ids.setValid();
46 hdr.int_port_ids.ingress_port_id = (bit<16>) smeta.ingress_port;
47 hdr.int_port_ids.egress_port_id = (bit<16>) smeta.egress_port;
48 }
49 // Hop latency.
50 action int_set_header_2() {
51 hdr.int_hop_latency.setValid();
52 hdr.int_hop_latency.hop_latency = (bit<32>) smeta.deq_timedelta;
53 }
54 // Queue occupancy.
55 action int_set_header_3() {
56 hdr.int_q_occupancy.setValid();
57 // TODO: support queues in BMv2. ATM we assume only one.
58 hdr.int_q_occupancy.q_id = 8w0;
59 hdr.int_q_occupancy.q_occupancy = (bit<24>) smeta.deq_qdepth;
60 }
61 // Ingress timestamp.
62 action int_set_header_4() {
63 hdr.int_ingress_tstamp.setValid();
64 hdr.int_ingress_tstamp.ingress_tstamp = (bit<32>) smeta.enq_timestamp;
65 }
66 // Egress timestamp.
67 action int_set_header_5() {
68 hdr.int_egress_tstamp.setValid();
69 hdr.int_egress_tstamp.egress_tstamp = (bit<32>) smeta.enq_timestamp + (bit<32>) smeta.deq_timedelta;
70 }
71 // Queue congestion.
72 action int_set_header_6() {
73 hdr.int_q_congestion.setValid();
74 // TODO: support queue congestion.
75 hdr.int_q_congestion.q_id = 8w0;
76 hdr.int_q_congestion.q_congestion = 24w0;
77 }
78 // Egress port utilization.
79 action int_set_header_7() {
80 hdr.int_egress_tx_util.setValid();
81 // TODO: implement tx utilization support in BMv2.
82 hdr.int_egress_tx_util.egress_port_tx_util = 32w0;
83 }
84#endif // _INT_METADATA_ACTIONS
85
86 // Actions to keep track of the new metadata added.
87 action add_1() {
88 fmeta.int_meta.new_words = fmeta.int_meta.new_words + 1;
89 fmeta.int_meta.new_bytes = fmeta.int_meta.new_bytes + 4;
90 }
91
92 action add_2() {
93 fmeta.int_meta.new_words = fmeta.int_meta.new_words + 2;
94 fmeta.int_meta.new_bytes = fmeta.int_meta.new_bytes + 8;
95 }
96
97 action add_3() {
98 fmeta.int_meta.new_words = fmeta.int_meta.new_words + 3;
99 fmeta.int_meta.new_bytes = fmeta.int_meta.new_bytes + 12;
100 }
101
102 action add_4() {
103 fmeta.int_meta.new_words = fmeta.int_meta.new_words + 4;
104 fmeta.int_meta.new_bytes = fmeta.int_meta.new_bytes + 16;
105 }
106
107 // Action function for bits 0-3 combinations, 0 is msb, 3 is lsb.
108 // Each bit set indicates that corresponding INT header should be added.
109 action int_set_header_0003_i0() {
110 }
111 action int_set_header_0003_i1() {
112 int_set_header_3();
113 add_1();
114 }
115 action int_set_header_0003_i2() {
116 int_set_header_2();
117 add_1();
118 }
119 action int_set_header_0003_i3() {
120 int_set_header_3();
121 int_set_header_2();
122 add_2();
123 }
124 action int_set_header_0003_i4() {
125 int_set_header_1();
126 add_1();
127 }
128 action int_set_header_0003_i5() {
129 int_set_header_3();
130 int_set_header_1();
131 add_2();
132 }
133 action int_set_header_0003_i6() {
134 int_set_header_2();
135 int_set_header_1();
136 add_2();
137 }
138 action int_set_header_0003_i7() {
139 int_set_header_3();
140 int_set_header_2();
141 int_set_header_1();
142 add_3();
143 }
144 action int_set_header_0003_i8() {
145 int_set_header_0();
146 add_1();
147 }
148 action int_set_header_0003_i9() {
149 int_set_header_3();
150 int_set_header_0();
151 add_2();
152 }
153 action int_set_header_0003_i10() {
154 int_set_header_2();
155 int_set_header_0();
156 add_2();
157 }
158 action int_set_header_0003_i11() {
159 int_set_header_3();
160 int_set_header_2();
161 int_set_header_0();
162 add_3();
163 }
164 action int_set_header_0003_i12() {
165 int_set_header_1();
166 int_set_header_0();
167 add_2();
168 }
169 action int_set_header_0003_i13() {
170 int_set_header_3();
171 int_set_header_1();
172 int_set_header_0();
173 add_3();
174 }
175 action int_set_header_0003_i14() {
176 int_set_header_2();
177 int_set_header_1();
178 int_set_header_0();
179 add_3();
180 }
181 action int_set_header_0003_i15() {
182 int_set_header_3();
183 int_set_header_2();
184 int_set_header_1();
185 int_set_header_0();
186 add_4();
187 }
188
189 // Action function for bits 4-7 combinations, 4 is msb, 7 is lsb.
190 action int_set_header_0407_i0() {
191 }
192 action int_set_header_0407_i1() {
193 int_set_header_7();
194 add_1();
195 }
196 action int_set_header_0407_i2() {
197 int_set_header_6();
198 add_1();
199 }
200 action int_set_header_0407_i3() {
201 int_set_header_7();
202 int_set_header_6();
203 add_2();
204 }
205 action int_set_header_0407_i4() {
206 int_set_header_5();
207 add_1();
208 }
209 action int_set_header_0407_i5() {
210 int_set_header_7();
211 int_set_header_5();
212 add_2();
213 }
214 action int_set_header_0407_i6() {
215 int_set_header_6();
216 int_set_header_5();
217 add_2();
218 }
219 action int_set_header_0407_i7() {
220 int_set_header_7();
221 int_set_header_6();
222 int_set_header_5();
223 add_3();
224 }
225 action int_set_header_0407_i8() {
226 int_set_header_4();
227 add_1();
228 }
229 action int_set_header_0407_i9() {
230 int_set_header_7();
231 int_set_header_4();
232 add_2();
233 }
234 action int_set_header_0407_i10() {
235 int_set_header_6();
236 int_set_header_4();
237 add_2();
238 }
239 action int_set_header_0407_i11() {
240 int_set_header_7();
241 int_set_header_6();
242 int_set_header_4();
243 add_3();
244 }
245 action int_set_header_0407_i12() {
246 int_set_header_5();
247 int_set_header_4();
248 add_2();
249 }
250 action int_set_header_0407_i13() {
251 int_set_header_7();
252 int_set_header_5();
253 int_set_header_4();
254 add_3();
255 }
256 action int_set_header_0407_i14() {
257 int_set_header_6();
258 int_set_header_5();
259 int_set_header_4();
260 add_3();
261 }
262 action int_set_header_0407_i15() {
263 int_set_header_7();
264 int_set_header_6();
265 int_set_header_5();
266 int_set_header_4();
267 add_4();
268 }
269
270 // Default action used to set switch ID.
271 table tb_int_insert {
Carmelo Casconefa421582018-09-13 10:05:57 -0700272 // We don't really need a key here, however we add a dummy one as a
273 // workaround to ONOS inability to properly support default actions.
274 key = {
275 hdr.int_header.isValid(): exact @name("hdr.int_header.is_valid");
276 }
Carmelo Cascone79a3a312018-08-16 17:14:43 -0700277 actions = {
278 init_metadata;
Carmelo Casconefa421582018-09-13 10:05:57 -0700279 @defaultonly nop;
Carmelo Cascone79a3a312018-08-16 17:14:43 -0700280 }
Carmelo Casconefa421582018-09-13 10:05:57 -0700281 const default_action = nop;
282 size = 1;
Carmelo Cascone79a3a312018-08-16 17:14:43 -0700283 }
284
285 // Table to process instruction bits 0-3.
286 table tb_int_inst_0003 {
287 key = {
288 hdr.int_header.instruction_mask_0003 : exact;
289 }
290 actions = {
291 int_set_header_0003_i0;
292 int_set_header_0003_i1;
293 int_set_header_0003_i2;
294 int_set_header_0003_i3;
295 int_set_header_0003_i4;
296 int_set_header_0003_i5;
297 int_set_header_0003_i6;
298 int_set_header_0003_i7;
299 int_set_header_0003_i8;
300 int_set_header_0003_i9;
301 int_set_header_0003_i10;
302 int_set_header_0003_i11;
303 int_set_header_0003_i12;
304 int_set_header_0003_i13;
305 int_set_header_0003_i14;
306 int_set_header_0003_i15;
307 }
308 size = 16;
309 const entries = {
310 (0x0) : int_set_header_0003_i0();
311 (0x1) : int_set_header_0003_i1();
312 (0x2) : int_set_header_0003_i2();
313 (0x3) : int_set_header_0003_i3();
314 (0x4) : int_set_header_0003_i4();
315 (0x5) : int_set_header_0003_i5();
316 (0x6) : int_set_header_0003_i6();
317 (0x7) : int_set_header_0003_i7();
318 (0x8) : int_set_header_0003_i8();
319 (0x9) : int_set_header_0003_i9();
320 (0xA) : int_set_header_0003_i10();
321 (0xB) : int_set_header_0003_i11();
322 (0xC) : int_set_header_0003_i12();
323 (0xD) : int_set_header_0003_i13();
324 (0xE) : int_set_header_0003_i14();
325 (0xF) : int_set_header_0003_i15();
326 }
327 }
328
329 // Table to process instruction bits 4-7.
330 table tb_int_inst_0407 {
331 key = {
332 hdr.int_header.instruction_mask_0407 : exact;
333 }
334 actions = {
335 int_set_header_0407_i0;
336 int_set_header_0407_i1;
337 int_set_header_0407_i2;
338 int_set_header_0407_i3;
339 int_set_header_0407_i4;
340 int_set_header_0407_i5;
341 int_set_header_0407_i6;
342 int_set_header_0407_i7;
343 int_set_header_0407_i8;
344 int_set_header_0407_i9;
345 int_set_header_0407_i10;
346 int_set_header_0407_i11;
347 int_set_header_0407_i12;
348 int_set_header_0407_i13;
349 int_set_header_0407_i14;
350 int_set_header_0407_i15;
351 }
352 size = 16;
353 const entries = {
354 (0x0) : int_set_header_0407_i0();
355 (0x1) : int_set_header_0407_i1();
356 (0x2) : int_set_header_0407_i2();
357 (0x3) : int_set_header_0407_i3();
358 (0x4) : int_set_header_0407_i4();
359 (0x5) : int_set_header_0407_i5();
360 (0x6) : int_set_header_0407_i6();
361 (0x7) : int_set_header_0407_i7();
362 (0x8) : int_set_header_0407_i8();
363 (0x9) : int_set_header_0407_i9();
364 (0xA) : int_set_header_0407_i10();
365 (0xB) : int_set_header_0407_i11();
366 (0xC) : int_set_header_0407_i12();
367 (0xD) : int_set_header_0407_i13();
368 (0xE) : int_set_header_0407_i14();
369 (0xF) : int_set_header_0407_i15();
370 }
371 }
372
373 apply {
374 tb_int_insert.apply();
375 if (fmeta.int_meta.transit == _FALSE) {
376 return;
377 }
378 tb_int_inst_0003.apply();
379 tb_int_inst_0407.apply();
380 // Increment hop cnt
381 hdr.int_header.total_hop_cnt = hdr.int_header.total_hop_cnt + 1;
382 // Update headers lengths.
383 if (hdr.ipv4.isValid()) {
384 hdr.ipv4.total_len = hdr.ipv4.total_len + fmeta.int_meta.new_bytes;
385 }
386 if (hdr.udp.isValid()) {
387 hdr.udp.len = hdr.udp.len + fmeta.int_meta.new_bytes;
388 }
389 if (hdr.intl4_shim.isValid()) {
390 hdr.intl4_shim.len_words = hdr.intl4_shim.len_words + fmeta.int_meta.new_words;
391 }
392 }
393}
394
395#endif