Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 1 | +---------------------------------------------------------------------+ |
| 2 | | Log file: mau.sram.log | |
| 3 | | Compiler version: 5.1.0 (fca32d1) | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 4 | | Created on: Fri Sep 8 08:23:45 2017 | |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 5 | +---------------------------------------------------------------------+ |
| 6 | |
| 7 | |
| 8 | |
| 9 | ======================================================= |
| 10 | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 11 | calling allocate and add with SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 12 | ======================================================= |
| 13 | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 14 | Requesting to use 2 RAMs and have 80 available. |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 15 | Requesting to use 0 Map RAMs and have 48 available. |
| 16 | |
| 17 | ======================================================== |
| 18 | Run Placement on Request List of size 1 in stage 0 |
| 19 | open_up_all_for_match=False |
| 20 | synth_two_port_first=False |
| 21 | ======================================================== |
| 22 | |
| 23 | Match Rams Need is 0 |
| 24 | Algorithmic TCAM Match RAMs Need is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 25 | Other Rams Need is 2 |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 26 | |
| 27 | +========================================= |
| 28 | | Placing algorithmic tcam |
| 29 | +========================================= |
| 30 | |
| 31 | sorted algorithmic tcam requests: (0) |
| 32 | |
| 33 | |
| 34 | ------------------------------------- |
| 35 | Columns need for match is 0 |
| 36 | columns for width is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 37 | other columns is 1 |
| 38 | reserved columns is 9 |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 39 | reserved columns for tind 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 40 | reserved columns for stateful 1 |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 41 | Ternary Indirection Rams Need is 0 |
| 42 | Depth sorted requested |
| 43 | Requesting to use 0 RAMs and have 32 available. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 44 | Result bus only needs (0): |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 45 | |
| 46 | +========================================= |
| 47 | | Placing action/stats/meters/selection |
| 48 | +========================================= |
| 49 | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 50 | Requesting to use 2 RAMs and have 80 available. |
| 51 | SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 52 | NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 53 | |
| 54 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 55 | Allocating: Statistics ALU 6 on right (128 bits) in stage 0 for table table0_counter. |
| 56 | Allocating: SRAM: Row 6 Col 6 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 57 | Allocating: Map RAM: Row 6 Unit 0 in stage 0 for table0_counter. |
| 58 | Allocating: SRAM: Row 6 Col 7 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 59 | Allocating: Map RAM: Row 6 Unit 1 in stage 0 for table0_counter. |
| 60 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 0 for table0_counter. |
| 61 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 0 for table0_counter. |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 62 | Depth sorted idletime requests: |
| 63 | |
| 64 | |
| 65 | ======================================================= |
| 66 | |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 67 | calling allocate and add with SRAM Resource Request for table table0 (of type ternary_indirection), with 1 ways wants 1 rams. (open-all=False, synth_two_port_first=False) |
| 68 | ======================================================= |
| 69 | |
| 70 | Requesting to use 1 RAMs and have 78 available. |
| 71 | Requesting to use 0 Map RAMs and have 46 available. |
| 72 | |
| 73 | ======================================================== |
| 74 | Run Placement on Request List of size 2 in stage 0 |
| 75 | open_up_all_for_match=False |
| 76 | synth_two_port_first=False |
| 77 | ======================================================== |
| 78 | |
| 79 | Match Rams Need is 0 |
| 80 | Algorithmic TCAM Match RAMs Need is 0 |
| 81 | Other Rams Need is 3 |
| 82 | |
| 83 | +========================================= |
| 84 | | Placing algorithmic tcam |
| 85 | +========================================= |
| 86 | |
| 87 | sorted algorithmic tcam requests: (0) |
| 88 | |
| 89 | |
| 90 | ------------------------------------- |
| 91 | Columns need for match is 0 |
| 92 | columns for width is 0 |
| 93 | other columns is 1 |
| 94 | reserved columns is 9 |
| 95 | reserved columns for tind 1 |
| 96 | reserved columns for stateful 1 |
| 97 | Ternary Indirection Rams Need is 1 |
| 98 | Depth sorted requested |
| 99 | Group 0 |
| 100 | Sram Resource Request for P4 table table0 with handle 16777220 of type ternary_indirection in stage 0 |
| 101 | table_type : ternary_indirection |
| 102 | rams_for_width : 1 |
| 103 | use_stash : False |
| 104 | number_ways : 1 |
| 105 | way #0 |
| 106 | SRAM Request Group 0 |
| 107 | rams_for_depth : 1 |
| 108 | map_rams : 0 |
| 109 | way_number : 0 |
| 110 | ram_word_select_bits : 0 |
| 111 | ram_enable_select_bits : 0 |
| 112 | |
| 113 | Requesting to use 1 RAMs and have 32 available. |
| 114 | Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 0 |
| 115 | Allocating: SRAM: Row 0 Col 2 in stage 0 for table table0's ternary indirection word range Words 0 to 1023. |
| 116 | Result bus only needs (0): |
| 117 | |
| 118 | +========================================= |
| 119 | | Placing action/stats/meters/selection |
| 120 | +========================================= |
| 121 | |
| 122 | Requesting to use 2 RAMs and have 79 available. |
| 123 | SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 124 | NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 125 | |
| 126 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 127 | Allocating: Statistics ALU 6 on right (128 bits) in stage 0 for table table0_counter. |
| 128 | Allocating: SRAM: Row 6 Col 6 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 129 | Allocating: Map RAM: Row 6 Unit 0 in stage 0 for table0_counter. |
| 130 | Allocating: SRAM: Row 6 Col 7 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 131 | Allocating: Map RAM: Row 6 Unit 1 in stage 0 for table0_counter. |
| 132 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 0 for table0_counter. |
| 133 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 0 for table0_counter. |
| 134 | Depth sorted idletime requests: |
| 135 | |
| 136 | |
| 137 | ======================================================= |
| 138 | |
| 139 | calling allocate and add with SRAM Resource Request for table table0 (of type idletime), with 1 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 140 | ======================================================= |
| 141 | |
| 142 | Requesting to use 0 RAMs and have 77 available. |
| 143 | Requesting to use 1 Map RAMs and have 46 available. |
| 144 | |
| 145 | ======================================================== |
| 146 | Run Placement on Request List of size 3 in stage 0 |
| 147 | open_up_all_for_match=False |
| 148 | synth_two_port_first=False |
| 149 | ======================================================== |
| 150 | |
| 151 | Match Rams Need is 0 |
| 152 | Algorithmic TCAM Match RAMs Need is 0 |
| 153 | Other Rams Need is 3 |
| 154 | |
| 155 | +========================================= |
| 156 | | Placing algorithmic tcam |
| 157 | +========================================= |
| 158 | |
| 159 | sorted algorithmic tcam requests: (0) |
| 160 | |
| 161 | |
| 162 | ------------------------------------- |
| 163 | Columns need for match is 0 |
| 164 | columns for width is 0 |
| 165 | other columns is 1 |
| 166 | reserved columns is 9 |
| 167 | reserved columns for tind 1 |
| 168 | reserved columns for stateful 1 |
| 169 | Ternary Indirection Rams Need is 1 |
| 170 | Depth sorted requested |
| 171 | Group 0 |
| 172 | Sram Resource Request for P4 table table0 with handle 16777220 of type ternary_indirection in stage 0 |
| 173 | table_type : ternary_indirection |
| 174 | rams_for_width : 1 |
| 175 | use_stash : False |
| 176 | number_ways : 1 |
| 177 | way #0 |
| 178 | SRAM Request Group 0 |
| 179 | rams_for_depth : 1 |
| 180 | map_rams : 0 |
| 181 | way_number : 0 |
| 182 | ram_word_select_bits : 0 |
| 183 | ram_enable_select_bits : 0 |
| 184 | |
| 185 | Requesting to use 1 RAMs and have 32 available. |
| 186 | Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 0 |
| 187 | Allocating: SRAM: Row 0 Col 2 in stage 0 for table table0's ternary indirection word range Words 0 to 1023. |
| 188 | Result bus only needs (0): |
| 189 | |
| 190 | +========================================= |
| 191 | | Placing action/stats/meters/selection |
| 192 | +========================================= |
| 193 | |
| 194 | Requesting to use 2 RAMs and have 79 available. |
| 195 | SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 196 | NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 197 | |
| 198 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 199 | Allocating: Statistics ALU 6 on right (128 bits) in stage 0 for table table0_counter. |
| 200 | Allocating: SRAM: Row 6 Col 6 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 201 | Allocating: Map RAM: Row 6 Unit 0 in stage 0 for table0_counter. |
| 202 | Allocating: SRAM: Row 6 Col 7 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 203 | Allocating: Map RAM: Row 6 Unit 1 in stage 0 for table0_counter. |
| 204 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 0 for table0_counter. |
| 205 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 0 for table0_counter. |
| 206 | Depth sorted idletime requests: |
| 207 | Sram Resource Request for P4 table table0 with handle 16777220 of type idletime in stage 0 |
| 208 | table_type : idletime |
| 209 | rams_for_width : 0 |
| 210 | use_stash : False |
| 211 | number_ways : 1 |
| 212 | way #0 |
| 213 | SRAM Request Group 0 |
| 214 | rams_for_depth : 0 |
| 215 | map_rams : 1 |
| 216 | way_number : 0 |
| 217 | ram_word_select_bits : 0 |
| 218 | ram_enable_select_bits : 0 |
| 219 | |
| 220 | Requesting to use 1 RAMs and have 46 available. |
| 221 | top_cnt = 1 and num requests = 1 |
| 222 | bottom_cnt = 0 and num requests = 0 |
| 223 | Working on idletime request SRAM Resource Request for table table0 (of type idletime), with 1 ways wants 0 rams. |
| 224 | >> wants 1 map rams |
| 225 | Allocating: Map RAM: Row 7 Unit 0 in stage 0 for table0. |
| 226 | Allocating: Ram Data Bus IdletimeHalfLogicalRow 0 top is 19 bits in stage 0 for table0. |
| 227 | |
| 228 | |
| 229 | ======================================================= |
| 230 | |
| 231 | calling allocate and add with SRAM Resource Request for table process_packet_out_table (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 232 | ======================================================= |
| 233 | |
| 234 | Requesting to use 0 RAMs and have 77 available. |
| 235 | Requesting to use 0 Map RAMs and have 45 available. |
| 236 | |
| 237 | ======================================================== |
| 238 | Run Placement on Request List of size 4 in stage 0 |
| 239 | open_up_all_for_match=False |
| 240 | synth_two_port_first=False |
| 241 | ======================================================== |
| 242 | |
| 243 | Match Rams Need is 0 |
| 244 | Algorithmic TCAM Match RAMs Need is 0 |
| 245 | Other Rams Need is 3 |
| 246 | |
| 247 | +========================================= |
| 248 | | Placing algorithmic tcam |
| 249 | +========================================= |
| 250 | |
| 251 | sorted algorithmic tcam requests: (0) |
| 252 | |
| 253 | |
| 254 | ------------------------------------- |
| 255 | Columns need for match is 0 |
| 256 | columns for width is 0 |
| 257 | other columns is 1 |
| 258 | reserved columns is 9 |
| 259 | reserved columns for tind 1 |
| 260 | reserved columns for stateful 1 |
| 261 | Ternary Indirection Rams Need is 1 |
| 262 | Depth sorted requested |
| 263 | Group 0 |
| 264 | Sram Resource Request for P4 table table0 with handle 16777220 of type ternary_indirection in stage 0 |
| 265 | table_type : ternary_indirection |
| 266 | rams_for_width : 1 |
| 267 | use_stash : False |
| 268 | number_ways : 1 |
| 269 | way #0 |
| 270 | SRAM Request Group 0 |
| 271 | rams_for_depth : 1 |
| 272 | map_rams : 0 |
| 273 | way_number : 0 |
| 274 | ram_word_select_bits : 0 |
| 275 | ram_enable_select_bits : 0 |
| 276 | |
| 277 | Requesting to use 1 RAMs and have 32 available. |
| 278 | Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 0 |
| 279 | Allocating: SRAM: Row 0 Col 2 in stage 0 for table table0's ternary indirection word range Words 0 to 1023. |
| 280 | Result bus only needs (1): |
| 281 | process_packet_out_table |
| 282 | Allocating: Ram Data Bus MatchResult2R 0 left_and_right is 83 bits in stage 0 |
| 283 | |
| 284 | +========================================= |
| 285 | | Placing action/stats/meters/selection |
| 286 | +========================================= |
| 287 | |
| 288 | Requesting to use 2 RAMs and have 79 available. |
| 289 | SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 290 | NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 291 | |
| 292 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 293 | Allocating: Statistics ALU 6 on right (128 bits) in stage 0 for table table0_counter. |
| 294 | Allocating: SRAM: Row 6 Col 6 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 295 | Allocating: Map RAM: Row 6 Unit 0 in stage 0 for table0_counter. |
| 296 | Allocating: SRAM: Row 6 Col 7 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 297 | Allocating: Map RAM: Row 6 Unit 1 in stage 0 for table0_counter. |
| 298 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 0 for table0_counter. |
| 299 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 0 for table0_counter. |
| 300 | Depth sorted idletime requests: |
| 301 | Sram Resource Request for P4 table table0 with handle 16777220 of type idletime in stage 0 |
| 302 | table_type : idletime |
| 303 | rams_for_width : 0 |
| 304 | use_stash : False |
| 305 | number_ways : 1 |
| 306 | way #0 |
| 307 | SRAM Request Group 0 |
| 308 | rams_for_depth : 0 |
| 309 | map_rams : 1 |
| 310 | way_number : 0 |
| 311 | ram_word_select_bits : 0 |
| 312 | ram_enable_select_bits : 0 |
| 313 | |
| 314 | Requesting to use 1 RAMs and have 46 available. |
| 315 | top_cnt = 1 and num requests = 1 |
| 316 | bottom_cnt = 0 and num requests = 0 |
| 317 | Working on idletime request SRAM Resource Request for table table0 (of type idletime), with 1 ways wants 0 rams. |
| 318 | >> wants 1 map rams |
| 319 | Allocating: Map RAM: Row 7 Unit 0 in stage 0 for table0. |
| 320 | Allocating: Ram Data Bus IdletimeHalfLogicalRow 0 top is 19 bits in stage 0 for table0. |
| 321 | |
| 322 | |
| 323 | ======================================================= |
| 324 | |
| 325 | calling allocate and add with SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 326 | ======================================================= |
| 327 | |
| 328 | Requesting to use 2 RAMs and have 80 available. |
| 329 | Requesting to use 0 Map RAMs and have 48 available. |
| 330 | |
| 331 | ======================================================== |
| 332 | Run Placement on Request List of size 1 in stage 1 |
| 333 | open_up_all_for_match=False |
| 334 | synth_two_port_first=False |
| 335 | ======================================================== |
| 336 | |
| 337 | Match Rams Need is 0 |
| 338 | Algorithmic TCAM Match RAMs Need is 0 |
| 339 | Other Rams Need is 2 |
| 340 | |
| 341 | +========================================= |
| 342 | | Placing algorithmic tcam |
| 343 | +========================================= |
| 344 | |
| 345 | sorted algorithmic tcam requests: (0) |
| 346 | |
| 347 | |
| 348 | ------------------------------------- |
| 349 | Columns need for match is 0 |
| 350 | columns for width is 0 |
| 351 | other columns is 1 |
| 352 | reserved columns is 9 |
| 353 | reserved columns for tind 0 |
| 354 | reserved columns for stateful 1 |
| 355 | Ternary Indirection Rams Need is 0 |
| 356 | Depth sorted requested |
| 357 | Requesting to use 0 RAMs and have 32 available. |
| 358 | Result bus only needs (0): |
| 359 | |
| 360 | +========================================= |
| 361 | | Placing action/stats/meters/selection |
| 362 | +========================================= |
| 363 | |
| 364 | Requesting to use 2 RAMs and have 80 available. |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 365 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 366 | NO Spill Required off of logical row 13 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 367 | |
| 368 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 369 | Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table ingress_port_counter. |
| 370 | Allocating: SRAM: Row 6 Col 6 in stage 1 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 371 | Allocating: Map RAM: Row 6 Unit 0 in stage 1 for ingress_port_counter. |
| 372 | Allocating: SRAM: Row 6 Col 7 in stage 1 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 373 | Allocating: Map RAM: Row 6 Unit 1 in stage 1 for ingress_port_counter. |
| 374 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for ingress_port_counter. |
| 375 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for ingress_port_counter. |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 376 | Depth sorted idletime requests: |
| 377 | |
| 378 | |
| 379 | ======================================================= |
| 380 | |
| 381 | calling allocate and add with SRAM Resource Request for table ingress_port_count_table (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 382 | ======================================================= |
| 383 | |
| 384 | Requesting to use 0 RAMs and have 78 available. |
| 385 | Requesting to use 0 Map RAMs and have 46 available. |
| 386 | |
| 387 | ======================================================== |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 388 | Run Placement on Request List of size 2 in stage 1 |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 389 | open_up_all_for_match=False |
| 390 | synth_two_port_first=False |
| 391 | ======================================================== |
| 392 | |
| 393 | Match Rams Need is 0 |
| 394 | Algorithmic TCAM Match RAMs Need is 0 |
| 395 | Other Rams Need is 2 |
| 396 | |
| 397 | +========================================= |
| 398 | | Placing algorithmic tcam |
| 399 | +========================================= |
| 400 | |
| 401 | sorted algorithmic tcam requests: (0) |
| 402 | |
| 403 | |
| 404 | ------------------------------------- |
| 405 | Columns need for match is 0 |
| 406 | columns for width is 0 |
| 407 | other columns is 1 |
| 408 | reserved columns is 9 |
| 409 | reserved columns for tind 0 |
| 410 | reserved columns for stateful 1 |
| 411 | Ternary Indirection Rams Need is 0 |
| 412 | Depth sorted requested |
| 413 | Requesting to use 0 RAMs and have 32 available. |
| 414 | Result bus only needs (1): |
| 415 | ingress_port_count_table |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 416 | Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 1 |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 417 | |
| 418 | +========================================= |
| 419 | | Placing action/stats/meters/selection |
| 420 | +========================================= |
| 421 | |
| 422 | Requesting to use 2 RAMs and have 80 available. |
| 423 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 424 | NO Spill Required off of logical row 13 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 425 | |
| 426 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 427 | Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table ingress_port_counter. |
| 428 | Allocating: SRAM: Row 6 Col 6 in stage 1 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 429 | Allocating: Map RAM: Row 6 Unit 0 in stage 1 for ingress_port_counter. |
| 430 | Allocating: SRAM: Row 6 Col 7 in stage 1 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 431 | Allocating: Map RAM: Row 6 Unit 1 in stage 1 for ingress_port_counter. |
| 432 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for ingress_port_counter. |
| 433 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for ingress_port_counter. |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 434 | Depth sorted idletime requests: |
| 435 | |
| 436 | |
| 437 | ======================================================= |
| 438 | |
| 439 | calling allocate and add with SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
| 440 | ======================================================= |
| 441 | |
| 442 | Requesting to use 2 RAMs and have 78 available. |
| 443 | Requesting to use 0 Map RAMs and have 46 available. |
| 444 | |
| 445 | ======================================================== |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 446 | Run Placement on Request List of size 3 in stage 1 |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 447 | open_up_all_for_match=False |
| 448 | synth_two_port_first=False |
| 449 | ======================================================== |
| 450 | |
| 451 | Match Rams Need is 0 |
| 452 | Algorithmic TCAM Match RAMs Need is 0 |
| 453 | Other Rams Need is 4 |
| 454 | |
| 455 | +========================================= |
| 456 | | Placing algorithmic tcam |
| 457 | +========================================= |
| 458 | |
| 459 | sorted algorithmic tcam requests: (0) |
| 460 | |
| 461 | |
| 462 | ------------------------------------- |
| 463 | Columns need for match is 0 |
| 464 | columns for width is 0 |
| 465 | other columns is 1 |
| 466 | reserved columns is 9 |
| 467 | reserved columns for tind 0 |
| 468 | reserved columns for stateful 1 |
| 469 | Ternary Indirection Rams Need is 0 |
| 470 | Depth sorted requested |
| 471 | Requesting to use 0 RAMs and have 32 available. |
| 472 | Result bus only needs (1): |
| 473 | ingress_port_count_table |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 474 | Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 1 |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 475 | |
| 476 | +========================================= |
| 477 | | Placing action/stats/meters/selection |
| 478 | +========================================= |
| 479 | |
| 480 | Requesting to use 4 RAMs and have 80 available. |
| 481 | SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 482 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 483 | NO Spill Required off of logical row 13 for SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 484 | |
| 485 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 486 | Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table egress_port_counter. |
| 487 | Allocating: SRAM: Row 6 Col 6 in stage 1 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 488 | Allocating: Map RAM: Row 6 Unit 0 in stage 1 for egress_port_counter. |
| 489 | Allocating: SRAM: Row 6 Col 7 in stage 1 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 490 | Allocating: Map RAM: Row 6 Unit 1 in stage 1 for egress_port_counter. |
| 491 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for egress_port_counter. |
| 492 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for egress_port_counter. |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 493 | NO Spill Required off of logical row 9 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 494 | |
| 495 | call to place_table_on_logical_row --- logical row 9 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 496 | Allocating: Statistics ALU 4 on right (128 bits) in stage 1 for table ingress_port_counter. |
| 497 | Allocating: SRAM: Row 4 Col 6 in stage 1 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 498 | Allocating: Map RAM: Row 4 Unit 0 in stage 1 for ingress_port_counter. |
| 499 | Allocating: SRAM: Row 4 Col 7 in stage 1 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 500 | Allocating: Map RAM: Row 4 Unit 1 in stage 1 for ingress_port_counter. |
| 501 | Allocating: Ram Data Bus StatsR 4 right is 128 bits in stage 1 for ingress_port_counter. |
| 502 | Allocating: Ram Data Bus StatsW 4 right is 128 bits in stage 1 for ingress_port_counter. |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 503 | Depth sorted idletime requests: |
| 504 | |
| 505 | |
| 506 | ======================================================= |
| 507 | |
| 508 | calling allocate and add with SRAM Resource Request for table egress_port_count_table (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 509 | ======================================================= |
| 510 | |
| 511 | Requesting to use 0 RAMs and have 76 available. |
| 512 | Requesting to use 0 Map RAMs and have 44 available. |
| 513 | |
| 514 | ======================================================== |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 515 | Run Placement on Request List of size 4 in stage 1 |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 516 | open_up_all_for_match=False |
| 517 | synth_two_port_first=False |
| 518 | ======================================================== |
| 519 | |
| 520 | Match Rams Need is 0 |
| 521 | Algorithmic TCAM Match RAMs Need is 0 |
| 522 | Other Rams Need is 4 |
| 523 | |
| 524 | +========================================= |
| 525 | | Placing algorithmic tcam |
| 526 | +========================================= |
| 527 | |
| 528 | sorted algorithmic tcam requests: (0) |
| 529 | |
| 530 | |
| 531 | ------------------------------------- |
| 532 | Columns need for match is 0 |
| 533 | columns for width is 0 |
| 534 | other columns is 1 |
| 535 | reserved columns is 9 |
| 536 | reserved columns for tind 0 |
| 537 | reserved columns for stateful 1 |
| 538 | Ternary Indirection Rams Need is 0 |
| 539 | Depth sorted requested |
| 540 | Requesting to use 0 RAMs and have 32 available. |
| 541 | Result bus only needs (2): |
| 542 | egress_port_count_table |
| 543 | ingress_port_count_table |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 544 | Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 1 |
| 545 | Allocating: Ram Data Bus MatchResult2R 0 left_and_right is 83 bits in stage 1 |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 546 | |
| 547 | +========================================= |
| 548 | | Placing action/stats/meters/selection |
| 549 | +========================================= |
| 550 | |
| 551 | Requesting to use 4 RAMs and have 80 available. |
| 552 | SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 553 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 554 | NO Spill Required off of logical row 13 for SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 555 | |
| 556 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 557 | Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table egress_port_counter. |
| 558 | Allocating: SRAM: Row 6 Col 6 in stage 1 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 559 | Allocating: Map RAM: Row 6 Unit 0 in stage 1 for egress_port_counter. |
| 560 | Allocating: SRAM: Row 6 Col 7 in stage 1 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 561 | Allocating: Map RAM: Row 6 Unit 1 in stage 1 for egress_port_counter. |
| 562 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for egress_port_counter. |
| 563 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for egress_port_counter. |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 564 | NO Spill Required off of logical row 9 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 565 | |
| 566 | call to place_table_on_logical_row --- logical row 9 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 567 | Allocating: Statistics ALU 4 on right (128 bits) in stage 1 for table ingress_port_counter. |
| 568 | Allocating: SRAM: Row 4 Col 6 in stage 1 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 569 | Allocating: Map RAM: Row 4 Unit 0 in stage 1 for ingress_port_counter. |
| 570 | Allocating: SRAM: Row 4 Col 7 in stage 1 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 571 | Allocating: Map RAM: Row 4 Unit 1 in stage 1 for ingress_port_counter. |
| 572 | Allocating: Ram Data Bus StatsR 4 right is 128 bits in stage 1 for ingress_port_counter. |
| 573 | Allocating: Ram Data Bus StatsW 4 right is 128 bits in stage 1 for ingress_port_counter. |
Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame] | 574 | Depth sorted idletime requests: |