| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame^] | 1 | +---------------------------------------------------------------------+ |
| 2 | | Log file: mau.log | |
| 3 | | Compiler version: 5.1.0 (fca32d1) | |
| 4 | | Created on: Thu Sep 7 13:56:53 2017 | |
| 5 | +---------------------------------------------------------------------+ |
| 6 | |
| 7 | Match Table table0 did not specify the number of entries required. A default value (512) will be used. |
| 8 | Match Entry Table table0 has already been associated with stat Table table0_counter. |
| 9 | Cannot implement ingress_pkt in phase 0 resources because table does not have the correct condition |
| 10 | Match Table table0 did not specify the number of entries required. A default value (512) will be used. |
| 11 | Match Entry Table table0 has already been associated with stat Table table0_counter. |
| 12 | Cannot implement ingress_pkt in phase 0 resources because table does not have the correct condition |
| 13 | Match Table table0 did not specify the number of entries required. A default value (512) will be used. |
| 14 | POV/metadata bridge containers added between ingress/egress: [0, 64, 128] |
| 15 | Metadata bridge_ingress_intrinsic containers added between ingress/egress: [128] |
| 16 | Match Entry Table table0 has already been associated with stat Table table0_counter. |
| 17 | Match table ingress_port_count_table has no match key fields |
| 18 | Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 254. |
| 19 | |
| 20 | ########################################## |
| 21 | Call to decide_action_data_placement(stage=0, table=ingress_port_count_table) |
| 22 | ########################################## |
| 23 | |
| 24 | |
| 25 | Max immediate bits used in any action is 0 bits. |
| 26 | Overhead bit width for table ingress_port_count_table is 22 bits. |
| 27 | Bits available in overhead for non-essential immediate data is 32 bits. |
| 28 | ~~~~~~~~~~~~~~~~~~~~~ |
| 29 | Examining placing 0 bits in match overhead |
| 30 | Overhead bit width for table ingress_port_count_table is 22 bits. |
| 31 | Overhead SRAMs to use = 97 |
| 32 | Entries requested = 1024 and match entries get = 0 |
| 33 | ram_size_matrix = |
| 34 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 35 | 0 0 0 0 0 0 0 0 # 0 |
| 36 | |
| 37 | immediate_size_matrix = |
| 38 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 39 | 0 0 0 0 0 0 0 0 # 0 |
| 40 | |
| 41 | hash_to_phv_matrix = |
| 42 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 43 | 0 0 0 0 0 0 0 0 # 0 |
| 44 | |
| 45 | total action ram packing size = [0, 0, 0] |
| 46 | action_ram_packing: |
| 47 | action count_ingress has [] |
| 48 | total action ram packing size = [0, 0, 0] |
| 49 | action_ram_packing: |
| 50 | action count_ingress has [] |
| 51 | total action ram packing size = [0, 0, 0] |
| 52 | action_ram_packing: |
| 53 | action count_ingress has [] |
| 54 | byte_enables = [] |
| 55 | After allocation of 32s, available_slots is [] |
| 56 | final packing is [] |
| 57 | byte_enables = [] |
| 58 | After allocation of 32s, available_slots is [] |
| 59 | final packing is [] |
| 60 | byte_enables = [] |
| 61 | After allocation of 32s, available_slots is [] |
| 62 | final packing is [] |
| 63 | Action Data SRAMs to use = 0 |
| 64 | TODO: Total RAMs use when put 0 bits in match overhead: 97 |
| 65 | TODO: Total RAMs use when put 0 bits in match overhead: 97 |
| 66 | ~~~~~~~~~~~~~~~~~~~~~ |
| 67 | Examining placing 8 bits in match overhead |
| 68 | ~~~~~~~~~~~~~~~~~~~~~ |
| 69 | Examining placing 16 bits in match overhead |
| 70 | ~~~~~~~~~~~~~~~~~~~~~ |
| 71 | Examining placing 24 bits in match overhead |
| 72 | ~~~~~~~~~~~~~~~~~~~~~ |
| 73 | Examining placing 32 bits in match overhead |
| 74 | |
| 75 | ########################################## |
| 76 | |
| 77 | Best Ram Usage is 97 rams |
| 78 | Best Immediate placement is 0 bits |
| 79 | Match table egress_port_count_table has no match key fields |
| 80 | Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 254. |
| 81 | |
| 82 | ########################################## |
| 83 | Call to decide_action_data_placement(stage=0, table=egress_port_count_table) |
| 84 | ########################################## |
| 85 | |
| 86 | |
| 87 | Max immediate bits used in any action is 0 bits. |
| 88 | Overhead bit width for table egress_port_count_table is 20 bits. |
| 89 | Bits available in overhead for non-essential immediate data is 32 bits. |
| 90 | ~~~~~~~~~~~~~~~~~~~~~ |
| 91 | Examining placing 0 bits in match overhead |
| 92 | Overhead bit width for table egress_port_count_table is 20 bits. |
| 93 | Overhead SRAMs to use = 97 |
| 94 | Entries requested = 1024 and match entries get = 0 |
| 95 | ram_size_matrix = |
| 96 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 97 | 0 0 0 0 0 0 0 0 # 0 |
| 98 | |
| 99 | immediate_size_matrix = |
| 100 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 101 | 0 0 0 0 0 0 0 0 # 0 |
| 102 | |
| 103 | hash_to_phv_matrix = |
| 104 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 105 | 0 0 0 0 0 0 0 0 # 0 |
| 106 | |
| 107 | total action ram packing size = [0, 0, 0] |
| 108 | action_ram_packing: |
| 109 | action count_egress has [] |
| 110 | total action ram packing size = [0, 0, 0] |
| 111 | action_ram_packing: |
| 112 | action count_egress has [] |
| 113 | total action ram packing size = [0, 0, 0] |
| 114 | action_ram_packing: |
| 115 | action count_egress has [] |
| 116 | byte_enables = [] |
| 117 | After allocation of 32s, available_slots is [] |
| 118 | final packing is [] |
| 119 | byte_enables = [] |
| 120 | After allocation of 32s, available_slots is [] |
| 121 | final packing is [] |
| 122 | byte_enables = [] |
| 123 | After allocation of 32s, available_slots is [] |
| 124 | final packing is [] |
| 125 | Action Data SRAMs to use = 0 |
| 126 | TODO: Total RAMs use when put 0 bits in match overhead: 97 |
| 127 | TODO: Total RAMs use when put 0 bits in match overhead: 97 |
| 128 | ~~~~~~~~~~~~~~~~~~~~~ |
| 129 | Examining placing 8 bits in match overhead |
| 130 | ~~~~~~~~~~~~~~~~~~~~~ |
| 131 | Examining placing 16 bits in match overhead |
| 132 | ~~~~~~~~~~~~~~~~~~~~~ |
| 133 | Examining placing 24 bits in match overhead |
| 134 | ~~~~~~~~~~~~~~~~~~~~~ |
| 135 | Examining placing 32 bits in match overhead |
| 136 | |
| 137 | ########################################## |
| 138 | |
| 139 | Best Ram Usage is 97 rams |
| 140 | Best Immediate placement is 0 bits |
| 141 | |
| 142 | ########################################## |
| 143 | Call to decide_action_data_placement(stage=0, table=ingress_pkt) |
| 144 | ########################################## |
| 145 | |
| 146 | |
| 147 | Max immediate bits used in any action is 0 bits. |
| 148 | Overhead bit width for table ingress_pkt is 2 bits. |
| 149 | Bits available in overhead for non-essential immediate data is 32 bits. |
| 150 | ~~~~~~~~~~~~~~~~~~~~~ |
| 151 | Examining placing 0 bits in match overhead |
| 152 | Overhead bit width for table ingress_pkt is 2 bits. |
| 153 | Overhead SRAMs to use = 97 |
| 154 | Entries requested = 1024 and match entries get = 0 |
| 155 | ram_size_matrix = |
| 156 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 157 | 0 0 0 0 0 0 0 0 # 0 |
| 158 | |
| 159 | immediate_size_matrix = |
| 160 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 161 | 0 0 0 0 0 0 0 0 # 0 |
| 162 | |
| 163 | hash_to_phv_matrix = |
| 164 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 165 | 0 0 0 0 0 0 0 0 # 0 |
| 166 | |
| 167 | total action ram packing size = [0, 0, 0] |
| 168 | action_ram_packing: |
| 169 | action _packet_out has [] |
| 170 | total action ram packing size = [0, 0, 0] |
| 171 | action_ram_packing: |
| 172 | action _packet_out has [] |
| 173 | total action ram packing size = [0, 0, 0] |
| 174 | action_ram_packing: |
| 175 | action _packet_out has [] |
| 176 | byte_enables = [] |
| 177 | After allocation of 32s, available_slots is [] |
| 178 | final packing is [] |
| 179 | byte_enables = [] |
| 180 | After allocation of 32s, available_slots is [] |
| 181 | final packing is [] |
| 182 | byte_enables = [] |
| 183 | After allocation of 32s, available_slots is [] |
| 184 | final packing is [] |
| 185 | Action Data SRAMs to use = 0 |
| 186 | TODO: Total RAMs use when put 0 bits in match overhead: 97 |
| 187 | TODO: Total RAMs use when put 0 bits in match overhead: 97 |
| 188 | ~~~~~~~~~~~~~~~~~~~~~ |
| 189 | Examining placing 8 bits in match overhead |
| 190 | ~~~~~~~~~~~~~~~~~~~~~ |
| 191 | Examining placing 16 bits in match overhead |
| 192 | ~~~~~~~~~~~~~~~~~~~~~ |
| 193 | Examining placing 24 bits in match overhead |
| 194 | ~~~~~~~~~~~~~~~~~~~~~ |
| 195 | Examining placing 32 bits in match overhead |
| 196 | |
| 197 | ########################################## |
| 198 | |
| 199 | Best Ram Usage is 97 rams |
| 200 | Best Immediate placement is 0 bits |
| 201 | |
| 202 | ########################################## |
| 203 | Call to decide_action_data_placement(stage=0, table=egress_pkt) |
| 204 | ########################################## |
| 205 | |
| 206 | |
| 207 | Max immediate bits used in any action is 0 bits. |
| 208 | Overhead bit width for table egress_pkt is 2 bits. |
| 209 | Bits available in overhead for non-essential immediate data is 32 bits. |
| 210 | ~~~~~~~~~~~~~~~~~~~~~ |
| 211 | Examining placing 0 bits in match overhead |
| 212 | Overhead bit width for table egress_pkt is 2 bits. |
| 213 | Overhead SRAMs to use = 97 |
| 214 | Entries requested = 1024 and match entries get = 0 |
| 215 | ram_size_matrix = |
| 216 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 217 | 0 0 0 0 0 0 0 0 # 0 |
| 218 | |
| 219 | immediate_size_matrix = |
| 220 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 221 | 0 0 0 0 0 0 0 0 # 0 |
| 222 | |
| 223 | hash_to_phv_matrix = |
| 224 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 225 | 0 0 0 0 0 0 0 0 # 0 |
| 226 | |
| 227 | total action ram packing size = [0, 0, 0] |
| 228 | action_ram_packing: |
| 229 | action add_packet_in_hdr has [] |
| 230 | total action ram packing size = [0, 0, 0] |
| 231 | action_ram_packing: |
| 232 | action add_packet_in_hdr has [] |
| 233 | total action ram packing size = [0, 0, 0] |
| 234 | action_ram_packing: |
| 235 | action add_packet_in_hdr has [] |
| 236 | byte_enables = [] |
| 237 | After allocation of 32s, available_slots is [] |
| 238 | final packing is [] |
| 239 | byte_enables = [] |
| 240 | After allocation of 32s, available_slots is [] |
| 241 | final packing is [] |
| 242 | byte_enables = [] |
| 243 | After allocation of 32s, available_slots is [] |
| 244 | final packing is [] |
| 245 | Action Data SRAMs to use = 0 |
| 246 | TODO: Total RAMs use when put 0 bits in match overhead: 97 |
| 247 | TODO: Total RAMs use when put 0 bits in match overhead: 97 |
| 248 | ~~~~~~~~~~~~~~~~~~~~~ |
| 249 | Examining placing 8 bits in match overhead |
| 250 | ~~~~~~~~~~~~~~~~~~~~~ |
| 251 | Examining placing 16 bits in match overhead |
| 252 | ~~~~~~~~~~~~~~~~~~~~~ |
| 253 | Examining placing 24 bits in match overhead |
| 254 | ~~~~~~~~~~~~~~~~~~~~~ |
| 255 | Examining placing 32 bits in match overhead |
| 256 | |
| 257 | ########################################## |
| 258 | |
| 259 | Best Ram Usage is 97 rams |
| 260 | Best Immediate placement is 0 bits |
| 261 | |
| 262 | ########################################## |
| 263 | Call to decide_action_data_placement(stage=0, table=table0) |
| 264 | ########################################## |
| 265 | |
| 266 | |
| 267 | Max immediate bits used in any action is 0 bits. |
| 268 | Overhead bit width for table table0 is 3 bits. |
| 269 | Bits available in overhead for non-essential immediate data is 32 bits. |
| 270 | ~~~~~~~~~~~~~~~~~~~~~ |
| 271 | Examining placing 0 bits in match overhead |
| 272 | Overhead bit width for table table0 is 3 bits. |
| 273 | Overhead SRAMs to use = 1 |
| 274 | Entries requested = 512 and match entries get = 512 |
| 275 | ram_size_matrix = |
| 276 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 277 | 0 0 0 1 0 0 0 0 # 0 |
| 278 | 0 0 0 0 0 0 0 0 # 1 |
| 279 | 0 0 0 0 0 0 0 0 # 2 |
| 280 | |
| 281 | immediate_size_matrix = |
| 282 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 283 | 0 0 0 0 0 0 0 0 # 0 |
| 284 | 0 0 0 0 0 0 0 0 # 1 |
| 285 | 0 0 0 0 0 0 0 0 # 2 |
| 286 | |
| 287 | hash_to_phv_matrix = |
| 288 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 289 | 0 0 0 0 0 0 0 0 # 0 |
| 290 | 0 0 0 0 0 0 0 0 # 1 |
| 291 | 0 0 0 0 0 0 0 0 # 2 |
| 292 | |
| 293 | total action ram packing size = [16, 0, 0] |
| 294 | action_ram_packing: |
| 295 | action set_egress_port has [(16, 16, False)] |
| 296 | action send_to_cpu has [] |
| 297 | action _drop has [] |
| 298 | total action ram packing size = [16, 0, 0] |
| 299 | action_ram_packing: |
| 300 | action set_egress_port has [] |
| 301 | action send_to_cpu has [] |
| 302 | action _drop has [] |
| 303 | total action ram packing size = [16, 0, 0] |
| 304 | action_ram_packing: |
| 305 | action set_egress_port has [] |
| 306 | action send_to_cpu has [] |
| 307 | action _drop has [] |
| 308 | byte_enables = [1, 1] |
| 309 | Allocating Action Parameter Bus Byte 32 in stage 0 for Byte 0 of 16-bit constant |
| 310 | Allocating Action Parameter Bus Byte 33 in stage 0 for Byte 1 of 16-bit constant |
| 311 | Allocating Action Parameter Bus Byte 34 in stage 0 for Byte 0 of 16-bit constant |
| 312 | Allocating Action Parameter Bus Byte 35 in stage 0 for Byte 1 of 16-bit constant |
| 313 | After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)] |
| 314 | final packing is [(16, 16, False)] |
| 315 | final packing is [] |
| 316 | final packing is [] |
| 317 | byte_enables = [] |
| 318 | After allocation of 32s, available_slots is [] |
| 319 | final packing is [] |
| 320 | final packing is [] |
| 321 | final packing is [] |
| 322 | byte_enables = [] |
| 323 | After allocation of 32s, available_slots is [] |
| 324 | final packing is [] |
| 325 | final packing is [] |
| 326 | final packing is [] |
| 327 | Action Data SRAMs to use = 1 |
| 328 | TODO: Total RAMs use when put 0 bits in match overhead: 2 |
| 329 | TODO: Total RAMs use when put 0 bits in match overhead: 2 |
| 330 | ~~~~~~~~~~~~~~~~~~~~~ |
| 331 | Examining placing 8 bits in match overhead |
| 332 | ~~~~~~~~~~~~~~~~~~~~~ |
| 333 | Examining placing 16 bits in match overhead |
| 334 | Overhead bit width for table table0 is 3 bits. |
| 335 | Overhead SRAMs to use = 1 |
| 336 | Entries requested = 512 and match entries get = 512 |
| 337 | ram_size_matrix = |
| 338 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 339 | 0 0 0 0 0 0 0 0 # 0 |
| 340 | 0 0 0 0 0 0 0 0 # 1 |
| 341 | 0 0 0 0 0 0 0 0 # 2 |
| 342 | |
| 343 | immediate_size_matrix = |
| 344 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 345 | 0 0 0 1 0 0 0 0 # 0 |
| 346 | 0 0 0 0 0 0 0 0 # 1 |
| 347 | 0 0 0 0 0 0 0 0 # 2 |
| 348 | |
| 349 | hash_to_phv_matrix = |
| 350 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 351 | 0 0 0 0 0 0 0 0 # 0 |
| 352 | 0 0 0 0 0 0 0 0 # 1 |
| 353 | 0 0 0 0 0 0 0 0 # 2 |
| 354 | |
| 355 | total action ram packing size = [0, 0, 0] |
| 356 | action_ram_packing: |
| 357 | action set_egress_port has [] |
| 358 | action send_to_cpu has [] |
| 359 | action _drop has [] |
| 360 | total action ram packing size = [0, 16, 0] |
| 361 | action_ram_packing: |
| 362 | action set_egress_port has [(16, 16, False)] |
| 363 | action send_to_cpu has [] |
| 364 | action _drop has [] |
| 365 | total action ram packing size = [0, 16, 0] |
| 366 | action_ram_packing: |
| 367 | action set_egress_port has [] |
| 368 | action send_to_cpu has [] |
| 369 | action _drop has [] |
| 370 | byte_enables = [] |
| 371 | After allocation of 32s, available_slots is [] |
| 372 | final packing is [] |
| 373 | final packing is [] |
| 374 | final packing is [] |
| 375 | byte_enables = [1, 1] |
| 376 | Allocating Action Parameter Bus Byte 32 in stage 0 for Byte 0 of 16-bit constant |
| 377 | Allocating Action Parameter Bus Byte 33 in stage 0 for Byte 1 of 16-bit constant |
| 378 | Allocating Action Parameter Bus Byte 34 in stage 0 for Byte 0 of 16-bit constant |
| 379 | Allocating Action Parameter Bus Byte 35 in stage 0 for Byte 1 of 16-bit constant |
| 380 | After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)] |
| 381 | final packing is [(16, 16, False)] |
| 382 | final packing is [] |
| 383 | final packing is [] |
| 384 | byte_enables = [] |
| 385 | After allocation of 32s, available_slots is [] |
| 386 | final packing is [] |
| 387 | final packing is [] |
| 388 | final packing is [] |
| 389 | Action Data SRAMs to use = 0 |
| 390 | TODO: Total RAMs use when put 16 bits in match overhead: 1 |
| 391 | TODO: Total RAMs use when put 16 bits in match overhead: 1 |
| 392 | ~~~~~~~~~~~~~~~~~~~~~ |
| 393 | Examining placing 24 bits in match overhead |
| 394 | Overhead bit width for table table0 is 3 bits. |
| 395 | Overhead SRAMs to use = 1 |
| 396 | Entries requested = 512 and match entries get = 512 |
| 397 | ram_size_matrix = |
| 398 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 399 | 0 0 0 0 0 0 0 0 # 0 |
| 400 | 0 0 0 0 0 0 0 0 # 1 |
| 401 | 0 0 0 0 0 0 0 0 # 2 |
| 402 | |
| 403 | immediate_size_matrix = |
| 404 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 405 | 0 0 0 1 0 0 0 0 # 0 |
| 406 | 0 0 0 0 0 0 0 0 # 1 |
| 407 | 0 0 0 0 0 0 0 0 # 2 |
| 408 | |
| 409 | hash_to_phv_matrix = |
| 410 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 411 | 0 0 0 0 0 0 0 0 # 0 |
| 412 | 0 0 0 0 0 0 0 0 # 1 |
| 413 | 0 0 0 0 0 0 0 0 # 2 |
| 414 | |
| 415 | total action ram packing size = [0, 0, 0] |
| 416 | action_ram_packing: |
| 417 | action set_egress_port has [] |
| 418 | action send_to_cpu has [] |
| 419 | action _drop has [] |
| 420 | total action ram packing size = [0, 16, 0] |
| 421 | action_ram_packing: |
| 422 | action set_egress_port has [(16, 16, False)] |
| 423 | action send_to_cpu has [] |
| 424 | action _drop has [] |
| 425 | total action ram packing size = [0, 16, 0] |
| 426 | action_ram_packing: |
| 427 | action set_egress_port has [] |
| 428 | action send_to_cpu has [] |
| 429 | action _drop has [] |
| 430 | byte_enables = [] |
| 431 | After allocation of 32s, available_slots is [] |
| 432 | final packing is [] |
| 433 | final packing is [] |
| 434 | final packing is [] |
| 435 | byte_enables = [1, 1] |
| 436 | Allocating Action Parameter Bus Byte 32 in stage 0 for Byte 0 of 16-bit constant |
| 437 | Allocating Action Parameter Bus Byte 33 in stage 0 for Byte 1 of 16-bit constant |
| 438 | Allocating Action Parameter Bus Byte 34 in stage 0 for Byte 0 of 16-bit constant |
| 439 | Allocating Action Parameter Bus Byte 35 in stage 0 for Byte 1 of 16-bit constant |
| 440 | After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)] |
| 441 | final packing is [(16, 16, False)] |
| 442 | final packing is [] |
| 443 | final packing is [] |
| 444 | byte_enables = [] |
| 445 | After allocation of 32s, available_slots is [] |
| 446 | final packing is [] |
| 447 | final packing is [] |
| 448 | final packing is [] |
| 449 | Action Data SRAMs to use = 0 |
| 450 | TODO: Total RAMs use when put 24 bits in match overhead: 1 |
| 451 | TODO: Total RAMs use when put 24 bits in match overhead: 1 |
| 452 | ~~~~~~~~~~~~~~~~~~~~~ |
| 453 | Examining placing 32 bits in match overhead |
| 454 | Overhead bit width for table table0 is 3 bits. |
| 455 | Overhead SRAMs to use = 1 |
| 456 | Entries requested = 512 and match entries get = 512 |
| 457 | ram_size_matrix = |
| 458 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 459 | 0 0 0 0 0 0 0 0 # 0 |
| 460 | 0 0 0 0 0 0 0 0 # 1 |
| 461 | 0 0 0 0 0 0 0 0 # 2 |
| 462 | |
| 463 | immediate_size_matrix = |
| 464 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 465 | 0 0 0 1 0 0 0 0 # 0 |
| 466 | 0 0 0 0 0 0 0 0 # 1 |
| 467 | 0 0 0 0 0 0 0 0 # 2 |
| 468 | |
| 469 | hash_to_phv_matrix = |
| 470 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 471 | 0 0 0 0 0 0 0 0 # 0 |
| 472 | 0 0 0 0 0 0 0 0 # 1 |
| 473 | 0 0 0 0 0 0 0 0 # 2 |
| 474 | |
| 475 | total action ram packing size = [0, 0, 0] |
| 476 | action_ram_packing: |
| 477 | action set_egress_port has [] |
| 478 | action send_to_cpu has [] |
| 479 | action _drop has [] |
| 480 | total action ram packing size = [0, 16, 0] |
| 481 | action_ram_packing: |
| 482 | action set_egress_port has [(16, 16, False)] |
| 483 | action send_to_cpu has [] |
| 484 | action _drop has [] |
| 485 | total action ram packing size = [0, 16, 0] |
| 486 | action_ram_packing: |
| 487 | action set_egress_port has [] |
| 488 | action send_to_cpu has [] |
| 489 | action _drop has [] |
| 490 | byte_enables = [] |
| 491 | After allocation of 32s, available_slots is [] |
| 492 | final packing is [] |
| 493 | final packing is [] |
| 494 | final packing is [] |
| 495 | byte_enables = [1, 1] |
| 496 | Allocating Action Parameter Bus Byte 32 in stage 0 for Byte 0 of 16-bit constant |
| 497 | Allocating Action Parameter Bus Byte 33 in stage 0 for Byte 1 of 16-bit constant |
| 498 | Allocating Action Parameter Bus Byte 34 in stage 0 for Byte 0 of 16-bit constant |
| 499 | Allocating Action Parameter Bus Byte 35 in stage 0 for Byte 1 of 16-bit constant |
| 500 | After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)] |
| 501 | final packing is [(16, 16, False)] |
| 502 | final packing is [] |
| 503 | final packing is [] |
| 504 | byte_enables = [] |
| 505 | After allocation of 32s, available_slots is [] |
| 506 | final packing is [] |
| 507 | final packing is [] |
| 508 | final packing is [] |
| 509 | Action Data SRAMs to use = 0 |
| 510 | TODO: Total RAMs use when put 32 bits in match overhead: 1 |
| 511 | TODO: Total RAMs use when put 32 bits in match overhead: 1 |
| 512 | |
| 513 | ########################################## |
| 514 | |
| 515 | Best Ram Usage is 1 rams |
| 516 | Best Immediate placement is 16 bits |
| 517 | Cannot implement ingress_pkt in phase 0 resources because table does not have the correct condition |
| 518 | |
| 519 | ---------------------------------------------- |
| 520 | Call to Allocate P4 Table with table ingress_pkt__action__, number_entries = 1024, table id = None, and match type = exact |
| 521 | Allocating in stage 0 |
| 522 | ---------------------------------------------- |
| 523 | |
| 524 | ram_size_matrix = |
| 525 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 526 | 0 0 0 0 0 0 0 0 # 0 |
| 527 | |
| 528 | immediate_size_matrix = |
| 529 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 530 | 0 0 0 0 0 0 0 0 # 0 |
| 531 | |
| 532 | hash_to_phv_matrix = |
| 533 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 534 | 0 0 0 0 0 0 0 0 # 0 |
| 535 | |
| 536 | total action ram packing size = [0, 0, 0] |
| 537 | action_ram_packing: |
| 538 | action _packet_out has [] |
| 539 | total action ram packing size = [0, 0, 0] |
| 540 | action_ram_packing: |
| 541 | action _packet_out has [] |
| 542 | total action ram packing size = [0, 0, 0] |
| 543 | action_ram_packing: |
| 544 | action _packet_out has [] |
| 545 | byte_enables = [] |
| 546 | After allocation of 32s, available_slots is [] |
| 547 | final packing is [] |
| 548 | byte_enables = [] |
| 549 | After allocation of 32s, available_slots is [] |
| 550 | final packing is [] |
| 551 | byte_enables = [] |
| 552 | After allocation of 32s, available_slots is [] |
| 553 | final packing is [] |
| 554 | Allocating Action Logical Table ID 0 in stage 0 |
| 555 | |
| 556 | ---------------------------------------------- |
| 557 | Call to Allocate P4 Table with table ingress_pkt, number_entries = 1024, table id = None, and match type = exact |
| 558 | Allocating in stage 0 |
| 559 | ---------------------------------------------- |
| 560 | |
| 561 | Logical Table ID in stage 0 was not supplied by table placement for table ingress_pkt. |
| 562 | Allocating Logical Table ID 0 in stage 0 |
| 563 | Allocating Table Type ID 0 of type exact in stage 0 |
| 564 | Match Overhead: |
| 565 | Field --version_valid-- [3:0] (4 bits) |
| 566 | Field --instruction_address-- [1:0] (2 bits) |
| 567 | |
| 568 | Logical Table ID in stage 0 was not supplied by table placement for table ingress_pkt. |
| 569 | Allocating Logical Table ID 0 in stage 0 |
| 570 | Allocating Table Type ID 0 of type exact in stage 0 |
| 571 | Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}. |
| 572 | Match Table Resource Request is: |
| 573 | SRAM Resource Request for table ingress_pkt (of type match), with 0 ways wants 0 rams. |
| 574 | Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}. |
| 575 | For action _packet_out, formed micro_instruction: |
| 576 | Micro Instruction deposit-field for PHV Container 130 has bit width 23 |
| 577 | Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| 578 | Field Src1 [4:0] : 0x1 (5 bits in instruction bits [8:4]) |
| 579 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 580 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 581 | Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11]) |
| 582 | Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15]) |
| 583 | Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16]) |
| 584 | Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| 585 | |
| 586 | For action _packet_out, formed micro_instruction: |
| 587 | Micro Instruction deposit-field for PHV Container 67 has bit width 20 |
| 588 | Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0]) |
| 589 | Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4]) |
| 590 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 591 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 592 | Field high_bit [2:0] : 0x1 (3 bits in instruction bits [13:11]) |
| 593 | Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14]) |
| 594 | Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16]) |
| 595 | Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19]) |
| 596 | |
| 597 | Allocating Action ALU 2 (16 bits) in stage 0 for match table ingress_pkt's action _packet_out |
| 598 | Allocating Action ALU 3 (8 bits) in stage 0 for match table ingress_pkt's action _packet_out |
| 599 | Allocating VLIW Instruction : 0 in stage 0 for match table ingress_pkt's action _packet_out |
| 600 | |
| 601 | ---------------------------------------------- |
| 602 | Call to Allocate P4 Table with table table0__action__, number_entries = 512, table id = None, and match type = exact |
| 603 | Allocating in stage 1 |
| 604 | ---------------------------------------------- |
| 605 | |
| 606 | ram_size_matrix = |
| 607 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 608 | 0 0 0 0 0 0 0 0 # 0 |
| 609 | 0 0 0 0 0 0 0 0 # 1 |
| 610 | 0 0 0 0 0 0 0 0 # 2 |
| 611 | |
| 612 | immediate_size_matrix = |
| 613 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 614 | 0 0 0 1 0 0 0 0 # 0 |
| 615 | 0 0 0 0 0 0 0 0 # 1 |
| 616 | 0 0 0 0 0 0 0 0 # 2 |
| 617 | |
| 618 | hash_to_phv_matrix = |
| 619 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 620 | 0 0 0 0 0 0 0 0 # 0 |
| 621 | 0 0 0 0 0 0 0 0 # 1 |
| 622 | 0 0 0 0 0 0 0 0 # 2 |
| 623 | |
| 624 | total action ram packing size = [0, 0, 0] |
| 625 | action_ram_packing: |
| 626 | action set_egress_port has [] |
| 627 | action send_to_cpu has [] |
| 628 | action _drop has [] |
| 629 | total action ram packing size = [0, 16, 0] |
| 630 | action_ram_packing: |
| 631 | action set_egress_port has [(16, 16, False)] |
| 632 | action send_to_cpu has [] |
| 633 | action _drop has [] |
| 634 | total action ram packing size = [0, 16, 0] |
| 635 | action_ram_packing: |
| 636 | action set_egress_port has [] |
| 637 | action send_to_cpu has [] |
| 638 | action _drop has [] |
| 639 | byte_enables = [] |
| 640 | After allocation of 32s, available_slots is [] |
| 641 | final packing is [] |
| 642 | final packing is [] |
| 643 | final packing is [] |
| 644 | byte_enables = [1, 1] |
| 645 | Allocating Action Parameter Bus Byte 32 in stage 1 for Byte 0 of 16-bit constant |
| 646 | Allocating Action Parameter Bus Byte 33 in stage 1 for Byte 1 of 16-bit constant |
| 647 | Allocating Action Parameter Bus Byte 34 in stage 1 for Byte 0 of 16-bit constant |
| 648 | Allocating Action Parameter Bus Byte 35 in stage 1 for Byte 1 of 16-bit constant |
| 649 | After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)] |
| 650 | final packing is [(16, 16, False)] |
| 651 | final packing is [] |
| 652 | final packing is [] |
| 653 | byte_enables = [] |
| 654 | After allocation of 32s, available_slots is [] |
| 655 | final packing is [] |
| 656 | final packing is [] |
| 657 | final packing is [] |
| 658 | Allocating Action Logical Table ID 0 in stage 1 |
| 659 | |
| 660 | ---------------------------------------------- |
| 661 | Call to Allocate P4 Table with table table0_counter, number_entries = 512, table id = None, and match type = exact |
| 662 | Allocating in stage 1 |
| 663 | ---------------------------------------------- |
| 664 | |
| 665 | stat_stage_table referenced: direct |
| 666 | stat Table Resource Request is: |
| 667 | SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 668 | Sram Resource Request for P4 table table0_counter with handle 67108867 of type statistics in stage 1 |
| 669 | table_type : statistics |
| 670 | rams_for_width : 1 |
| 671 | use_stash : False |
| 672 | number_ways : 1 |
| 673 | way #0 |
| 674 | SRAM Request Group 0 |
| 675 | rams_for_depth : 2 |
| 676 | map_rams : 0 |
| 677 | way_number : 0 |
| 678 | ram_word_select_bits : 0 |
| 679 | ram_enable_select_bits : 0 |
| 680 | |
| 681 | |
| 682 | ---------------------------------------------- |
| 683 | Call to Allocate P4 Table with table table0, number_entries = 512, table id = None, and match type = ternary |
| 684 | Allocating in stage 1 |
| 685 | ---------------------------------------------- |
| 686 | |
| 687 | Logical Table ID in stage 1 was not supplied by table placement for table table0. |
| 688 | Allocating Logical Table ID 0 in stage 1 |
| 689 | Allocating Table Type ID 0 of type ternary in stage 1 |
| 690 | |
| 691 | ----------------------------------------- |
| 692 | Call to allocate_ternary_match_key_2 |
| 693 | ----------------------------------------- |
| 694 | Total crossbar bytes to allocate = 16 |
| 695 | Minimum key bytes required by this match key = 16 |
| 696 | Allocating: Byte 133 is of type ternary and member of group 0 with 1 bytes |
| 697 | version/valid in nibble 1 for table table0. for version/valid |
| 698 | {unused[6:0], ig_intr_md.ingress_port[8:8]}. |
| 699 | Allocating: Byte 128 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[7:0]}. |
| 700 | Allocating: Byte 129 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[15:8]}. |
| 701 | Allocating: Byte 130 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[23:16]}. |
| 702 | Allocating: Byte 131 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[31:24]}. |
| 703 | Allocating: Byte 132 is of type ternary and member of group 0 with 5 bytes. for {ethernet.dstAddr[15:8]}. |
| 704 | Allocating: Byte 134 is of type ternary and member of group 1 with 5 bytes. for {ethernet.dstAddr[31:24]}. |
| 705 | Allocating: Byte 135 is of type ternary and member of group 1 with 5 bytes. for {ethernet.dstAddr[39:32]}. |
| 706 | Allocating: Byte 136 is of type ternary and member of group 1 with 5 bytes. for {ethernet.etherType[7:0]}. |
| 707 | Allocating: Byte 137 is of type ternary and member of group 1 with 5 bytes. for {ethernet.dstAddr[23:16]}. |
| 708 | Allocating: Byte 138 is of type ternary and member of group 1 with 5 bytes. for {ethernet.srcAddr[47:40]}. |
| 709 | Allocating: Byte 139 is of type ternary and member of group 2 with 5 bytes. for {ethernet.etherType[15:8]}. |
| 710 | Allocating: Byte 140 is of type ternary and member of group 2 with 5 bytes. for {ig_intr_md.ingress_port[7:0]}. |
| 711 | Allocating: Byte 141 is of type ternary and member of group 2 with 5 bytes. for {ethernet.dstAddr[7:0]}. |
| 712 | Allocating: Byte 142 is of type ternary and member of group 2 with 5 bytes. for {ethernet.srcAddr[39:32]}. |
| 713 | Allocating: Byte 143 is of type ternary and member of group 2 with 5 bytes. for {ethernet.dstAddr[47:40]}. |
| 714 | Formed Ternary Match Key: |
| 715 | {--unused--[3:0], ethernet.dstAddr[47:40], ethernet.srcAddr[39:32], ethernet.dstAddr[7:0], ig_intr_md.ingress_port[7:0], ethernet.etherType[15:8], --version--[1:0], --unused--[1:0], ethernet.srcAddr[47:40], ethernet.dstAddr[23:16], ethernet.etherType[7:0], ethernet.dstAddr[39:24], --unused--[2:0], ig_intr_md.ingress_port[8:8], ethernet.dstAddr[15:8], ethernet.srcAddr[31:0]} |
| 716 | |
| 717 | --------------------------------------------- |
| 718 | Call to can_any_match_key_fields_be_shared(stage=1, table=table0) |
| 719 | --------------------------------------------- |
| 720 | Decided way to allocate for table table0 in stage 1 WAS non_shared |
| 721 | |
| 722 | ----------------------------------------- |
| 723 | Call to allocate_ternary_match_key_2 |
| 724 | ----------------------------------------- |
| 725 | Total crossbar bytes to allocate = 16 |
| 726 | Minimum key bytes required by this match key = 16 |
| 727 | Allocating: Byte 133 is of type ternary and member of group 0 with 1 bytes |
| 728 | version/valid in nibble 1 for table table0. for version/valid |
| 729 | {unused[6:0], ig_intr_md.ingress_port[8:8]}. |
| 730 | Allocating: Byte 128 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[7:0]}. |
| 731 | Allocating: Byte 129 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[15:8]}. |
| 732 | Allocating: Byte 130 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[23:16]}. |
| 733 | Allocating: Byte 131 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[31:24]}. |
| 734 | Allocating: Byte 132 is of type ternary and member of group 0 with 5 bytes. for {ethernet.dstAddr[15:8]}. |
| 735 | Allocating: Byte 134 is of type ternary and member of group 1 with 5 bytes. for {ethernet.dstAddr[31:24]}. |
| 736 | Allocating: Byte 135 is of type ternary and member of group 1 with 5 bytes. for {ethernet.dstAddr[39:32]}. |
| 737 | Allocating: Byte 136 is of type ternary and member of group 1 with 5 bytes. for {ethernet.etherType[7:0]}. |
| 738 | Allocating: Byte 137 is of type ternary and member of group 1 with 5 bytes. for {ethernet.dstAddr[23:16]}. |
| 739 | Allocating: Byte 138 is of type ternary and member of group 1 with 5 bytes. for {ethernet.srcAddr[47:40]}. |
| 740 | Allocating: Byte 139 is of type ternary and member of group 2 with 5 bytes. for {ethernet.etherType[15:8]}. |
| 741 | Allocating: Byte 140 is of type ternary and member of group 2 with 5 bytes. for {ig_intr_md.ingress_port[7:0]}. |
| 742 | Allocating: Byte 141 is of type ternary and member of group 2 with 5 bytes. for {ethernet.dstAddr[7:0]}. |
| 743 | Allocating: Byte 142 is of type ternary and member of group 2 with 5 bytes. for {ethernet.srcAddr[39:32]}. |
| 744 | Allocating: Byte 143 is of type ternary and member of group 2 with 5 bytes. for {ethernet.dstAddr[47:40]}. |
| 745 | Formed Ternary Match Key: |
| 746 | {--unused--[3:0], ethernet.dstAddr[47:40], ethernet.srcAddr[39:32], ethernet.dstAddr[7:0], ig_intr_md.ingress_port[7:0], ethernet.etherType[15:8], --version--[1:0], --unused--[1:0], ethernet.srcAddr[47:40], ethernet.dstAddr[23:16], ethernet.etherType[7:0], ethernet.dstAddr[39:24], --unused--[2:0], ig_intr_md.ingress_port[8:8], ethernet.dstAddr[15:8], ethernet.srcAddr[31:0]} |
| 747 | Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}. |
| 748 | Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}. |
| 749 | For action set_egress_port, formed micro_instruction: |
| 750 | Micro Instruction deposit-field for PHV Container 130 has bit width 23 |
| 751 | Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| 752 | Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4]) |
| 753 | Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9]) |
| 754 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 755 | Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11]) |
| 756 | Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15]) |
| 757 | Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16]) |
| 758 | Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| 759 | |
| 760 | Allocating Action ALU 2 (16 bits) in stage 1 for match table table0's action set_egress_port |
| 761 | Allocating VLIW Instruction : 0 in stage 1 for match table table0's action set_egress_port |
| 762 | For action send_to_cpu, formed micro_instruction: |
| 763 | Micro Instruction deposit-field for PHV Container 64 has bit width 20 |
| 764 | Field Src2 [3:0] : 0x0 (4 bits in instruction bits [3:0]) |
| 765 | Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4]) |
| 766 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 767 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 768 | Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11]) |
| 769 | Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14]) |
| 770 | Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16]) |
| 771 | Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19]) |
| 772 | |
| 773 | Allocating Action ALU 0 (8 bits) in stage 1 for match table table0's action send_to_cpu |
| 774 | Allocating VLIW Instruction : 1 in stage 1 for match table table0's action send_to_cpu |
| 775 | For action _drop, formed micro_instruction: |
| 776 | Micro Instruction deposit-field for PHV Container 68 has bit width 20 |
| 777 | Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0]) |
| 778 | Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4]) |
| 779 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 780 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 781 | Field high_bit [2:0] : 0x7 (3 bits in instruction bits [13:11]) |
| 782 | Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14]) |
| 783 | Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16]) |
| 784 | Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19]) |
| 785 | |
| 786 | Allocating Action ALU 4 (8 bits) in stage 1 for match table table0's action _drop |
| 787 | Allocating VLIW Instruction : 1 in stage 1 for match table table0's action _drop |
| 788 | Ternary table Pack Format = |
| 789 | Pack Format: |
| 790 | table_word_width: 141 |
| 791 | memory_word_width: 47 |
| 792 | entries_per_table_word: 1 |
| 793 | number_memory_units_per_table_word: 3 |
| 794 | entry_list: [ |
| 795 | entry_number : 0 |
| 796 | field_list : [ |
| 797 | ] |
| 798 | Field --tcam_parity_2-- [1:0] : in bits [140:139] |
| 799 | Field --unused-- [3:0] : in bits [138:135] |
| 800 | Field ethernet.dstAddr [47:40] : in bits [134:127] |
| 801 | Field ethernet.srcAddr [39:32] : in bits [126:119] |
| 802 | Field ethernet.dstAddr [7:0] : in bits [118:111] |
| 803 | Field ig_intr_md.ingress_port [7:0] : in bits [110:103] |
| 804 | Field ethernet.etherType [15:8] : in bits [102:95] |
| 805 | Field --tcam_payload_2-- [0:0] : in bits [94:94] |
| 806 | Field --tcam_parity_1-- [1:0] : in bits [93:92] |
| 807 | Field --version-- [1:0] : in bits [91:90] |
| 808 | Field --unused-- [1:0] : in bits [89:88] |
| 809 | Field ethernet.srcAddr [47:40] : in bits [87:80] |
| 810 | Field ethernet.dstAddr [23:16] : in bits [79:72] |
| 811 | Field ethernet.etherType [7:0] : in bits [71:64] |
| 812 | Field ethernet.dstAddr [39:24] : in bits [63:48] |
| 813 | Field --tcam_payload_1-- [0:0] : in bits [47:47] |
| 814 | Field --tcam_parity_0-- [1:0] : in bits [46:45] |
| 815 | Field --unused-- [2:0] : in bits [44:42] |
| 816 | Field ig_intr_md.ingress_port [8:8] : in bits [41:41] |
| 817 | Field ethernet.dstAddr [15:8] : in bits [40:33] |
| 818 | Field ethernet.srcAddr [31:0] : in bits [32:1] |
| 819 | Field --tcam_payload_0-- [0:0] : in bits [0:0] |
| 820 | ] |
| 821 | |
| 822 | |
| 823 | ---------------------------------------------- |
| 824 | Call to Allocate P4 Table with table ingress_port_count_table__action__, number_entries = 1024, table id = None, and match type = exact |
| 825 | Allocating in stage 2 |
| 826 | ---------------------------------------------- |
| 827 | |
| 828 | ram_size_matrix = |
| 829 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 830 | 0 0 0 0 0 0 0 0 # 0 |
| 831 | |
| 832 | immediate_size_matrix = |
| 833 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 834 | 0 0 0 0 0 0 0 0 # 0 |
| 835 | |
| 836 | hash_to_phv_matrix = |
| 837 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 838 | 0 0 0 0 0 0 0 0 # 0 |
| 839 | |
| 840 | total action ram packing size = [0, 0, 0] |
| 841 | action_ram_packing: |
| 842 | action count_ingress has [] |
| 843 | total action ram packing size = [0, 0, 0] |
| 844 | action_ram_packing: |
| 845 | action count_ingress has [] |
| 846 | total action ram packing size = [0, 0, 0] |
| 847 | action_ram_packing: |
| 848 | action count_ingress has [] |
| 849 | byte_enables = [] |
| 850 | After allocation of 32s, available_slots is [] |
| 851 | final packing is [] |
| 852 | byte_enables = [] |
| 853 | After allocation of 32s, available_slots is [] |
| 854 | final packing is [] |
| 855 | byte_enables = [] |
| 856 | After allocation of 32s, available_slots is [] |
| 857 | final packing is [] |
| 858 | Allocating Action Logical Table ID 0 in stage 2 |
| 859 | |
| 860 | ---------------------------------------------- |
| 861 | Call to Allocate P4 Table with table ingress_port_counter, number_entries = 254, table id = None, and match type = exact |
| 862 | Allocating in stage 2 |
| 863 | ---------------------------------------------- |
| 864 | |
| 865 | stat_stage_table referenced: indirect |
| 866 | stat Table Resource Request is: |
| 867 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 868 | Sram Resource Request for P4 table ingress_port_counter with handle 67108865 of type statistics in stage 2 |
| 869 | table_type : statistics |
| 870 | rams_for_width : 1 |
| 871 | use_stash : False |
| 872 | number_ways : 1 |
| 873 | way #0 |
| 874 | SRAM Request Group 0 |
| 875 | rams_for_depth : 2 |
| 876 | map_rams : 0 |
| 877 | way_number : 0 |
| 878 | ram_word_select_bits : 0 |
| 879 | ram_enable_select_bits : 0 |
| 880 | |
| 881 | |
| 882 | ---------------------------------------------- |
| 883 | Call to Allocate P4 Table with table ingress_port_count_table, number_entries = 1024, table id = None, and match type = exact |
| 884 | Allocating in stage 2 |
| 885 | ---------------------------------------------- |
| 886 | |
| 887 | Logical Table ID in stage 2 was not supplied by table placement for table ingress_port_count_table. |
| 888 | Allocating Logical Table ID 0 in stage 2 |
| 889 | Allocating Table Type ID 0 of type exact in stage 2 |
| 890 | Match Overhead: |
| 891 | Field --version_valid-- [3:0] (4 bits) |
| 892 | Field --instruction_address-- [1:0] (2 bits) |
| 893 | Field --statistics_pointer-- [19:0] (20 bits) |
| 894 | |
| 895 | Logical Table ID in stage 2 was not supplied by table placement for table ingress_port_count_table. |
| 896 | Allocating Logical Table ID 0 in stage 2 |
| 897 | Allocating Table Type ID 0 of type exact in stage 2 |
| 898 | Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}. |
| 899 | Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}. |
| 900 | Match Table Resource Request is: |
| 901 | SRAM Resource Request for table ingress_port_count_table (of type match), with 0 ways wants 0 rams. |
| 902 | Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}. |
| 903 | Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}. |
| 904 | No micro instructions needed for action count_ingress executed from table ingress_port_count_table. |
| 905 | Allocating Action ALU 0 (32 bits) in stage 2 for match table ingress_port_count_table's action count_ingress |
| 906 | Allocating VLIW Instruction : 0 in stage 2 for match table ingress_port_count_table's action count_ingress |
| 907 | |
| 908 | ---------------------------------------------- |
| 909 | Call to Allocate P4 Table with table egress_port_count_table__action__, number_entries = 1024, table id = None, and match type = exact |
| 910 | Allocating in stage 2 |
| 911 | ---------------------------------------------- |
| 912 | |
| 913 | ram_size_matrix = |
| 914 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 915 | 0 0 0 0 0 0 0 0 # 0 |
| 916 | |
| 917 | immediate_size_matrix = |
| 918 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 919 | 0 0 0 0 0 0 0 0 # 0 |
| 920 | |
| 921 | hash_to_phv_matrix = |
| 922 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 923 | 0 0 0 0 0 0 0 0 # 0 |
| 924 | |
| 925 | total action ram packing size = [0, 0, 0] |
| 926 | action_ram_packing: |
| 927 | action count_egress has [] |
| 928 | total action ram packing size = [0, 0, 0] |
| 929 | action_ram_packing: |
| 930 | action count_egress has [] |
| 931 | total action ram packing size = [0, 0, 0] |
| 932 | action_ram_packing: |
| 933 | action count_egress has [] |
| 934 | byte_enables = [] |
| 935 | After allocation of 32s, available_slots is [] |
| 936 | final packing is [] |
| 937 | byte_enables = [] |
| 938 | After allocation of 32s, available_slots is [] |
| 939 | final packing is [] |
| 940 | byte_enables = [] |
| 941 | After allocation of 32s, available_slots is [] |
| 942 | final packing is [] |
| 943 | Allocating Action Logical Table ID 1 in stage 2 |
| 944 | |
| 945 | ---------------------------------------------- |
| 946 | Call to Allocate P4 Table with table egress_port_counter, number_entries = 254, table id = None, and match type = exact |
| 947 | Allocating in stage 2 |
| 948 | ---------------------------------------------- |
| 949 | |
| 950 | stat_stage_table referenced: indirect |
| 951 | stat Table Resource Request is: |
| 952 | SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 953 | Sram Resource Request for P4 table egress_port_counter with handle 67108866 of type statistics in stage 2 |
| 954 | table_type : statistics |
| 955 | rams_for_width : 1 |
| 956 | use_stash : False |
| 957 | number_ways : 1 |
| 958 | way #0 |
| 959 | SRAM Request Group 0 |
| 960 | rams_for_depth : 2 |
| 961 | map_rams : 0 |
| 962 | way_number : 0 |
| 963 | ram_word_select_bits : 0 |
| 964 | ram_enable_select_bits : 0 |
| 965 | |
| 966 | Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}. |
| 967 | Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}. |
| 968 | |
| 969 | ---------------------------------------------- |
| 970 | Call to Allocate P4 Table with table egress_port_count_table, number_entries = 1024, table id = None, and match type = exact |
| 971 | Allocating in stage 2 |
| 972 | ---------------------------------------------- |
| 973 | |
| 974 | Logical Table ID in stage 2 was not supplied by table placement for table egress_port_count_table. |
| 975 | Allocating Logical Table ID 1 in stage 2 |
| 976 | Allocating Table Type ID 1 of type exact in stage 2 |
| 977 | Match Overhead: |
| 978 | Field --version_valid-- [3:0] (4 bits) |
| 979 | Field --statistics_pointer-- [19:0] (20 bits) |
| 980 | |
| 981 | Logical Table ID in stage 2 was not supplied by table placement for table egress_port_count_table. |
| 982 | Allocating Logical Table ID 1 in stage 2 |
| 983 | Allocating Table Type ID 1 of type exact in stage 2 |
| 984 | Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}. |
| 985 | Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}. |
| 986 | Match Table Resource Request is: |
| 987 | SRAM Resource Request for table egress_port_count_table (of type match), with 0 ways wants 0 rams. |
| 988 | Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}. |
| 989 | Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}. |
| 990 | No micro instructions needed for action count_egress executed from table egress_port_count_table. |
| 991 | Allocating Action ALU 0 (32 bits) in stage 2 for match table egress_port_count_table's action count_egress |
| 992 | Allocating VLIW Instruction : 0 in stage 2 for match table egress_port_count_table's action count_egress |
| 993 | |
| 994 | ---------------------------------------------- |
| 995 | Call to Allocate P4 Table with table egress_pkt__action__, number_entries = 1024, table id = None, and match type = exact |
| 996 | Allocating in stage 0 |
| 997 | ---------------------------------------------- |
| 998 | |
| 999 | ram_size_matrix = |
| 1000 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 1001 | 0 0 0 0 0 0 0 0 # 0 |
| 1002 | |
| 1003 | immediate_size_matrix = |
| 1004 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 1005 | 0 0 0 0 0 0 0 0 # 0 |
| 1006 | |
| 1007 | hash_to_phv_matrix = |
| 1008 | (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True) |
| 1009 | 0 0 0 0 0 0 0 0 # 0 |
| 1010 | |
| 1011 | total action ram packing size = [0, 0, 0] |
| 1012 | action_ram_packing: |
| 1013 | action add_packet_in_hdr has [] |
| 1014 | total action ram packing size = [0, 0, 0] |
| 1015 | action_ram_packing: |
| 1016 | action add_packet_in_hdr has [] |
| 1017 | total action ram packing size = [0, 0, 0] |
| 1018 | action_ram_packing: |
| 1019 | action add_packet_in_hdr has [] |
| 1020 | byte_enables = [] |
| 1021 | After allocation of 32s, available_slots is [] |
| 1022 | final packing is [] |
| 1023 | byte_enables = [] |
| 1024 | After allocation of 32s, available_slots is [] |
| 1025 | final packing is [] |
| 1026 | byte_enables = [] |
| 1027 | After allocation of 32s, available_slots is [] |
| 1028 | final packing is [] |
| 1029 | Allocating Action Logical Table ID 1 in stage 0 |
| 1030 | |
| 1031 | ---------------------------------------------- |
| 1032 | Call to Allocate P4 Table with table egress_pkt, number_entries = 1024, table id = None, and match type = exact |
| 1033 | Allocating in stage 0 |
| 1034 | ---------------------------------------------- |
| 1035 | |
| 1036 | Logical Table ID in stage 0 was not supplied by table placement for table egress_pkt. |
| 1037 | Allocating Logical Table ID 1 in stage 0 |
| 1038 | Allocating Table Type ID 1 of type exact in stage 0 |
| 1039 | Match Overhead: |
| 1040 | Field --version_valid-- [3:0] (4 bits) |
| 1041 | Field --instruction_address-- [1:0] (2 bits) |
| 1042 | |
| 1043 | Logical Table ID in stage 0 was not supplied by table placement for table egress_pkt. |
| 1044 | Allocating Logical Table ID 1 in stage 0 |
| 1045 | Allocating Table Type ID 1 of type exact in stage 0 |
| 1046 | Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.copy_to_cpu[0:0]}. |
| 1047 | Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}. |
| 1048 | Match Table Resource Request is: |
| 1049 | SRAM Resource Request for table egress_pkt (of type match), with 0 ways wants 0 rams. |
| 1050 | Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.copy_to_cpu[0:0]}. |
| 1051 | Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}. |
| 1052 | For action add_packet_in_hdr, formed micro_instruction: |
| 1053 | Micro Instruction deposit-field for PHV Container 82 has bit width 20 |
| 1054 | Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| 1055 | Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4]) |
| 1056 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 1057 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 1058 | Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11]) |
| 1059 | Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14]) |
| 1060 | Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16]) |
| 1061 | Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19]) |
| 1062 | |
| 1063 | For action add_packet_in_hdr, formed micro_instruction: |
| 1064 | Micro Instruction deposit-field for PHV Container 145 has bit width 23 |
| 1065 | Field Src2 [3:0] : 0x1 (4 bits in instruction bits [3:0]) |
| 1066 | Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4]) |
| 1067 | Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| 1068 | Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| 1069 | Field high_bit [3:0] : 0xf (4 bits in instruction bits [14:11]) |
| 1070 | Field low_bit_lo [0:0] : 0x1 (1 bits in instruction bits [15:15]) |
| 1071 | Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16]) |
| 1072 | Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20]) |
| 1073 | |
| 1074 | Allocating Action ALU 18 (8 bits) in stage 0 for match table egress_pkt's action add_packet_in_hdr |
| 1075 | Allocating Action ALU 17 (16 bits) in stage 0 for match table egress_pkt's action add_packet_in_hdr |
| 1076 | Allocating VLIW Instruction : 0 in stage 0 for match table egress_pkt's action add_packet_in_hdr |
| 1077 | Cannot find table object for 'egress_port_count_table_always_true_condition'. |
| 1078 | Cannot find table object for 'egress_port_count_table_always_true_condition'. |
| 1079 | Cannot find table object for 'egress_port_count_table_always_true_condition'. |
| 1080 | Cannot find table object for 'egress_port_count_table_always_true_condition'. |
| 1081 | Cannot find table object for 'egress_port_count_table_always_true_condition'. |
| 1082 | Cannot find table object for 'egress_port_count_table_always_true_condition'. |
| 1083 | Cannot find table object for 'egress_port_count_table_always_true_condition'. |
| 1084 | Cannot find table object for 'egress_port_count_table_always_true_condition'. |
| 1085 | Cannot find table object for 'egress_port_count_table_always_true_condition'. |
| 1086 | Cannot find table object for 'egress_port_count_table_always_true_condition'. |
| 1087 | Cannot find table object for 'egress_port_count_table_always_true_condition'. |
| 1088 | Field ig_intr_md_for_tm.ucast_egress_port not contiguous on gateway input |
| 1089 | Field ig_intr_md_for_tm.ucast_egress_port not contiguous on gateway input |
| 1090 | Writing configuration registers: regs.match_action_stage.00 |
| 1091 | Writing configuration registers: regs.match_action_stage.01 |
| 1092 | Writing configuration registers: regs.match_action_stage.02 |
| 1093 | Writing configuration registers: regs.match_action_stage.03 |
| 1094 | Writing configuration registers: regs.match_action_stage.04 |
| 1095 | Writing configuration registers: regs.match_action_stage.05 |
| 1096 | Writing configuration registers: regs.match_action_stage.06 |
| 1097 | Writing configuration registers: regs.match_action_stage.07 |
| 1098 | Writing configuration registers: regs.match_action_stage.08 |
| 1099 | Writing configuration registers: regs.match_action_stage.09 |
| 1100 | Writing configuration registers: regs.match_action_stage.0a |
| 1101 | Writing configuration registers: regs.match_action_stage.0b |