| Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame^] | 1 | +---------------------------------------------------------------------+ |
| 2 | | Log file: mau.gw.log | |
| 3 | | Compiler version: 5.1.0 (fca32d1) | |
| 4 | | Created on: Thu Sep 7 13:56:08 2017 | |
| 5 | +---------------------------------------------------------------------+ |
| 6 | |
| 7 | cond _condition_0: valid packet_out_hdr |
| 8 | valid packet_out_hdr |
| 9 | ! not valid packet_out_hdr |
| 10 | cond _condition_0 can be gateway (1+0)x1 |
| 11 | cond !_condition_0 can be gateway (1+0)x1 |
| 12 | _condition_0 is gateway for ingress_pkt |
| 13 | cond _condition_1: not valid packet_out_hdr |
| 14 | not valid packet_out_hdr |
| 15 | ! not not valid packet_out_hdr |
| 16 | cond _condition_1 can be gateway (1+0)x1 |
| 17 | cond !_condition_1 can be gateway (1+0)x1 |
| 18 | _condition_1 is gateway for table0 |
| 19 | cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 254 |
| 20 | ig_intr_md_for_tm.ucast_egress_port < 254 |
| 21 | ! ig_intr_md_for_tm.ucast_egress_port >= 254 |
| 22 | cond _condition_2 can be gateway (9+0)x1 |
| 23 | cond !_condition_2 can be gateway (9+0)x1 |
| 24 | _condition_2 is gateway for ingress_port_count_table |
| 25 | cond _condition_3: ig_intr_md_for_tm.copy_to_cpu == 1 |
| 26 | ig_intr_md_for_tm.copy_to_cpu == 1 |
| 27 | ! ig_intr_md_for_tm.copy_to_cpu != 1 |
| 28 | cond _condition_3 can be gateway (0+1)x1 |
| 29 | cond !_condition_3 can be gateway (0+1)x2 |
| 30 | _condition_3 is gateway for egress_pkt |
| 31 | fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f5dd974c1d0>]) and and xor_fields is OrderedSet() |
| 32 | fields = OrderedSet() and and xor_fields is OrderedSet() |
| 33 | fields = OrderedSet() and and xor_fields is OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f5dd974c490>]) |
| 34 | fields = OrderedSet() and and xor_fields is OrderedSet() |
| 35 | cond _condition_0: valid packet_out_hdr |
| 36 | valid packet_out_hdr |
| 37 | ! not valid packet_out_hdr |
| 38 | cond _condition_0 can be gateway (1+0)x1 |
| 39 | cond !_condition_0 can be gateway (1+0)x1 |
| 40 | _condition_0 is gateway for ingress_pkt |
| 41 | cond _condition_1: not valid packet_out_hdr |
| 42 | not valid packet_out_hdr |
| 43 | ! not not valid packet_out_hdr |
| 44 | cond _condition_1 can be gateway (1+0)x1 |
| 45 | cond !_condition_1 can be gateway (1+0)x1 |
| 46 | _condition_1 is gateway for table0 |
| 47 | cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 254 |
| 48 | ig_intr_md_for_tm.ucast_egress_port < 254 |
| 49 | ! ig_intr_md_for_tm.ucast_egress_port >= 254 |
| 50 | cond _condition_2 can be gateway (9+0)x1 |
| 51 | cond !_condition_2 can be gateway (9+0)x1 |
| 52 | _condition_2 is gateway for ingress_port_count_table |
| 53 | cond _condition_3: ig_intr_md_for_tm.copy_to_cpu == 1 |
| 54 | ig_intr_md_for_tm.copy_to_cpu == 1 |
| 55 | ! ig_intr_md_for_tm.copy_to_cpu != 1 |
| 56 | cond _condition_3 can be gateway (0+1)x1 |
| 57 | cond !_condition_3 can be gateway (0+1)x2 |
| 58 | _condition_3 is gateway for egress_pkt |
| 59 | fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f5dd974c1d0>]) and and xor_fields is OrderedSet() |
| 60 | fields = OrderedSet() and and xor_fields is OrderedSet() |
| 61 | fields = OrderedSet() and and xor_fields is OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f5dd974c490>]) |
| 62 | fields = OrderedSet() and and xor_fields is OrderedSet() |
| 63 | cond _condition_0: valid packet_out_hdr |
| 64 | valid packet_out_hdr |
| 65 | ! not valid packet_out_hdr |
| 66 | cond _condition_0 can be gateway (1+0)x1 |
| 67 | cond !_condition_0 can be gateway (1+0)x1 |
| 68 | _condition_0 is gateway for ingress_pkt |
| 69 | cond _condition_1: not valid packet_out_hdr |
| 70 | not valid packet_out_hdr |
| 71 | ! not not valid packet_out_hdr |
| 72 | cond _condition_1 can be gateway (1+0)x1 |
| 73 | cond !_condition_1 can be gateway (1+0)x1 |
| 74 | _condition_1 is gateway for table0 |
| 75 | cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 254 |
| 76 | ig_intr_md_for_tm.ucast_egress_port < 254 |
| 77 | ! ig_intr_md_for_tm.ucast_egress_port >= 254 |
| 78 | cond _condition_2 can be gateway (9+0)x1 |
| 79 | cond !_condition_2 can be gateway (9+0)x1 |
| 80 | _condition_2 is gateway for ingress_port_count_table |
| 81 | cond _condition_3: ig_intr_md_for_tm.copy_to_cpu == 1 |
| 82 | ig_intr_md_for_tm.copy_to_cpu == 1 |
| 83 | ! ig_intr_md_for_tm.copy_to_cpu != 1 |
| 84 | cond _condition_3 can be gateway (0+1)x1 |
| 85 | cond !_condition_3 can be gateway (0+1)x2 |
| 86 | _condition_3 is gateway for egress_pkt |
| 87 | fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f5dd974c1d0>]) and and xor_fields is OrderedSet() |
| 88 | fields = OrderedSet() and and xor_fields is OrderedSet() |
| 89 | fields = OrderedSet() and and xor_fields is OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f5dd974c490>]) |
| 90 | fields = OrderedSet() and and xor_fields is OrderedSet() |
| 91 | cond _always_true: True == True |
| 92 | True |
| 93 | ! False |
| 94 | --> Stage Gateway Table for condition _condition_0 in stage 0 |
| 95 | T -> ingress_pkt(0), F -> _condition_1(16) |
| 96 | building tcam for GatewayTest('valid packet_out_hdr') |
| 97 | adding line (match=200000000 mask=200000000 T) |
| 98 | tcam data: [(match=200000000 mask=200000000 T)] |
| 99 | final.tcam: [(match=200000000 mask=200000000 T)], miss=False |
| 100 | --> Stage Gateway Table for condition _condition_3 in stage 0 |
| 101 | T -> egress_pkt(1), F -> None(255) |
| 102 | building tcam for GatewayTest('ig_intr_md_for_tm.copy_to_cpu == 1') |
| 103 | adding line (match=100000000 mask=100000000 T) |
| 104 | tcam data: [(match=100000000 mask=100000000 T)] |
| 105 | final.tcam: [(match=100000000 mask=100000000 T)], miss=False |
| 106 | --> Stage Gateway Table for condition _condition_1 in stage 1 |
| 107 | T -> table0(16), F -> _condition_2(32) |
| 108 | building tcam for GatewayTest('not valid packet_out_hdr') |
| 109 | adding line (match=0 mask=100000000 T) |
| 110 | tcam data: [(match=0 mask=100000000 T)] |
| 111 | final.tcam: [(match=0 mask=100000000 T)], miss=False |
| 112 | --> Stage Gateway Table for condition _condition_2 in stage 2 |
| 113 | T -> ingress_port_count_table(32), F -> None(255) |
| 114 | building tcam for GatewayTest('ig_intr_md_for_tm.ucast_egress_port < 254') |
| 115 | adding line (range=[ffff ffff 3fff] match=0 mask=0 T) |
| 116 | adding line (range=[ffff 7fff ffff] match=0 mask=0 T) |
| 117 | adding line (range=[0 ffff ffff] match=0 mask=0 T) |
| 118 | tcam data: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[0 ffff ffff] match=0 mask=0 T)] |
| 119 | final.tcam: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[0 ffff ffff] match=0 mask=0 T)], miss=False |
| 120 | --> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 2 |
| 121 | T -> egress_port_count_table(33), F -> egress_port_count_table(33) |
| 122 | building tcam for GatewayTest('True') |
| 123 | adding line (match=0 mask=0 T) |
| 124 | tcam data: [(match=0 mask=0 T)] |
| 125 | final.tcam: [(match=0 mask=0 T)], miss=False |