Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 1 | +---------------------------------------------------------------------+ |
| 2 | | Log file: mau.sram.log | |
| 3 | | Compiler version: 5.1.0 (fca32d1) | |
Carmelo Cascone | 133c7b1 | 2017-09-13 15:36:08 +0200 | [diff] [blame] | 4 | | Created on: Wed Sep 13 12:57:41 2017 | |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 5 | +---------------------------------------------------------------------+ |
| 6 | |
| 7 | |
| 8 | |
| 9 | ======================================================= |
| 10 | |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 11 | calling allocate and add with SRAM Resource Request for table table0__action__ (of type action), with 1 ways wants 1 rams. (open-all=False, synth_two_port_first=False) |
| 12 | ======================================================= |
| 13 | |
| 14 | Requesting to use 1 RAMs and have 80 available. |
| 15 | Requesting to use 0 Map RAMs and have 48 available. |
| 16 | |
| 17 | ======================================================== |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 18 | Run Placement on Request List of size 1 in stage 0 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 19 | open_up_all_for_match=False |
| 20 | synth_two_port_first=False |
| 21 | ======================================================== |
| 22 | |
| 23 | Match Rams Need is 0 |
| 24 | Algorithmic TCAM Match RAMs Need is 0 |
| 25 | Other Rams Need is 1 |
| 26 | |
| 27 | +========================================= |
| 28 | | Placing algorithmic tcam |
| 29 | +========================================= |
| 30 | |
| 31 | sorted algorithmic tcam requests: (0) |
| 32 | |
| 33 | |
| 34 | ------------------------------------- |
| 35 | Columns need for match is 0 |
| 36 | columns for width is 0 |
| 37 | other columns is 1 |
| 38 | reserved columns is 9 |
| 39 | reserved columns for tind 0 |
| 40 | reserved columns for stateful 0 |
| 41 | Ternary Indirection Rams Need is 0 |
| 42 | Depth sorted requested |
| 43 | Requesting to use 0 RAMs and have 32 available. |
| 44 | Result bus only needs (0): |
| 45 | |
| 46 | +========================================= |
| 47 | | Placing action/stats/meters/selection |
| 48 | +========================================= |
| 49 | |
| 50 | Requesting to use 1 RAMs and have 80 available. |
| 51 | SRAM Resource Request for table table0__action__ (of type action), with 1 ways wants 1 rams. |
| 52 | NO Spill Required off of logical row 15 for SRAM Resource Request for table table0__action__ (of type action), with 1 ways wants 1 rams. |
| 53 | |
| 54 | call to place_table_on_logical_row --- logical row 15 and rams to place is 1 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 55 | Allocating: SRAM: Row 7 Col 6 in stage 0 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 56 | Allocating: Ram Data Bus ActionR 7 right is 128 bits in stage 0 for table0__action__. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 57 | Depth sorted idletime requests: |
| 58 | |
| 59 | |
| 60 | ======================================================= |
| 61 | |
| 62 | calling allocate and add with SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
| 63 | ======================================================= |
| 64 | |
| 65 | Requesting to use 2 RAMs and have 79 available. |
| 66 | Requesting to use 0 Map RAMs and have 48 available. |
| 67 | |
| 68 | ======================================================== |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 69 | Run Placement on Request List of size 2 in stage 0 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 70 | open_up_all_for_match=False |
| 71 | synth_two_port_first=False |
| 72 | ======================================================== |
| 73 | |
| 74 | Match Rams Need is 0 |
| 75 | Algorithmic TCAM Match RAMs Need is 0 |
| 76 | Other Rams Need is 3 |
| 77 | |
| 78 | +========================================= |
| 79 | | Placing algorithmic tcam |
| 80 | +========================================= |
| 81 | |
| 82 | sorted algorithmic tcam requests: (0) |
| 83 | |
| 84 | |
| 85 | ------------------------------------- |
| 86 | Columns need for match is 0 |
| 87 | columns for width is 0 |
| 88 | other columns is 1 |
| 89 | reserved columns is 9 |
| 90 | reserved columns for tind 0 |
| 91 | reserved columns for stateful 1 |
| 92 | Ternary Indirection Rams Need is 0 |
| 93 | Depth sorted requested |
| 94 | Requesting to use 0 RAMs and have 32 available. |
| 95 | Result bus only needs (0): |
| 96 | |
| 97 | +========================================= |
| 98 | | Placing action/stats/meters/selection |
| 99 | +========================================= |
| 100 | |
| 101 | Requesting to use 3 RAMs and have 80 available. |
| 102 | SRAM Resource Request for table table0__action__ (of type action), with 1 ways wants 1 rams. |
| 103 | SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 104 | NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 105 | |
| 106 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 107 | Allocating: Statistics ALU 6 on right (128 bits) in stage 0 for table table0_counter. |
| 108 | Allocating: SRAM: Row 6 Col 6 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 109 | Allocating: Map RAM: Row 6 Unit 0 in stage 0 for table0_counter. |
| 110 | Allocating: SRAM: Row 6 Col 7 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 111 | Allocating: Map RAM: Row 6 Unit 1 in stage 0 for table0_counter. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 112 | |
| 113 | call to place_table_on_logical_row --- logical row 13 and rams to place is 1 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 114 | Allocating: SRAM: Row 6 Col 8 in stage 0 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 115 | Allocating: Ram Data Bus ActionR 6 right is 128 bits in stage 0 |
| 116 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 0 for table0_counter. |
| 117 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 0 for table0_counter. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 118 | Depth sorted idletime requests: |
| 119 | |
| 120 | |
| 121 | ======================================================= |
| 122 | |
| 123 | calling allocate and add with SRAM Resource Request for table table0 (of type ternary_indirection), with 1 ways wants 1 rams. (open-all=False, synth_two_port_first=False) |
| 124 | ======================================================= |
| 125 | |
| 126 | Requesting to use 1 RAMs and have 77 available. |
| 127 | Requesting to use 0 Map RAMs and have 46 available. |
| 128 | |
| 129 | ======================================================== |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 130 | Run Placement on Request List of size 3 in stage 0 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 131 | open_up_all_for_match=False |
| 132 | synth_two_port_first=False |
| 133 | ======================================================== |
| 134 | |
| 135 | Match Rams Need is 0 |
| 136 | Algorithmic TCAM Match RAMs Need is 0 |
| 137 | Other Rams Need is 4 |
| 138 | |
| 139 | +========================================= |
| 140 | | Placing algorithmic tcam |
| 141 | +========================================= |
| 142 | |
| 143 | sorted algorithmic tcam requests: (0) |
| 144 | |
| 145 | |
| 146 | ------------------------------------- |
| 147 | Columns need for match is 0 |
| 148 | columns for width is 0 |
| 149 | other columns is 1 |
| 150 | reserved columns is 9 |
| 151 | reserved columns for tind 1 |
| 152 | reserved columns for stateful 1 |
| 153 | Ternary Indirection Rams Need is 1 |
| 154 | Depth sorted requested |
| 155 | Group 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 156 | Sram Resource Request for P4 table table0 with handle 16777220 of type ternary_indirection in stage 0 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 157 | table_type : ternary_indirection |
| 158 | rams_for_width : 1 |
| 159 | use_stash : False |
| 160 | number_ways : 1 |
| 161 | way #0 |
| 162 | SRAM Request Group 0 |
| 163 | rams_for_depth : 1 |
| 164 | map_rams : 0 |
| 165 | way_number : 0 |
| 166 | ram_word_select_bits : 0 |
| 167 | ram_enable_select_bits : 0 |
| 168 | |
| 169 | Requesting to use 1 RAMs and have 32 available. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 170 | Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 0 |
| 171 | Allocating: SRAM: Row 0 Col 2 in stage 0 for table table0's ternary indirection word range Words 0 to 1023. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 172 | Result bus only needs (0): |
| 173 | |
| 174 | +========================================= |
| 175 | | Placing action/stats/meters/selection |
| 176 | +========================================= |
| 177 | |
| 178 | Requesting to use 3 RAMs and have 79 available. |
| 179 | SRAM Resource Request for table table0__action__ (of type action), with 1 ways wants 1 rams. |
| 180 | SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 181 | NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 182 | |
| 183 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 184 | Allocating: Statistics ALU 6 on right (128 bits) in stage 0 for table table0_counter. |
| 185 | Allocating: SRAM: Row 6 Col 6 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 186 | Allocating: Map RAM: Row 6 Unit 0 in stage 0 for table0_counter. |
| 187 | Allocating: SRAM: Row 6 Col 7 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 188 | Allocating: Map RAM: Row 6 Unit 1 in stage 0 for table0_counter. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 189 | |
| 190 | call to place_table_on_logical_row --- logical row 13 and rams to place is 1 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 191 | Allocating: SRAM: Row 6 Col 8 in stage 0 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 192 | Allocating: Ram Data Bus ActionR 6 right is 128 bits in stage 0 |
| 193 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 0 for table0_counter. |
| 194 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 0 for table0_counter. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 195 | Depth sorted idletime requests: |
| 196 | |
| 197 | |
| 198 | ======================================================= |
| 199 | |
| 200 | calling allocate and add with SRAM Resource Request for table table0 (of type idletime), with 1 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 201 | ======================================================= |
| 202 | |
| 203 | Requesting to use 0 RAMs and have 76 available. |
| 204 | Requesting to use 1 Map RAMs and have 46 available. |
| 205 | |
| 206 | ======================================================== |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 207 | Run Placement on Request List of size 4 in stage 0 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 208 | open_up_all_for_match=False |
| 209 | synth_two_port_first=False |
| 210 | ======================================================== |
| 211 | |
| 212 | Match Rams Need is 0 |
| 213 | Algorithmic TCAM Match RAMs Need is 0 |
| 214 | Other Rams Need is 4 |
| 215 | |
| 216 | +========================================= |
| 217 | | Placing algorithmic tcam |
| 218 | +========================================= |
| 219 | |
| 220 | sorted algorithmic tcam requests: (0) |
| 221 | |
| 222 | |
| 223 | ------------------------------------- |
| 224 | Columns need for match is 0 |
| 225 | columns for width is 0 |
| 226 | other columns is 1 |
| 227 | reserved columns is 9 |
| 228 | reserved columns for tind 1 |
| 229 | reserved columns for stateful 1 |
| 230 | Ternary Indirection Rams Need is 1 |
| 231 | Depth sorted requested |
| 232 | Group 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 233 | Sram Resource Request for P4 table table0 with handle 16777220 of type ternary_indirection in stage 0 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 234 | table_type : ternary_indirection |
| 235 | rams_for_width : 1 |
| 236 | use_stash : False |
| 237 | number_ways : 1 |
| 238 | way #0 |
| 239 | SRAM Request Group 0 |
| 240 | rams_for_depth : 1 |
| 241 | map_rams : 0 |
| 242 | way_number : 0 |
| 243 | ram_word_select_bits : 0 |
| 244 | ram_enable_select_bits : 0 |
| 245 | |
| 246 | Requesting to use 1 RAMs and have 32 available. |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 247 | Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 0 |
| 248 | Allocating: SRAM: Row 0 Col 2 in stage 0 for table table0's ternary indirection word range Words 0 to 1023. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 249 | Result bus only needs (0): |
| 250 | |
| 251 | +========================================= |
| 252 | | Placing action/stats/meters/selection |
| 253 | +========================================= |
| 254 | |
| 255 | Requesting to use 3 RAMs and have 79 available. |
| 256 | SRAM Resource Request for table table0__action__ (of type action), with 1 ways wants 1 rams. |
| 257 | SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 258 | NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 259 | |
| 260 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 261 | Allocating: Statistics ALU 6 on right (128 bits) in stage 0 for table table0_counter. |
| 262 | Allocating: SRAM: Row 6 Col 6 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 263 | Allocating: Map RAM: Row 6 Unit 0 in stage 0 for table0_counter. |
| 264 | Allocating: SRAM: Row 6 Col 7 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 265 | Allocating: Map RAM: Row 6 Unit 1 in stage 0 for table0_counter. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 266 | |
| 267 | call to place_table_on_logical_row --- logical row 13 and rams to place is 1 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 268 | Allocating: SRAM: Row 6 Col 8 in stage 0 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 269 | Allocating: Ram Data Bus ActionR 6 right is 128 bits in stage 0 |
| 270 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 0 for table0_counter. |
| 271 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 0 for table0_counter. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 272 | Depth sorted idletime requests: |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 273 | Sram Resource Request for P4 table table0 with handle 16777220 of type idletime in stage 0 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 274 | table_type : idletime |
| 275 | rams_for_width : 0 |
| 276 | use_stash : False |
| 277 | number_ways : 1 |
| 278 | way #0 |
| 279 | SRAM Request Group 0 |
| 280 | rams_for_depth : 0 |
| 281 | map_rams : 1 |
| 282 | way_number : 0 |
| 283 | ram_word_select_bits : 0 |
| 284 | ram_enable_select_bits : 0 |
| 285 | |
| 286 | Requesting to use 1 RAMs and have 46 available. |
| 287 | top_cnt = 1 and num requests = 1 |
| 288 | bottom_cnt = 0 and num requests = 0 |
| 289 | Working on idletime request SRAM Resource Request for table table0 (of type idletime), with 1 ways wants 0 rams. |
| 290 | >> wants 1 map rams |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 291 | Allocating: Map RAM: Row 7 Unit 0 in stage 0 for table0. |
| 292 | Allocating: Ram Data Bus IdletimeHalfLogicalRow 0 top is 19 bits in stage 0 for table0. |
| 293 | |
| 294 | |
| 295 | ======================================================= |
| 296 | |
| 297 | calling allocate and add with SRAM Resource Request for table process_packet_out_table (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 298 | ======================================================= |
| 299 | |
| 300 | Requesting to use 0 RAMs and have 76 available. |
| 301 | Requesting to use 0 Map RAMs and have 45 available. |
| 302 | |
| 303 | ======================================================== |
| 304 | Run Placement on Request List of size 5 in stage 0 |
| 305 | open_up_all_for_match=False |
| 306 | synth_two_port_first=False |
| 307 | ======================================================== |
| 308 | |
| 309 | Match Rams Need is 0 |
| 310 | Algorithmic TCAM Match RAMs Need is 0 |
| 311 | Other Rams Need is 4 |
| 312 | |
| 313 | +========================================= |
| 314 | | Placing algorithmic tcam |
| 315 | +========================================= |
| 316 | |
| 317 | sorted algorithmic tcam requests: (0) |
| 318 | |
| 319 | |
| 320 | ------------------------------------- |
| 321 | Columns need for match is 0 |
| 322 | columns for width is 0 |
| 323 | other columns is 1 |
| 324 | reserved columns is 9 |
| 325 | reserved columns for tind 1 |
| 326 | reserved columns for stateful 1 |
| 327 | Ternary Indirection Rams Need is 1 |
| 328 | Depth sorted requested |
| 329 | Group 0 |
| 330 | Sram Resource Request for P4 table table0 with handle 16777220 of type ternary_indirection in stage 0 |
| 331 | table_type : ternary_indirection |
| 332 | rams_for_width : 1 |
| 333 | use_stash : False |
| 334 | number_ways : 1 |
| 335 | way #0 |
| 336 | SRAM Request Group 0 |
| 337 | rams_for_depth : 1 |
| 338 | map_rams : 0 |
| 339 | way_number : 0 |
| 340 | ram_word_select_bits : 0 |
| 341 | ram_enable_select_bits : 0 |
| 342 | |
| 343 | Requesting to use 1 RAMs and have 32 available. |
| 344 | Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 0 |
| 345 | Allocating: SRAM: Row 0 Col 2 in stage 0 for table table0's ternary indirection word range Words 0 to 1023. |
| 346 | Result bus only needs (1): |
| 347 | process_packet_out_table |
| 348 | Allocating: Ram Data Bus MatchResult2R 0 left_and_right is 83 bits in stage 0 |
| 349 | |
| 350 | +========================================= |
| 351 | | Placing action/stats/meters/selection |
| 352 | +========================================= |
| 353 | |
| 354 | Requesting to use 3 RAMs and have 79 available. |
| 355 | SRAM Resource Request for table table0__action__ (of type action), with 1 ways wants 1 rams. |
| 356 | SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 357 | NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams. |
| 358 | |
| 359 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 360 | Allocating: Statistics ALU 6 on right (128 bits) in stage 0 for table table0_counter. |
| 361 | Allocating: SRAM: Row 6 Col 6 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 362 | Allocating: Map RAM: Row 6 Unit 0 in stage 0 for table0_counter. |
| 363 | Allocating: SRAM: Row 6 Col 7 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 364 | Allocating: Map RAM: Row 6 Unit 1 in stage 0 for table0_counter. |
| 365 | |
| 366 | call to place_table_on_logical_row --- logical row 13 and rams to place is 1 and depth index is 0 |
| 367 | Allocating: SRAM: Row 6 Col 8 in stage 0 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 368 | Allocating: Ram Data Bus ActionR 6 right is 128 bits in stage 0 |
| 369 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 0 for table0_counter. |
| 370 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 0 for table0_counter. |
| 371 | Depth sorted idletime requests: |
| 372 | Sram Resource Request for P4 table table0 with handle 16777220 of type idletime in stage 0 |
| 373 | table_type : idletime |
| 374 | rams_for_width : 0 |
| 375 | use_stash : False |
| 376 | number_ways : 1 |
| 377 | way #0 |
| 378 | SRAM Request Group 0 |
| 379 | rams_for_depth : 0 |
| 380 | map_rams : 1 |
| 381 | way_number : 0 |
| 382 | ram_word_select_bits : 0 |
| 383 | ram_enable_select_bits : 0 |
| 384 | |
| 385 | Requesting to use 1 RAMs and have 46 available. |
| 386 | top_cnt = 1 and num requests = 1 |
| 387 | bottom_cnt = 0 and num requests = 0 |
| 388 | Working on idletime request SRAM Resource Request for table table0 (of type idletime), with 1 ways wants 0 rams. |
| 389 | >> wants 1 map rams |
| 390 | Allocating: Map RAM: Row 7 Unit 0 in stage 0 for table0. |
| 391 | Allocating: Ram Data Bus IdletimeHalfLogicalRow 0 top is 19 bits in stage 0 for table0. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 392 | |
| 393 | |
| 394 | ======================================================= |
| 395 | |
| 396 | calling allocate and add with SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
| 397 | ======================================================= |
| 398 | |
| 399 | Requesting to use 2 RAMs and have 80 available. |
| 400 | Requesting to use 0 Map RAMs and have 48 available. |
| 401 | |
| 402 | ======================================================== |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 403 | Run Placement on Request List of size 1 in stage 1 |
| 404 | open_up_all_for_match=False |
| 405 | synth_two_port_first=False |
| 406 | ======================================================== |
| 407 | |
| 408 | Match Rams Need is 0 |
| 409 | Algorithmic TCAM Match RAMs Need is 0 |
| 410 | Other Rams Need is 2 |
| 411 | |
| 412 | +========================================= |
| 413 | | Placing algorithmic tcam |
| 414 | +========================================= |
| 415 | |
| 416 | sorted algorithmic tcam requests: (0) |
| 417 | |
| 418 | |
| 419 | ------------------------------------- |
| 420 | Columns need for match is 0 |
| 421 | columns for width is 0 |
| 422 | other columns is 1 |
| 423 | reserved columns is 9 |
| 424 | reserved columns for tind 0 |
| 425 | reserved columns for stateful 1 |
| 426 | Ternary Indirection Rams Need is 0 |
| 427 | Depth sorted requested |
| 428 | Requesting to use 0 RAMs and have 32 available. |
| 429 | Result bus only needs (0): |
| 430 | |
| 431 | +========================================= |
| 432 | | Placing action/stats/meters/selection |
| 433 | +========================================= |
| 434 | |
| 435 | Requesting to use 2 RAMs and have 80 available. |
| 436 | SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams. |
| 437 | NO Spill Required off of logical row 13 for SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams. |
| 438 | |
| 439 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 440 | Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table ecmp_group_table_counter. |
| 441 | Allocating: SRAM: Row 6 Col 6 in stage 1 for table ecmp_group_table_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 442 | Allocating: Map RAM: Row 6 Unit 0 in stage 1 for ecmp_group_table_counter. |
| 443 | Allocating: SRAM: Row 6 Col 7 in stage 1 for table ecmp_group_table_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 444 | Allocating: Map RAM: Row 6 Unit 1 in stage 1 for ecmp_group_table_counter. |
| 445 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for ecmp_group_table_counter. |
| 446 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for ecmp_group_table_counter. |
| 447 | Depth sorted idletime requests: |
| 448 | |
| 449 | |
| 450 | ======================================================= |
| 451 | |
| 452 | calling allocate and add with SRAM Resource Request for table ecmp_group_table (of type match), with 3 ways wants 3 rams. (open-all=False, synth_two_port_first=False) |
| 453 | ======================================================= |
| 454 | |
| 455 | Requesting to use 3 RAMs and have 78 available. |
| 456 | Requesting to use 0 Map RAMs and have 46 available. |
| 457 | |
| 458 | ======================================================== |
| 459 | Run Placement on Request List of size 2 in stage 1 |
| 460 | open_up_all_for_match=False |
| 461 | synth_two_port_first=False |
| 462 | ======================================================== |
| 463 | |
| 464 | Match Rams Need is 3 |
| 465 | Algorithmic TCAM Match RAMs Need is 0 |
| 466 | Other Rams Need is 2 |
| 467 | |
| 468 | +========================================= |
| 469 | | Placing algorithmic tcam |
| 470 | +========================================= |
| 471 | |
| 472 | sorted algorithmic tcam requests: (0) |
| 473 | |
| 474 | |
| 475 | ------------------------------------- |
| 476 | Columns need for match is 1 |
| 477 | columns for width is 1 |
| 478 | other columns is 1 |
| 479 | reserved columns is 9 |
| 480 | reserved columns for tind 0 |
| 481 | reserved columns for stateful 1 |
| 482 | For group request 0 |
| 483 | Dealing with way that starts at 0 of match request SRAM Resource Request for table ecmp_group_table (of type match), with 3 ways wants 3 rams. |
| 484 | Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 1 |
| 485 | Allocating: Ram Data Bus MatchResult1R 7 left_and_right is 83 bits in stage 1 |
| 486 | Allocating: SRAM: Row 7 Col 2 in stage 1 for table ecmp_group_table's match way 0 for entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 487 | Allocating: SRAM: Row 7 Col 3 in stage 1 for table ecmp_group_table's match way 1 for entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 488 | Allocating: SRAM: Row 7 Col 4 in stage 1 for table ecmp_group_table's match way 2 for entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 489 | Ternary Indirection Rams Need is 0 |
| 490 | Depth sorted requested |
| 491 | Requesting to use 0 RAMs and have 29 available. |
| 492 | Result bus only needs (0): |
| 493 | |
| 494 | +========================================= |
| 495 | | Placing action/stats/meters/selection |
| 496 | +========================================= |
| 497 | |
| 498 | Requesting to use 2 RAMs and have 77 available. |
| 499 | SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams. |
| 500 | NO Spill Required off of logical row 13 for SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams. |
| 501 | |
| 502 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
| 503 | Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table ecmp_group_table_counter. |
| 504 | Allocating: SRAM: Row 6 Col 6 in stage 1 for table ecmp_group_table_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 505 | Allocating: Map RAM: Row 6 Unit 0 in stage 1 for ecmp_group_table_counter. |
| 506 | Allocating: SRAM: Row 6 Col 7 in stage 1 for table ecmp_group_table_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 507 | Allocating: Map RAM: Row 6 Unit 1 in stage 1 for ecmp_group_table_counter. |
| 508 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for ecmp_group_table_counter. |
| 509 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for ecmp_group_table_counter. |
| 510 | Depth sorted idletime requests: |
| 511 | |
| 512 | |
| 513 | ======================================================= |
| 514 | |
| 515 | calling allocate and add with SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
| 516 | ======================================================= |
| 517 | |
| 518 | Requesting to use 2 RAMs and have 80 available. |
| 519 | Requesting to use 0 Map RAMs and have 48 available. |
| 520 | |
| 521 | ======================================================== |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 522 | Run Placement on Request List of size 1 in stage 2 |
| 523 | open_up_all_for_match=False |
| 524 | synth_two_port_first=False |
| 525 | ======================================================== |
| 526 | |
| 527 | Match Rams Need is 0 |
| 528 | Algorithmic TCAM Match RAMs Need is 0 |
| 529 | Other Rams Need is 2 |
| 530 | |
| 531 | +========================================= |
| 532 | | Placing algorithmic tcam |
| 533 | +========================================= |
| 534 | |
| 535 | sorted algorithmic tcam requests: (0) |
| 536 | |
| 537 | |
| 538 | ------------------------------------- |
| 539 | Columns need for match is 0 |
| 540 | columns for width is 0 |
| 541 | other columns is 1 |
| 542 | reserved columns is 9 |
| 543 | reserved columns for tind 0 |
| 544 | reserved columns for stateful 1 |
| 545 | Ternary Indirection Rams Need is 0 |
| 546 | Depth sorted requested |
| 547 | Requesting to use 0 RAMs and have 32 available. |
| 548 | Result bus only needs (0): |
| 549 | |
| 550 | +========================================= |
| 551 | | Placing action/stats/meters/selection |
| 552 | +========================================= |
| 553 | |
| 554 | Requesting to use 2 RAMs and have 80 available. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 555 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 556 | NO Spill Required off of logical row 13 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 557 | |
| 558 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 559 | Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table ingress_port_counter. |
| 560 | Allocating: SRAM: Row 6 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 561 | Allocating: Map RAM: Row 6 Unit 0 in stage 2 for ingress_port_counter. |
| 562 | Allocating: SRAM: Row 6 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 563 | Allocating: Map RAM: Row 6 Unit 1 in stage 2 for ingress_port_counter. |
| 564 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for ingress_port_counter. |
| 565 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for ingress_port_counter. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 566 | Depth sorted idletime requests: |
| 567 | |
| 568 | |
| 569 | ======================================================= |
| 570 | |
| 571 | calling allocate and add with SRAM Resource Request for table ingress_port_count_table (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 572 | ======================================================= |
| 573 | |
| 574 | Requesting to use 0 RAMs and have 78 available. |
| 575 | Requesting to use 0 Map RAMs and have 46 available. |
| 576 | |
| 577 | ======================================================== |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 578 | Run Placement on Request List of size 2 in stage 2 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 579 | open_up_all_for_match=False |
| 580 | synth_two_port_first=False |
| 581 | ======================================================== |
| 582 | |
| 583 | Match Rams Need is 0 |
| 584 | Algorithmic TCAM Match RAMs Need is 0 |
| 585 | Other Rams Need is 2 |
| 586 | |
| 587 | +========================================= |
| 588 | | Placing algorithmic tcam |
| 589 | +========================================= |
| 590 | |
| 591 | sorted algorithmic tcam requests: (0) |
| 592 | |
| 593 | |
| 594 | ------------------------------------- |
| 595 | Columns need for match is 0 |
| 596 | columns for width is 0 |
| 597 | other columns is 1 |
| 598 | reserved columns is 9 |
| 599 | reserved columns for tind 0 |
| 600 | reserved columns for stateful 1 |
| 601 | Ternary Indirection Rams Need is 0 |
| 602 | Depth sorted requested |
| 603 | Requesting to use 0 RAMs and have 32 available. |
| 604 | Result bus only needs (1): |
| 605 | ingress_port_count_table |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 606 | Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 2 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 607 | |
| 608 | +========================================= |
| 609 | | Placing action/stats/meters/selection |
| 610 | +========================================= |
| 611 | |
| 612 | Requesting to use 2 RAMs and have 80 available. |
| 613 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 614 | NO Spill Required off of logical row 13 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 615 | |
| 616 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 617 | Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table ingress_port_counter. |
| 618 | Allocating: SRAM: Row 6 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 619 | Allocating: Map RAM: Row 6 Unit 0 in stage 2 for ingress_port_counter. |
| 620 | Allocating: SRAM: Row 6 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 621 | Allocating: Map RAM: Row 6 Unit 1 in stage 2 for ingress_port_counter. |
| 622 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for ingress_port_counter. |
| 623 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for ingress_port_counter. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 624 | Depth sorted idletime requests: |
| 625 | |
| 626 | |
| 627 | ======================================================= |
| 628 | |
| 629 | calling allocate and add with SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False) |
| 630 | ======================================================= |
| 631 | |
| 632 | Requesting to use 2 RAMs and have 78 available. |
| 633 | Requesting to use 0 Map RAMs and have 46 available. |
| 634 | |
| 635 | ======================================================== |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 636 | Run Placement on Request List of size 3 in stage 2 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 637 | open_up_all_for_match=False |
| 638 | synth_two_port_first=False |
| 639 | ======================================================== |
| 640 | |
| 641 | Match Rams Need is 0 |
| 642 | Algorithmic TCAM Match RAMs Need is 0 |
| 643 | Other Rams Need is 4 |
| 644 | |
| 645 | +========================================= |
| 646 | | Placing algorithmic tcam |
| 647 | +========================================= |
| 648 | |
| 649 | sorted algorithmic tcam requests: (0) |
| 650 | |
| 651 | |
| 652 | ------------------------------------- |
| 653 | Columns need for match is 0 |
| 654 | columns for width is 0 |
| 655 | other columns is 1 |
| 656 | reserved columns is 9 |
| 657 | reserved columns for tind 0 |
| 658 | reserved columns for stateful 1 |
| 659 | Ternary Indirection Rams Need is 0 |
| 660 | Depth sorted requested |
| 661 | Requesting to use 0 RAMs and have 32 available. |
| 662 | Result bus only needs (1): |
| 663 | ingress_port_count_table |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 664 | Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 2 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 665 | |
| 666 | +========================================= |
| 667 | | Placing action/stats/meters/selection |
| 668 | +========================================= |
| 669 | |
| 670 | Requesting to use 4 RAMs and have 80 available. |
| 671 | SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 672 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 673 | NO Spill Required off of logical row 13 for SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 674 | |
| 675 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 676 | Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table egress_port_counter. |
| 677 | Allocating: SRAM: Row 6 Col 6 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 678 | Allocating: Map RAM: Row 6 Unit 0 in stage 2 for egress_port_counter. |
| 679 | Allocating: SRAM: Row 6 Col 7 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 680 | Allocating: Map RAM: Row 6 Unit 1 in stage 2 for egress_port_counter. |
| 681 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for egress_port_counter. |
| 682 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for egress_port_counter. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 683 | NO Spill Required off of logical row 9 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 684 | |
| 685 | call to place_table_on_logical_row --- logical row 9 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 686 | Allocating: Statistics ALU 4 on right (128 bits) in stage 2 for table ingress_port_counter. |
| 687 | Allocating: SRAM: Row 4 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 688 | Allocating: Map RAM: Row 4 Unit 0 in stage 2 for ingress_port_counter. |
| 689 | Allocating: SRAM: Row 4 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 690 | Allocating: Map RAM: Row 4 Unit 1 in stage 2 for ingress_port_counter. |
| 691 | Allocating: Ram Data Bus StatsR 4 right is 128 bits in stage 2 for ingress_port_counter. |
| 692 | Allocating: Ram Data Bus StatsW 4 right is 128 bits in stage 2 for ingress_port_counter. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 693 | Depth sorted idletime requests: |
| 694 | |
| 695 | |
| 696 | ======================================================= |
| 697 | |
| 698 | calling allocate and add with SRAM Resource Request for table egress_port_count_table (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False) |
| 699 | ======================================================= |
| 700 | |
| 701 | Requesting to use 0 RAMs and have 76 available. |
| 702 | Requesting to use 0 Map RAMs and have 44 available. |
| 703 | |
| 704 | ======================================================== |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 705 | Run Placement on Request List of size 4 in stage 2 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 706 | open_up_all_for_match=False |
| 707 | synth_two_port_first=False |
| 708 | ======================================================== |
| 709 | |
| 710 | Match Rams Need is 0 |
| 711 | Algorithmic TCAM Match RAMs Need is 0 |
| 712 | Other Rams Need is 4 |
| 713 | |
| 714 | +========================================= |
| 715 | | Placing algorithmic tcam |
| 716 | +========================================= |
| 717 | |
| 718 | sorted algorithmic tcam requests: (0) |
| 719 | |
| 720 | |
| 721 | ------------------------------------- |
| 722 | Columns need for match is 0 |
| 723 | columns for width is 0 |
| 724 | other columns is 1 |
| 725 | reserved columns is 9 |
| 726 | reserved columns for tind 0 |
| 727 | reserved columns for stateful 1 |
| 728 | Ternary Indirection Rams Need is 0 |
| 729 | Depth sorted requested |
| 730 | Requesting to use 0 RAMs and have 32 available. |
| 731 | Result bus only needs (2): |
| 732 | egress_port_count_table |
| 733 | ingress_port_count_table |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 734 | Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 2 |
| 735 | Allocating: Ram Data Bus MatchResult2R 0 left_and_right is 83 bits in stage 2 |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 736 | |
| 737 | +========================================= |
| 738 | | Placing action/stats/meters/selection |
| 739 | +========================================= |
| 740 | |
| 741 | Requesting to use 4 RAMs and have 80 available. |
| 742 | SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 743 | SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 744 | NO Spill Required off of logical row 13 for SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 745 | |
| 746 | call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 747 | Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table egress_port_counter. |
| 748 | Allocating: SRAM: Row 6 Col 6 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 749 | Allocating: Map RAM: Row 6 Unit 0 in stage 2 for egress_port_counter. |
| 750 | Allocating: SRAM: Row 6 Col 7 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 751 | Allocating: Map RAM: Row 6 Unit 1 in stage 2 for egress_port_counter. |
| 752 | Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for egress_port_counter. |
| 753 | Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for egress_port_counter. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 754 | NO Spill Required off of logical row 9 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. |
| 755 | |
| 756 | call to place_table_on_logical_row --- logical row 9 and rams to place is 2 and depth index is 0 |
Brian O'Connor | a6862e0 | 2017-09-08 01:17:39 -0700 | [diff] [blame] | 757 | Allocating: Statistics ALU 4 on right (128 bits) in stage 2 for table ingress_port_counter. |
| 758 | Allocating: SRAM: Row 4 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023. |
| 759 | Allocating: Map RAM: Row 4 Unit 0 in stage 2 for ingress_port_counter. |
| 760 | Allocating: SRAM: Row 4 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047. |
| 761 | Allocating: Map RAM: Row 4 Unit 1 in stage 2 for ingress_port_counter. |
| 762 | Allocating: Ram Data Bus StatsR 4 right is 128 bits in stage 2 for ingress_port_counter. |
| 763 | Allocating: Ram Data Bus StatsW 4 right is 128 bits in stage 2 for ingress_port_counter. |
Carmelo Cascone | f1d0a42 | 2017-09-07 17:21:46 +0200 | [diff] [blame] | 764 | Depth sorted idletime requests: |