Carmelo Cascone | f87dc2e | 2018-01-26 18:52:44 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2017-present Open Networking Foundation |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #define S1U_PORT 1 |
| 19 | #define SGI_PORT 2 |
| 20 | #define AS_MAC_ADDR 0x52540029c9b7 |
| 21 | #define S1U_MAC_ADDR 0xc242592d3a84 |
| 22 | #define SGI_MAC_ADDR 0x3ac1e253e150 |
| 23 | #define ENB_MAC_ADDR 0x525400057b59 |
| 24 | |
| 25 | #include <core.p4> |
| 26 | #include <v1model.p4> |
| 27 | |
| 28 | #include "include/define.p4" |
| 29 | #include "include/header.p4" |
| 30 | #include "include/checksum.p4" |
| 31 | #include "include/parser.p4" |
| 32 | #include "include/control/packetio.p4" |
| 33 | |
| 34 | #include "include/spgw.p4" |
| 35 | |
| 36 | control table0_control(inout parsed_headers_t hdr, |
| 37 | inout fabric_metadata_t fabric_metadata, |
| 38 | inout standard_metadata_t standard_metadata) { |
| 39 | |
| 40 | action send_to_cpu() { |
| 41 | standard_metadata.egress_spec = CPU_PORT; |
| 42 | exit; |
| 43 | } |
| 44 | |
| 45 | table table0 { |
| 46 | key = { |
| 47 | standard_metadata.ingress_port : ternary; |
| 48 | hdr.ethernet.src_addr : ternary; |
| 49 | hdr.ethernet.dst_addr : ternary; |
| 50 | hdr.ethernet.ether_type : ternary; |
| 51 | hdr.ipv4.src_addr : ternary; |
| 52 | hdr.ipv4.dst_addr : ternary; |
| 53 | hdr.ipv4.protocol : ternary; |
| 54 | fabric_metadata.l4_src_port : ternary; |
| 55 | fabric_metadata.l4_dst_port : ternary; |
| 56 | } |
| 57 | actions = { |
| 58 | send_to_cpu(); |
| 59 | NoAction(); |
| 60 | } |
| 61 | const default_action = NoAction(); |
| 62 | } |
| 63 | |
| 64 | apply { |
| 65 | table0.apply(); |
| 66 | } |
| 67 | } |
| 68 | |
| 69 | //------------------------------------------------------------------------------ |
| 70 | // INGRESS PIPELINE |
| 71 | //------------------------------------------------------------------------------ |
| 72 | |
| 73 | control ingress_impl(inout parsed_headers_t hdr, |
| 74 | inout fabric_metadata_t fabric_metadata, |
| 75 | inout standard_metadata_t standard_metadata) { |
| 76 | |
| 77 | apply { |
| 78 | |
| 79 | PacketIoIngress.apply(hdr, fabric_metadata, standard_metadata); |
| 80 | |
| 81 | // Drop garbage, so we get a clean pcap. |
| 82 | if (standard_metadata.ingress_port == S1U_PORT |
| 83 | && hdr.ethernet.src_addr != ENB_MAC_ADDR) { |
| 84 | mark_to_drop(); |
| 85 | exit; |
| 86 | } else if (standard_metadata.ingress_port == SGI_PORT |
| 87 | && hdr.ethernet.src_addr != AS_MAC_ADDR) { |
| 88 | mark_to_drop(); |
| 89 | exit; |
| 90 | } |
| 91 | |
| 92 | table0_control.apply(hdr, fabric_metadata, standard_metadata); |
| 93 | |
| 94 | if (standard_metadata.egress_spec == CPU_PORT) { |
| 95 | return; |
| 96 | } |
| 97 | |
| 98 | if (standard_metadata.ingress_port == S1U_PORT) { |
| 99 | if (hdr.ethernet.dst_addr != S1U_MAC_ADDR) { |
| 100 | mark_to_drop(); |
| 101 | exit; |
| 102 | } |
| 103 | standard_metadata.egress_spec = SGI_PORT; |
| 104 | hdr.ethernet.src_addr = SGI_MAC_ADDR; |
| 105 | hdr.ethernet.dst_addr = AS_MAC_ADDR; |
| 106 | } else if (standard_metadata.ingress_port == SGI_PORT) { |
| 107 | if (hdr.ethernet.dst_addr != SGI_MAC_ADDR) { |
| 108 | mark_to_drop(); |
| 109 | exit; |
| 110 | } |
| 111 | standard_metadata.egress_spec = S1U_PORT; |
| 112 | hdr.ethernet.src_addr = S1U_MAC_ADDR; |
| 113 | hdr.ethernet.dst_addr = ENB_MAC_ADDR; |
| 114 | } |
| 115 | |
| 116 | #ifdef WITH_SPGW_PCC_GATING |
| 117 | fabric_metadata.spgw.l4_src_port = fabric_metadata.l4_src_port; |
| 118 | fabric_metadata.spgw.l4_dst_port = fabric_metadata.l4_dst_port; |
| 119 | #endif // WITH_SPGW_PCC_GATING |
| 120 | spgw_ingress.apply(hdr.gtpu_ipv4, hdr.gtpu_udp, hdr.gtpu, |
| 121 | hdr.ipv4, hdr.udp, fabric_metadata.spgw); |
| 122 | } |
| 123 | } |
| 124 | |
| 125 | //------------------------------------------------------------------------------ |
| 126 | // EGRESS PIPELINE |
| 127 | //------------------------------------------------------------------------------ |
| 128 | |
| 129 | control egress_impl(inout parsed_headers_t hdr, |
| 130 | inout fabric_metadata_t fabric_metadata, |
| 131 | inout standard_metadata_t standard_metadata) { |
| 132 | apply { |
| 133 | PacketIoEgress.apply(hdr, fabric_metadata, standard_metadata); |
| 134 | spgw_egress.apply(hdr.gtpu_ipv4, hdr.gtpu_udp, hdr.gtpu, |
| 135 | fabric_metadata.spgw, standard_metadata); |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | //------------------------------------------------------------------------------ |
| 140 | // SWITCH INSTANTIATION |
| 141 | //------------------------------------------------------------------------------ |
| 142 | |
| 143 | V1Switch(FabricParser(), |
| 144 | FabricVerifyChecksum(), |
| 145 | ingress_impl(), |
| 146 | egress_impl(), |
| 147 | FabricComputeChecksum(), |
| 148 | FabricDeparser()) main; |