Fixing packet_io and regenerating default.p4 for tofino
Change-Id: I5c2c6565f71a13b375a8ec8da864e9157b8e56ed
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/asm.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/asm.log
index 3506a4f..2b7ff8d 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/asm.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/asm.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: asm.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.characterize.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.characterize.log
index ea74364..37c2fe6 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.characterize.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.characterize.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.characterize.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
Match+Action Resource Usage
@@ -16,19 +16,16 @@
| | | | | | | | | | ver/vld | | | | | | | | Units | Units | | | |
| | | | | | | | | | | | | | | | | | (bits) | (bits) | | | |
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-| ingress_pkt | ingress | 0 | | - | 0 (0/0/0/0/0) | 0 | 1024 / 1 (-1023) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 1 in 0 (0) | - / - | - / - | - / - |
-| egress_pkt | egress | 0 | | - | 0 (0/0/0/0/0) | 0 | 1024 / 1 (-1023) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 1 in 0 (0) | - / - | - / - | - / - |
-| stage 0 totals | - | - | - | - | 0 (0/0/0/0/0) | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
+| table0 | ingress | 0 | ternary | tcam | 4 (0/1/2/0/1) | 3 | 512 / 512 (0) | 121 / 121 (0) | 4 | 5 | 1/4/0/0/0/0/0/0 | 0 / 0 (0) | 125 / 132 (7) | 5 / 8 (3) | 16 | 16 / 16 (0) | 1 in 3 (132) | 1 in 3 (132) | 91.7% / 91.7% | - / - | 100.0% / 100.0% |
+| process_packet_out_table | ingress | 0 | | - | 0 (0/0/0/0/0) | 0 | 1024 / 1 (-1023) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 1 in 0 (0) | - / - | - / - | - / - |
+| stage 0 totals | - | - | - | - | 4 (0/1/2/0/1) | 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| | | | | | | | | | | | | | | | | | | | | | |
-| table0 | ingress | 1 | ternary | tcam | 4 (0/1/2/0/1) | 3 | 512 / 512 (0) | 121 / 121 (0) | 4 | 5 | 1/4/0/0/0/0/0/0 | 0 / 0 (0) | 125 / 132 (7) | 5 / 8 (3) | 16 | 16 / 16 (0) | 1 in 3 (132) | 1 in 3 (132) | 91.7% / 91.7% | - / - | 100.0% / 100.0% |
-| stage 1 totals | - | - | - | - | 4 (0/1/2/0/1) | 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
+| ecmp_group_table | ingress | 1 | exact | sram | 5 (3/0/2/0/0) | 0 | 1024 / 3072 (2048) | 32 / 22 (-10) | 0 | 20 | 0/0/0/0/0/0/4/16 | 9 / 16 (7) | 0 / 0 (0) | 52 / 42 (-10) | 9 | 0 / 0 (0) | 3 in 1 (128) | 1 in 1 (128) | - / - | 96.1% / 29.7% | - / - |
+| stage 1 totals | - | - | - | - | 5 (3/0/2/0/0) | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| | | | | | | | | | | | | | | | | | | | | | |
-| ecmp_group_table | ingress | 2 | exact | sram | 5 (3/0/2/0/0) | 0 | 1024 / 3072 (2048) | 32 / 22 (-10) | 0 | 20 | 0/0/0/0/0/0/4/16 | 9 / 16 (7) | 0 / 0 (0) | 52 / 42 (-10) | 9 | 0 / 0 (0) | 3 in 1 (128) | 1 in 1 (128) | - / - | 96.1% / 29.7% | - / - |
-| stage 2 totals | - | - | - | - | 5 (3/0/2/0/0) | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
-| | | | | | | | | | | | | | | | | | | | | | |
-| ingress_port_count_table | ingress | 3 | | - | 2 (0/0/2/0/0) | 0 | 1024 / 1 (-1023) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 1 in 0 (0) | - / - | - / - | - / - |
-| egress_port_count_table | ingress | 3 | | - | 2 (0/0/2/0/0) | 0 | 1024 / 1 (-1023) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 1 in 0 (0) | - / - | - / - | - / - |
-| stage 3 totals | - | - | - | - | 4 (0/0/4/0/0) | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
+| ingress_port_count_table | ingress | 2 | | - | 2 (0/0/2/0/0) | 0 | 1024 / 1 (-1023) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 1 in 0 (0) | - / - | - / - | - / - |
+| egress_port_count_table | ingress | 2 | | - | 2 (0/0/2/0/0) | 0 | 1024 / 1 (-1023) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 1 in 0 (0) | - / - | - / - | - / - |
+| stage 2 totals | - | - | - | - | 4 (0/0/4/0/0) | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| | | | | | | | | | | | | | | | | | | | | | |
| overall totals | - | - | - | - | 13 (3/1/8/0/1) | 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -77,19 +74,11 @@
Total bits: 20
+----------------------------------------------------------------+
- ingress_pkt
+ process_packet_out_table
+----------------------------------------------------------------+
Match Overhead:
- Field --instruction_address-- [1:0] (2 bits)
- Total bits: 2
-+----------------------------------------------------------------+
- egress_pkt
-+----------------------------------------------------------------+
-Match Overhead:
- Field --instruction_address-- [1:0] (2 bits)
-
- Total bits: 2
+ Total bits: 0
+----------------------------------------------------------------+
table0
+----------------------------------------------------------------+
@@ -148,28 +137,10 @@
]
+----------------------------------------------------------------+
- ingress_pkt__action__:
+ process_packet_out_table__action__:
+----------------------------------------------------------------+
-Action _packet_out:
----------------------------
-Pack Format:
- table_word_width: 128
- memory_word_width: 128
- entries_per_table_word: 1
- number_memory_units_per_table_word: 1
- entry_list: [
- entry_number : 0
- field_list : [
- ]
- Field --padding-- is 0 bits : in bits [127:0]
-]
-
-+----------------------------------------------------------------+
- egress_pkt__action__:
-+----------------------------------------------------------------+
-
-Action add_packet_in_hdr:
+Action _process_packet_out:
---------------------------
Pack Format:
table_word_width: 128
@@ -292,35 +263,43 @@
entry_number : 7
field_list : [
]
- Field --padding-- [15:0] : in bits [127:112]
+ Field --padding-- [6:0] : in bits [127:121]
+ Field --constant-0-- [8:0] : in bits [120:112]
entry_number : 6
field_list : [
]
- Field --padding-- [15:0] : in bits [111:96]
+ Field --padding-- [6:0] : in bits [111:105]
+ Field --constant-0-- [8:0] : in bits [104:96]
entry_number : 5
field_list : [
]
- Field --padding-- [15:0] : in bits [95:80]
+ Field --padding-- [6:0] : in bits [95:89]
+ Field --constant-0-- [8:0] : in bits [88:80]
entry_number : 4
field_list : [
]
- Field --padding-- [15:0] : in bits [79:64]
+ Field --padding-- [6:0] : in bits [79:73]
+ Field --constant-0-- [8:0] : in bits [72:64]
entry_number : 3
field_list : [
]
- Field --padding-- [15:0] : in bits [63:48]
+ Field --padding-- [6:0] : in bits [63:57]
+ Field --constant-0-- [8:0] : in bits [56:48]
entry_number : 2
field_list : [
]
- Field --padding-- [15:0] : in bits [47:32]
+ Field --padding-- [6:0] : in bits [47:41]
+ Field --constant-0-- [8:0] : in bits [40:32]
entry_number : 1
field_list : [
]
- Field --padding-- [15:0] : in bits [31:16]
+ Field --padding-- [6:0] : in bits [31:25]
+ Field --constant-0-- [8:0] : in bits [24:16]
entry_number : 0
field_list : [
]
- Field --padding-- [15:0] : in bits [15:0]
+ Field --padding-- [6:0] : in bits [15:9]
+ Field --constant-0-- [8:0] : in bits [8:0]
]
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.config.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.config.log
index fafc038..44fe6ff 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.config.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.config.log
@@ -1,14 +1,14 @@
+---------------------------------------------------------------------+
| Log file: mau.config.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
Final Stage dependencies are:
(0, 'ingress') : match
(1, 'ingress') : match
(2, 'ingress') : match
- (3, 'ingress') : match
+ (3, 'ingress') : concurrent
(4, 'ingress') : concurrent
(5, 'ingress') : concurrent
(6, 'ingress') : match
@@ -29,7 +29,7 @@
(9, 'egress') : concurrent
(10, 'egress') : concurrent
(11, 'egress') : concurrent
-Action/Concurrent chaining in ingress consists of [4, 5]
+Action/Concurrent chaining in ingress consists of [3, 4, 5]
Action/Concurrent chaining in ingress consists of [7, 8, 9, 10, 11]
Action/Concurrent chaining in egress consists of [1, 2, 3, 4, 5]
Action/Concurrent chaining in egress consists of [7, 8, 9, 10, 11]
@@ -48,322 +48,13 @@
Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
-Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
-Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 4.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 1 to come from 8-bit PHV container 4.
- That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10)
-Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
-Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=41].byte1 to be 0x2.
-Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
-Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
-Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
-Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
-Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
-Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x0
-Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0
-Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
-Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
-Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
-Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff
-Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff
-Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xfffffd
-Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff
-Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8
-Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x10
-Configuring rams.match.merge.gateway_en.gateway_en to be 0x1
-Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xe
-Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1
-allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
-Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x0
-Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1
-Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2
-Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x1
-Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0
-Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x1
-Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0
-Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff
-Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff
-
-+------------------------------------------------------------------------
-| Working on table _condition_3 in stage 0 ---
-+------------------------------------------------------------------------
---> Stage Gateway Table for condition _condition_3 in stage 0
-Configuring rams.match.merge.predication_ctl[direction_index=1].table_thread to be 0x2 (previous_value=0x0 OR new_value=0x2).
-Configuring dp.imem_table_addr_egress to be 0x2 (previous_value = 0x0 OR new_value = 0x2).
-Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=1][copy_index=0].adr_dist_table_thread to be 0x2 (previous_value=0x0 OR new_value=0x2).
-Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=1][copy_index=1].adr_dist_table_thread to be 0x2 (previous_value=0x0 OR new_value=0x2).
-Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_egress to be 0x2 (previous_value=0x0 OR new_value=0x2).
-Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_egress to be 0x2 (previous_value=0x0 OR new_value=0x2).
-Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_egress to be 0x2 (previous_value=0x0 OR new_value=0x2).
-Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=1].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
-Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=1].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=2][output_byte=0].match_input_xbar_816b_ctl_address to be 0.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=2][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 0 to come from 8-bit PHV container 16.
- That PHV byte contains {unused[6:0], ig_intr_md_for_tm.copy_to_cpu[0:0]}.
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=6].match_input_xbar_din_power_ctl to be 0x1. (previous value = 0x0 OR new value = 0x1)
-Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x1)
-Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte0 to be 0x1.
-Configuring dp.hashout_ctl.hash_group_egress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
-Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
-Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
-Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0.
-Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1.
-Configuring cfg_regs.mau_cfg_lt_thread.mau_cfg_lt_thread to be 0x2. (previous value = 0x0 OR new value = 0x2)
-Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
-Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
-Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
-Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
-Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x1
-Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x1
-Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
-Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
-Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
-Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xfffffe
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffffff
-Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8
-Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0xff
-Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2)
-Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xf
-Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1
-allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
-Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_logical_select to be 0x1
-Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_inhibit_enable to be 0x1
-Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x3 (previous value 0x2 OR new value 0x1)
-Configuring rams.match.merge.gateway_payload_data[0][0][0][0].gateway_payload_data to be 0x1
-Configuring rams.match.merge.gateway_payload_data[0][0][1][0].gateway_payload_data to be 0x0
-Configuring rams.match.merge.gateway_payload_data[0][0][0][1].gateway_payload_data to be 0x1
-Configuring rams.match.merge.gateway_payload_data[0][0][1][1].gateway_payload_data to be 0x0
-Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff
-Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff
-
-+------------------------------------------------------------------------
-| Working on table ingress_pkt__action__ in stage 0 ---
-+------------------------------------------------------------------------
---> Action Data Table ingress_pkt__action__ with logical_table_id 0 that is reference type is 'direct'
-
-+------------------------------------------------------------------------
-| Working on table ingress_pkt in stage 0 ---
-+------------------------------------------------------------------------
---> Match Table with no key ingress_pkt with logical_table_id 0
-allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
-Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
-Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
-Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
-Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
-Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
-Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
-Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id).
-Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
-Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id).
-Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
-Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x0.
-Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x1.
-Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x10.
-Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
-Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2080.
-Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
-Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x74412.
-Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1.
-Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 0.
-Micro instruction added in VLIW 0 for 16-bit position 2 for table ingress_pkt.
- Assembled as 0x74412 (or decimal 476178)
- Micro Instruction deposit-field for PHV Container 130 has bit width 23
- Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
- Field Src1 [4:0] : 0x1 (5 bits in instruction bits [8:4])
- Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
- Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
- Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
- Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
- Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16])
- Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
-
-Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=0].imem_subword8_instr to be 0x74d84.
-Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=0].imem_subword8_color to be 1.
-Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=0].imem_subword8_parity to be 0.
-Micro instruction added in VLIW 0 for 8-bit position 4 for table ingress_pkt.
- Assembled as 0x74d84 (or decimal 478596)
- Micro Instruction deposit-field for PHV Container 68 has bit width 20
- Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
- Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4])
- Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
- Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
- Field high_bit [2:0] : 0x1 (3 bits in instruction bits [13:11])
- Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14])
- Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16])
- Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
-
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10)
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6)
-Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
-
-+------------------------------------------------------------------------
-| Working on table egress_pkt__action__ in stage 0 ---
-+------------------------------------------------------------------------
---> Action Data Table egress_pkt__action__ with logical_table_id 1 that is reference type is 'direct'
-
-+------------------------------------------------------------------------
-| Working on table egress_pkt in stage 0 ---
-+------------------------------------------------------------------------
---> Match Table with no key egress_pkt with logical_table_id 1
-allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
-Configuring dp.imem_table_addr_egress to be 0x2 (previous_value = 0x2 OR new_value = 0x2).
-Configuring rams.match.merge.predication_ctl[direction_index=1].table_thread to be 0x2 (previous_value=0x2 OR new_value=0x2).
-Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_egress to be 0x2 (previous_value=0x2 OR new_value=0x2).
-Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_egress to be 0x2 (previous_value=0x2 OR new_value=0x2).
-Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_egress to be 0x2 (previous_value=0x2 OR new_value=0x2).
-Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=1][copy_index=0].adr_dist_table_thread to be 0x2 (previous_value=0x2 OR new_value=0x2).
-Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=1][copy_index=1].adr_dist_table_thread to be 0x2 (previous_value=0x2 OR new_value=0x2).
-Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id).
-Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
-Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id).
-Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
-Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_default to be 0x0.
-Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x1.
-Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0xff.
-Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2).
-Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x2080.
-Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
-Configuring dp.imem.imem_subword8[unit_number=18][vliw_instruction_number=0].imem_subword8_instr to be 0x592.
-Configuring dp.imem.imem_subword8[unit_number=18][vliw_instruction_number=0].imem_subword8_color to be 1.
-Configuring dp.imem.imem_subword8[unit_number=18][vliw_instruction_number=0].imem_subword8_parity to be 0.
-Micro instruction added in VLIW 0 for 8-bit position 18 for table egress_pkt.
- Assembled as 0x592 (or decimal 1426)
- Micro Instruction deposit-field for PHV Container 82 has bit width 20
- Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
- Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
- Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
- Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
- Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11])
- Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14])
- Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16])
- Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
-
-Configuring dp.imem.imem_subword16[unit_number=17][vliw_instruction_number=0].imem_subword16_instr to be 0x39fc01.
-Configuring dp.imem.imem_subword16[unit_number=17][vliw_instruction_number=0].imem_subword16_color to be 1.
-Configuring dp.imem.imem_subword16[unit_number=17][vliw_instruction_number=0].imem_subword16_parity to be 0.
-Micro instruction added in VLIW 0 for 16-bit position 17 for table egress_pkt.
- Assembled as 0x39fc01 (or decimal 3800065)
- Micro Instruction deposit-field for PHV Container 145 has bit width 23
- Field Src2 [3:0] : 0x1 (4 bits in instruction bits [3:0])
- Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
- Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
- Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
- Field high_bit [3:0] : 0xf (4 bits in instruction bits [14:11])
- Field low_bit_lo [0:0] : 0x1 (1 bits in instruction bits [15:15])
- Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16])
- Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20])
-
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=6].actionmux_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=10].actionmux_din_power_ctl to be 0x3. (previous value = 0x0 OR new value = 0x3)
-Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=0].action_instruction_adr_payload_shifter_en to be 1.
-+------------------------------------------------------------------------
-Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 10.
-Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
-Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 1.
-Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 10.
-Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
-Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 1.
-Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
-Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
-Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
-Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
-Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
-Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x3.
-Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
-Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
-Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x3.
-Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
-Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x1.
-Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
-Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
-Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19.
-Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
-Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
-Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
-Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
-Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
-Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
-Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
-Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
---------------------------------------------
-Configuration for unused statistics ALUs.
-Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
-Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
-Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
-Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
-+------------------------------------------------------------------------
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
-Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
-Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
-Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
-Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
-Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
-Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
-Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
-Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
-Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
-Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
-Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
-Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
-+------------------------------------------------------------------------
-Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
-Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
-Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0.
-Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
-Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
-Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
-Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0.
-Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
-Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
-Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0.
-Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
-Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
-Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
-Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
-
-+------------------------------------------------------------------------
-| MAU Stage 1
-+------------------------------------------------------------------------
-
-+------------------------------------------------------------------------
-| Working on table _condition_1 in stage 1 ---
-+------------------------------------------------------------------------
---> Stage Gateway Table for condition _condition_1 in stage 1
-Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
-Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
-Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
-Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
-Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
-Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x2. (old value = 0x0 OR new value = 0x2)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_address to be 4.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_address to be 3.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=12].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 12 to come from 8-bit PHV container 4.
+Configuring match input crossbar byte 12 to come from 8-bit PHV container 3.
That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x10. (previous value = 0x0 OR new value = 0x10)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=6][hash_bit_index=40].byte0 to be 0x2.
@@ -386,7 +77,7 @@
Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xfffffe
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x10
-Configuring rams.match.merge.gateway_next_table_lut[0][4] to be 0x30
+Configuring rams.match.merge.gateway_next_table_lut[0][4] to be 0x1
Configuring rams.match.merge.gateway_en.gateway_en to be 0x1
Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf
Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1
@@ -396,7 +87,110 @@
Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff
+------------------------------------------------------------------------
-| Working on table table0__action__ in stage 1 ---
+| Working on table process_packet_out_table__action__ in stage 0 ---
++------------------------------------------------------------------------
+--> Action Data Table process_packet_out_table__action__ with logical_table_id 1 that is reference type is 'direct'
+
++------------------------------------------------------------------------
+| Working on table process_packet_out_table in stage 0 ---
++------------------------------------------------------------------------
+--> Match Table with no key process_packet_out_table with logical_table_id 1
+allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
+Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
+Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
+Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
+Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
+Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
+Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
+Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 1 (logical table id).
+Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
+Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 1 (logical table id).
+Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1.
+Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x40.
+Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x0.
+Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0x20.
+Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0x20.
+Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x2 (previous_value=0x0 OR new_value=0x2).
+Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x45.
+Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
+Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_instr to be 0x74412.
+Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_color to be 1.
+Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=2].imem_subword16_parity to be 0.
+Micro instruction added in VLIW 2 for 16-bit position 2 for table process_packet_out_table.
+ Assembled as 0x74412 (or decimal 476178)
+ Micro Instruction deposit-field for PHV Container 130 has bit width 23
+ Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
+ Field Src1 [4:0] : 0x1 (5 bits in instruction bits [8:4])
+ Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
+ Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
+ Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
+ Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
+ Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16])
+ Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
+
+Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=2].imem_subword8_instr to be 0x74d83.
+Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=2].imem_subword8_color to be 1.
+Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=2].imem_subword8_parity to be 1.
+Micro instruction added in VLIW 2 for 8-bit position 3 for table process_packet_out_table.
+ Assembled as 0x74d83 (or decimal 478595)
+ Micro Instruction deposit-field for PHV Container 67 has bit width 20
+ Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
+ Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4])
+ Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
+ Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
+ Field high_bit [2:0] : 0x1 (3 bits in instruction bits [13:11])
+ Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14])
+ Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16])
+ Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
+
+Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
+Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6)
+--> Stage Gateway Table for condition process_packet_out_table_always_true_condition in stage 0
+Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
+Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
+Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
+Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
+Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
+Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
+Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x2. (old value = 0x2 OR new value = 0x0)
+Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x2 OR new value = 0x0)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
+Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
+Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
+Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
+Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
+Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0
+Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1
+Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0
+Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0
+Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3
+Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3
+Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff
+Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff
+Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff
+Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff
+Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8
+Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0x20
+Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10)
+Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0x20
+Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2)
+Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe
+Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1
+allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
+Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x1
+Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1
+Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2
+Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x0
+Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0
+Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x0
+Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0
+Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff
+Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff
+Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
+
++------------------------------------------------------------------------
+| Working on table table0__action__ in stage 0 ---
+------------------------------------------------------------------------
--> Action Data Table table0__action__ with logical_table_id 0 that is reference type is 'direct'
Configuring rams.array.row[row=6].action_hv_xbar.action_hv_ixbar_input_bytemask[array_half=1].action_hv_ixbar_input_bytemask to be 0x3.
@@ -465,12 +259,12 @@
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=10].match_input_xbar_816b_ctl_enable to be 1.
Configuring match input crossbar byte 10 to come from 16-bit PHV container 3.
That PHV byte contains {ipv4.srcAddr[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_address to be 1.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_address to be 0.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=11].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 11 to come from 8-bit PHV container 1.
+Configuring match input crossbar byte 11 to come from 8-bit PHV container 0.
That PHV byte contains {ipv4.srcAddr[23:16]}.
Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x26. (previous value = 0x0 OR new value = 0x26)
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x12. (previous value = 0x10 OR new value = 0x2)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x9. (previous value = 0x8 OR new value = 0x1)
Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8)
Configuring dp.xbar_hash.hash.hash_seed[output_bit=0].hash_seed to be 0x1 (previous value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x3. (previous value = 0x2 OR new value = 0x3)
@@ -496,15 +290,15 @@
Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=1][control_group_index=0].mau_hash_group_xbar_ctl to be 0x8 (old value = 0x0 OR new value = 0x8).
+------------------------------------------------------------------------
-| Working on table table0 in stage 1 ---
+| Working on table table0 in stage 0 ---
+------------------------------------------------------------------------
--> Ternary Match Table table0 with logical_table_id 0
-Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
-Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
-Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
-Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
-Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
-Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
+Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1).
+Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1).
+Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1).
+Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x1).
+Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1).
+Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x1).
Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id).
Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_enable to be 1.
Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id).
@@ -517,9 +311,9 @@
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x870a080.
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x44.
Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
-Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x30.
-Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data1 to be 0x20.
-Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x30.
+Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x20.
+Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data1 to be 0x10.
+Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x20.
Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x1.
Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=1][result_bus_number=0].mau_immediate_data_mask to be 0x0.
Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=1][result_bus_number=0].mau_stats_adr_mask to be 0xffffe.
@@ -583,19 +377,19 @@
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_enable to be 1.
Configuring match input crossbar byte 141 to come from 16-bit PHV container 4.
That PHV byte contains {ethernet.dstAddr[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 3.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 2.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 142 to come from 8-bit PHV container 3.
+Configuring match input crossbar byte 142 to come from 8-bit PHV container 2.
That PHV byte contains {ethernet.srcAddr[39:32]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 1.
Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 143 to come from 8-bit PHV container 2.
+Configuring match input crossbar byte 143 to come from 8-bit PHV container 1.
That PHV byte contains {ethernet.dstAddr[47:40]}.
Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x3e. (previous value = 0x26 OR new value = 0x18)
-Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x1e. (previous value = 0x12 OR new value = 0xc)
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0xf. (previous value = 0x9 OR new value = 0x6)
Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x39. (previous value = 0x8 OR new value = 0x31)
---> Idletime Table for match table table0 in stage 1
+--> Idletime Table for match table table0 in stage 0
Looking at Map RAM: Row 7 Unit 0
Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 0.
Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 1.
@@ -652,7 +446,7 @@
Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
+Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x6 OR new value = 0x4)
Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_instr to be 0xc7a06.
Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_color to be 0.
Configuring dp.imem.imem_subword16[unit_number=6][vliw_instruction_number=1].imem_subword16_parity to be 1.
@@ -677,13 +471,28 @@
Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20])
-Configuring dp.imem.imem_subword8[unit_number=0][vliw_instruction_number=1].imem_subword8_instr to be 0x590.
-Configuring dp.imem.imem_subword8[unit_number=0][vliw_instruction_number=1].imem_subword8_color to be 1.
-Configuring dp.imem.imem_subword8[unit_number=0][vliw_instruction_number=1].imem_subword8_parity to be 1.
-Micro instruction added in VLIW 1 for 8-bit position 0 for table table0.
- Assembled as 0x590 (or decimal 1424)
- Micro Instruction deposit-field for PHV Container 64 has bit width 20
- Field Src2 [3:0] : 0x0 (4 bits in instruction bits [3:0])
+Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_instr to be 0x4602.
+Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_color to be 1.
+Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=1].imem_subword16_parity to be 1.
+Micro instruction added in VLIW 1 for 16-bit position 2 for table table0.
+ Assembled as 0x4602 (or decimal 17922)
+ Micro Instruction deposit-field for PHV Container 130 has bit width 23
+ Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
+ Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
+ Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
+ Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
+ Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
+ Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
+ Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
+ Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
+
+Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_instr to be 0x593.
+Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_color to be 1.
+Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=1].imem_subword8_parity to be 1.
+Micro instruction added in VLIW 1 for 8-bit position 3 for table table0.
+ Assembled as 0x593 (or decimal 1427)
+ Micro Instruction deposit-field for PHV Container 67 has bit width 20
+ Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -692,14 +501,30 @@
Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16])
Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x1. (previous value = 0x0 OR new value = 0x1)
-Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_instr to be 0xb7d95.
-Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_color to be 0.
-Configuring dp.imem.imem_subword8[unit_number=5][vliw_instruction_number=2].imem_subword8_parity to be 1.
-Micro instruction added in VLIW 2 for 8-bit position 5 for table table0.
- Assembled as 0xb7d95 (or decimal 753045)
- Micro Instruction deposit-field for PHV Container 69 has bit width 20
- Field Src2 [3:0] : 0x5 (4 bits in instruction bits [3:0])
+Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_instr to be 0x39fc01.
+Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_color to be 1.
+Configuring dp.imem.imem_subword16[unit_number=1][vliw_instruction_number=1].imem_subword16_parity to be 0.
+Micro instruction added in VLIW 1 for 16-bit position 1 for table table0.
+ Assembled as 0x39fc01 (or decimal 3800065)
+ Micro Instruction deposit-field for PHV Container 129 has bit width 23
+ Field Src2 [3:0] : 0x1 (4 bits in instruction bits [3:0])
+ Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
+ Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
+ Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
+ Field high_bit [3:0] : 0xf (4 bits in instruction bits [14:11])
+ Field low_bit_lo [0:0] : 0x1 (1 bits in instruction bits [15:15])
+ Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16])
+ Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20])
+
+Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x8. (previous value = 0x8 OR new value = 0x8)
+Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x7. (previous value = 0x6 OR new value = 0x7)
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_instr to be 0xb7d94.
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_color to be 0.
+Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=2].imem_subword8_parity to be 0.
+Micro instruction added in VLIW 2 for 8-bit position 4 for table table0.
+ Assembled as 0xb7d94 (or decimal 753044)
+ Micro Instruction deposit-field for PHV Container 68 has bit width 20
+ Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -708,7 +533,7 @@
Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16])
Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19])
-Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x21. (previous value = 0x1 OR new value = 0x20)
+Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x18. (previous value = 0x8 OR new value = 0x10)
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].idletime_adr_payload_shifter_en to be 1.
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].stats_adr_payload_shifter_en to be 1.
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].actiondata_adr_payload_shifter_en to be 1.
@@ -822,7 +647,7 @@
Configuring cfg_regs.mau_cfg_movereg_tcam_only.mau_cfg_movereg_tcam_only to be 0x1. (previous value = 0x0 OR new value = 0x1)
+------------------------------------------------------------------------
-| Working on table table0_counter in stage 1 ---
+| Working on table table0_counter in stage 0 ---
+------------------------------------------------------------------------
Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
@@ -908,24 +733,24 @@
Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x7. ( previous value = 0x0 OR new value = 0x7)
Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x1.
+------------------------------------------------------------------------
-Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 21.
-Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9.
-Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3.
+Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 12.
+Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
+Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 1.
Configuring rams.match.merge.exact_match_delay_thread[copy_index=0].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
Configuring rams.match.merge.exact_match_delay_thread[copy_index=1].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
Configuring rams.match.merge.exact_match_delay_thread[copy_index=2].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1)
-Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
+Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 10.
Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
-Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
+Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 1.
Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
-Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x1.
-Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
-Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
+Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x3.
+Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x2.
+Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x2.
Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
-Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
+Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x2.
Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
@@ -948,18 +773,18 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
@@ -979,28 +804,28 @@
Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0.
Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
-Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
+Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0.
Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
-Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1.
-Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2.
+Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
+Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0.
Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
+------------------------------------------------------------------------
-| MAU Stage 2
+| MAU Stage 1
+------------------------------------------------------------------------
+------------------------------------------------------------------------
-| Working on table ecmp_group_table__action__ in stage 2 ---
+| Working on table ecmp_group_table__action__ in stage 1 ---
+------------------------------------------------------------------------
--> Action Data Table ecmp_group_table__action__ with logical_table_id 0 that is reference type is 'direct'
Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_select to be 4.
Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_enable to be 1.
+------------------------------------------------------------------------
-| Working on table ecmp_group_table in stage 2 ---
+| Working on table ecmp_group_table in stage 1 ---
+------------------------------------------------------------------------
--> Hash Match Table ecmp_group_table with logical_table_id 0
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
@@ -1020,8 +845,8 @@
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x41.
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
-Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x30.
-Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x30.
+Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x20.
+Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x20.
Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x0.
Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=0][result_bus_number=14].mau_immediate_data_mask to be 0xffff.
Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=0][result_bus_number=14].mau_stats_adr_mask to be 0xffffe.
@@ -1818,7 +1643,7 @@
Configuring rams.match.merge.col[col_number=4].hitmap_output_map[hit_signal=14].enabled_4bit_muxctl_enable to be 1.
+------------------------------------------------------------------------
-| Working on table ecmp_group_table_counter in stage 2 ---
+| Working on table ecmp_group_table_counter in stage 1 ---
+------------------------------------------------------------------------
Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
@@ -1940,18 +1765,18 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
@@ -1981,13 +1806,13 @@
Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
+------------------------------------------------------------------------
-| MAU Stage 3
+| MAU Stage 2
+------------------------------------------------------------------------
+------------------------------------------------------------------------
-| Working on table _condition_2 in stage 3 ---
+| Working on table _condition_2 in stage 2 ---
+------------------------------------------------------------------------
---> Stage Gateway Table for condition _condition_2 in stage 3
+--> Stage Gateway Table for condition _condition_2 in stage 2
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1).
@@ -2036,7 +1861,7 @@
Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff3f
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8
-Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x31
+Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x21
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid0 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid1 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][0] to be 0xffffffff
@@ -2044,15 +1869,15 @@
Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff7fff
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xc (previous value 0x8 OR new value 0x4)
-Configuring rams.match.merge.gateway_next_table_lut[0][2] to be 0x31
+Configuring rams.match.merge.gateway_next_table_lut[0][2] to be 0x21
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid0 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid1 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][0] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][1] to be 0xffffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0xffff
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0x1ffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][1] to be 0xffff
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xe (previous value 0xc OR new value 0x2)
-Configuring rams.match.merge.gateway_next_table_lut[0][1] to be 0x31
+Configuring rams.match.merge.gateway_next_table_lut[0][1] to be 0x21
Configuring rams.match.merge.gateway_en.gateway_en to be 0x1
Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf
Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1
@@ -2068,12 +1893,12 @@
Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff
+------------------------------------------------------------------------
-| Working on table ingress_port_count_table__action__ in stage 3 ---
+| Working on table ingress_port_count_table__action__ in stage 2 ---
+------------------------------------------------------------------------
--> Action Data Table ingress_port_count_table__action__ with logical_table_id 0 that is reference type is 'direct'
+------------------------------------------------------------------------
-| Working on table ingress_port_count_table in stage 3 ---
+| Working on table ingress_port_count_table in stage 2 ---
+------------------------------------------------------------------------
--> Match Table with no key ingress_port_count_table with logical_table_id 0
allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
@@ -2099,12 +1924,12 @@
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
+------------------------------------------------------------------------
-| Working on table egress_port_count_table__action__ in stage 3 ---
+| Working on table egress_port_count_table__action__ in stage 2 ---
+------------------------------------------------------------------------
--> Action Data Table egress_port_count_table__action__ with logical_table_id 1 that is reference type is 'direct'
+------------------------------------------------------------------------
-| Working on table egress_port_count_table in stage 3 ---
+| Working on table egress_port_count_table in stage 2 ---
+------------------------------------------------------------------------
--> Match Table with no key egress_port_count_table with logical_table_id 1
allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
@@ -2126,7 +1951,7 @@
Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2).
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x40.
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
---> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 3
+--> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 2
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
@@ -2171,7 +1996,7 @@
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=0].action_instruction_adr_payload_shifter_en to be 1.
+------------------------------------------------------------------------
-| Working on table ingress_port_counter in stage 3 ---
+| Working on table ingress_port_counter in stage 2 ---
+------------------------------------------------------------------------
Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
@@ -2255,7 +2080,7 @@
Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=2].mau_ad_stats_virt_lt be 0x1.
+------------------------------------------------------------------------
-| Working on table egress_port_counter in stage 3 ---
+| Working on table egress_port_counter in stage 2 ---
+------------------------------------------------------------------------
Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1.
Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0.
@@ -2374,18 +2199,18 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
@@ -2415,6 +2240,88 @@
Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
+------------------------------------------------------------------------
+| MAU Stage 3
++------------------------------------------------------------------------
++------------------------------------------------------------------------
+Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0.
+Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0.
+Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0.
+Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0.
+Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0.
+Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0.
+Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0.
+Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0.
+Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0.
+Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0.
+Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0.
+Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0.
+Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0.
+Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0.
+Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0.
+Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0.
+Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0.
+Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0.
+Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14.
+Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0.
+Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1.
+Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14.
+Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0.
+Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1.
+Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0.
+Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0.
+Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0.
+Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0.
+--------------------------------------------
+Configuration for unused statistics ALUs.
+Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf.
+Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf.
+Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf.
+Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf.
++------------------------------------------------------------------------
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
+Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
+Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
+Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
+Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1.
+Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0.
+Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0.
+Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1.
+Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1.
+Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1.
+Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1.
+Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0.
+Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0.
++------------------------------------------------------------------------
+Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17.
+Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0.
+Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2.
+Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2.
+Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17.
+Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0.
+Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2.
+Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2.
+Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0.
+Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3.
+Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1.
+Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0.
+Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1.
+Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
+
++------------------------------------------------------------------------
| MAU Stage 4
+------------------------------------------------------------------------
+------------------------------------------------------------------------
@@ -2456,18 +2363,18 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
@@ -2538,18 +2445,18 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
@@ -2620,18 +2527,18 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
@@ -2702,18 +2609,18 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
@@ -2784,18 +2691,18 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
@@ -2866,18 +2773,18 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
@@ -2948,18 +2855,18 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
@@ -3030,18 +2937,18 @@
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x3f.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x3f.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x3f.
-Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x3f.
-Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x3f.
-Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x3f.
+Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f.
+Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f.
+Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f.
Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0xff.
Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0xff.
Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0xff.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7.
-Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7.
-Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7.
-Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x3.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x3.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x3.
+Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x1.
+Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x1.
+Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x1.
Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1.
Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1.
@@ -3071,7 +2978,7 @@
Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
+------------------------------------------------------------------------
-| Number of configuration field values set in Match-Action Stages: 2168
+| Number of configuration field values set in Match-Action Stages: 2100
+------------------------------------------------------------------------
+------------------------------------------------------------------------
@@ -3084,10 +2991,10 @@
| Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency |
| | | | | LPF | (max words) | | to Previous |
-----------------------------------------------------------------------------------------------
-| 0 | Yes | No | No | No | No (0) | No | match |
-| 1 | No | Yes | Yes | No | No (0) | No | match |
+| 0 | Yes | Yes | Yes | No | No (0) | No | match |
+| 1 | Yes | No | Yes | No | No (0) | No | match |
| 2 | Yes | No | Yes | No | No (0) | No | match |
-| 3 | Yes | No | Yes | No | No (0) | No | match |
+| 3 | Yes* | No | Yes* | No | No (0) | No | concurrent |
| 4 | Yes* | No | Yes* | No | No (0) | No | concurrent |
| 5 | Yes* | No | Yes* | No | No (0) | No | concurrent |
| 6 | No | No | No | No | No (0) | No | match |
@@ -3106,12 +3013,12 @@
| Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency |
| | | | | LPF | (max words) | | to Previous |
-----------------------------------------------------------------------------------------------
-| 0 | Yes | No | No | No | No (0) | No | match |
-| 1 | Yes* | No | No | No | No (0) | No | concurrent |
-| 2 | Yes* | No | No | No | No (0) | No | concurrent |
-| 3 | Yes* | No | No | No | No (0) | No | concurrent |
-| 4 | Yes* | No | No | No | No (0) | No | concurrent |
-| 5 | Yes* | No | No | No | No (0) | No | concurrent |
+| 0 | No | No | No | No | No (0) | No | match |
+| 1 | No | No | No | No | No (0) | No | concurrent |
+| 2 | No | No | No | No | No (0) | No | concurrent |
+| 3 | No | No | No | No | No (0) | No | concurrent |
+| 4 | No | No | No | No | No (0) | No | concurrent |
+| 5 | No | No | No | No | No (0) | No | concurrent |
| 6 | No | No | No | No | No (0) | No | match |
| 7 | No | No | No | No | No (0) | No | concurrent |
| 8 | No | No | No | No | No (0) | No | concurrent |
@@ -3131,10 +3038,10 @@
-----------------------------------------------------------------------------------------------------
| Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency |
-----------------------------------------------------------------------------------------------------
-| 0 | 20 | 11 | match | 20 |
-| 1 | 22 | 13 | match | 22 |
+| 0 | 22 | 13 | match | 22 |
+| 1 | 20 | 11 | match | 20 |
| 2 | 20 | 11 | match | 20 |
-| 3 | 20 | 11 | match | 20 |
+| 3 | 20 | 11 | concurrent | 1 |
| 4 | 20 | 11 | concurrent | 1 |
| 5 | 20 | 11 | concurrent | 1 |
| 6 | 20 | 11 | match | 20 |
@@ -3145,7 +3052,7 @@
| 11 | 20 | 11 | concurrent | 1 |
-----------------------------------------------------------------------------------------------------
-Total latency for ingress: 113
+Total latency for ingress: 94
Clock Cycles Per Stage For egress:
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gateway.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gateway.log
index c9e46f6..948e767 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gateway.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gateway.log
@@ -1,9 +1,24 @@
+---------------------------------------------------------------------+
| Log file: mau.gateway.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
+
+========================================================
+ Run Gateway Placement on Request List of size 0
+========================================================
+
+
+========================================================
+ Run Gateway Placement on Request List of size 0
+========================================================
+
+
+========================================================
+ Run Gateway Placement on Request List of size 0
+========================================================
+
valid:
f = packet_out_hdr
const:
@@ -110,7 +125,7 @@
match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
- final_parity_group_ids = [(0, []), (1, [])]
+ final_parity_group_ids = [(0, [0]), (1, [0])]
open_parity_group_ids = [0, 1]
----------------------------
@@ -120,13 +135,13 @@
Call to _place_fields_for_constant_comparison
constant_match_key_partition is:
Byte Position 0
- (68, 0)
+ (67, 0)
Byte Position 1
- (68, 0)
+ (67, 0)
Byte Position 2
- (68, 0)
+ (67, 0)
Byte Position 3
- (68, 0)
+ (67, 0)
Available bytes in ram word is [0, 1, 2, 3, 4, 5, 6, 7]
Available data bytes for constants are [0, 1, 2, 3]
@@ -245,7 +260,7 @@
[42] = None
[43] = None
Hash Bit Mapping:
- (0, 1) --> 40
+ (12, 1) --> 40
Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 0 for gateway
Allocating: Gateway 15 in stage 0 for _condition_0.
@@ -341,7 +356,7 @@
match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
- final_parity_group_ids = [(0, []), (1, [])]
+ final_parity_group_ids = [(0, [0]), (1, [0])]
open_parity_group_ids = [0, 1]
----------------------------
@@ -351,13 +366,13 @@
Call to _place_fields_for_constant_comparison
constant_match_key_partition is:
Byte Position 0
- (68, 0)
+ (67, 0)
Byte Position 1
- (68, 0)
+ (67, 0)
Byte Position 2
- (68, 0)
+ (67, 0)
Byte Position 3
- (68, 0)
+ (67, 0)
Available bytes in ram word is [0, 1, 2, 3, 4, 5, 6, 7]
Available data bytes for constants are [0, 1, 2, 3]
@@ -476,42 +491,26 @@
[42] = None
[43] = None
Hash Bit Mapping:
- (0, 1) --> 40
+ (12, 1) --> 40
Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 0 for gateway
Allocating: Gateway 15 in stage 0 for _condition_0.
-
-========================================================
- Run Gateway Placement on Request List of size 0
-========================================================
-
-
-========================================================
- Run Gateway Placement on Request List of size 0
-========================================================
-
-
-========================================================
- Run Gateway Placement on Request List of size 0
-========================================================
-
valid:
- f = packet_out_hdr
const:
xor:
-Gateway Resource Request for P4 table _condition_1 with handle 117440514 in stage 1
+Gateway Resource Request for P4 table process_packet_out_table_always_true_condition with handle -1 in stage 0
Validity checks:
- Field --validity_check--packet_out_hdr [0:0]
+ <none>
Fields to check against constants:
<none>
Field pairs to compare to each other:
<none>
-Gateway Resource Request for table _condition_1 needs access to 1 input bits
+Gateway Resource Request for table process_packet_out_table_always_true_condition needs access to 0 input bits
========================================================
- Run Gateway Placement on Request List of size 1
+ Run Gateway Placement on Request List of size 2
========================================================
Available Gateways are: (16)
@@ -605,19 +604,19 @@
open_parity_group_ids = [0, 1]
----------------------------
- Trying to place Gateway Resource Request for table _condition_1 needs access to 1 input bits in exact match group 0 (parity groups [0, 1]) and hash group 0 for gateway 15.
+ Trying to place Gateway Resource Request for table _condition_0 needs access to 1 input bits in exact match group 0 (parity groups [0, 1]) and hash group 0 for gateway 15.
----------------------------
--------------
Call to _place_fields_for_constant_comparison
constant_match_key_partition is:
Byte Position 0
- (68, 0)
+ (67, 0)
Byte Position 1
- (68, 0)
+ (67, 0)
Byte Position 2
- (68, 0)
+ (67, 0)
Byte Position 3
- (68, 0)
+ (67, 0)
Available bytes in ram word is [0, 1, 2, 3, 4, 5, 6, 7]
Available data bytes for constants are [0, 1, 2, 3]
@@ -738,11 +737,149 @@
Hash Bit Mapping:
(12, 1) --> 40
-Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 1 for gateway
-Allocating: Gateway 15 in stage 1 for _condition_1.
+Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 0 for gateway
+Allocating: Gateway 15 in stage 0 for _condition_0.
+Available Gateways are: (15)
+Gateway 0
+Gateway 1
+Gateway 2
+Gateway 3
+Gateway 4
+Gateway 5
+Gateway 6
+Gateway 7
+Gateway 8
+Gateway 9
+Gateway 10
+Gateway 11
+Gateway 12
+Gateway 13
+Gateway 14
+------- Phase 0 -------------
+Looking at gateway table 14
+match_groups_attached_to_gateway = OrderedDict([(0, (0, [1], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f498e8ad150>, 0)])), (1, (None, [], None, [], []))])
+Search bus 0 on row 7
+----------------------------
+ Trying to place Gateway Resource Request for table process_packet_out_table_always_true_condition needs access to 0 input bits in exact match group 0 (parity groups [1]) and hash group 0 for gateway 14.
+----------------------------
+Gateway data search bus packing is:
+ [0] = None
+ [1] = None
+ [2] = None
+ [3] = None
+ [4] = None
+ [5] = None
+ [6] = None
+ [7] = None
+ [8] = None
+ [9] = None
+ [10] = None
+ [11] = None
+ [12] = None
+ [13] = None
+ [14] = None
+ [15] = None
+ [16] = None
+ [17] = None
+ [18] = None
+ [19] = None
+ [20] = None
+ [21] = None
+ [22] = None
+ [23] = None
+ [24] = None
+ [25] = None
+ [26] = None
+ [27] = None
+ [28] = None
+ [29] = None
+ [30] = None
+ [31] = None
+ [32] = None
+ [33] = None
+ [34] = None
+ [35] = None
+ [36] = None
+ [37] = None
+ [38] = None
+ [39] = None
+ [40] = None
+ [41] = None
+ [42] = None
+ [43] = None
+ [44] = None
+ [45] = None
+ [46] = None
+ [47] = None
+ [48] = None
+ [49] = None
+ [50] = None
+ [51] = None
+ [52] = None
+ [53] = None
+ [54] = None
+ [55] = None
+ [56] = None
+ [57] = None
+ [58] = None
+ [59] = None
+ [60] = None
+ [61] = None
+ [62] = None
+ [63] = None
+ Move Byte Mapping:
+
+Final Gateway Key is:
+ [0] = None
+ [1] = None
+ [2] = None
+ [3] = None
+ [4] = None
+ [5] = None
+ [6] = None
+ [7] = None
+ [8] = None
+ [9] = None
+ [10] = None
+ [11] = None
+ [12] = None
+ [13] = None
+ [14] = None
+ [15] = None
+ [16] = None
+ [17] = None
+ [18] = None
+ [19] = None
+ [20] = None
+ [21] = None
+ [22] = None
+ [23] = None
+ [24] = None
+ [25] = None
+ [26] = None
+ [27] = None
+ [28] = None
+ [29] = None
+ [30] = None
+ [31] = None
+ [32] = None
+ [33] = None
+ [34] = None
+ [35] = None
+ [36] = None
+ [37] = None
+ [38] = None
+ [39] = None
+ [40] = None
+ [41] = None
+ [42] = None
+ [43] = None
+ Hash Bit Mapping:
+
+Allocating: Gateway 14 in stage 0 for process_packet_out_table_always_true_condition.
========================================================
- Run Gateway Placement on Request List of size 1
+ Run Gateway Placement on Request List of size 2
========================================================
Available Gateways are: (16)
@@ -836,19 +973,19 @@
open_parity_group_ids = [0, 1]
----------------------------
- Trying to place Gateway Resource Request for table _condition_1 needs access to 1 input bits in exact match group 0 (parity groups [0, 1]) and hash group 0 for gateway 15.
+ Trying to place Gateway Resource Request for table _condition_0 needs access to 1 input bits in exact match group 0 (parity groups [0, 1]) and hash group 0 for gateway 15.
----------------------------
--------------
Call to _place_fields_for_constant_comparison
constant_match_key_partition is:
Byte Position 0
- (68, 0)
+ (67, 0)
Byte Position 1
- (68, 0)
+ (67, 0)
Byte Position 2
- (68, 0)
+ (67, 0)
Byte Position 3
- (68, 0)
+ (67, 0)
Available bytes in ram word is [0, 1, 2, 3, 4, 5, 6, 7]
Available data bytes for constants are [0, 1, 2, 3]
@@ -969,8 +1106,146 @@
Hash Bit Mapping:
(12, 1) --> 40
-Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 1 for gateway
-Allocating: Gateway 15 in stage 1 for _condition_1.
+Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 0 for gateway
+Allocating: Gateway 15 in stage 0 for _condition_0.
+Available Gateways are: (15)
+Gateway 0
+Gateway 1
+Gateway 2
+Gateway 3
+Gateway 4
+Gateway 5
+Gateway 6
+Gateway 7
+Gateway 8
+Gateway 9
+Gateway 10
+Gateway 11
+Gateway 12
+Gateway 13
+Gateway 14
+------- Phase 0 -------------
+Looking at gateway table 14
+match_groups_attached_to_gateway = OrderedDict([(0, (0, [1], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f498e2edb10>, 0)])), (1, (None, [], None, [], []))])
+Search bus 0 on row 7
+----------------------------
+ Trying to place Gateway Resource Request for table process_packet_out_table_always_true_condition needs access to 0 input bits in exact match group 0 (parity groups [1]) and hash group 0 for gateway 14.
+----------------------------
+Gateway data search bus packing is:
+ [0] = None
+ [1] = None
+ [2] = None
+ [3] = None
+ [4] = None
+ [5] = None
+ [6] = None
+ [7] = None
+ [8] = None
+ [9] = None
+ [10] = None
+ [11] = None
+ [12] = None
+ [13] = None
+ [14] = None
+ [15] = None
+ [16] = None
+ [17] = None
+ [18] = None
+ [19] = None
+ [20] = None
+ [21] = None
+ [22] = None
+ [23] = None
+ [24] = None
+ [25] = None
+ [26] = None
+ [27] = None
+ [28] = None
+ [29] = None
+ [30] = None
+ [31] = None
+ [32] = None
+ [33] = None
+ [34] = None
+ [35] = None
+ [36] = None
+ [37] = None
+ [38] = None
+ [39] = None
+ [40] = None
+ [41] = None
+ [42] = None
+ [43] = None
+ [44] = None
+ [45] = None
+ [46] = None
+ [47] = None
+ [48] = None
+ [49] = None
+ [50] = None
+ [51] = None
+ [52] = None
+ [53] = None
+ [54] = None
+ [55] = None
+ [56] = None
+ [57] = None
+ [58] = None
+ [59] = None
+ [60] = None
+ [61] = None
+ [62] = None
+ [63] = None
+ Move Byte Mapping:
+
+Final Gateway Key is:
+ [0] = None
+ [1] = None
+ [2] = None
+ [3] = None
+ [4] = None
+ [5] = None
+ [6] = None
+ [7] = None
+ [8] = None
+ [9] = None
+ [10] = None
+ [11] = None
+ [12] = None
+ [13] = None
+ [14] = None
+ [15] = None
+ [16] = None
+ [17] = None
+ [18] = None
+ [19] = None
+ [20] = None
+ [21] = None
+ [22] = None
+ [23] = None
+ [24] = None
+ [25] = None
+ [26] = None
+ [27] = None
+ [28] = None
+ [29] = None
+ [30] = None
+ [31] = None
+ [32] = None
+ [33] = None
+ [34] = None
+ [35] = None
+ [36] = None
+ [37] = None
+ [38] = None
+ [39] = None
+ [40] = None
+ [41] = None
+ [42] = None
+ [43] = None
+ Hash Bit Mapping:
+
+Allocating: Gateway 14 in stage 0 for process_packet_out_table_always_true_condition.
========================================================
Run Gateway Placement on Request List of size 0
@@ -990,7 +1265,7 @@
const:
f = ig_intr_md_for_tm.ucast_egress_port
xor:
-Gateway Resource Request for P4 table _condition_2 with handle 117440515 in stage 3
+Gateway Resource Request for P4 table _condition_2 with handle 117440514 in stage 2
Validity checks:
<none>
Fields to check against constants:
@@ -1245,8 +1520,8 @@
(0, 6) --> 47
(0, 7) --> 48
-Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 3 for gateway
-Allocating: Gateway 15 in stage 3 for _condition_2.
+Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 2 for gateway
+Allocating: Gateway 15 in stage 2 for _condition_2.
========================================================
Run Gateway Placement on Request List of size 1
@@ -1492,8 +1767,8 @@
(0, 6) --> 47
(0, 7) --> 48
-Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 3 for gateway
-Allocating: Gateway 15 in stage 3 for _condition_2.
+Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 2 for gateway
+Allocating: Gateway 15 in stage 2 for _condition_2.
========================================================
Run Gateway Placement on Request List of size 1
@@ -1739,12 +2014,12 @@
(0, 6) --> 47
(0, 7) --> 48
-Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 3 for gateway
-Allocating: Gateway 15 in stage 3 for _condition_2.
+Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 2 for gateway
+Allocating: Gateway 15 in stage 2 for _condition_2.
valid:
const:
xor:
-Gateway Resource Request for P4 table egress_port_count_table_always_true_condition with handle -1 in stage 3
+Gateway Resource Request for P4 table egress_port_count_table_always_true_condition with handle -1 in stage 2
Validity checks:
<none>
Fields to check against constants:
@@ -1999,8 +2274,8 @@
(0, 6) --> 47
(0, 7) --> 48
-Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 3 for gateway
-Allocating: Gateway 15 in stage 3 for _condition_2.
+Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 2 for gateway
+Allocating: Gateway 15 in stage 2 for _condition_2.
Available Gateways are: (15)
Gateway 0
Gateway 1
@@ -2019,7 +2294,7 @@
Gateway 14
------- Phase 0 -------------
Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f84d5cbff10>, 0)])), (1, (None, [], None, [], []))])
+match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f49924f5210>, 0)])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
----------------------------
Trying to place Gateway Resource Request for table egress_port_count_table_always_true_condition needs access to 0 input bits in exact match group 0 (parity groups [0]) and hash group 0 for gateway 14.
@@ -2138,7 +2413,7 @@
[43] = None
Hash Bit Mapping:
-Allocating: Gateway 14 in stage 3 for egress_port_count_table_always_true_condition.
+Allocating: Gateway 14 in stage 2 for egress_port_count_table_always_true_condition.
========================================================
Run Gateway Placement on Request List of size 2
@@ -2384,8 +2659,8 @@
(0, 6) --> 47
(0, 7) --> 48
-Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 3 for gateway
-Allocating: Gateway 15 in stage 3 for _condition_2.
+Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 2 for gateway
+Allocating: Gateway 15 in stage 2 for _condition_2.
Available Gateways are: (15)
Gateway 0
Gateway 1
@@ -2404,7 +2679,7 @@
Gateway 14
------- Phase 0 -------------
Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f84d27b5710>, 0)])), (1, (None, [], None, [], []))])
+match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f498e781990>, 0)])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
----------------------------
Trying to place Gateway Resource Request for table egress_port_count_table_always_true_condition needs access to 0 input bits in exact match group 0 (parity groups [0]) and hash group 0 for gateway 14.
@@ -2523,798 +2798,4 @@
[43] = None
Hash Bit Mapping:
-Allocating: Gateway 14 in stage 3 for egress_port_count_table_always_true_condition.
-valid:
-const:
- f = ig_intr_md_for_tm.copy_to_cpu
-xor:
-Gateway Resource Request for P4 table _condition_3 with handle 117440516 in stage 0
- Validity checks:
- <none>
- Fields to check against constants:
- Field ig_intr_md_for_tm.copy_to_cpu [0:0]
- Field pairs to compare to each other:
- <none>
-
-Gateway Resource Request for table _condition_3 needs access to 1 input bits
-
-
-========================================================
- Run Gateway Placement on Request List of size 2
-========================================================
-
-Available Gateways are: (16)
-Gateway 0
-Gateway 1
-Gateway 2
-Gateway 3
-Gateway 4
-Gateway 5
-Gateway 6
-Gateway 7
-Gateway 8
-Gateway 9
-Gateway 10
-Gateway 11
-Gateway 12
-Gateway 13
-Gateway 14
-Gateway 15
-------- Phase 0 -------------
-Looking at gateway table 15
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 7
-Search bus 1 on row 7
-Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 7
-Search bus 1 on row 7
-Looking at gateway table 13
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 6
-Search bus 1 on row 6
-Looking at gateway table 12
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 6
-Search bus 1 on row 6
-Looking at gateway table 11
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 5
-Search bus 1 on row 5
-Looking at gateway table 10
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 5
-Search bus 1 on row 5
-Looking at gateway table 9
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 4
-Search bus 1 on row 4
-Looking at gateway table 8
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 4
-Search bus 1 on row 4
-Looking at gateway table 7
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 3
-Search bus 1 on row 3
-Looking at gateway table 6
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 3
-Search bus 1 on row 3
-Looking at gateway table 5
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 2
-Search bus 1 on row 2
-Looking at gateway table 4
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 2
-Search bus 1 on row 2
-Looking at gateway table 3
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 1
-Search bus 1 on row 1
-Looking at gateway table 2
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 1
-Search bus 1 on row 1
-Looking at gateway table 1
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 0
-Search bus 1 on row 0
-Looking at gateway table 0
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 0
-Search bus 1 on row 0
-------- Phase 1 -------------
-Looking at gateway table 15
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 7
-
- final_parity_group_ids = [(0, []), (1, [])]
-
- open_parity_group_ids = [0, 1]
-----------------------------
- Trying to place Gateway Resource Request for table _condition_3 needs access to 1 input bits in exact match group 0 (parity groups [0, 1]) and hash group 0 for gateway 15.
-----------------------------
---------------
-Call to _place_fields_for_constant_comparison
-constant_match_key_partition is:
-Byte Position 0
- (80, 0)
-Byte Position 1
- (80, 0)
-Byte Position 2
- (80, 0)
-Byte Position 3
- (80, 0)
-
-Available bytes in ram word is [0, 1, 2, 3, 4, 5, 6, 7]
-Available data bytes for constants are [0, 1, 2, 3]
-Put all gateway constant field bits into the hash bits.
-Allocating: Hash Bit 40 in hash match group 0 for ('ig_intr_md_for_tm.copy_to_cpu', 0).
-Gateway data search bus packing is:
- [0] = None
- [1] = None
- [2] = None
- [3] = None
- [4] = None
- [5] = None
- [6] = None
- [7] = None
- [8] = None
- [9] = None
- [10] = None
- [11] = None
- [12] = None
- [13] = None
- [14] = None
- [15] = None
- [16] = None
- [17] = None
- [18] = None
- [19] = None
- [20] = None
- [21] = None
- [22] = None
- [23] = None
- [24] = None
- [25] = None
- [26] = None
- [27] = None
- [28] = None
- [29] = None
- [30] = None
- [31] = None
- [32] = None
- [33] = None
- [34] = None
- [35] = None
- [36] = None
- [37] = None
- [38] = None
- [39] = None
- [40] = None
- [41] = None
- [42] = None
- [43] = None
- [44] = None
- [45] = None
- [46] = None
- [47] = None
- [48] = None
- [49] = None
- [50] = None
- [51] = None
- [52] = None
- [53] = None
- [54] = None
- [55] = None
- [56] = None
- [57] = None
- [58] = None
- [59] = None
- [60] = None
- [61] = None
- [62] = None
- [63] = None
- Move Byte Mapping:
-
-Final Gateway Key is:
- [0] = None
- [1] = None
- [2] = None
- [3] = None
- [4] = None
- [5] = None
- [6] = None
- [7] = None
- [8] = None
- [9] = None
- [10] = None
- [11] = None
- [12] = None
- [13] = None
- [14] = None
- [15] = None
- [16] = None
- [17] = None
- [18] = None
- [19] = None
- [20] = None
- [21] = None
- [22] = None
- [23] = None
- [24] = None
- [25] = None
- [26] = None
- [27] = None
- [28] = None
- [29] = None
- [30] = None
- [31] = None
- [32] = (('ig_intr_md_for_tm.copy_to_cpu', 0), 'exact')
- [33] = None
- [34] = None
- [35] = None
- [36] = None
- [37] = None
- [38] = None
- [39] = None
- [40] = None
- [41] = None
- [42] = None
- [43] = None
- Hash Bit Mapping:
- (0, 0) --> 40
-
-Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 0 for gateway
-Allocating: Gateway 15 in stage 0 for _condition_3.
-Available Gateways are: (15)
-Gateway 0
-Gateway 1
-Gateway 2
-Gateway 3
-Gateway 4
-Gateway 5
-Gateway 6
-Gateway 7
-Gateway 8
-Gateway 9
-Gateway 10
-Gateway 11
-Gateway 12
-Gateway 13
-Gateway 14
-------- Phase 0 -------------
-Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f84d6772cd0>, 0)])), (1, (None, [], None, [], []))])
-Search bus 0 on row 7
-----------------------------
- Trying to place Gateway Resource Request for table _condition_0 needs access to 1 input bits in exact match group 0 (parity groups [0]) and hash group 0 for gateway 14.
-----------------------------
---------------
-Call to _place_fields_for_constant_comparison
-constant_match_key_partition is:
-Byte Position 0
- (68, 0)
-Byte Position 1
- (68, 0)
-Byte Position 2
- (68, 0)
-Byte Position 3
- (68, 0)
-
-Removing available byte Byte 8 is of type exact and member of group 0 (parity group 1) with 16 bytes. because not in available parity group(s) [0]
-Removing available byte Byte 10 is of type exact and member of group 0 (parity group 1) with 16 bytes. because not in available parity group(s) [0]
-Removing available byte Byte 12 is of type exact and member of group 0 (parity group 1) with 16 bytes. because not in available parity group(s) [0]
-Removing available byte Byte 14 is of type exact and member of group 0 (parity group 1) with 16 bytes. because not in available parity group(s) [0]
-Available bytes in ram word is [0, 1, 2, 3, 4, 5, 6, 7]
-Available data bytes for constants are [0, 1, 2, 3]
-Put all gateway constant field bits into the hash bits.
-Allocating: Hash Bit 41 in hash match group 0 for ('--validity_check--packet_out_hdr', 0).
-Gateway data search bus packing is:
- [0] = None
- [1] = None
- [2] = None
- [3] = None
- [4] = None
- [5] = None
- [6] = None
- [7] = None
- [8] = None
- [9] = None
- [10] = None
- [11] = None
- [12] = None
- [13] = None
- [14] = None
- [15] = None
- [16] = None
- [17] = None
- [18] = None
- [19] = None
- [20] = None
- [21] = None
- [22] = None
- [23] = None
- [24] = None
- [25] = None
- [26] = None
- [27] = None
- [28] = None
- [29] = None
- [30] = None
- [31] = None
- [32] = None
- [33] = None
- [34] = None
- [35] = None
- [36] = None
- [37] = None
- [38] = None
- [39] = None
- [40] = None
- [41] = None
- [42] = None
- [43] = None
- [44] = None
- [45] = None
- [46] = None
- [47] = None
- [48] = None
- [49] = None
- [50] = None
- [51] = None
- [52] = None
- [53] = None
- [54] = None
- [55] = None
- [56] = None
- [57] = None
- [58] = None
- [59] = None
- [60] = None
- [61] = None
- [62] = None
- [63] = None
- Move Byte Mapping:
-
-Final Gateway Key is:
- [0] = None
- [1] = None
- [2] = None
- [3] = None
- [4] = None
- [5] = None
- [6] = None
- [7] = None
- [8] = None
- [9] = None
- [10] = None
- [11] = None
- [12] = None
- [13] = None
- [14] = None
- [15] = None
- [16] = None
- [17] = None
- [18] = None
- [19] = None
- [20] = None
- [21] = None
- [22] = None
- [23] = None
- [24] = None
- [25] = None
- [26] = None
- [27] = None
- [28] = None
- [29] = None
- [30] = None
- [31] = None
- [32] = None
- [33] = (('--validity_check--packet_out_hdr', 0), 'exact')
- [34] = None
- [35] = None
- [36] = None
- [37] = None
- [38] = None
- [39] = None
- [40] = None
- [41] = None
- [42] = None
- [43] = None
- Hash Bit Mapping:
- (1, 1) --> 41
-
-Allocating: Gateway 14 in stage 0 for _condition_0.
-
-========================================================
- Run Gateway Placement on Request List of size 2
-========================================================
-
-Available Gateways are: (16)
-Gateway 0
-Gateway 1
-Gateway 2
-Gateway 3
-Gateway 4
-Gateway 5
-Gateway 6
-Gateway 7
-Gateway 8
-Gateway 9
-Gateway 10
-Gateway 11
-Gateway 12
-Gateway 13
-Gateway 14
-Gateway 15
-------- Phase 0 -------------
-Looking at gateway table 15
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 7
-Search bus 1 on row 7
-Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 7
-Search bus 1 on row 7
-Looking at gateway table 13
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 6
-Search bus 1 on row 6
-Looking at gateway table 12
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 6
-Search bus 1 on row 6
-Looking at gateway table 11
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 5
-Search bus 1 on row 5
-Looking at gateway table 10
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 5
-Search bus 1 on row 5
-Looking at gateway table 9
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 4
-Search bus 1 on row 4
-Looking at gateway table 8
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 4
-Search bus 1 on row 4
-Looking at gateway table 7
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 3
-Search bus 1 on row 3
-Looking at gateway table 6
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 3
-Search bus 1 on row 3
-Looking at gateway table 5
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 2
-Search bus 1 on row 2
-Looking at gateway table 4
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 2
-Search bus 1 on row 2
-Looking at gateway table 3
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 1
-Search bus 1 on row 1
-Looking at gateway table 2
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 1
-Search bus 1 on row 1
-Looking at gateway table 1
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 0
-Search bus 1 on row 0
-Looking at gateway table 0
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 0
-Search bus 1 on row 0
-------- Phase 1 -------------
-Looking at gateway table 15
-match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
-Search bus 0 on row 7
-
- final_parity_group_ids = [(0, []), (1, [])]
-
- open_parity_group_ids = [0, 1]
-----------------------------
- Trying to place Gateway Resource Request for table _condition_3 needs access to 1 input bits in exact match group 0 (parity groups [0, 1]) and hash group 0 for gateway 15.
-----------------------------
---------------
-Call to _place_fields_for_constant_comparison
-constant_match_key_partition is:
-Byte Position 0
- (80, 0)
-Byte Position 1
- (80, 0)
-Byte Position 2
- (80, 0)
-Byte Position 3
- (80, 0)
-
-Available bytes in ram word is [0, 1, 2, 3, 4, 5, 6, 7]
-Available data bytes for constants are [0, 1, 2, 3]
-Put all gateway constant field bits into the hash bits.
-Allocating: Hash Bit 40 in hash match group 0 for ('ig_intr_md_for_tm.copy_to_cpu', 0).
-Gateway data search bus packing is:
- [0] = None
- [1] = None
- [2] = None
- [3] = None
- [4] = None
- [5] = None
- [6] = None
- [7] = None
- [8] = None
- [9] = None
- [10] = None
- [11] = None
- [12] = None
- [13] = None
- [14] = None
- [15] = None
- [16] = None
- [17] = None
- [18] = None
- [19] = None
- [20] = None
- [21] = None
- [22] = None
- [23] = None
- [24] = None
- [25] = None
- [26] = None
- [27] = None
- [28] = None
- [29] = None
- [30] = None
- [31] = None
- [32] = None
- [33] = None
- [34] = None
- [35] = None
- [36] = None
- [37] = None
- [38] = None
- [39] = None
- [40] = None
- [41] = None
- [42] = None
- [43] = None
- [44] = None
- [45] = None
- [46] = None
- [47] = None
- [48] = None
- [49] = None
- [50] = None
- [51] = None
- [52] = None
- [53] = None
- [54] = None
- [55] = None
- [56] = None
- [57] = None
- [58] = None
- [59] = None
- [60] = None
- [61] = None
- [62] = None
- [63] = None
- Move Byte Mapping:
-
-Final Gateway Key is:
- [0] = None
- [1] = None
- [2] = None
- [3] = None
- [4] = None
- [5] = None
- [6] = None
- [7] = None
- [8] = None
- [9] = None
- [10] = None
- [11] = None
- [12] = None
- [13] = None
- [14] = None
- [15] = None
- [16] = None
- [17] = None
- [18] = None
- [19] = None
- [20] = None
- [21] = None
- [22] = None
- [23] = None
- [24] = None
- [25] = None
- [26] = None
- [27] = None
- [28] = None
- [29] = None
- [30] = None
- [31] = None
- [32] = (('ig_intr_md_for_tm.copy_to_cpu', 0), 'exact')
- [33] = None
- [34] = None
- [35] = None
- [36] = None
- [37] = None
- [38] = None
- [39] = None
- [40] = None
- [41] = None
- [42] = None
- [43] = None
- Hash Bit Mapping:
- (0, 0) --> 40
-
-Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 0 for gateway
-Allocating: Gateway 15 in stage 0 for _condition_3.
-Available Gateways are: (15)
-Gateway 0
-Gateway 1
-Gateway 2
-Gateway 3
-Gateway 4
-Gateway 5
-Gateway 6
-Gateway 7
-Gateway 8
-Gateway 9
-Gateway 10
-Gateway 11
-Gateway 12
-Gateway 13
-Gateway 14
-------- Phase 0 -------------
-Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f84d1f439d0>, 0)])), (1, (None, [], None, [], []))])
-Search bus 0 on row 7
-----------------------------
- Trying to place Gateway Resource Request for table _condition_0 needs access to 1 input bits in exact match group 0 (parity groups [0]) and hash group 0 for gateway 14.
-----------------------------
---------------
-Call to _place_fields_for_constant_comparison
-constant_match_key_partition is:
-Byte Position 0
- (68, 0)
-Byte Position 1
- (68, 0)
-Byte Position 2
- (68, 0)
-Byte Position 3
- (68, 0)
-
-Removing available byte Byte 8 is of type exact and member of group 0 (parity group 1) with 16 bytes. because not in available parity group(s) [0]
-Removing available byte Byte 10 is of type exact and member of group 0 (parity group 1) with 16 bytes. because not in available parity group(s) [0]
-Removing available byte Byte 12 is of type exact and member of group 0 (parity group 1) with 16 bytes. because not in available parity group(s) [0]
-Removing available byte Byte 14 is of type exact and member of group 0 (parity group 1) with 16 bytes. because not in available parity group(s) [0]
-Available bytes in ram word is [0, 1, 2, 3, 4, 5, 6, 7]
-Available data bytes for constants are [0, 1, 2, 3]
-Put all gateway constant field bits into the hash bits.
-Allocating: Hash Bit 41 in hash match group 0 for ('--validity_check--packet_out_hdr', 0).
-Gateway data search bus packing is:
- [0] = None
- [1] = None
- [2] = None
- [3] = None
- [4] = None
- [5] = None
- [6] = None
- [7] = None
- [8] = None
- [9] = None
- [10] = None
- [11] = None
- [12] = None
- [13] = None
- [14] = None
- [15] = None
- [16] = None
- [17] = None
- [18] = None
- [19] = None
- [20] = None
- [21] = None
- [22] = None
- [23] = None
- [24] = None
- [25] = None
- [26] = None
- [27] = None
- [28] = None
- [29] = None
- [30] = None
- [31] = None
- [32] = None
- [33] = None
- [34] = None
- [35] = None
- [36] = None
- [37] = None
- [38] = None
- [39] = None
- [40] = None
- [41] = None
- [42] = None
- [43] = None
- [44] = None
- [45] = None
- [46] = None
- [47] = None
- [48] = None
- [49] = None
- [50] = None
- [51] = None
- [52] = None
- [53] = None
- [54] = None
- [55] = None
- [56] = None
- [57] = None
- [58] = None
- [59] = None
- [60] = None
- [61] = None
- [62] = None
- [63] = None
- Move Byte Mapping:
-
-Final Gateway Key is:
- [0] = None
- [1] = None
- [2] = None
- [3] = None
- [4] = None
- [5] = None
- [6] = None
- [7] = None
- [8] = None
- [9] = None
- [10] = None
- [11] = None
- [12] = None
- [13] = None
- [14] = None
- [15] = None
- [16] = None
- [17] = None
- [18] = None
- [19] = None
- [20] = None
- [21] = None
- [22] = None
- [23] = None
- [24] = None
- [25] = None
- [26] = None
- [27] = None
- [28] = None
- [29] = None
- [30] = None
- [31] = None
- [32] = None
- [33] = (('--validity_check--packet_out_hdr', 0), 'exact')
- [34] = None
- [35] = None
- [36] = None
- [37] = None
- [38] = None
- [39] = None
- [40] = None
- [41] = None
- [42] = None
- [43] = None
- Hash Bit Mapping:
- (1, 1) --> 41
-
-Allocating: Gateway 14 in stage 0 for _condition_0.
+Allocating: Gateway 14 in stage 2 for egress_port_count_table_always_true_condition.
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gw.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gw.log
index 0affae5..177ac51 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gw.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gw.log
@@ -1,124 +1,79 @@
+---------------------------------------------------------------------+
| Log file: mau.gw.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
-cond _condition_0: valid packet_out_hdr
- valid packet_out_hdr
- ! not valid packet_out_hdr
-cond _condition_0 can be gateway (1+0)x1
-cond !_condition_0 can be gateway (1+0)x1
-_condition_0 is gateway for ingress_pkt
-cond _condition_1: not valid packet_out_hdr
+cond _condition_0: not valid packet_out_hdr
not valid packet_out_hdr
! not not valid packet_out_hdr
-cond _condition_1 can be gateway (1+0)x1
-cond !_condition_1 can be gateway (1+0)x1
-_condition_1 is gateway for table0
-cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 254
- ig_intr_md_for_tm.ucast_egress_port < 254
- ! ig_intr_md_for_tm.ucast_egress_port >= 254
+cond _condition_0 can be gateway (1+0)x1
+cond !_condition_0 can be gateway (1+0)x1
+_condition_0 is gateway for table0
+cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 510
+ ig_intr_md_for_tm.ucast_egress_port < 510
+ ! ig_intr_md_for_tm.ucast_egress_port >= 510
cond _condition_2 can be gateway (9+0)x1
cond !_condition_2 can be gateway (9+0)x1
_condition_2 is gateway for ingress_port_count_table
-cond _condition_3: ig_intr_md_for_tm.copy_to_cpu == 1
- ig_intr_md_for_tm.copy_to_cpu == 1
- ! ig_intr_md_for_tm.copy_to_cpu != 1
-cond _condition_3 can be gateway (0+1)x1
-cond !_condition_3 can be gateway (0+1)x2
-_condition_3 is gateway for egress_pkt
-fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f84d6b710d0>]) and and xor_fields is OrderedSet()
+fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f4993049bd0>]) and and xor_fields is OrderedSet()
fields = OrderedSet() and and xor_fields is OrderedSet()
-fields = OrderedSet() and and xor_fields is OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f84d6b71390>])
-fields = OrderedSet() and and xor_fields is OrderedSet()
-cond _condition_0: valid packet_out_hdr
- valid packet_out_hdr
- ! not valid packet_out_hdr
-cond _condition_0 can be gateway (1+0)x1
-cond !_condition_0 can be gateway (1+0)x1
-_condition_0 is gateway for ingress_pkt
-cond _condition_1: not valid packet_out_hdr
+cond _condition_0: not valid packet_out_hdr
not valid packet_out_hdr
! not not valid packet_out_hdr
-cond _condition_1 can be gateway (1+0)x1
-cond !_condition_1 can be gateway (1+0)x1
-_condition_1 is gateway for table0
-cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 254
- ig_intr_md_for_tm.ucast_egress_port < 254
- ! ig_intr_md_for_tm.ucast_egress_port >= 254
+cond _condition_0 can be gateway (1+0)x1
+cond !_condition_0 can be gateway (1+0)x1
+_condition_0 is gateway for table0
+cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 510
+ ig_intr_md_for_tm.ucast_egress_port < 510
+ ! ig_intr_md_for_tm.ucast_egress_port >= 510
cond _condition_2 can be gateway (9+0)x1
cond !_condition_2 can be gateway (9+0)x1
_condition_2 is gateway for ingress_port_count_table
-cond _condition_3: ig_intr_md_for_tm.copy_to_cpu == 1
- ig_intr_md_for_tm.copy_to_cpu == 1
- ! ig_intr_md_for_tm.copy_to_cpu != 1
-cond _condition_3 can be gateway (0+1)x1
-cond !_condition_3 can be gateway (0+1)x2
-_condition_3 is gateway for egress_pkt
-fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f84d6b710d0>]) and and xor_fields is OrderedSet()
+fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f4993049bd0>]) and and xor_fields is OrderedSet()
fields = OrderedSet() and and xor_fields is OrderedSet()
-fields = OrderedSet() and and xor_fields is OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f84d6b71390>])
-fields = OrderedSet() and and xor_fields is OrderedSet()
-cond _condition_0: valid packet_out_hdr
- valid packet_out_hdr
- ! not valid packet_out_hdr
-cond _condition_0 can be gateway (1+0)x1
-cond !_condition_0 can be gateway (1+0)x1
-_condition_0 is gateway for ingress_pkt
-cond _condition_1: not valid packet_out_hdr
+cond _condition_0: not valid packet_out_hdr
not valid packet_out_hdr
! not not valid packet_out_hdr
-cond _condition_1 can be gateway (1+0)x1
-cond !_condition_1 can be gateway (1+0)x1
-_condition_1 is gateway for table0
-cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 254
- ig_intr_md_for_tm.ucast_egress_port < 254
- ! ig_intr_md_for_tm.ucast_egress_port >= 254
+cond _condition_0 can be gateway (1+0)x1
+cond !_condition_0 can be gateway (1+0)x1
+_condition_0 is gateway for table0
+cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 510
+ ig_intr_md_for_tm.ucast_egress_port < 510
+ ! ig_intr_md_for_tm.ucast_egress_port >= 510
cond _condition_2 can be gateway (9+0)x1
cond !_condition_2 can be gateway (9+0)x1
_condition_2 is gateway for ingress_port_count_table
-cond _condition_3: ig_intr_md_for_tm.copy_to_cpu == 1
- ig_intr_md_for_tm.copy_to_cpu == 1
- ! ig_intr_md_for_tm.copy_to_cpu != 1
-cond _condition_3 can be gateway (0+1)x1
-cond !_condition_3 can be gateway (0+1)x2
-_condition_3 is gateway for egress_pkt
-fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f84d6b710d0>]) and and xor_fields is OrderedSet()
-fields = OrderedSet() and and xor_fields is OrderedSet()
-fields = OrderedSet() and and xor_fields is OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f84d6b71390>])
+fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f4993049bd0>]) and and xor_fields is OrderedSet()
fields = OrderedSet() and and xor_fields is OrderedSet()
cond _always_true: True == True
True
! False
+cond _always_true: True == True
+ True
+ ! False
--> Stage Gateway Table for condition _condition_0 in stage 0
-T -> ingress_pkt(0), F -> _condition_1(16)
-building tcam for GatewayTest('valid packet_out_hdr')
- adding line (match=200000000 mask=200000000 T)
-tcam data: [(match=200000000 mask=200000000 T)]
-final.tcam: [(match=200000000 mask=200000000 T)], miss=False
---> Stage Gateway Table for condition _condition_3 in stage 0
-T -> egress_pkt(1), F -> None(255)
-building tcam for GatewayTest('ig_intr_md_for_tm.copy_to_cpu == 1')
- adding line (match=100000000 mask=100000000 T)
-tcam data: [(match=100000000 mask=100000000 T)]
-final.tcam: [(match=100000000 mask=100000000 T)], miss=False
---> Stage Gateway Table for condition _condition_1 in stage 1
-T -> table0(16), F -> _condition_2(48)
+T -> table0(0), F -> process_packet_out_table(1)
building tcam for GatewayTest('not valid packet_out_hdr')
adding line (match=0 mask=100000000 T)
tcam data: [(match=0 mask=100000000 T)]
final.tcam: [(match=0 mask=100000000 T)], miss=False
---> Stage Gateway Table for condition _condition_2 in stage 3
-T -> ingress_port_count_table(48), F -> None(255)
-building tcam for GatewayTest('ig_intr_md_for_tm.ucast_egress_port < 254')
+--> Stage Gateway Table for condition process_packet_out_table_always_true_condition in stage 0
+T -> process_packet_out_table(1), F -> process_packet_out_table(1)
+building tcam for GatewayTest('True')
+ adding line (match=0 mask=0 T)
+tcam data: [(match=0 mask=0 T)]
+final.tcam: [(match=0 mask=0 T)], miss=False
+--> Stage Gateway Table for condition _condition_2 in stage 2
+T -> ingress_port_count_table(32), F -> None(255)
+building tcam for GatewayTest('ig_intr_md_for_tm.ucast_egress_port < 510')
adding line (range=[ffff ffff 3fff] match=0 mask=0 T)
adding line (range=[ffff 7fff ffff] match=0 mask=0 T)
- adding line (range=[0 ffff ffff] match=0 mask=0 T)
-tcam data: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[0 ffff ffff] match=0 mask=0 T)]
-final.tcam: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[0 ffff ffff] match=0 mask=0 T)], miss=False
---> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 3
-T -> egress_port_count_table(49), F -> egress_port_count_table(49)
+ adding line (range=[1 ffff ffff] match=0 mask=0 T)
+tcam data: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[1 ffff ffff] match=0 mask=0 T)]
+final.tcam: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[1 ffff ffff] match=0 mask=0 T)], miss=False
+--> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 2
+T -> egress_port_count_table(33), F -> egress_port_count_table(33)
building tcam for GatewayTest('True')
adding line (match=0 mask=0 T)
tcam data: [(match=0 mask=0 T)]
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.log
index 2ac02f6..a265f41 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.log
@@ -1,27 +1,27 @@
+---------------------------------------------------------------------+
| Log file: mau.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
Match Table table0 did not specify the number of entries required. A default value (512) will be used.
Match Table ecmp_group_table did not specify the number of entries required. A default value (1024) will be used.
Match Entry Table table0 has already been associated with stat Table table0_counter.
Match Entry Table ecmp_group_table has already been associated with stat Table ecmp_group_table_counter.
-Cannot implement ingress_pkt in phase 0 resources because table does not have the correct condition
+Cannot implement table0 in phase 0 resources because table uses side effect tables.
Match Table table0 did not specify the number of entries required. A default value (512) will be used.
Match Table ecmp_group_table did not specify the number of entries required. A default value (1024) will be used.
Match Entry Table table0 has already been associated with stat Table table0_counter.
Match Entry Table ecmp_group_table has already been associated with stat Table ecmp_group_table_counter.
-Cannot implement ingress_pkt in phase 0 resources because table does not have the correct condition
+Cannot implement table0 in phase 0 resources because table uses side effect tables.
Match Table table0 did not specify the number of entries required. A default value (512) will be used.
Match Table ecmp_group_table did not specify the number of entries required. A default value (1024) will be used.
-POV/metadata bridge containers added between ingress/egress: [0, 64, 128]
+POV/metadata bridge containers added between ingress/egress: [0]
Metadata bridge_ingress_intrinsic containers added between ingress/egress: [128]
Match Entry Table table0 has already been associated with stat Table table0_counter.
Match Entry Table ecmp_group_table has already been associated with stat Table ecmp_group_table_counter.
Match table ingress_port_count_table has no match key fields
-Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 254.
+Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 510.
##########################################
Call to decide_action_data_placement(stage=0, table=ingress_port_count_table)
@@ -83,7 +83,7 @@
Best Ram Usage is 97 rams
Best Immediate placement is 0 bits
Match table egress_port_count_table has no match key fields
-Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 254.
+Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 510.
##########################################
Call to decide_action_data_placement(stage=0, table=egress_port_count_table)
@@ -146,16 +146,16 @@
Best Immediate placement is 0 bits
##########################################
- Call to decide_action_data_placement(stage=0, table=ingress_pkt)
+ Call to decide_action_data_placement(stage=0, table=process_packet_out_table)
##########################################
Max immediate bits used in any action is 0 bits.
-Overhead bit width for table ingress_pkt is 2 bits.
+Overhead bit width for table process_packet_out_table is 0 bits.
Bits available in overhead for non-essential immediate data is 32 bits.
~~~~~~~~~~~~~~~~~~~~~
Examining placing 0 bits in match overhead
-Overhead bit width for table ingress_pkt is 2 bits.
+Overhead bit width for table process_packet_out_table is 0 bits.
Overhead SRAMs to use = 97
Entries requested = 1024 and match entries get = 0
ram_size_matrix =
@@ -172,73 +172,13 @@
total action ram packing size = [0, 0, 0]
action_ram_packing:
- action _packet_out has []
+ action _process_packet_out has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
- action _packet_out has []
+ action _process_packet_out has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
- action _packet_out has []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-Action Data SRAMs to use = 0
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 8 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 16 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 24 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 32 bits in match overhead
-
-##########################################
-
-Best Ram Usage is 97 rams
-Best Immediate placement is 0 bits
-
-##########################################
- Call to decide_action_data_placement(stage=0, table=egress_pkt)
-##########################################
-
-
-Max immediate bits used in any action is 0 bits.
-Overhead bit width for table egress_pkt is 2 bits.
-Bits available in overhead for non-essential immediate data is 32 bits.
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 0 bits in match overhead
-Overhead bit width for table egress_pkt is 2 bits.
-Overhead SRAMs to use = 97
- Entries requested = 1024 and match entries get = 0
-ram_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-immediate_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-hash_to_phv_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action add_packet_in_hdr has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action add_packet_in_hdr has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action add_packet_in_hdr has []
+ action _process_packet_out has []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
@@ -501,100 +441,18 @@
Best Ram Usage is 3 rams
Best Immediate placement is 16 bits
-Cannot implement ingress_pkt in phase 0 resources because table does not have the correct condition
-
-----------------------------------------------
-Call to Allocate P4 Table with table ingress_pkt__action__, number_entries = 1024, table id = None, and match type = exact
- Allocating in stage 0
-----------------------------------------------
-
-ram_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-immediate_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-hash_to_phv_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action _packet_out has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action _packet_out has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action _packet_out has []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-Allocating Action Logical Table ID 0 in stage 0
-
-----------------------------------------------
-Call to Allocate P4 Table with table ingress_pkt, number_entries = 1024, table id = None, and match type = exact
- Allocating in stage 0
-----------------------------------------------
-
-Logical Table ID in stage 0 was not supplied by table placement for table ingress_pkt.
-Allocating Logical Table ID 0 in stage 0
-Allocating Table Type ID 0 of type exact in stage 0
-Match Overhead:
- Field --version_valid-- [3:0] (4 bits)
- Field --instruction_address-- [1:0] (2 bits)
-
-Logical Table ID in stage 0 was not supplied by table placement for table ingress_pkt.
-Allocating Logical Table ID 0 in stage 0
-Allocating Table Type ID 0 of type exact in stage 0
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
-Match Table Resource Request is:
-SRAM Resource Request for table ingress_pkt (of type match), with 0 ways wants 0 rams.
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
-For action _packet_out, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 130 has bit width 23
- Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
- Field Src1 [4:0] : 0x1 (5 bits in instruction bits [8:4])
- Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
- Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
- Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
- Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
- Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16])
- Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
-
-For action _packet_out, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 68 has bit width 20
- Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
- Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4])
- Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
- Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
- Field high_bit [2:0] : 0x1 (3 bits in instruction bits [13:11])
- Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14])
- Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16])
- Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
-
-Allocating Action ALU 2 (16 bits) in stage 0 for match table ingress_pkt's action _packet_out
-Allocating Action ALU 4 (8 bits) in stage 0 for match table ingress_pkt's action _packet_out
-Allocating VLIW Instruction : 0 in stage 0 for match table ingress_pkt's action _packet_out
+Cannot implement table0 in phase 0 resources because table uses side effect tables.
----------------------------------------------
Call to Allocate P4 Table with table table0__action__, number_entries = 512, table id = None, and match type = exact
- Allocating in stage 1
+ Allocating in stage 0
----------------------------------------------
ram_size_matrix =
(8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
0 0 0 1 0 0 0 0 # 0
0 0 0 1 0 0 0 0 # 1
- 0 0 0 0 0 0 0 0 # 2
+ 0 0 0 1 0 0 0 0 # 2
0 0 0 0 0 0 0 0 # 3
immediate_size_matrix =
@@ -615,7 +473,7 @@
action_ram_packing:
action set_egress_port has [(16, 16, False)]
action ecmp_group has [(16, 16, False)]
- action send_to_cpu has []
+ action send_to_cpu has [(16, 16, False)]
action _drop has []
total action ram packing size = [16, 0, 0]
action_ram_packing:
@@ -630,14 +488,14 @@
action send_to_cpu has [(16, 0, False)]
action _drop has [(16, 0, False)]
byte_enables = [1, 1]
-Allocating Action Parameter Bus Byte 32 in stage 1 for Byte 0 of 16-bit constant
-Allocating Action Parameter Bus Byte 33 in stage 1 for Byte 1 of 16-bit constant
-Allocating Action Parameter Bus Byte 34 in stage 1 for Byte 0 of 16-bit constant
-Allocating Action Parameter Bus Byte 35 in stage 1 for Byte 1 of 16-bit constant
+Allocating Action Parameter Bus Byte 32 in stage 0 for Byte 0 of 16-bit constant
+Allocating Action Parameter Bus Byte 33 in stage 0 for Byte 1 of 16-bit constant
+Allocating Action Parameter Bus Byte 34 in stage 0 for Byte 0 of 16-bit constant
+Allocating Action Parameter Bus Byte 35 in stage 0 for Byte 1 of 16-bit constant
After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)]
final packing is [(16, 16, False)]
final packing is [(16, 16, False)]
-final packing is []
+final packing is [(16, 16, False)]
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
@@ -646,10 +504,10 @@
final packing is []
final packing is []
byte_enables = [1, 1]
-Allocating Action Parameter Bus Byte 36 in stage 1 for Byte 0 of 16-bit constant
-Allocating Action Parameter Bus Byte 37 in stage 1 for Byte 1 of 16-bit constant
-Allocating Action Parameter Bus Byte 38 in stage 1 for Byte 0 of 16-bit constant
-Allocating Action Parameter Bus Byte 39 in stage 1 for Byte 1 of 16-bit constant
+Allocating Action Parameter Bus Byte 36 in stage 0 for Byte 0 of 16-bit constant
+Allocating Action Parameter Bus Byte 37 in stage 0 for Byte 1 of 16-bit constant
+Allocating Action Parameter Bus Byte 38 in stage 0 for Byte 0 of 16-bit constant
+Allocating Action Parameter Bus Byte 39 in stage 0 for Byte 1 of 16-bit constant
After allocation of 32s, available_slots is [(16, 2, 0), (32, 9, 0), (16, 3, 16)]
final packing is [(16, 0, False)]
final packing is [(16, 16, False)]
@@ -688,8 +546,8 @@
hash_bits_in_units = OrderedDict([(0, [0])])
address_left_shift = 0
-------------------
-Allocating Hash Distribution Group 0/0 for table table0__action__ in stage 1.
-Allocating Hash Bit 0 in hash match group 0 for table table0__action__ in stage 1.
+Allocating Hash Distribution Group 0/0 for table table0__action__ in stage 0.
+Allocating Hash Bit 0 in hash match group 0 for table table0__action__ in stage 0.
seed = 0x7bd5c66f
set the seed to be [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
Hash Function 0
@@ -746,17 +604,17 @@
hash_bit_50 = 0
hash_bit_51 = 0
-Allocating Action Logical Table ID 0 in stage 1
+Allocating Action Logical Table ID 0 in stage 0
----------------------------------------------
Call to Allocate P4 Table with table table0_counter, number_entries = 512, table id = None, and match type = exact
- Allocating in stage 1
+ Allocating in stage 0
----------------------------------------------
stat_stage_table referenced: direct
stat Table Resource Request is:
SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams.
-Sram Resource Request for P4 table table0_counter with handle 67108867 of type statistics in stage 1
+Sram Resource Request for P4 table table0_counter with handle 67108867 of type statistics in stage 0
table_type : statistics
rams_for_width : 1
use_stash : False
@@ -772,12 +630,12 @@
----------------------------------------------
Call to Allocate P4 Table with table table0, number_entries = 512, table id = None, and match type = ternary
- Allocating in stage 1
+ Allocating in stage 0
----------------------------------------------
-Logical Table ID in stage 1 was not supplied by table placement for table table0.
-Allocating Logical Table ID 0 in stage 1
-Allocating Table Type ID 0 of type ternary in stage 1
+Logical Table ID in stage 0 was not supplied by table placement for table table0.
+Allocating Logical Table ID 0 in stage 0
+Allocating Table Type ID 0 of type ternary in stage 0
-----------------------------------------
Call to allocate_ternary_match_key_2
@@ -806,9 +664,9 @@
{--unused--[3:0], ethernet.dstAddr[47:40], ethernet.srcAddr[39:32], ethernet.dstAddr[7:0], ig_intr_md.ingress_port[7:0], ethernet.etherType[15:8], --version--[1:0], --unused--[1:0], ethernet.srcAddr[47:40], ethernet.dstAddr[23:16], ethernet.etherType[7:0], ethernet.dstAddr[39:24], --unused--[2:0], ig_intr_md.ingress_port[8:8], ethernet.dstAddr[15:8], ethernet.srcAddr[31:0]}
---------------------------------------------
-Call to can_any_match_key_fields_be_shared(stage=1, table=table0)
+Call to can_any_match_key_fields_be_shared(stage=0, table=table0)
---------------------------------------------
-Decided way to allocate for table table0 in stage 1 WAS non_shared
+Decided way to allocate for table table0 in stage 0 WAS non_shared
-----------------------------------------
Call to allocate_ternary_match_key_2
@@ -849,8 +707,8 @@
Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
-Allocating Action ALU 2 (16 bits) in stage 1 for match table table0's action set_egress_port
-Allocating VLIW Instruction : 0 in stage 1 for match table table0's action set_egress_port
+Allocating Action ALU 2 (16 bits) in stage 0 for match table table0's action set_egress_port
+Allocating VLIW Instruction : 0 in stage 0 for match table table0's action set_egress_port
For action ecmp_group, formed micro_instruction:
Micro Instruction alu_a for PHV Container 134 has bit width 23
Field Src2 [3:0] : 0x6 (4 bits in instruction bits [3:0])
@@ -867,12 +725,23 @@
Field opcode [9:0] : 0x31e (10 bits in instruction bits [19:10])
Field unused [2:0] : 0x0 (3 bits in instruction bits [22:20])
-Allocating Action ALU 6 (16 bits) in stage 1 for match table table0's action ecmp_group
-Allocating Action ALU 7 (16 bits) in stage 1 for match table table0's action ecmp_group
-Allocating VLIW Instruction : 1 in stage 1 for match table table0's action ecmp_group
+Allocating Action ALU 6 (16 bits) in stage 0 for match table table0's action ecmp_group
+Allocating Action ALU 7 (16 bits) in stage 0 for match table table0's action ecmp_group
+Allocating VLIW Instruction : 1 in stage 0 for match table table0's action ecmp_group
For action send_to_cpu, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 64 has bit width 20
- Field Src2 [3:0] : 0x0 (4 bits in instruction bits [3:0])
+Micro Instruction deposit-field for PHV Container 130 has bit width 23
+ Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
+ Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
+ Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9])
+ Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
+ Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
+ Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
+ Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
+ Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
+
+For action send_to_cpu, formed micro_instruction:
+Micro Instruction deposit-field for PHV Container 67 has bit width 20
+ Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -881,11 +750,24 @@
Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16])
Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
-Allocating Action ALU 0 (8 bits) in stage 1 for match table table0's action send_to_cpu
-Allocating VLIW Instruction : 1 in stage 1 for match table table0's action send_to_cpu
+For action send_to_cpu, formed micro_instruction:
+Micro Instruction deposit-field for PHV Container 129 has bit width 23
+ Field Src2 [3:0] : 0x1 (4 bits in instruction bits [3:0])
+ Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
+ Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
+ Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
+ Field high_bit [3:0] : 0xf (4 bits in instruction bits [14:11])
+ Field low_bit_lo [0:0] : 0x1 (1 bits in instruction bits [15:15])
+ Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16])
+ Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20])
+
+Allocating Action ALU 2 (16 bits) in stage 0 for match table table0's action send_to_cpu
+Allocating Action ALU 3 (8 bits) in stage 0 for match table table0's action send_to_cpu
+Allocating Action ALU 1 (16 bits) in stage 0 for match table table0's action send_to_cpu
+Allocating VLIW Instruction : 1 in stage 0 for match table table0's action send_to_cpu
For action _drop, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 69 has bit width 20
- Field Src2 [3:0] : 0x5 (4 bits in instruction bits [3:0])
+Micro Instruction deposit-field for PHV Container 68 has bit width 20
+ Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0])
Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
@@ -894,8 +776,8 @@
Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16])
Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19])
-Allocating Action ALU 5 (8 bits) in stage 1 for match table table0's action _drop
-Allocating VLIW Instruction : 2 in stage 1 for match table table0's action _drop
+Allocating Action ALU 4 (8 bits) in stage 0 for match table table0's action _drop
+Allocating VLIW Instruction : 2 in stage 0 for match table table0's action _drop
Ternary table Pack Format =
Pack Format:
table_word_width: 141
@@ -932,8 +814,89 @@
----------------------------------------------
+Call to Allocate P4 Table with table process_packet_out_table__action__, number_entries = 1024, table id = None, and match type = exact
+ Allocating in stage 0
+----------------------------------------------
+
+ram_size_matrix =
+ (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
+ 0 0 0 0 0 0 0 0 # 0
+
+immediate_size_matrix =
+ (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
+ 0 0 0 0 0 0 0 0 # 0
+
+hash_to_phv_matrix =
+ (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
+ 0 0 0 0 0 0 0 0 # 0
+
+total action ram packing size = [0, 0, 0]
+action_ram_packing:
+ action _process_packet_out has []
+total action ram packing size = [0, 0, 0]
+action_ram_packing:
+ action _process_packet_out has []
+total action ram packing size = [0, 0, 0]
+action_ram_packing:
+ action _process_packet_out has []
+byte_enables = []
+After allocation of 32s, available_slots is []
+final packing is []
+byte_enables = []
+After allocation of 32s, available_slots is []
+final packing is []
+byte_enables = []
+After allocation of 32s, available_slots is []
+final packing is []
+Allocating Action Logical Table ID 1 in stage 0
+
+----------------------------------------------
+Call to Allocate P4 Table with table process_packet_out_table, number_entries = 1024, table id = None, and match type = exact
+ Allocating in stage 0
+----------------------------------------------
+
+Logical Table ID in stage 0 was not supplied by table placement for table process_packet_out_table.
+Allocating Logical Table ID 1 in stage 0
+Allocating Table Type ID 0 of type exact in stage 0
+Match Overhead:
+ Field --version_valid-- [3:0] (4 bits)
+
+Logical Table ID in stage 0 was not supplied by table placement for table process_packet_out_table.
+Allocating Logical Table ID 1 in stage 0
+Allocating Table Type ID 0 of type exact in stage 0
+Allocating: Byte 12 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
+Match Table Resource Request is:
+SRAM Resource Request for table process_packet_out_table (of type match), with 0 ways wants 0 rams.
+Allocating: Byte 12 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
+For action _process_packet_out, formed micro_instruction:
+Micro Instruction deposit-field for PHV Container 130 has bit width 23
+ Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
+ Field Src1 [4:0] : 0x1 (5 bits in instruction bits [8:4])
+ Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
+ Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
+ Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11])
+ Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15])
+ Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16])
+ Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
+
+For action _process_packet_out, formed micro_instruction:
+Micro Instruction deposit-field for PHV Container 67 has bit width 20
+ Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0])
+ Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4])
+ Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
+ Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
+ Field high_bit [2:0] : 0x1 (3 bits in instruction bits [13:11])
+ Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14])
+ Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16])
+ Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
+
+Allocating Action ALU 2 (16 bits) in stage 0 for match table process_packet_out_table's action _process_packet_out
+Allocating Action ALU 3 (8 bits) in stage 0 for match table process_packet_out_table's action _process_packet_out
+Allocating VLIW Instruction : 2 in stage 0 for match table process_packet_out_table's action _process_packet_out
+
+----------------------------------------------
Call to Allocate P4 Table with table ecmp_group_table__action__, number_entries = 1024, table id = None, and match type = exact
- Allocating in stage 2
+ Allocating in stage 1
----------------------------------------------
ram_size_matrix =
@@ -961,26 +924,26 @@
After allocation of 32s, available_slots is []
final packing is []
byte_enables = [1, 1]
-Allocating Action Parameter Bus Byte 32 in stage 2 for Byte 0 of 16-bit constant
-Allocating Action Parameter Bus Byte 33 in stage 2 for Byte 1 of 16-bit constant
-Allocating Action Parameter Bus Byte 34 in stage 2 for Byte 0 of 16-bit constant
-Allocating Action Parameter Bus Byte 35 in stage 2 for Byte 1 of 16-bit constant
+Allocating Action Parameter Bus Byte 32 in stage 1 for Byte 0 of 16-bit constant
+Allocating Action Parameter Bus Byte 33 in stage 1 for Byte 1 of 16-bit constant
+Allocating Action Parameter Bus Byte 34 in stage 1 for Byte 0 of 16-bit constant
+Allocating Action Parameter Bus Byte 35 in stage 1 for Byte 1 of 16-bit constant
After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)]
final packing is [(16, 16, False)]
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
-Allocating Action Logical Table ID 0 in stage 2
+Allocating Action Logical Table ID 0 in stage 1
----------------------------------------------
Call to Allocate P4 Table with table ecmp_group_table_counter, number_entries = 1024, table id = None, and match type = exact
- Allocating in stage 2
+ Allocating in stage 1
----------------------------------------------
stat_stage_table referenced: direct
stat Table Resource Request is:
SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams.
-Sram Resource Request for P4 table ecmp_group_table_counter with handle 67108868 of type statistics in stage 2
+Sram Resource Request for P4 table ecmp_group_table_counter with handle 67108868 of type statistics in stage 1
table_type : statistics
rams_for_width : 1
use_stash : False
@@ -996,12 +959,12 @@
----------------------------------------------
Call to Allocate P4 Table with table ecmp_group_table, number_entries = 1024, table id = None, and match type = exact
- Allocating in stage 2
+ Allocating in stage 1
----------------------------------------------
-Logical Table ID in stage 2 was not supplied by table placement for table ecmp_group_table.
-Allocating Logical Table ID 0 in stage 2
-Allocating Table Type ID 0 of type exact in stage 2
+Logical Table ID in stage 1 was not supplied by table placement for table ecmp_group_table.
+Allocating Logical Table ID 0 in stage 1
+Allocating Table Type ID 0 of type exact in stage 1
Match Overhead:
Field --version_valid-- [3:0] (4 bits)
Field --immediate-- [15:0] (16 bits)
@@ -1012,9 +975,9 @@
Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ecmp_metadata.groupId[15:8]}.
---------------------------------------------
-Call to can_any_match_key_fields_be_shared(stage=2, table=ecmp_group_table)
+Call to can_any_match_key_fields_be_shared(stage=1, table=ecmp_group_table)
---------------------------------------------
-Decided way to allocate for table ecmp_group_table in stage 2 WAS non_shared
+Decided way to allocate for table ecmp_group_table in stage 1 WAS non_shared
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ecmp_metadata.selector[7:0]}.
Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ecmp_metadata.selector[15:8]}.
Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ecmp_metadata.groupId[7:0]}.
@@ -1139,12 +1102,12 @@
Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16])
Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20])
-Allocating Action ALU 2 (16 bits) in stage 2 for match table ecmp_group_table's action set_egress_port
-Allocating VLIW Instruction : 0 in stage 2 for match table ecmp_group_table's action set_egress_port
+Allocating Action ALU 2 (16 bits) in stage 1 for match table ecmp_group_table's action set_egress_port
+Allocating VLIW Instruction : 0 in stage 1 for match table ecmp_group_table's action set_egress_port
----------------------------------------------
Call to Allocate P4 Table with table ingress_port_count_table__action__, number_entries = 1024, table id = None, and match type = exact
- Allocating in stage 3
+ Allocating in stage 2
----------------------------------------------
ram_size_matrix =
@@ -1177,17 +1140,17 @@
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
-Allocating Action Logical Table ID 0 in stage 3
+Allocating Action Logical Table ID 0 in stage 2
----------------------------------------------
-Call to Allocate P4 Table with table ingress_port_counter, number_entries = 254, table id = None, and match type = exact
- Allocating in stage 3
+Call to Allocate P4 Table with table ingress_port_counter, number_entries = 510, table id = None, and match type = exact
+ Allocating in stage 2
----------------------------------------------
stat_stage_table referenced: indirect
stat Table Resource Request is:
SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams.
-Sram Resource Request for P4 table ingress_port_counter with handle 67108865 of type statistics in stage 3
+Sram Resource Request for P4 table ingress_port_counter with handle 67108865 of type statistics in stage 2
table_type : statistics
rams_for_width : 1
use_stash : False
@@ -1203,20 +1166,20 @@
----------------------------------------------
Call to Allocate P4 Table with table ingress_port_count_table, number_entries = 1024, table id = None, and match type = exact
- Allocating in stage 3
+ Allocating in stage 2
----------------------------------------------
-Logical Table ID in stage 3 was not supplied by table placement for table ingress_port_count_table.
-Allocating Logical Table ID 0 in stage 3
-Allocating Table Type ID 0 of type exact in stage 3
+Logical Table ID in stage 2 was not supplied by table placement for table ingress_port_count_table.
+Allocating Logical Table ID 0 in stage 2
+Allocating Table Type ID 0 of type exact in stage 2
Match Overhead:
Field --version_valid-- [3:0] (4 bits)
Field --instruction_address-- [1:0] (2 bits)
Field --statistics_pointer-- [19:0] (20 bits)
-Logical Table ID in stage 3 was not supplied by table placement for table ingress_port_count_table.
-Allocating Logical Table ID 0 in stage 3
-Allocating Table Type ID 0 of type exact in stage 3
+Logical Table ID in stage 2 was not supplied by table placement for table ingress_port_count_table.
+Allocating Logical Table ID 0 in stage 2
+Allocating Table Type ID 0 of type exact in stage 2
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
Match Table Resource Request is:
@@ -1224,12 +1187,12 @@
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
No micro instructions needed for action count_ingress executed from table ingress_port_count_table.
-Allocating Action ALU 0 (32 bits) in stage 3 for match table ingress_port_count_table's action count_ingress
-Allocating VLIW Instruction : 0 in stage 3 for match table ingress_port_count_table's action count_ingress
+Allocating Action ALU 0 (32 bits) in stage 2 for match table ingress_port_count_table's action count_ingress
+Allocating VLIW Instruction : 0 in stage 2 for match table ingress_port_count_table's action count_ingress
----------------------------------------------
Call to Allocate P4 Table with table egress_port_count_table__action__, number_entries = 1024, table id = None, and match type = exact
- Allocating in stage 3
+ Allocating in stage 2
----------------------------------------------
ram_size_matrix =
@@ -1262,17 +1225,17 @@
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
-Allocating Action Logical Table ID 1 in stage 3
+Allocating Action Logical Table ID 1 in stage 2
----------------------------------------------
-Call to Allocate P4 Table with table egress_port_counter, number_entries = 254, table id = None, and match type = exact
- Allocating in stage 3
+Call to Allocate P4 Table with table egress_port_counter, number_entries = 510, table id = None, and match type = exact
+ Allocating in stage 2
----------------------------------------------
stat_stage_table referenced: indirect
stat Table Resource Request is:
SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams.
-Sram Resource Request for P4 table egress_port_counter with handle 67108866 of type statistics in stage 3
+Sram Resource Request for P4 table egress_port_counter with handle 67108866 of type statistics in stage 2
table_type : statistics
rams_for_width : 1
use_stash : False
@@ -1290,19 +1253,19 @@
----------------------------------------------
Call to Allocate P4 Table with table egress_port_count_table, number_entries = 1024, table id = None, and match type = exact
- Allocating in stage 3
+ Allocating in stage 2
----------------------------------------------
-Logical Table ID in stage 3 was not supplied by table placement for table egress_port_count_table.
-Allocating Logical Table ID 1 in stage 3
-Allocating Table Type ID 1 of type exact in stage 3
+Logical Table ID in stage 2 was not supplied by table placement for table egress_port_count_table.
+Allocating Logical Table ID 1 in stage 2
+Allocating Table Type ID 1 of type exact in stage 2
Match Overhead:
Field --version_valid-- [3:0] (4 bits)
Field --statistics_pointer-- [19:0] (20 bits)
-Logical Table ID in stage 3 was not supplied by table placement for table egress_port_count_table.
-Allocating Logical Table ID 1 in stage 3
-Allocating Table Type ID 1 of type exact in stage 3
+Logical Table ID in stage 2 was not supplied by table placement for table egress_port_count_table.
+Allocating Logical Table ID 1 in stage 2
+Allocating Table Type ID 1 of type exact in stage 2
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
Match Table Resource Request is:
@@ -1310,102 +1273,32 @@
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
No micro instructions needed for action count_egress executed from table egress_port_count_table.
-Allocating Action ALU 0 (32 bits) in stage 3 for match table egress_port_count_table's action count_egress
-Allocating VLIW Instruction : 0 in stage 3 for match table egress_port_count_table's action count_egress
-
-----------------------------------------------
-Call to Allocate P4 Table with table egress_pkt__action__, number_entries = 1024, table id = None, and match type = exact
- Allocating in stage 0
-----------------------------------------------
-
-ram_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-immediate_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-hash_to_phv_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action add_packet_in_hdr has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action add_packet_in_hdr has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action add_packet_in_hdr has []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-Allocating Action Logical Table ID 1 in stage 0
-
-----------------------------------------------
-Call to Allocate P4 Table with table egress_pkt, number_entries = 1024, table id = None, and match type = exact
- Allocating in stage 0
-----------------------------------------------
-
-Logical Table ID in stage 0 was not supplied by table placement for table egress_pkt.
-Allocating Logical Table ID 1 in stage 0
-Allocating Table Type ID 1 of type exact in stage 0
-Match Overhead:
- Field --version_valid-- [3:0] (4 bits)
- Field --instruction_address-- [1:0] (2 bits)
-
-Logical Table ID in stage 0 was not supplied by table placement for table egress_pkt.
-Allocating Logical Table ID 1 in stage 0
-Allocating Table Type ID 1 of type exact in stage 0
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.copy_to_cpu[0:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
-Match Table Resource Request is:
-SRAM Resource Request for table egress_pkt (of type match), with 0 ways wants 0 rams.
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.copy_to_cpu[0:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
-For action add_packet_in_hdr, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 82 has bit width 20
- Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0])
- Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4])
- Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
- Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
- Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11])
- Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14])
- Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16])
- Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19])
-
-For action add_packet_in_hdr, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 145 has bit width 23
- Field Src2 [3:0] : 0x1 (4 bits in instruction bits [3:0])
- Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4])
- Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9])
- Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10])
- Field high_bit [3:0] : 0xf (4 bits in instruction bits [14:11])
- Field low_bit_lo [0:0] : 0x1 (1 bits in instruction bits [15:15])
- Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16])
- Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20])
-
-Allocating Action ALU 18 (8 bits) in stage 0 for match table egress_pkt's action add_packet_in_hdr
-Allocating Action ALU 17 (16 bits) in stage 0 for match table egress_pkt's action add_packet_in_hdr
-Allocating VLIW Instruction : 0 in stage 0 for match table egress_pkt's action add_packet_in_hdr
+Allocating Action ALU 0 (32 bits) in stage 2 for match table egress_port_count_table's action count_egress
+Allocating VLIW Instruction : 0 in stage 2 for match table egress_port_count_table's action count_egress
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
+Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
Skipping p4_primitive StageModifyFieldFromHashBitsPrimitive from overhead calculation.
Action ecmp_group for table table0 cannot be used as a default action (table miss action). The action requires the use of hash distribution, which is not available when a table misses.
Field ig_intr_md_for_tm.ucast_egress_port not contiguous on gateway input
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.resources.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.resources.log
index 5eae9b3..16b77f3 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.resources.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.resources.log
@@ -1,17 +1,17 @@
+---------------------------------------------------------------------+
| Log file: mau.resources.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-| 0 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |
-| 1 | 13 | 16 | 2 | 1 | 1 | 4 | 3 | 3 | 3 | 0 | 1 | 0 | 8 | 0 | 4 | 2 | 1 |
-| 2 | 4 | 0 | 30 | 0 | 0 | 5 | 2 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 2 | 1 | 1 |
-| 3 | 2 | 0 | 9 | 0 | 2 | 4 | 4 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 |
+| 0 | 13 | 16 | 2 | 1 | 2 | 4 | 3 | 3 | 3 | 0 | 1 | 0 | 8 | 0 | 4 | 2 | 2 |
+| 1 | 4 | 0 | 30 | 0 | 0 | 5 | 2 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 2 | 1 | 1 |
+| 2 | 2 | 0 | 9 | 0 | 2 | 4 | 4 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 |
+| 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
@@ -21,17 +21,17 @@
| 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| | | | | | | | | | | | | | | | | | |
-| Totals | 21 | 16 | 43 | 1 | 5 | 13 | 9 | 3 | 6 | 0 | 4 | 0 | 12 | 0 | 6 | 3 | 6 |
+| Totals | 19 | 16 | 41 | 1 | 4 | 13 | 9 | 3 | 5 | 0 | 4 | 0 | 12 | 0 | 6 | 3 | 5 |
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-| 0 | 1.56% | 0.00% | 0.48% | 0.00% | 12.50% | 0.00% | 0.00% | 0.00% | 3.12% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% |
-| 1 | 10.16% | 24.24% | 0.48% | 16.67% | 6.25% | 5.00% | 6.25% | 12.50% | 9.38% | 0.00% | 25.00% | 0.00% | 6.25% | 0.00% | 12.50% | 6.25% | 6.25% |
-| 2 | 3.12% | 0.00% | 7.21% | 0.00% | 0.00% | 6.25% | 4.17% | 0.00% | 3.12% | 0.00% | 25.00% | 0.00% | 3.12% | 0.00% | 6.25% | 3.12% | 6.25% |
-| 3 | 1.56% | 0.00% | 2.16% | 0.00% | 12.50% | 5.00% | 8.33% | 0.00% | 3.12% | 0.00% | 50.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% |
+| 0 | 10.16% | 24.24% | 0.48% | 16.67% | 12.50% | 5.00% | 6.25% | 12.50% | 9.38% | 0.00% | 25.00% | 0.00% | 6.25% | 0.00% | 12.50% | 6.25% | 12.50% |
+| 1 | 3.12% | 0.00% | 7.21% | 0.00% | 0.00% | 6.25% | 4.17% | 0.00% | 3.12% | 0.00% | 25.00% | 0.00% | 3.12% | 0.00% | 6.25% | 3.12% | 6.25% |
+| 2 | 1.56% | 0.00% | 2.16% | 0.00% | 12.50% | 5.00% | 8.33% | 0.00% | 3.12% | 0.00% | 50.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% |
+| 3 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| 4 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| 5 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| 6 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
@@ -41,7 +41,7 @@
| 10 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| 11 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| | | | | | | | | | | | | | | | | | |
-| Average | 1.37% | 2.02% | 0.86% | 1.39% | 2.60% | 1.35% | 1.56% | 1.04% | 1.56% | 0.00% | 8.33% | 0.00% | 0.78% | 0.00% | 1.56% | 0.78% | 3.12% |
+| Average | 1.24% | 2.02% | 0.82% | 1.39% | 2.08% | 1.35% | 1.56% | 1.04% | 1.30% | 0.00% | 8.33% | 0.00% | 0.78% | 0.00% | 1.56% | 0.78% | 2.60% |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -53,24 +53,20 @@
| | | | | | | | | Bytes | |
--------------------------------------------------------------------------------------------------------------------
| _condition_0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
-| _condition_3 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
-| ingress_pkt__action__ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| ingress_pkt | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
-| egress_pkt__action__ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| egress_pkt | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
-| _condition_1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
-| table0__action__ | 1 | 12 | 1 | 0 | 1 | 0 | 0 | 8 | 0 |
-| table0 | 1 | 16 | 0 | 0 | 1 | 3 | 1 | 0 | 4 |
-| table0_counter | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
-| ecmp_group_table__action__ | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 |
-| ecmp_group_table | 2 | 4 | 30 | 0 | 3 | 0 | 0 | 0 | 1 |
-| ecmp_group_table_counter | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
-| _condition_2 | 3 | 2 | 9 | 1 | 0 | 0 | 0 | 0 | 0 |
-| ingress_port_count_table__action__ | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| ingress_port_count_table | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
-| egress_port_count_table__action__ | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| egress_port_count_table | 3 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
-| ingress_port_counter | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
-| egress_port_counter | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
+| process_packet_out_table__action__ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| process_packet_out_table | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
+| table0__action__ | 0 | 12 | 1 | 0 | 1 | 0 | 0 | 8 | 0 |
+| table0 | 0 | 16 | 0 | 0 | 1 | 3 | 1 | 0 | 4 |
+| table0_counter | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
+| ecmp_group_table__action__ | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 |
+| ecmp_group_table | 1 | 4 | 30 | 0 | 3 | 0 | 0 | 0 | 1 |
+| ecmp_group_table_counter | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
+| _condition_2 | 2 | 2 | 9 | 1 | 0 | 0 | 0 | 0 | 0 |
+| ingress_port_count_table__action__ | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| ingress_port_count_table | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
+| egress_port_count_table__action__ | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| egress_port_count_table | 2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
+| ingress_port_counter | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
+| egress_port_counter | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
--------------------------------------------------------------------------------------------------------------------
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.rf.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.rf.log
index 644b517..dd29351 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.rf.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.rf.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: mau.rf.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.sram.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.sram.log
index 5dca0d0..8ac8b2a 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.sram.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.sram.log
@@ -1,60 +1,13 @@
+---------------------------------------------------------------------+
| Log file: mau.sram.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
=======================================================
- calling allocate and add with SRAM Resource Request for table ingress_pkt (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False)
-=======================================================
-
-Requesting to use 0 RAMs and have 80 available.
-Requesting to use 0 Map RAMs and have 48 available.
-
-========================================================
- Run Placement on Request List of size 1 in stage 0
- open_up_all_for_match=False
- synth_two_port_first=False
-========================================================
-
-Match Rams Need is 0
-Algorithmic TCAM Match RAMs Need is 0
-Other Rams Need is 0
-
-+=========================================
-| Placing algorithmic tcam
-+=========================================
-
-sorted algorithmic tcam requests: (0)
-
-
--------------------------------------
-Columns need for match is 0
-columns for width is 0
-other columns is 0
-reserved columns is 10
-reserved columns for tind 0
-reserved columns for stateful 0
-Ternary Indirection Rams Need is 0
-Depth sorted requested
-Requesting to use 0 RAMs and have 32 available.
-Result bus only needs (1):
- ingress_pkt
-Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 0
-
-+=========================================
-| Placing action/stats/meters/selection
-+=========================================
-
-Requesting to use 0 RAMs and have 80 available.
-Depth sorted idletime requests:
-
-
-=======================================================
-
calling allocate and add with SRAM Resource Request for table table0__action__ (of type action), with 1 ways wants 1 rams. (open-all=False, synth_two_port_first=False)
=======================================================
@@ -62,7 +15,7 @@
Requesting to use 0 Map RAMs and have 48 available.
========================================================
- Run Placement on Request List of size 1 in stage 1
+ Run Placement on Request List of size 1 in stage 0
open_up_all_for_match=False
synth_two_port_first=False
========================================================
@@ -99,8 +52,8 @@
NO Spill Required off of logical row 15 for SRAM Resource Request for table table0__action__ (of type action), with 1 ways wants 1 rams.
call to place_table_on_logical_row --- logical row 15 and rams to place is 1 and depth index is 0
-Allocating: SRAM: Row 7 Col 6 in stage 1 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Ram Data Bus ActionR 7 right is 128 bits in stage 1 for table0__action__.
+Allocating: SRAM: Row 7 Col 6 in stage 0 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Ram Data Bus ActionR 7 right is 128 bits in stage 0 for table0__action__.
Depth sorted idletime requests:
@@ -113,7 +66,7 @@
Requesting to use 0 Map RAMs and have 48 available.
========================================================
- Run Placement on Request List of size 2 in stage 1
+ Run Placement on Request List of size 2 in stage 0
open_up_all_for_match=False
synth_two_port_first=False
========================================================
@@ -151,17 +104,17 @@
NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams.
call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0
-Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table table0_counter.
-Allocating: SRAM: Row 6 Col 6 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Map RAM: Row 6 Unit 0 in stage 1 for table0_counter.
-Allocating: SRAM: Row 6 Col 7 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
-Allocating: Map RAM: Row 6 Unit 1 in stage 1 for table0_counter.
+Allocating: Statistics ALU 6 on right (128 bits) in stage 0 for table table0_counter.
+Allocating: SRAM: Row 6 Col 6 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Map RAM: Row 6 Unit 0 in stage 0 for table0_counter.
+Allocating: SRAM: Row 6 Col 7 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
+Allocating: Map RAM: Row 6 Unit 1 in stage 0 for table0_counter.
call to place_table_on_logical_row --- logical row 13 and rams to place is 1 and depth index is 0
-Allocating: SRAM: Row 6 Col 8 in stage 1 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Ram Data Bus ActionR 6 right is 128 bits in stage 1
-Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for table0_counter.
-Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for table0_counter.
+Allocating: SRAM: Row 6 Col 8 in stage 0 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Ram Data Bus ActionR 6 right is 128 bits in stage 0
+Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 0 for table0_counter.
+Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 0 for table0_counter.
Depth sorted idletime requests:
@@ -174,7 +127,7 @@
Requesting to use 0 Map RAMs and have 46 available.
========================================================
- Run Placement on Request List of size 3 in stage 1
+ Run Placement on Request List of size 3 in stage 0
open_up_all_for_match=False
synth_two_port_first=False
========================================================
@@ -200,7 +153,7 @@
Ternary Indirection Rams Need is 1
Depth sorted requested
Group 0
-Sram Resource Request for P4 table table0 with handle 16777221 of type ternary_indirection in stage 1
+Sram Resource Request for P4 table table0 with handle 16777220 of type ternary_indirection in stage 0
table_type : ternary_indirection
rams_for_width : 1
use_stash : False
@@ -214,8 +167,8 @@
ram_enable_select_bits : 0
Requesting to use 1 RAMs and have 32 available.
-Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 1
-Allocating: SRAM: Row 0 Col 2 in stage 1 for table table0's ternary indirection word range Words 0 to 1023.
+Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 0
+Allocating: SRAM: Row 0 Col 2 in stage 0 for table table0's ternary indirection word range Words 0 to 1023.
Result bus only needs (0):
+=========================================
@@ -228,17 +181,17 @@
NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams.
call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0
-Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table table0_counter.
-Allocating: SRAM: Row 6 Col 6 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Map RAM: Row 6 Unit 0 in stage 1 for table0_counter.
-Allocating: SRAM: Row 6 Col 7 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
-Allocating: Map RAM: Row 6 Unit 1 in stage 1 for table0_counter.
+Allocating: Statistics ALU 6 on right (128 bits) in stage 0 for table table0_counter.
+Allocating: SRAM: Row 6 Col 6 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Map RAM: Row 6 Unit 0 in stage 0 for table0_counter.
+Allocating: SRAM: Row 6 Col 7 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
+Allocating: Map RAM: Row 6 Unit 1 in stage 0 for table0_counter.
call to place_table_on_logical_row --- logical row 13 and rams to place is 1 and depth index is 0
-Allocating: SRAM: Row 6 Col 8 in stage 1 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Ram Data Bus ActionR 6 right is 128 bits in stage 1
-Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for table0_counter.
-Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for table0_counter.
+Allocating: SRAM: Row 6 Col 8 in stage 0 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Ram Data Bus ActionR 6 right is 128 bits in stage 0
+Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 0 for table0_counter.
+Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 0 for table0_counter.
Depth sorted idletime requests:
@@ -251,7 +204,7 @@
Requesting to use 1 Map RAMs and have 46 available.
========================================================
- Run Placement on Request List of size 4 in stage 1
+ Run Placement on Request List of size 4 in stage 0
open_up_all_for_match=False
synth_two_port_first=False
========================================================
@@ -277,7 +230,7 @@
Ternary Indirection Rams Need is 1
Depth sorted requested
Group 0
-Sram Resource Request for P4 table table0 with handle 16777221 of type ternary_indirection in stage 1
+Sram Resource Request for P4 table table0 with handle 16777220 of type ternary_indirection in stage 0
table_type : ternary_indirection
rams_for_width : 1
use_stash : False
@@ -291,8 +244,8 @@
ram_enable_select_bits : 0
Requesting to use 1 RAMs and have 32 available.
-Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 1
-Allocating: SRAM: Row 0 Col 2 in stage 1 for table table0's ternary indirection word range Words 0 to 1023.
+Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 0
+Allocating: SRAM: Row 0 Col 2 in stage 0 for table table0's ternary indirection word range Words 0 to 1023.
Result bus only needs (0):
+=========================================
@@ -305,19 +258,19 @@
NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams.
call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0
-Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table table0_counter.
-Allocating: SRAM: Row 6 Col 6 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Map RAM: Row 6 Unit 0 in stage 1 for table0_counter.
-Allocating: SRAM: Row 6 Col 7 in stage 1 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
-Allocating: Map RAM: Row 6 Unit 1 in stage 1 for table0_counter.
+Allocating: Statistics ALU 6 on right (128 bits) in stage 0 for table table0_counter.
+Allocating: SRAM: Row 6 Col 6 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Map RAM: Row 6 Unit 0 in stage 0 for table0_counter.
+Allocating: SRAM: Row 6 Col 7 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
+Allocating: Map RAM: Row 6 Unit 1 in stage 0 for table0_counter.
call to place_table_on_logical_row --- logical row 13 and rams to place is 1 and depth index is 0
-Allocating: SRAM: Row 6 Col 8 in stage 1 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Ram Data Bus ActionR 6 right is 128 bits in stage 1
-Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for table0_counter.
-Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for table0_counter.
+Allocating: SRAM: Row 6 Col 8 in stage 0 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Ram Data Bus ActionR 6 right is 128 bits in stage 0
+Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 0 for table0_counter.
+Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 0 for table0_counter.
Depth sorted idletime requests:
-Sram Resource Request for P4 table table0 with handle 16777221 of type idletime in stage 1
+Sram Resource Request for P4 table table0 with handle 16777220 of type idletime in stage 0
table_type : idletime
rams_for_width : 0
use_stash : False
@@ -335,8 +288,107 @@
bottom_cnt = 0 and num requests = 0
Working on idletime request SRAM Resource Request for table table0 (of type idletime), with 1 ways wants 0 rams.
>> wants 1 map rams
-Allocating: Map RAM: Row 7 Unit 0 in stage 1 for table0.
-Allocating: Ram Data Bus IdletimeHalfLogicalRow 0 top is 19 bits in stage 1 for table0.
+Allocating: Map RAM: Row 7 Unit 0 in stage 0 for table0.
+Allocating: Ram Data Bus IdletimeHalfLogicalRow 0 top is 19 bits in stage 0 for table0.
+
+
+=======================================================
+
+ calling allocate and add with SRAM Resource Request for table process_packet_out_table (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False)
+=======================================================
+
+Requesting to use 0 RAMs and have 76 available.
+Requesting to use 0 Map RAMs and have 45 available.
+
+========================================================
+ Run Placement on Request List of size 5 in stage 0
+ open_up_all_for_match=False
+ synth_two_port_first=False
+========================================================
+
+Match Rams Need is 0
+Algorithmic TCAM Match RAMs Need is 0
+Other Rams Need is 4
+
++=========================================
+| Placing algorithmic tcam
++=========================================
+
+sorted algorithmic tcam requests: (0)
+
+
+-------------------------------------
+Columns need for match is 0
+columns for width is 0
+other columns is 1
+reserved columns is 9
+reserved columns for tind 1
+reserved columns for stateful 1
+Ternary Indirection Rams Need is 1
+Depth sorted requested
+Group 0
+Sram Resource Request for P4 table table0 with handle 16777220 of type ternary_indirection in stage 0
+ table_type : ternary_indirection
+ rams_for_width : 1
+ use_stash : False
+ number_ways : 1
+ way #0
+ SRAM Request Group 0
+ rams_for_depth : 1
+ map_rams : 0
+ way_number : 0
+ ram_word_select_bits : 0
+ ram_enable_select_bits : 0
+
+Requesting to use 1 RAMs and have 32 available.
+Allocating: Ram Data Bus TernaryIndirection1R 0 left is 64 bits in stage 0
+Allocating: SRAM: Row 0 Col 2 in stage 0 for table table0's ternary indirection word range Words 0 to 1023.
+Result bus only needs (1):
+ process_packet_out_table
+Allocating: Ram Data Bus MatchResult2R 0 left_and_right is 83 bits in stage 0
+
++=========================================
+| Placing action/stats/meters/selection
++=========================================
+
+Requesting to use 3 RAMs and have 79 available.
+SRAM Resource Request for table table0__action__ (of type action), with 1 ways wants 1 rams.
+SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams.
+NO Spill Required off of logical row 13 for SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams.
+
+call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0
+Allocating: Statistics ALU 6 on right (128 bits) in stage 0 for table table0_counter.
+Allocating: SRAM: Row 6 Col 6 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Map RAM: Row 6 Unit 0 in stage 0 for table0_counter.
+Allocating: SRAM: Row 6 Col 7 in stage 0 for table table0_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
+Allocating: Map RAM: Row 6 Unit 1 in stage 0 for table0_counter.
+
+call to place_table_on_logical_row --- logical row 13 and rams to place is 1 and depth index is 0
+Allocating: SRAM: Row 6 Col 8 in stage 0 for table table0__action__'s entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Ram Data Bus ActionR 6 right is 128 bits in stage 0
+Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 0 for table0_counter.
+Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 0 for table0_counter.
+Depth sorted idletime requests:
+Sram Resource Request for P4 table table0 with handle 16777220 of type idletime in stage 0
+ table_type : idletime
+ rams_for_width : 0
+ use_stash : False
+ number_ways : 1
+ way #0
+ SRAM Request Group 0
+ rams_for_depth : 0
+ map_rams : 1
+ way_number : 0
+ ram_word_select_bits : 0
+ ram_enable_select_bits : 0
+
+Requesting to use 1 RAMs and have 46 available.
+top_cnt = 1 and num requests = 1
+bottom_cnt = 0 and num requests = 0
+Working on idletime request SRAM Resource Request for table table0 (of type idletime), with 1 ways wants 0 rams.
+>> wants 1 map rams
+Allocating: Map RAM: Row 7 Unit 0 in stage 0 for table0.
+Allocating: Ram Data Bus IdletimeHalfLogicalRow 0 top is 19 bits in stage 0 for table0.
=======================================================
@@ -348,6 +400,125 @@
Requesting to use 0 Map RAMs and have 48 available.
========================================================
+ Run Placement on Request List of size 1 in stage 1
+ open_up_all_for_match=False
+ synth_two_port_first=False
+========================================================
+
+Match Rams Need is 0
+Algorithmic TCAM Match RAMs Need is 0
+Other Rams Need is 2
+
++=========================================
+| Placing algorithmic tcam
++=========================================
+
+sorted algorithmic tcam requests: (0)
+
+
+-------------------------------------
+Columns need for match is 0
+columns for width is 0
+other columns is 1
+reserved columns is 9
+reserved columns for tind 0
+reserved columns for stateful 1
+Ternary Indirection Rams Need is 0
+Depth sorted requested
+Requesting to use 0 RAMs and have 32 available.
+Result bus only needs (0):
+
++=========================================
+| Placing action/stats/meters/selection
++=========================================
+
+Requesting to use 2 RAMs and have 80 available.
+SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams.
+NO Spill Required off of logical row 13 for SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams.
+
+call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0
+Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table ecmp_group_table_counter.
+Allocating: SRAM: Row 6 Col 6 in stage 1 for table ecmp_group_table_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Map RAM: Row 6 Unit 0 in stage 1 for ecmp_group_table_counter.
+Allocating: SRAM: Row 6 Col 7 in stage 1 for table ecmp_group_table_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
+Allocating: Map RAM: Row 6 Unit 1 in stage 1 for ecmp_group_table_counter.
+Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for ecmp_group_table_counter.
+Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for ecmp_group_table_counter.
+Depth sorted idletime requests:
+
+
+=======================================================
+
+ calling allocate and add with SRAM Resource Request for table ecmp_group_table (of type match), with 3 ways wants 3 rams. (open-all=False, synth_two_port_first=False)
+=======================================================
+
+Requesting to use 3 RAMs and have 78 available.
+Requesting to use 0 Map RAMs and have 46 available.
+
+========================================================
+ Run Placement on Request List of size 2 in stage 1
+ open_up_all_for_match=False
+ synth_two_port_first=False
+========================================================
+
+Match Rams Need is 3
+Algorithmic TCAM Match RAMs Need is 0
+Other Rams Need is 2
+
++=========================================
+| Placing algorithmic tcam
++=========================================
+
+sorted algorithmic tcam requests: (0)
+
+
+-------------------------------------
+Columns need for match is 1
+columns for width is 1
+other columns is 1
+reserved columns is 9
+reserved columns for tind 0
+reserved columns for stateful 1
+For group request 0
+ Dealing with way that starts at 0 of match request SRAM Resource Request for table ecmp_group_table (of type match), with 3 ways wants 3 rams.
+Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 1
+Allocating: Ram Data Bus MatchResult1R 7 left_and_right is 83 bits in stage 1
+Allocating: SRAM: Row 7 Col 2 in stage 1 for table ecmp_group_table's match way 0 for entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: SRAM: Row 7 Col 3 in stage 1 for table ecmp_group_table's match way 1 for entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: SRAM: Row 7 Col 4 in stage 1 for table ecmp_group_table's match way 2 for entry Entry bits [127: 0] and word range Words 0 to 1023.
+Ternary Indirection Rams Need is 0
+Depth sorted requested
+Requesting to use 0 RAMs and have 29 available.
+Result bus only needs (0):
+
++=========================================
+| Placing action/stats/meters/selection
++=========================================
+
+Requesting to use 2 RAMs and have 77 available.
+SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams.
+NO Spill Required off of logical row 13 for SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams.
+
+call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0
+Allocating: Statistics ALU 6 on right (128 bits) in stage 1 for table ecmp_group_table_counter.
+Allocating: SRAM: Row 6 Col 6 in stage 1 for table ecmp_group_table_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Map RAM: Row 6 Unit 0 in stage 1 for ecmp_group_table_counter.
+Allocating: SRAM: Row 6 Col 7 in stage 1 for table ecmp_group_table_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
+Allocating: Map RAM: Row 6 Unit 1 in stage 1 for ecmp_group_table_counter.
+Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 1 for ecmp_group_table_counter.
+Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 1 for ecmp_group_table_counter.
+Depth sorted idletime requests:
+
+
+=======================================================
+
+ calling allocate and add with SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False)
+=======================================================
+
+Requesting to use 2 RAMs and have 80 available.
+Requesting to use 0 Map RAMs and have 48 available.
+
+========================================================
Run Placement on Request List of size 1 in stage 2
open_up_all_for_match=False
synth_two_port_first=False
@@ -381,136 +552,17 @@
+=========================================
Requesting to use 2 RAMs and have 80 available.
-SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams.
-NO Spill Required off of logical row 13 for SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams.
-
-call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0
-Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table ecmp_group_table_counter.
-Allocating: SRAM: Row 6 Col 6 in stage 2 for table ecmp_group_table_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Map RAM: Row 6 Unit 0 in stage 2 for ecmp_group_table_counter.
-Allocating: SRAM: Row 6 Col 7 in stage 2 for table ecmp_group_table_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
-Allocating: Map RAM: Row 6 Unit 1 in stage 2 for ecmp_group_table_counter.
-Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for ecmp_group_table_counter.
-Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for ecmp_group_table_counter.
-Depth sorted idletime requests:
-
-
-=======================================================
-
- calling allocate and add with SRAM Resource Request for table ecmp_group_table (of type match), with 3 ways wants 3 rams. (open-all=False, synth_two_port_first=False)
-=======================================================
-
-Requesting to use 3 RAMs and have 78 available.
-Requesting to use 0 Map RAMs and have 46 available.
-
-========================================================
- Run Placement on Request List of size 2 in stage 2
- open_up_all_for_match=False
- synth_two_port_first=False
-========================================================
-
-Match Rams Need is 3
-Algorithmic TCAM Match RAMs Need is 0
-Other Rams Need is 2
-
-+=========================================
-| Placing algorithmic tcam
-+=========================================
-
-sorted algorithmic tcam requests: (0)
-
-
--------------------------------------
-Columns need for match is 1
-columns for width is 1
-other columns is 1
-reserved columns is 9
-reserved columns for tind 0
-reserved columns for stateful 1
-For group request 0
- Dealing with way that starts at 0 of match request SRAM Resource Request for table ecmp_group_table (of type match), with 3 ways wants 3 rams.
-Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 2
-Allocating: Ram Data Bus MatchResult1R 7 left_and_right is 83 bits in stage 2
-Allocating: SRAM: Row 7 Col 2 in stage 2 for table ecmp_group_table's match way 0 for entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: SRAM: Row 7 Col 3 in stage 2 for table ecmp_group_table's match way 1 for entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: SRAM: Row 7 Col 4 in stage 2 for table ecmp_group_table's match way 2 for entry Entry bits [127: 0] and word range Words 0 to 1023.
-Ternary Indirection Rams Need is 0
-Depth sorted requested
-Requesting to use 0 RAMs and have 29 available.
-Result bus only needs (0):
-
-+=========================================
-| Placing action/stats/meters/selection
-+=========================================
-
-Requesting to use 2 RAMs and have 77 available.
-SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams.
-NO Spill Required off of logical row 13 for SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams.
-
-call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0
-Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table ecmp_group_table_counter.
-Allocating: SRAM: Row 6 Col 6 in stage 2 for table ecmp_group_table_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Map RAM: Row 6 Unit 0 in stage 2 for ecmp_group_table_counter.
-Allocating: SRAM: Row 6 Col 7 in stage 2 for table ecmp_group_table_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
-Allocating: Map RAM: Row 6 Unit 1 in stage 2 for ecmp_group_table_counter.
-Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for ecmp_group_table_counter.
-Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for ecmp_group_table_counter.
-Depth sorted idletime requests:
-
-
-=======================================================
-
- calling allocate and add with SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams. (open-all=False, synth_two_port_first=False)
-=======================================================
-
-Requesting to use 2 RAMs and have 80 available.
-Requesting to use 0 Map RAMs and have 48 available.
-
-========================================================
- Run Placement on Request List of size 1 in stage 3
- open_up_all_for_match=False
- synth_two_port_first=False
-========================================================
-
-Match Rams Need is 0
-Algorithmic TCAM Match RAMs Need is 0
-Other Rams Need is 2
-
-+=========================================
-| Placing algorithmic tcam
-+=========================================
-
-sorted algorithmic tcam requests: (0)
-
-
--------------------------------------
-Columns need for match is 0
-columns for width is 0
-other columns is 1
-reserved columns is 9
-reserved columns for tind 0
-reserved columns for stateful 1
-Ternary Indirection Rams Need is 0
-Depth sorted requested
-Requesting to use 0 RAMs and have 32 available.
-Result bus only needs (0):
-
-+=========================================
-| Placing action/stats/meters/selection
-+=========================================
-
-Requesting to use 2 RAMs and have 80 available.
SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams.
NO Spill Required off of logical row 13 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams.
call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0
-Allocating: Statistics ALU 6 on right (128 bits) in stage 3 for table ingress_port_counter.
-Allocating: SRAM: Row 6 Col 6 in stage 3 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Map RAM: Row 6 Unit 0 in stage 3 for ingress_port_counter.
-Allocating: SRAM: Row 6 Col 7 in stage 3 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
-Allocating: Map RAM: Row 6 Unit 1 in stage 3 for ingress_port_counter.
-Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 3 for ingress_port_counter.
-Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 3 for ingress_port_counter.
+Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table ingress_port_counter.
+Allocating: SRAM: Row 6 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Map RAM: Row 6 Unit 0 in stage 2 for ingress_port_counter.
+Allocating: SRAM: Row 6 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
+Allocating: Map RAM: Row 6 Unit 1 in stage 2 for ingress_port_counter.
+Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for ingress_port_counter.
+Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for ingress_port_counter.
Depth sorted idletime requests:
@@ -523,7 +575,7 @@
Requesting to use 0 Map RAMs and have 46 available.
========================================================
- Run Placement on Request List of size 2 in stage 3
+ Run Placement on Request List of size 2 in stage 2
open_up_all_for_match=False
synth_two_port_first=False
========================================================
@@ -551,7 +603,7 @@
Requesting to use 0 RAMs and have 32 available.
Result bus only needs (1):
ingress_port_count_table
-Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 3
+Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 2
+=========================================
| Placing action/stats/meters/selection
@@ -562,13 +614,13 @@
NO Spill Required off of logical row 13 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams.
call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0
-Allocating: Statistics ALU 6 on right (128 bits) in stage 3 for table ingress_port_counter.
-Allocating: SRAM: Row 6 Col 6 in stage 3 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Map RAM: Row 6 Unit 0 in stage 3 for ingress_port_counter.
-Allocating: SRAM: Row 6 Col 7 in stage 3 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
-Allocating: Map RAM: Row 6 Unit 1 in stage 3 for ingress_port_counter.
-Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 3 for ingress_port_counter.
-Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 3 for ingress_port_counter.
+Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table ingress_port_counter.
+Allocating: SRAM: Row 6 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Map RAM: Row 6 Unit 0 in stage 2 for ingress_port_counter.
+Allocating: SRAM: Row 6 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
+Allocating: Map RAM: Row 6 Unit 1 in stage 2 for ingress_port_counter.
+Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for ingress_port_counter.
+Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for ingress_port_counter.
Depth sorted idletime requests:
@@ -581,7 +633,7 @@
Requesting to use 0 Map RAMs and have 46 available.
========================================================
- Run Placement on Request List of size 3 in stage 3
+ Run Placement on Request List of size 3 in stage 2
open_up_all_for_match=False
synth_two_port_first=False
========================================================
@@ -609,7 +661,7 @@
Requesting to use 0 RAMs and have 32 available.
Result bus only needs (1):
ingress_port_count_table
-Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 3
+Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 2
+=========================================
| Placing action/stats/meters/selection
@@ -621,23 +673,23 @@
NO Spill Required off of logical row 13 for SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams.
call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0
-Allocating: Statistics ALU 6 on right (128 bits) in stage 3 for table egress_port_counter.
-Allocating: SRAM: Row 6 Col 6 in stage 3 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Map RAM: Row 6 Unit 0 in stage 3 for egress_port_counter.
-Allocating: SRAM: Row 6 Col 7 in stage 3 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
-Allocating: Map RAM: Row 6 Unit 1 in stage 3 for egress_port_counter.
-Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 3 for egress_port_counter.
-Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 3 for egress_port_counter.
+Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table egress_port_counter.
+Allocating: SRAM: Row 6 Col 6 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Map RAM: Row 6 Unit 0 in stage 2 for egress_port_counter.
+Allocating: SRAM: Row 6 Col 7 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
+Allocating: Map RAM: Row 6 Unit 1 in stage 2 for egress_port_counter.
+Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for egress_port_counter.
+Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for egress_port_counter.
NO Spill Required off of logical row 9 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams.
call to place_table_on_logical_row --- logical row 9 and rams to place is 2 and depth index is 0
-Allocating: Statistics ALU 4 on right (128 bits) in stage 3 for table ingress_port_counter.
-Allocating: SRAM: Row 4 Col 6 in stage 3 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Map RAM: Row 4 Unit 0 in stage 3 for ingress_port_counter.
-Allocating: SRAM: Row 4 Col 7 in stage 3 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
-Allocating: Map RAM: Row 4 Unit 1 in stage 3 for ingress_port_counter.
-Allocating: Ram Data Bus StatsR 4 right is 128 bits in stage 3 for ingress_port_counter.
-Allocating: Ram Data Bus StatsW 4 right is 128 bits in stage 3 for ingress_port_counter.
+Allocating: Statistics ALU 4 on right (128 bits) in stage 2 for table ingress_port_counter.
+Allocating: SRAM: Row 4 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Map RAM: Row 4 Unit 0 in stage 2 for ingress_port_counter.
+Allocating: SRAM: Row 4 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
+Allocating: Map RAM: Row 4 Unit 1 in stage 2 for ingress_port_counter.
+Allocating: Ram Data Bus StatsR 4 right is 128 bits in stage 2 for ingress_port_counter.
+Allocating: Ram Data Bus StatsW 4 right is 128 bits in stage 2 for ingress_port_counter.
Depth sorted idletime requests:
@@ -650,7 +702,7 @@
Requesting to use 0 Map RAMs and have 44 available.
========================================================
- Run Placement on Request List of size 4 in stage 3
+ Run Placement on Request List of size 4 in stage 2
open_up_all_for_match=False
synth_two_port_first=False
========================================================
@@ -679,8 +731,8 @@
Result bus only needs (2):
egress_port_count_table
ingress_port_count_table
-Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 3
-Allocating: Ram Data Bus MatchResult2R 0 left_and_right is 83 bits in stage 3
+Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 2
+Allocating: Ram Data Bus MatchResult2R 0 left_and_right is 83 bits in stage 2
+=========================================
| Placing action/stats/meters/selection
@@ -692,70 +744,21 @@
NO Spill Required off of logical row 13 for SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams.
call to place_table_on_logical_row --- logical row 13 and rams to place is 2 and depth index is 0
-Allocating: Statistics ALU 6 on right (128 bits) in stage 3 for table egress_port_counter.
-Allocating: SRAM: Row 6 Col 6 in stage 3 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Map RAM: Row 6 Unit 0 in stage 3 for egress_port_counter.
-Allocating: SRAM: Row 6 Col 7 in stage 3 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
-Allocating: Map RAM: Row 6 Unit 1 in stage 3 for egress_port_counter.
-Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 3 for egress_port_counter.
-Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 3 for egress_port_counter.
+Allocating: Statistics ALU 6 on right (128 bits) in stage 2 for table egress_port_counter.
+Allocating: SRAM: Row 6 Col 6 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Map RAM: Row 6 Unit 0 in stage 2 for egress_port_counter.
+Allocating: SRAM: Row 6 Col 7 in stage 2 for table egress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
+Allocating: Map RAM: Row 6 Unit 1 in stage 2 for egress_port_counter.
+Allocating: Ram Data Bus StatsR 6 right is 128 bits in stage 2 for egress_port_counter.
+Allocating: Ram Data Bus StatsW 6 right is 128 bits in stage 2 for egress_port_counter.
NO Spill Required off of logical row 9 for SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams.
call to place_table_on_logical_row --- logical row 9 and rams to place is 2 and depth index is 0
-Allocating: Statistics ALU 4 on right (128 bits) in stage 3 for table ingress_port_counter.
-Allocating: SRAM: Row 4 Col 6 in stage 3 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
-Allocating: Map RAM: Row 4 Unit 0 in stage 3 for ingress_port_counter.
-Allocating: SRAM: Row 4 Col 7 in stage 3 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
-Allocating: Map RAM: Row 4 Unit 1 in stage 3 for ingress_port_counter.
-Allocating: Ram Data Bus StatsR 4 right is 128 bits in stage 3 for ingress_port_counter.
-Allocating: Ram Data Bus StatsW 4 right is 128 bits in stage 3 for ingress_port_counter.
-Depth sorted idletime requests:
-
-
-=======================================================
-
- calling allocate and add with SRAM Resource Request for table egress_pkt (of type match), with 0 ways wants 0 rams. (open-all=False, synth_two_port_first=False)
-=======================================================
-
-Requesting to use 0 RAMs and have 80 available.
-Requesting to use 0 Map RAMs and have 48 available.
-
-========================================================
- Run Placement on Request List of size 2 in stage 0
- open_up_all_for_match=False
- synth_two_port_first=False
-========================================================
-
-Match Rams Need is 0
-Algorithmic TCAM Match RAMs Need is 0
-Other Rams Need is 0
-
-+=========================================
-| Placing algorithmic tcam
-+=========================================
-
-sorted algorithmic tcam requests: (0)
-
-
--------------------------------------
-Columns need for match is 0
-columns for width is 0
-other columns is 0
-reserved columns is 10
-reserved columns for tind 0
-reserved columns for stateful 0
-Ternary Indirection Rams Need is 0
-Depth sorted requested
-Requesting to use 0 RAMs and have 32 available.
-Result bus only needs (2):
- egress_pkt
- ingress_pkt
-Allocating: Ram Data Bus MatchResult1R 0 left_and_right is 83 bits in stage 0
-Allocating: Ram Data Bus MatchResult2R 0 left_and_right is 83 bits in stage 0
-
-+=========================================
-| Placing action/stats/meters/selection
-+=========================================
-
-Requesting to use 0 RAMs and have 80 available.
+Allocating: Statistics ALU 4 on right (128 bits) in stage 2 for table ingress_port_counter.
+Allocating: SRAM: Row 4 Col 6 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 0 to 1023.
+Allocating: Map RAM: Row 4 Unit 0 in stage 2 for ingress_port_counter.
+Allocating: SRAM: Row 4 Col 7 in stage 2 for table ingress_port_counter's entry Entry bits [127: 0] and word range Words 1024 to 2047.
+Allocating: Map RAM: Row 4 Unit 1 in stage 2 for ingress_port_counter.
+Allocating: Ram Data Bus StatsR 4 right is 128 bits in stage 2 for ingress_port_counter.
+Allocating: Ram Data Bus StatsW 4 right is 128 bits in stage 2 for ingress_port_counter.
Depth sorted idletime requests:
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tcam.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tcam.log
index faa98f7..7db6441 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tcam.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tcam.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.tcam.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
@@ -17,9 +17,9 @@
Run Placement on Request List of size 1
========================================================
-Allocating: TCAM: Row 11 Col 1 in stage 1 for table table0 for entries Entry bits [43:0] and word range Words 0 to 511.
-Allocating: TCAM: Row 10 Col 1 in stage 1 for table table0 for entries Entry bits [87:44] and word range Words 0 to 511.
-Allocating: TCAM: Row 9 Col 1 in stage 1 for table table0 for entries Entry bits [131:88] and word range Words 0 to 511.
-Allocating: Ram Data Bus TcamMatchSearch2 11 left_and_right is 44 bits in stage 1
-Allocating: Ram Data Bus TcamMatchSearch2 10 left_and_right is 44 bits in stage 1
-Allocating: Ram Data Bus TcamMatchSearch2 9 left_and_right is 44 bits in stage 1
+Allocating: TCAM: Row 11 Col 1 in stage 0 for table table0 for entries Entry bits [43:0] and word range Words 0 to 511.
+Allocating: TCAM: Row 10 Col 1 in stage 0 for table table0 for entries Entry bits [87:44] and word range Words 0 to 511.
+Allocating: TCAM: Row 9 Col 1 in stage 0 for table table0 for entries Entry bits [131:88] and word range Words 0 to 511.
+Allocating: Ram Data Bus TcamMatchSearch2 11 left_and_right is 44 bits in stage 0
+Allocating: Ram Data Bus TcamMatchSearch2 10 left_and_right is 44 bits in stage 0
+Allocating: Ram Data Bus TcamMatchSearch2 9 left_and_right is 44 bits in stage 0
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tp.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tp.log
index dc2c79b..7b6e2c0 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tp.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.tp.log
@@ -1,35 +1,48 @@
+---------------------------------------------------------------------+
| Log file: mau.tp.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
----- Stage 0 ------
_condition_0
- ingress_pkt
------ Stage 1 ------
- _condition_1
+ process_packet_out_table
table0
------ Stage 2 ------
+----- Stage 1 ------
ecmp_group_table
------ Stage 3 ------
+----- Stage 2 ------
_condition_2
ingress_port_count_table
egress_port_count_table
----- Stage 0 ------
- _condition_3
- egress_pkt
+ _condition_0
+ process_packet_out_table
+ table0
+----- Stage 1 ------
+ ecmp_group_table
+----- Stage 2 ------
+ _condition_2
+ ingress_port_count_table
+ egress_port_count_table
+----- Stage 0 ------
+ _condition_0
+ process_packet_out_table
+ table0
+----- Stage 1 ------
+ ecmp_group_table
+----- Stage 2 ------
+ _condition_2
+ ingress_port_count_table
+ egress_port_count_table
------------------------------------------
Running Table Placement 4
------------------------------------------
Cannot use hash action for table ingress_port_count_table.
-Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 254.
+Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 510.
Cannot use hash action for table egress_port_count_table.
-Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 254.
-Cannot use hash action for table ingress_pkt.
-Table ingress_pkt has no side effect tables.
-Cannot use hash action for table egress_pkt.
-Table egress_pkt has no side effect tables.
+Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 510.
+Cannot use hash action for table process_packet_out_table.
+Table process_packet_out_table has no side effect tables.
User requested to not attempt to place action data parameters in the match overhead.
Cannot use hash action for table table0.
Cannot use hash-action for table table0 because it requires a ternary-style match for field ig_intr_md.ingress_port.
@@ -38,68 +51,70 @@
------------------------------------------
Table Groups
------------------------------------------
-Table Grouping (ingress) with match table ingress_port_count_table (1024) [ingress_port_count_table__action__ (1024), ingress_port_counter (254)]
-Table Grouping (ingress) with match table egress_port_count_table (1024) [egress_port_count_table__action__ (1024), egress_port_counter (254)]
-Table Grouping (ingress) with match table ingress_pkt (1024) [ingress_pkt__action__ (1024)]
-Table Grouping (egress) with match table egress_pkt (1024) [egress_pkt__action__ (1024)]
+Table Grouping (ingress) with match table ingress_port_count_table (1024) [ingress_port_count_table__action__ (1024), ingress_port_counter (510)]
+Table Grouping (ingress) with match table egress_port_count_table (1024) [egress_port_count_table__action__ (1024), egress_port_counter (510)]
+Table Grouping (ingress) with match table process_packet_out_table (1024) [process_packet_out_table__action__ (1024)]
Table Grouping (ingress) with match table table0 (512) [table0__action__ (512), table0_counter (512)]
Table Grouping (ingress) with match table ecmp_group_table (1024) [ecmp_group_table__action__ (1024), ecmp_group_table_counter (1024)]
Table Grouping (ingress) with condition table _condition_0 (0) []
-Table Grouping (ingress) with condition table _condition_1 (0) []
Table Grouping (ingress) with condition table _condition_2 (0) []
-Table Grouping (egress) with condition table _condition_3 (0) []
-Phase 0 possible? False Cannot implement ingress_pkt in phase 0 resources because table does not have the correct condition
+Phase 0 possible? False Cannot implement table0 in phase 0 resources because table uses side effect tables.
------------------------------------
Starting placement pass 0
------------------------------------
Nodes could place:
_condition_0 (2)
->> choose Table Grouping (ingress) with match table ingress_pkt (1024) [ingress_pkt__action__ (1024)]
-Earliest stage can place: 0
-Placing table: ingress_pkt__action__ with 1024 entries
-Table ingress_pkt__action__ with 0 entries is directly referenced
-Match Table ingress_pkt has a total of 1 entries in stage 0
- Direct mapped table ingress_pkt__action__ has 0 entries
->> set ingress_pkt (9) to placed
->> set _condition_0 (2) to placed
-
-Nodes could place:
- _condition_1 (3)
>> choose Table Grouping (ingress) with match table table0 (512) [table0__action__ (512), table0_counter (512)]
-Earliest stage can place: 1
+Earliest stage can place: 0
Placing table: table0__action__ with 512 entries
Placing table: table0_counter with 512 entries
Table table0__action__ with 8192 entries is directly referenced
Table table0_counter with 4096 entries is directly referenced
-Match Table table0 has a total of 512 entries in stage 1
+Match Table table0 has a total of 512 entries in stage 0
Direct mapped table table0__action__ has 8192 entries
Direct mapped table table0_counter has 4096 entries
>> set table0 (7) to placed
->> set _condition_1 (3) to placed
+>> set _condition_0 (2) to placed
+
+Nodes could place:
+ process_packet_out_table (3)
+ ecmp_group_table (8)
+process_packet_out_table and _condition_0 not mutually exclusive
+ >> earliest stage can place Table Grouping (ingress) with match table process_packet_out_table (1024) [process_packet_out_table__action__ (1024)] is 0
+ >> earliest stage can place Table Grouping (ingress) with match table ecmp_group_table (1024) [ecmp_group_table__action__ (1024), ecmp_group_table_counter (1024)] is 1
+process_packet_out_table and _condition_0 not mutually exclusive
+>> choose Table Grouping (ingress) with match table process_packet_out_table (1024) [process_packet_out_table__action__ (1024)]
+Earliest stage can place: 0
+process_packet_out_table and _condition_0 not mutually exclusive
+Placing table: process_packet_out_table__action__ with 1024 entries
+Table process_packet_out_table__action__ with 0 entries is directly referenced
+Match Table process_packet_out_table has a total of 1 entries in stage 0
+ Direct mapped table process_packet_out_table__action__ has 0 entries
+>> set process_packet_out_table (3) to placed
Nodes could place:
ecmp_group_table (8)
>> choose Table Grouping (ingress) with match table ecmp_group_table (1024) [ecmp_group_table__action__ (1024), ecmp_group_table_counter (1024)]
-Earliest stage can place: 2
+Earliest stage can place: 1
Placing table: ecmp_group_table__action__ with 1024 entries
Placing table: ecmp_group_table_counter with 1024 entries
Table ecmp_group_table__action__ with 0 entries is directly referenced
Table ecmp_group_table_counter with 4096 entries is directly referenced
-Match Table ecmp_group_table has a total of 3072 entries in stage 2
+Match Table ecmp_group_table has a total of 3072 entries in stage 1
Direct mapped table ecmp_group_table__action__ has 0 entries
Direct mapped table ecmp_group_table_counter has 4096 entries
>> set ecmp_group_table (8) to placed
Nodes could place:
_condition_2 (4)
->> choose Table Grouping (ingress) with match table ingress_port_count_table (1024) [ingress_port_count_table__action__ (1024), ingress_port_counter (254)]
-Earliest stage can place: 3
+>> choose Table Grouping (ingress) with match table ingress_port_count_table (1024) [ingress_port_count_table__action__ (1024), ingress_port_counter (510)]
+Earliest stage can place: 2
Placing table: ingress_port_count_table__action__ with 1024 entries
-Placing table: ingress_port_counter with 254 entries
+Placing table: ingress_port_counter with 510 entries
Table ingress_port_count_table__action__ with 0 entries is directly referenced
Table ingress_port_counter with 4096 entries is indirectly referenced
-Match Table ingress_port_count_table has a total of 1 entries in stage 3
+Match Table ingress_port_count_table has a total of 1 entries in stage 2
Direct mapped table ingress_port_count_table__action__ has 0 entries
>> set ingress_port_count_table (5) to placed
>> set _condition_2 (4) to placed
@@ -108,43 +123,27 @@
egress_port_count_table (6)
egress_port_count_table and _condition_2 not mutually exclusive
egress_port_count_table and ingress_port_count_table not mutually exclusive
->> choose Table Grouping (ingress) with match table egress_port_count_table (1024) [egress_port_count_table__action__ (1024), egress_port_counter (254)]
-Earliest stage can place: 3
+>> choose Table Grouping (ingress) with match table egress_port_count_table (1024) [egress_port_count_table__action__ (1024), egress_port_counter (510)]
+Earliest stage can place: 2
egress_port_count_table and _condition_2 not mutually exclusive
egress_port_count_table and ingress_port_count_table not mutually exclusive
Placing table: egress_port_count_table__action__ with 1024 entries
-Placing table: egress_port_counter with 254 entries
+Placing table: egress_port_counter with 510 entries
Table egress_port_count_table__action__ with 0 entries is directly referenced
Table egress_port_counter with 4096 entries is indirectly referenced
-Match Table egress_port_count_table has a total of 1 entries in stage 3
+Match Table egress_port_count_table has a total of 1 entries in stage 2
Direct mapped table egress_port_count_table__action__ has 0 entries
>> set egress_port_count_table (6) to placed
-------------------------------------
- Starting placement pass 1
-------------------------------------
-
-Nodes could place:
- _condition_3 (2)
->> choose Table Grouping (egress) with match table egress_pkt (1024) [egress_pkt__action__ (1024)]
-Earliest stage can place: 0
-Placing table: egress_pkt__action__ with 1024 entries
-Table egress_pkt__action__ with 0 entries is directly referenced
-Match Table egress_pkt has a total of 1 entries in stage 0
- Direct mapped table egress_pkt__action__ has 0 entries
->> set egress_pkt (3) to placed
->> set _condition_3 (2) to placed
------------------------------------------
Logical Table IDs
------------------------------------------
Logical Table IDs in stage 0 are:
- 0 : ingress_pkt
- 1 : egress_pkt
-Logical Table IDs in stage 1 are:
0 : table0
-Logical Table IDs in stage 2 are:
+ 1 : process_packet_out_table
+Logical Table IDs in stage 1 are:
0 : ecmp_group_table
-Logical Table IDs in stage 3 are:
+Logical Table IDs in stage 2 are:
0 : ingress_port_count_table
1 : egress_port_count_table
@@ -154,10 +153,8 @@
count_ingress -> egress_port_count_table
action mapping for egress_port_count_table
count_egress -> --END_OF_PIPELINE--
-action mapping for ingress_pkt
- _packet_out -> _condition_1
-action mapping for egress_pkt
- add_packet_in_hdr -> --END_OF_PIPELINE--
+action mapping for process_packet_out_table
+ _process_packet_out -> _condition_2
action mapping for table0
set_egress_port -> _condition_2
ecmp_group -> ecmp_group_table
@@ -166,14 +163,8 @@
action mapping for ecmp_group_table
set_egress_port -> _condition_2
true/false mapping for _condition_0
- False -> _condition_1
- True -> ingress_pkt
-true/false mapping for _condition_1
- False -> _condition_2
+ False -> process_packet_out_table
True -> table0
true/false mapping for _condition_2
False -> --END_OF_PIPELINE--
True -> ingress_port_count_table
-true/false mapping for _condition_3
- False -> --END_OF_PIPELINE--
- True -> egress_pkt
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.characterize.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.characterize.log
index d65de27..83c9670 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.characterize.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.characterize.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: pa.characterize.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
Program: ecmp
@@ -14,16 +14,16 @@
| phv1 | ingress | | SH | | | | | | | | | | | | | | | |
| [31:24] | ingress | ipv4.protocol[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [23:8] | ingress | ipv4.hdrChecksum[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [7:0] | ingress | ipv4.srcAddr[31:24] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [7:0] | ingress | ipv4.srcAddr[31:24] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv2 | ingress | | | | | | | | | | | | | | | | | |
-| [31:0] | ingress | ipv4.dstAddr[31:0] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [31:0] | ingress | ipv4.dstAddr[31:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv3 | ingress | | | | | | | | | | | | | | | | | |
-| [31:0] | ingress | ethernet.dstAddr[39:8] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [31:0] | ingress | ethernet.dstAddr[39:8] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv4 | ingress | | | | | | | | | | | | | | | | | |
-| [31:0] | ingress | ethernet.srcAddr[31:0] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [31:0] | ingress | ethernet.srcAddr[31:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv5 | ingress | | SH | | | | | | | | | | | | | | | |
-| [31:16] | ingress | udp.srcPort[15:0] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [15:0] | ingress | udp.dstPort[15:0] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [31:16] | ingress | udp.srcPort[15:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [15:0] | ingress | udp.dstPort[15:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv6 | - | | | | | | | | | | | | | | | | | |
| phv7 | - | | | | | | | | | | | | | | | | | |
| phv8 | - | | | | | | | | | | | | | | | | | |
@@ -86,25 +86,23 @@
| phv62 | - | | | | | | | | | | | | | | | | | |
| phv63 | - | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | |
-| phv64 | ingress | | SH | | | | | | | | | | | | | | | |
-| [7:1] | ingress | -pad-0-[6:0] | meta | | | | | | | | | | | | | | | |
-| [0:0] | ingress | ig_intr_md_for_tm.copy_to_cpu[0:0] | imeta | | | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv64 | ingress | | | | | | | | | | | | | | | | | |
+| [7:0] | ingress | ipv4.srcAddr[23:16] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv65 | ingress | | | | | | | | | | | | | | | | | |
-| [7:0] | ingress | ipv4.srcAddr[23:16] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [7:0] | ingress | ethernet.dstAddr[47:40] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv66 | ingress | | | | | | | | | | | | | | | | | |
-| [7:0] | ingress | ethernet.dstAddr[47:40] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv67 | ingress | | | | | | | | | | | | | | | | | |
-| [7:0] | ingress | ethernet.srcAddr[39:32] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv68 | ingress | | SH | | | | | | | | | | | | | | | |
+| [7:0] | ingress | ethernet.srcAddr[39:32] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv67 | ingress | | SH | | | | | | | | | | | | | | | |
| [6:6] | ingress | --validity_check--metadata_bridge[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [5:5] | ingress | --validity_check--udp[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [4:4] | ingress | --validity_check--tcp[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [3:3] | ingress | --validity_check--ipv4[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [2:2] | ingress | --validity_check--ethernet[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [1:1] | ingress | --validity_check--packet_out_hdr[0:0] | pov | | W | RW | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [0:0] | ingress | --validity_check--packet_in_hdr[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv69 | ingress | | | | | | | | | | | | | | | | | |
-| [7:5] | ingress | ig_intr_md_for_tm.drop_ctl[2:0] | imeta | | | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [1:1] | ingress | --validity_check--packet_out_hdr[0:0] | pov | | W | RW | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [0:0] | ingress | --validity_check--packet_in_hdr[0:0] | pov | | W | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv68 | ingress | | | | | | | | | | | | | | | | | |
+| [7:5] | ingress | ig_intr_md_for_tm.drop_ctl[2:0] | imeta | | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv69 | - | | | | | | | | | | | | | | | | | |
| phv70 | - | | | | | | | | | | | | | | | | | |
| phv71 | - | | | | | | | | | | | | | | | | | |
| phv72 | - | | | | | | | | | | | | | | | | | |
@@ -117,18 +115,16 @@
| phv79 | - | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | |
| phv80 | egress | | SH | | | | | | | | | | | | | | | |
-| [7:1] | egress | -pad-0-[6:0] | meta | | | | | | | | | | | | | | | |
-| [0:0] | egress | ig_intr_md_for_tm.copy_to_cpu[0:0] | imeta | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv81 | egress | | SH | | | | | | | | | | | | | | | |
| [7:3] | egress | eg_intr_md._pad7[4:0] | imeta | | W | | | | | | | | | | | | | |
| [2:0] | egress | eg_intr_md.egress_cos[2:0] | imeta | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv82 | egress | | SH | | | | | | | | | | | | | | | |
+| phv81 | egress | | SH | | | | | | | | | | | | | | | |
| [5:5] | egress | --validity_check--udp[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [4:4] | egress | --validity_check--tcp[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [3:3] | egress | --validity_check--ipv4[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [2:2] | egress | --validity_check--ethernet[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [1:1] | egress | --validity_check--packet_out_hdr[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [0:0] | egress | --validity_check--packet_in_hdr[0:0] | pov | | W | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [0:0] | egress | --validity_check--packet_in_hdr[0:0] | pov | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv82 | - | | | | | | | | | | | | | | | | | |
| phv83 | - | | | | | | | | | | | | | | | | | |
| phv84 | - | | | | | | | | | | | | | | | | | |
| phv85 | - | | | | | | | | | | | | | | | | | |
@@ -178,29 +174,29 @@
| phv127 | - | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | |
| phv128 | ingress | | SH | | | | | | | | | | | | | | | |
-| [15:15] | ingress | ig_intr_md.resubmit_flag[0:0] | imeta | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [14:14] | ingress | ig_intr_md._pad1[0:0] | imeta | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [13:12] | ingress | ig_intr_md._pad2[1:0] | imeta | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [11:9] | ingress | ig_intr_md._pad3[2:0] | imeta | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [8:0] | ingress | ig_intr_md.ingress_port[8:0] | imeta | | W | ~ | R | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [15:15] | ingress | ig_intr_md.resubmit_flag[0:0] | imeta | | W | | | | | | | | | | | | | |
+| [14:14] | ingress | ig_intr_md._pad1[0:0] | imeta | | W | | | | | | | | | | | | | |
+| [13:12] | ingress | ig_intr_md._pad2[1:0] | imeta | | W | | | | | | | | | | | | | |
+| [11:9] | ingress | ig_intr_md._pad3[2:0] | imeta | | W | | | | | | | | | | | | | |
+| [8:0] | ingress | ig_intr_md.ingress_port[8:0] | imeta | | W | R | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv129 | ingress | | OL,SH | | | | | | | | | | | | | | | |
| [15:7] | ingress | packet_out_hdr.egress_port[8:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [15:7] | ingress | packet_in_hdr.ingress_port[8:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [15:7] | ingress | packet_in_hdr.ingress_port[8:0] | pkt | | W | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [6:0] | ingress | packet_out_hdr._padding[6:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [6:0] | ingress | packet_in_hdr._padding[6:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv130 | ingress | | | | | | | | | | | | | | | | | |
-| [8:0] | ingress | ig_intr_md_for_tm.ucast_egress_port[8:0] | imeta | | | W | W | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [8:0] | ingress | ig_intr_md_for_tm.ucast_egress_port[8:0] | imeta | | | W | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv131 | ingress | | | | | | | | | | | | | | | | | |
-| [15:0] | ingress | ipv4.srcAddr[15:0] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [15:0] | ingress | ipv4.srcAddr[15:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv132 | ingress | | SH | | | | | | | | | | | | | | | |
-| [15:8] | ingress | ethernet.dstAddr[7:0] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [7:0] | ingress | ethernet.srcAddr[47:40] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [15:8] | ingress | ethernet.dstAddr[7:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [7:0] | ingress | ethernet.srcAddr[47:40] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv133 | ingress | | | | | | | | | | | | | | | | | |
-| [15:0] | ingress | ethernet.etherType[15:0] | pkt | | W | ~ | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [15:0] | ingress | ethernet.etherType[15:0] | pkt | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv134 | ingress | | | | | | | | | | | | | | | | | |
-| [15:0] | ingress | ecmp_metadata.groupId[15:0] | meta | | | | W | R | | | | | | | | | | |
+| [15:0] | ingress | ecmp_metadata.groupId[15:0] | meta | | | W | R | | | | | | | | | | | |
| phv135 | ingress | | | | | | | | | | | | | | | | | |
-| [15:0] | ingress | ecmp_metadata.selector[15:0] | meta | | | | W | R | | | | | | | | | | |
+| [15:0] | ingress | ecmp_metadata.selector[15:0] | meta | | | W | R | | | | | | | | | | | |
| phv136 | - | | | | | | | | | | | | | | | | | |
| phv137 | - | | | | | | | | | | | | | | | | | |
| phv138 | - | | | | | | | | | | | | | | | | | |
@@ -211,14 +207,10 @@
| phv143 | - | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | |
| phv144 | egress | | SH | | | | | | | | | | | | | | | |
-| [15:9] | egress | -pad-1-[6:0] | meta | | | | | | | | | | | | | | | |
-| [8:0] | egress | ig_intr_md.ingress_port[8:0] | imeta | | W | R | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv145 | egress | | SH | | | | | | | | | | | | | | | |
-| [15:7] | egress | packet_in_hdr.ingress_port[8:0] | pkt | | W | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [6:0] | egress | packet_in_hdr._padding[6:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv146 | egress | | SH | | | | | | | | | | | | | | | |
| [15:9] | egress | eg_intr_md._pad0[6:0] | imeta | | W | | | | | | | | | | | | | |
| [8:0] | egress | eg_intr_md.egress_port[8:0] | imeta | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv145 | - | | | | | | | | | | | | | | | | | |
+| phv146 | - | | | | | | | | | | | | | | | | | |
| phv147 | - | | | | | | | | | | | | | | | | | |
| phv148 | - | | | | | | | | | | | | | | | | | |
| phv149 | - | | | | | | | | | | | | | | | | | |
@@ -306,46 +298,45 @@
| [23:21] | ingress | ipv4.flags[2:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [20:8] | ingress | ipv4.fragOffset[12:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [7:0] | ingress | ipv4.ttl[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv257 | ingress | | | | | | | | | | | | | | | | | |
-| [31:0] | ingress | tcp.ackNo[31:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv258 | ingress | | SH | | | | | | | | | | | | | | | |
+| phv257 | ingress | | SH | | | | | | | | | | | | | | | |
| [31:28] | ingress | tcp.dataOffset[3:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [27:25] | ingress | tcp.res[2:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [24:22] | ingress | tcp.ecn[2:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [21:16] | ingress | tcp.ctrl[5:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | ingress | tcp.window[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv259 | ingress | | SH | | | | | | | | | | | | | | | |
+| phv258 | ingress | | SH | | | | | | | | | | | | | | | |
| [31:16] | ingress | tcp.checksum[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | ingress | tcp.urgentPtr[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv260 | egress | | SH | | | | | | | | | | | | | | | |
+| phv259 | - | | | | | | | | | | | | | | | | | |
+| phv260 | - | | | | | | | | | | | | | | | | | |
+| phv261 | - | | | | | | | | | | | | | | | | | |
+| phv262 | - | | | | | | | | | | | | | | | | | |
+| phv263 | - | | | | | | | | | | | | | | | | | |
+| phv264 | egress | | SH | | | | | | | | | | | | | | | |
| [31:24] | egress | ipv4.ttl[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [23:16] | egress | ipv4.protocol[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | egress | ipv4.hdrChecksum[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv261 | egress | | | | | | | | | | | | | | | | | |
+| phv265 | egress | | | | | | | | | | | | | | | | | |
| [31:0] | egress | ipv4.srcAddr[31:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv262 | egress | | | | | | | | | | | | | | | | | |
+| phv266 | egress | | | | | | | | | | | | | | | | | |
| [31:0] | egress | ipv4.dstAddr[31:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv263 | egress | | OL,SH | | | | | | | | | | | | | | | |
+| phv267 | egress | | OL,SH | | | | | | | | | | | | | | | |
| [31:16] | egress | udp.length_[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [31:0] | egress | tcp.ackNo[31:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | egress | udp.checksum[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv264 | egress | | SH | | | | | | | | | | | | | | | |
+| phv268 | egress | | SH | | | | | | | | | | | | | | | |
| [31:28] | egress | tcp.dataOffset[3:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [27:25] | egress | tcp.res[2:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [24:22] | egress | tcp.ecn[2:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [21:16] | egress | tcp.ctrl[5:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | egress | tcp.window[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv265 | egress | | SH | | | | | | | | | | | | | | | |
+| phv269 | egress | | SH | | | | | | | | | | | | | | | |
| [31:16] | egress | tcp.checksum[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | egress | tcp.urgentPtr[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv266 | egress | | | | | | | | | | | | | | | | | |
+| phv270 | egress | | | | | | | | | | | | | | | | | |
| [31:0] | egress | ethernet.dstAddr[39:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv267 | egress | | | | | | | | | | | | | | | | | |
+| phv271 | egress | | | | | | | | | | | | | | | | | |
| [31:0] | egress | ethernet.srcAddr[31:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv268 | - | | | | | | | | | | | | | | | | | |
-| phv269 | - | | | | | | | | | | | | | | | | | |
-| phv270 | - | | | | | | | | | | | | | | | | | |
-| phv271 | - | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | |
| phv272 | - | | | | | | | | | | | | | | | | | |
| phv273 | - | | | | | | | | | | | | | | | | | |
@@ -373,26 +364,28 @@
| phv290 | ingress | | OL,SH | | | | | | | | | | | | | | | |
| [7:0] | ingress | tcp.srcPort[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [7:0] | ingress | udp.length_[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv291 | - | | | | | | | | | | | | | | | | | |
-| phv292 | egress | | SH | | | | | | | | | | | | | | | |
+| phv291 | ingress | | | | | | | | | | | | | | | | | |
+| [7:0] | ingress | tcp.dstPort[15:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv292 | ingress | | | | | | | | | | | | | | | | | |
+| [7:0] | ingress | tcp.dstPort[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv293 | - | | | | | | | | | | | | | | | | | |
+| phv294 | - | | | | | | | | | | | | | | | | | |
+| phv295 | - | | | | | | | | | | | | | | | | | |
+| phv296 | egress | | SH | | | | | | | | | | | | | | | |
| [7:4] | egress | ipv4.version[3:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [3:0] | egress | ipv4.ihl[3:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv293 | egress | | | | | | | | | | | | | | | | | |
+| phv297 | egress | | | | | | | | | | | | | | | | | |
| [7:0] | egress | ipv4.diffserv[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv294 | egress | | OL,SH | | | | | | | | | | | | | | | |
+| phv298 | egress | | OL,SH | | | | | | | | | | | | | | | |
| [7:0] | egress | tcp.srcPort[15:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [7:0] | egress | udp.srcPort[15:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv295 | egress | | OL,SH | | | | | | | | | | | | | | | |
+| phv299 | egress | | OL,SH | | | | | | | | | | | | | | | |
| [7:0] | egress | tcp.srcPort[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [7:0] | egress | udp.srcPort[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv296 | egress | | | | | | | | | | | | | | | | | |
+| phv300 | egress | | | | | | | | | | | | | | | | | |
| [7:0] | egress | ethernet.dstAddr[47:40] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv297 | egress | | | | | | | | | | | | | | | | | |
+| phv301 | egress | | | | | | | | | | | | | | | | | |
| [7:0] | egress | ethernet.srcAddr[39:32] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv298 | - | | | | | | | | | | | | | | | | | |
-| phv299 | - | | | | | | | | | | | | | | | | | |
-| phv300 | - | | | | | | | | | | | | | | | | | |
-| phv301 | - | | | | | | | | | | | | | | | | | |
| phv302 | - | | | | | | | | | | | | | | | | | |
| phv303 | - | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | |
@@ -420,42 +413,45 @@
| [15:8] | ingress | ipv4.totalLen[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [7:0] | ingress | ipv4.identification[15:8] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv322 | ingress | | OL,SH | | | | | | | | | | | | | | | |
-| [15:0] | ingress | tcp.dstPort[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [15:0] | ingress | tcp.seqNo[31:16] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [15:0] | ingress | udp.checksum[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv323 | ingress | | | | | | | | | | | | | | | | | |
-| [15:0] | ingress | tcp.seqNo[31:16] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv324 | ingress | | | | | | | | | | | | | | | | | |
| [15:0] | ingress | tcp.seqNo[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv325 | - | | | | | | | | | | | | | | | | | |
-| phv326 | egress | | | | | | | | | | | | | | | | | |
+| phv324 | ingress | | | | | | | | | | | | | | | | | |
+| [15:0] | ingress | tcp.ackNo[31:16] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv325 | ingress | | | | | | | | | | | | | | | | | |
+| [15:0] | ingress | tcp.ackNo[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv326 | - | | | | | | | | | | | | | | | | | |
+| phv327 | - | | | | | | | | | | | | | | | | | |
+| phv328 | - | | | | | | | | | | | | | | | | | |
+| phv329 | - | | | | | | | | | | | | | | | | | |
+| phv330 | - | | | | | | | | | | | | | | | | | |
+| phv331 | - | | | | | | | | | | | | | | | | | |
+| phv332 | egress | | | | | | | | | | | | | | | | | |
| [15:0] | egress | ipv4.totalLen[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv327 | egress | | | | | | | | | | | | | | | | | |
+| phv333 | egress | | | | | | | | | | | | | | | | | |
| [15:0] | egress | ipv4.identification[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv328 | egress | | SH | | | | | | | | | | | | | | | |
+| phv334 | egress | | SH | | | | | | | | | | | | | | | |
| [15:13] | egress | ipv4.flags[2:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [12:0] | egress | ipv4.fragOffset[12:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv329 | egress | | OL,SH | | | | | | | | | | | | | | | |
+| phv335 | egress | | | | | | | | | | | | | | | | | |
| [15:0] | egress | tcp.dstPort[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| [15:0] | egress | udp.dstPort[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv330 | egress | | | | | | | | | | | | | | | | | |
+| | | | | | | | | | | | | | | | | | | |
+| phv336 | egress | | OL,SH | | | | | | | | | | | | | | | |
| [15:0] | egress | tcp.seqNo[31:16] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv331 | egress | | | | | | | | | | | | | | | | | |
+| [15:0] | egress | udp.dstPort[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| phv337 | egress | | | | | | | | | | | | | | | | | |
| [15:0] | egress | tcp.seqNo[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv332 | egress | | SH | | | | | | | | | | | | | | | |
+| phv338 | egress | | SH | | | | | | | | | | | | | | | |
| [15:8] | egress | ethernet.dstAddr[7:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [7:0] | egress | ethernet.srcAddr[47:40] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv333 | egress | | | | | | | | | | | | | | | | | |
+| phv339 | egress | | | | | | | | | | | | | | | | | |
| [15:0] | egress | ethernet.etherType[15:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv334 | egress | | SH | | | | | | | | | | | | | | | |
+| phv340 | egress | | OL,SH | | | | | | | | | | | | | | | |
| [15:7] | egress | packet_out_hdr.egress_port[8:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
+| [15:7] | egress | packet_in_hdr.ingress_port[8:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| [6:0] | egress | packet_out_hdr._padding[6:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
-| phv335 | - | | | | | | | | | | | | | | | | | |
-| | | | | | | | | | | | | | | | | | | |
-| phv336 | - | | | | | | | | | | | | | | | | | |
-| phv337 | - | | | | | | | | | | | | | | | | | |
-| phv338 | - | | | | | | | | | | | | | | | | | |
-| phv339 | - | | | | | | | | | | | | | | | | | |
-| phv340 | - | | | | | | | | | | | | | | | | | |
+| [6:0] | egress | packet_in_hdr._padding[6:0] | pkt | | W | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | ~ | R |
| phv341 | - | | | | | | | | | | | | | | | | | |
| phv342 | - | | | | | | | | | | | | | | | | | |
| phv343 | - | | | | | | | | | | | | | | | | | |
@@ -487,9 +483,9 @@
-----------------------------------------------------------------------------------------------------------------------------------------
-Containers used: 61
-Containers with data overlayed: 8 (13.11%)
-Containers shared: 33 (54.10%)
+Containers used: 59
+Containers with data overlayed: 9 (15.25%)
+Containers shared: 29 (49.15%)
------------------------
Legend:
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.constraints.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.constraints.log
index 5bb8103..f408f0a 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.constraints.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.constraints.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: pa.constraints.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
To populate this log file, include --print-pa-constraints as a compiler argument.
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.liveness.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.liveness.log
index 4ba6eee..9699d1b 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.liveness.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.liveness.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: pa.liveness.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.log
index b6941b9..7aecfb6 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: pa.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
HLIR Version: 0.10.5
@@ -60,7 +60,7 @@
-----------------------------------------------
-----------------------------------------------
- Eliminating unused metadata (99 instances)
+ Eliminating unused metadata (100 instances)
-----------------------------------------------
Removing standard_metadata.ingress_port in ingress
Removing standard_metadata.packet_length in ingress
@@ -80,6 +80,7 @@
Removing ig_intr_md_for_tm.qid in ingress
Removing ig_intr_md_for_tm.icos_for_copy_to_cpu in ingress
Removing ig_intr_md_for_tm._pad2 in ingress
+Removing ig_intr_md_for_tm.copy_to_cpu in ingress
Removing ig_intr_md_for_tm.packet_color in ingress
Removing ig_intr_md_for_tm.disable_ucast_cutthru in ingress
Removing ig_intr_md_for_tm.enable_mcast_cutthru in ingress
@@ -175,10 +176,10 @@
--------------------------------------------
ingress field instance bit width histogram
--------------------------------------------
- Total fields: 51
+ Total fields: 50
Max value: 15
- 1 : xxxxxxxxxx (10)
+ 1 : xxxxxxxxx (9)
2 : x (1)
3 : xxxxx (5)
4 : xxx (3)
@@ -194,17 +195,17 @@
--------------------------------------------
egress field instance bit width histogram
--------------------------------------------
- Total fields: 46
+ Total fields: 44
Max value: 13
- 1 : xxxxxxx (7)
+ 1 : xxxxxx (6)
3 : xxxx (4)
4 : xxx (3)
5 : x (1)
6 : x (1)
7 : xxx (3)
8 : xxx (3)
- 9 : xxxx (4)
+ 9 : xxx (3)
13 : x (1)
16 : xxxxxxxxxxxxx (13)
32 : xxxx (4)
@@ -266,7 +267,7 @@
-----------------------------------------------
-----------------------------------------------
- Eliminating unused metadata (99 instances)
+ Eliminating unused metadata (100 instances)
-----------------------------------------------
Removing standard_metadata.ingress_port in ingress
Removing standard_metadata.packet_length in ingress
@@ -286,6 +287,7 @@
Removing ig_intr_md_for_tm.qid in ingress
Removing ig_intr_md_for_tm.icos_for_copy_to_cpu in ingress
Removing ig_intr_md_for_tm._pad2 in ingress
+Removing ig_intr_md_for_tm.copy_to_cpu in ingress
Removing ig_intr_md_for_tm.packet_color in ingress
Removing ig_intr_md_for_tm.disable_ucast_cutthru in ingress
Removing ig_intr_md_for_tm.enable_mcast_cutthru in ingress
@@ -381,10 +383,10 @@
--------------------------------------------
ingress field instance bit width histogram
--------------------------------------------
- Total fields: 51
+ Total fields: 50
Max value: 15
- 1 : xxxxxxxxxx (10)
+ 1 : xxxxxxxxx (9)
2 : x (1)
3 : xxxxx (5)
4 : xxx (3)
@@ -400,17 +402,17 @@
--------------------------------------------
egress field instance bit width histogram
--------------------------------------------
- Total fields: 46
+ Total fields: 44
Max value: 13
- 1 : xxxxxxx (7)
+ 1 : xxxxxx (6)
3 : xxxx (4)
4 : xxx (3)
5 : x (1)
6 : x (1)
7 : xxx (3)
8 : xxx (3)
- 9 : xxxx (4)
+ 9 : xxx (3)
13 : x (1)
16 : xxxxxxxxxxxxx (13)
32 : xxxx (4)
@@ -421,7 +423,7 @@
---------------------------------------------------------------------------------------------------------------------------------
| --validity_check--ethernet | 1 | egress | x | x | | | |
| --validity_check--ipv4 | 1 | egress | x | x | | | |
-| --validity_check--packet_in_hdr | 1 | egress | x | x | | | x |
+| --validity_check--packet_in_hdr | 1 | egress | x | x | | | |
| --validity_check--packet_out_hdr | 1 | egress | x | x | | | |
| --validity_check--tcp | 1 | egress | x | x | | | |
| --validity_check--udp | 1 | egress | x | x | | | |
@@ -432,8 +434,6 @@
| ethernet.dstAddr | 48 | egress | x | x | | | |
| ethernet.etherType | 16 | egress | x | x | | | |
| ethernet.srcAddr | 48 | egress | x | x | | | |
-| ig_intr_md.ingress_port | 9 | egress | x | | x | x | |
-| ig_intr_md_for_tm.copy_to_cpu | 1 | egress | x | | x | x | |
| ipv4.diffserv | 8 | egress | x | x | | | |
| ipv4.dstAddr | 32 | egress | x | x | | | |
| ipv4.flags | 3 | egress | x | x | | | |
@@ -447,7 +447,7 @@
| ipv4.ttl | 8 | egress | x | x | | | |
| ipv4.version | 4 | egress | x | x | | | |
| packet_in_hdr._padding | 7 | egress | x | x | | | |
-| packet_in_hdr.ingress_port | 9 | egress | x | x | | | x |
+| packet_in_hdr.ingress_port | 9 | egress | x | x | | | |
| packet_out_hdr._padding | 7 | egress | x | x | | | |
| packet_out_hdr.egress_port | 9 | egress | x | x | | | |
| tcp.ackNo | 32 | egress | x | x | | | |
@@ -468,7 +468,7 @@
| --validity_check--ethernet | 1 | ingress | x | x | | | |
| --validity_check--ipv4 | 1 | ingress | x | x | | | |
| --validity_check--metadata_bridge | 1 | ingress | x | x | | | |
-| --validity_check--packet_in_hdr | 1 | ingress | x | x | | | |
+| --validity_check--packet_in_hdr | 1 | ingress | x | x | | | x |
| --validity_check--packet_out_hdr | 1 | ingress | x | x | | x | x |
| --validity_check--tcp | 1 | ingress | x | x | | | |
| --validity_check--udp | 1 | ingress | x | x | | | |
@@ -482,7 +482,6 @@
| ig_intr_md._pad3 | 3 | ingress | x | | x | | |
| ig_intr_md.ingress_port | 9 | ingress | x | x | x | x | |
| ig_intr_md.resubmit_flag | 1 | ingress | x | | x | | |
-| ig_intr_md_for_tm.copy_to_cpu | 1 | ingress | | x | x | | x |
| ig_intr_md_for_tm.drop_ctl | 3 | ingress | | x | x | | x |
| ig_intr_md_for_tm.ucast_egress_port | 9 | ingress | | x | x | x | x |
| ipv4.diffserv | 8 | ingress | x | x | | | |
@@ -498,7 +497,7 @@
| ipv4.ttl | 8 | ingress | x | x | | | |
| ipv4.version | 4 | ingress | x | x | | | |
| packet_in_hdr._padding | 7 | ingress | x | x | | | |
-| packet_in_hdr.ingress_port | 9 | ingress | x | x | | | |
+| packet_in_hdr.ingress_port | 9 | ingress | x | x | | | x |
| packet_out_hdr._padding | 7 | ingress | x | x | | | |
| packet_out_hdr.egress_port | 9 | ingress | x | x | | x | |
| tcp.ackNo | 32 | ingress | x | x | | | |
@@ -554,19 +553,19 @@
parse_pkt_in and parse_pkt_out are exclusive parse states
parse_tcp and parse_udp are exclusive parse states
->>Event 'pa_init' at time 1504795731.64
+>>Event 'pa_init' at time 1504859117.63
Took 0.01 seconds
--------------------------------------------
-PHV MAU Groups: 95
+PHV MAU Groups: 92
--------------------------------------------
Phv Mau Group (ingress) -- 2 instances for total bit width of 18.
+ ig_intr_md.ingress_port <9 bits ingress parsed imeta R>
+ packet_in_hdr.ingress_port <9 bits ingress parsed W>
+
+Phv Mau Group (ingress) -- 2 instances for total bit width of 18.
ig_intr_md_for_tm.ucast_egress_port <9 bits ingress imeta R W>
packet_out_hdr.egress_port <9 bits ingress parsed R>
-Phv Mau Group (egress) -- 2 instances for total bit width of 18.
- packet_in_hdr.ingress_port <9 bits egress parsed W>
- ig_intr_md.ingress_port <9 bits egress parsed imeta R>
-
Phv Mau Group (ingress) -- 1 instance for total bit width of 1.
ig_intr_md.resubmit_flag <1 bits ingress parsed imeta>
@@ -579,20 +578,11 @@
Phv Mau Group (ingress) -- 1 instance for total bit width of 3.
ig_intr_md._pad3 <3 bits ingress parsed imeta>
-Phv Mau Group (ingress) -- 1 instance for total bit width of 9.
- ig_intr_md.ingress_port <9 bits ingress parsed imeta R>
-
Phv Mau Group (ingress) -- 1 instance for total bit width of 3.
ig_intr_md_for_tm.drop_ctl <3 bits ingress imeta W>
Phv Mau Group (ingress) -- 1 instance for total bit width of 1.
- ig_intr_md_for_tm.copy_to_cpu <1 bits ingress imeta W>
-
-Phv Mau Group (ingress) -- 1 instance for total bit width of 9.
- packet_in_hdr.ingress_port <9 bits ingress parsed tagalong>
-
-Phv Mau Group (ingress) -- 1 instance for total bit width of 1.
- --validity_check--packet_in_hdr <1 bits ingress parsed pov>
+ --validity_check--packet_in_hdr <1 bits ingress parsed pov W>
Phv Mau Group (ingress) -- 1 instance for total bit width of 7.
packet_in_hdr._padding <7 bits ingress parsed tagalong>
@@ -714,8 +704,11 @@
Phv Mau Group (ingress) -- 1 instance for total bit width of 1.
--validity_check--metadata_bridge <1 bits ingress parsed pov>
+Phv Mau Group (egress) -- 1 instance for total bit width of 9.
+ packet_in_hdr.ingress_port <9 bits egress parsed tagalong>
+
Phv Mau Group (egress) -- 1 instance for total bit width of 1.
- --validity_check--packet_in_hdr <1 bits egress parsed pov W>
+ --validity_check--packet_in_hdr <1 bits egress parsed pov>
Phv Mau Group (egress) -- 1 instance for total bit width of 7.
packet_in_hdr._padding <7 bits egress parsed tagalong>
@@ -831,9 +824,6 @@
Phv Mau Group (egress) -- 1 instance for total bit width of 16.
udp.checksum <16 bits egress parsed tagalong>
-Phv Mau Group (egress) -- 1 instance for total bit width of 1.
- ig_intr_md_for_tm.copy_to_cpu <1 bits egress parsed imeta R>
-
Phv Mau Group (egress) -- 1 instance for total bit width of 7.
eg_intr_md._pad0 <7 bits egress parsed imeta>
@@ -847,7 +837,7 @@
eg_intr_md.egress_cos <3 bits egress parsed imeta>
->>Event 'pa_resv' at time 1504795731.64
+>>Event 'pa_resv' at time 1504859117.63
Took 0.00 seconds
-----------------------------------------------
@@ -889,239 +879,14 @@
Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
Reserving 32-bit container for ingress: phv0
->>Event 'pa_bridge' at time 1504795731.68
+>>Event 'pa_bridge' at time 1504859117.67
Took 0.04 seconds
-----------------------------------------------
Allocating fields related to bridged metadata
-----------------------------------------------
Allocation Step
- ig_intr_md.ingress_port <9 bits ingress parsed imeta R> and ig_intr_md.ingress_port <9 bits egress parsed imeta R>
- ig_intr_md_for_tm.copy_to_cpu <1 bits ingress imeta W> and ig_intr_md_for_tm.copy_to_cpu <1 bits egress parsed imeta R>
-
-
-Allowed alignment for fields:
- ig_intr_md.ingress_port -> [0, 8, 16, 24]
- ig_intr_md_for_tm.copy_to_cpu -> [0, 1, 2, 3, 4, 5, 6, 7]
-
-Required packing for bridged metadata: 1
- ig_intr_md.ingress_port (ingress)
- phv[15:15] = ig_intr_md.resubmit_flag[0:0]
- phv[14:14] = ig_intr_md._pad1[0:0]
- phv[13:12] = ig_intr_md._pad2[1:0]
- phv[11:9] = ig_intr_md._pad3[2:0]
- phv[8:0] = ig_intr_md.ingress_port[8:0]
-ig_intr_md_for_tm.copy_to_cpu cannot share with any fields: total bits 1
-
-
-All combinations = 1
-Valid combinations = 1
-Choosing to pack non-byte multiple metadata as below, which wastes 0 bits
-
-Sharing capabilities of groups: (2)
-Group ['ig_intr_md.resubmit_flag', 'ig_intr_md._pad1', 'ig_intr_md._pad2', 'ig_intr_md._pad3', 'ig_intr_md.ingress_port'] can share with 0 other groups:
-Group ['ig_intr_md_for_tm.copy_to_cpu'] can share with 0 other groups:
-
-Merged sharing capabilities of groups: (2)
-Group ['ig_intr_md.resubmit_flag', 'ig_intr_md._pad1', 'ig_intr_md._pad2', 'ig_intr_md._pad3', 'ig_intr_md.ingress_port'] can share with 0 other groups (16 bits):
-Group ['ig_intr_md_for_tm.copy_to_cpu'] can share with 0 other groups (1 bits):
-
-Final group packing:
-Group 0:
- ['ig_intr_md_for_tm.copy_to_cpu']
-Group 1:
- ['ig_intr_md.resubmit_flag', 'ig_intr_md._pad1', 'ig_intr_md._pad2', 'ig_intr_md._pad3', 'ig_intr_md.ingress_port']
-Preferred packing is [8, 16]
-
-Final ingress bridged metadata packing: 24 bits (3 bytes)
- -pad-0- / 7 bits
- ig_intr_md_for_tm.copy_to_cpu / 1 bits
- ig_intr_md.resubmit_flag / 1 bits
- ig_intr_md._pad1 / 1 bits
- ig_intr_md._pad2 / 2 bits
- ig_intr_md._pad3 / 3 bits
- ig_intr_md.ingress_port / 9 bits
-
-Final egress bridged metadata packing: 24 bits (3 bytes)
- -pad-0- / 7 bits
- ig_intr_md_for_tm.copy_to_cpu / 1 bits
- -pad-1- / 7 bits
- ig_intr_md.ingress_port / 9 bits
-
--------------------------------------------
-Allocating parsed header: pkt fields (7) / meta fields (0) using extraction bandwidth 224
--------------------------------------------
-Extracted bits: 24
-Set metadata bits: 0
-Gress: ingress
-bits_will_need_to_parse = 24
-unused_metadata_container_bits = 0
-min_parse_states = 1
-bits_per_state = 24
-Parse state 0 (24 bits)
- -pad-0- [6:0]
- ig_intr_md_for_tm.copy_to_cpu [0:0]
- ig_intr_md.resubmit_flag [0:0]
- ig_intr_md._pad1 [0:0]
- ig_intr_md._pad2 [1:0]
- ig_intr_md._pad3 [2:0]
- ig_intr_md.ingress_port [8:0]
-----------------------------------------------------------------------------------------------------
-| Name | BW | Tagalong? | Req | Pref | Not Allow | MaxSplit | Group Size |
-----------------------------------------------------------------------------------------------------
-| -pad-0- | 7 | True | - | - | - | None | 1 |
-| ig_intr_md_for_tm.copy_to_cpu | 1 | False | - | - | - | 1 | 1 |
-| ig_intr_md.resubmit_flag | 1 | False | - | - | - | 1 | 1 |
-| ig_intr_md._pad1 | 1 | False | - | - | - | 1 | 1 |
-| ig_intr_md._pad2 | 2 | False | - | - | - | 1 | 1 |
-| ig_intr_md._pad3 | 3 | False | - | - | - | 1 | 1 |
-| ig_intr_md.ingress_port | 9 | False | - | - | - | 2 | 1 |
-----------------------------------------------------------------------------------------------------
-
-Packing options: 5
-MAU containers available:
- 8-bit: 48
- 16-bit: 80
- 32-bit: 47
-Tagalong containers available:
- 8-bit: 32
- 16-bit: 48
- 32-bit: 32
-Initial packing options: 5
-
-Packing option 0: [8, 16]
-MAU containers after:
- 8-bit: 47
- 16-bit: 79
- 32-bit: 47
-+----------------------------------------+
-| -pad-0- [6:0] |
-| ig_intr_md_for_tm.copy_to_cpu [0:0] |
-+----------------------------------------+
-| ig_intr_md.resubmit_flag [0:0] |
-| ig_intr_md._pad1 [0:0] |
-| ig_intr_md._pad2 [1:0] |
-| ig_intr_md._pad3 [2:0] |
-| ig_intr_md.ingress_port [8:0] |
-+----------------------------------------+
-
-Looking at -pad-0- (ingress) [6:0], with test_alloc = False
-Looking at ig_intr_md_for_tm.copy_to_cpu (ingress) [0:0], with test_alloc = True
-----> ig_intr_md_for_tm.copy_to_cpu (ingress) is allocated? False
-Checking if can overlay metadata field.
-No required PHV group.
-Could not find container to overlay in.
-
-MAU groups: 3
- Group 4 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv64
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-***Allocating phv64[7:1] for -pad-0-[6:0]
-***Allocating phv64[0:0] for ig_intr_md_for_tm.copy_to_cpu[0:0]
-Looking at ig_intr_md.resubmit_flag (ingress) [0:0], with test_alloc = True
-----> ig_intr_md.resubmit_flag (ingress) is allocated? False
-Looking at ig_intr_md._pad1 (ingress) [0:0], with test_alloc = True
-Looking at ig_intr_md._pad2 (ingress) [1:0], with test_alloc = True
-Looking at ig_intr_md._pad3 (ingress) [2:0], with test_alloc = True
-Looking at ig_intr_md.ingress_port (ingress) [8:0], with test_alloc = True
-Checking if can overlay metadata field.
-No required PHV group.
-Could not find container to overlay in.
-
-MAU groups: 5
- Group 8 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv128
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
-***Allocating phv128[15:15] for ig_intr_md.resubmit_flag[0:0]
-***Allocating phv128[14:14] for ig_intr_md._pad1[0:0]
-***Allocating phv128[13:12] for ig_intr_md._pad2[1:0]
-***Allocating phv128[11:9] for ig_intr_md._pad3[2:0]
-***Allocating phv128[8:0] for ig_intr_md.ingress_port[8:0]
-Packing options tried: 1
-Packing options skipped: 0
-
-
--------------------------------------------
-Allocating parsed header: pkt fields (4) / meta fields (0) using extraction bandwidth 224
--------------------------------------------
-Extracted bits: 24
-Set metadata bits: 0
-Gress: egress
-bits_will_need_to_parse = 24
-unused_metadata_container_bits = 0
-min_parse_states = 1
-bits_per_state = 24
-Parse state 0 (24 bits)
- -pad-0- [6:0]
- ig_intr_md_for_tm.copy_to_cpu [0:0]
- -pad-1- [6:0]
- ig_intr_md.ingress_port [8:0]
-----------------------------------------------------------------------------------------------------
-| Name | BW | Tagalong? | Req | Pref | Not Allow | MaxSplit | Group Size |
-----------------------------------------------------------------------------------------------------
-| -pad-0- | 7 | True | - | - | - | None | 1 |
-| ig_intr_md_for_tm.copy_to_cpu | 1 | False | - | - | - | None | 1 |
-| -pad-1- | 7 | True | - | - | - | None | 1 |
-| ig_intr_md.ingress_port | 9 | False | - | - | [32] | None | 2 |
-----------------------------------------------------------------------------------------------------
-
-Packing options: 5
-MAU containers available:
- 8-bit: 48
- 16-bit: 80
- 32-bit: 48
-Tagalong containers available:
- 8-bit: 32
- 16-bit: 48
- 32-bit: 32
-Initial packing options: 5
-
-Packing option 0: [8, 16]
-MAU containers after:
- 8-bit: 47
- 16-bit: 78
- 32-bit: 48
-+----------------------------------------+
-| -pad-0- [6:0] |
-| ig_intr_md_for_tm.copy_to_cpu [0:0] |
-+----------------------------------------+
-| -pad-1- [6:0] |
-| ig_intr_md.ingress_port [8:0] |
-+----------------------------------------+
-
-Looking at -pad-0- (egress) [6:0], with test_alloc = False
-Looking at ig_intr_md_for_tm.copy_to_cpu (egress) [0:0], with test_alloc = True
-----> ig_intr_md_for_tm.copy_to_cpu (egress) is allocated? False
-Checking if can overlay metadata field.
-No required PHV group.
-Could not find container to overlay in.
-
-MAU groups: 3
- Group 5 8 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 15 and promised 1 and req 1 -- as if deparsed True -- container_to_use phv80
- Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 15 and promised 1 and req 1 -- as if deparsed True -- container_to_use phv96
- Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 15 and promised 1 and req 1 -- as if deparsed True -- container_to_use phv112
-***Allocating phv80[7:1] for -pad-0-[6:0]
-***Allocating phv80[0:0] for ig_intr_md_for_tm.copy_to_cpu[0:0]
-Looking at -pad-1- (egress) [6:0], with test_alloc = False
-Looking at ig_intr_md.ingress_port (egress) [8:0], with test_alloc = True
-----> ig_intr_md.ingress_port (egress) is allocated? False
-Checking if can overlay metadata field.
-No required PHV group.
-Could not find container to overlay in.
-
-MAU groups: 5
- Group 9 16 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 14 and promised 2 and req 2 -- as if deparsed True -- container_to_use phv144
- Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 14 and promised 2 and req 2 -- as if deparsed True -- container_to_use phv160
- Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 14 and promised 2 and req 2 -- as if deparsed True -- container_to_use phv176
- Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 14 and promised 2 and req 2 -- as if deparsed True -- container_to_use phv192
- Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 14 and promised 2 and req 2 -- as if deparsed True -- container_to_use phv208
-***Allocating phv144[15:9] for -pad-1-[6:0]
-***Allocating phv144[8:0] for ig_intr_md.ingress_port[8:0]
-Packing options tried: 1
-Packing options skipped: 0
-
+ No bridged metadata field instances required
After allocating bridged metadata:
Allocation state: Final Allocation
@@ -1135,19 +900,19 @@
| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
| Total for 32 bit | 1 (1.56%) | 32 (1.56%) | 2048 |
| | | | |
-| 4 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
-| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
+| 4 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| 5 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 2 (3.12%) | 16 (3.12%) | 512 |
+| Total for 8 bit | 0 (0.00%) | 0 (0.00%) | 512 |
| | | | |
-| 8 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
-| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
+| 8 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 9 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 2 (2.08%) | 32 (2.08%) | 1536 |
+| Total for 16 bit | 0 (0.00%) | 0 (0.00%) | 1536 |
| | | | |
| 14 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
@@ -1162,13 +927,13 @@
| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
| Total for 16 bit | 0 (0.00%) | 0 (0.00%) | 768 |
| | | | |
-| MAU total | 5 (2.23%) | 80 (1.95%) | 4096 |
+| MAU total | 1 (0.45%) | 32 (0.78%) | 4096 |
| Tagalong total | 0 (0.00%) | 0 (0.00%) | 2048 |
-| Overall total | 5 (1.49%) | 80 (1.30%) | 6144 |
+| Overall total | 1 (0.30%) | 32 (0.52%) | 6144 |
---------------------------------------------------------------------------
->>Event 'pa_phase0' at time 1504795732.08
- Took 0.40 seconds
+>>Event 'pa_phase0' at time 1504859117.67
+ Took 0.00 seconds
-----------------------------------------------
Allocating Phase 0-related metadata
@@ -1188,19 +953,19 @@
| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
| Total for 32 bit | 1 (1.56%) | 32 (1.56%) | 2048 |
| | | | |
-| 4 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
-| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
+| 4 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| 5 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 2 (3.12%) | 16 (3.12%) | 512 |
+| Total for 8 bit | 0 (0.00%) | 0 (0.00%) | 512 |
| | | | |
-| 8 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
-| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
+| 8 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 9 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 2 (2.08%) | 32 (2.08%) | 1536 |
+| Total for 16 bit | 0 (0.00%) | 0 (0.00%) | 1536 |
| | | | |
| 14 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
@@ -1215,12 +980,12 @@
| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
| Total for 16 bit | 0 (0.00%) | 0 (0.00%) | 768 |
| | | | |
-| MAU total | 5 (2.23%) | 80 (1.95%) | 4096 |
+| MAU total | 1 (0.45%) | 32 (0.78%) | 4096 |
| Tagalong total | 0 (0.00%) | 0 (0.00%) | 2048 |
-| Overall total | 5 (1.49%) | 80 (1.30%) | 6144 |
+| Overall total | 1 (0.30%) | 32 (0.52%) | 6144 |
---------------------------------------------------------------------------
->>Event 'pa_critical' at time 1504795732.09
+>>Event 'pa_critical' at time 1504859117.68
Took 0.00 seconds
-----------------------------------------------
@@ -1229,6 +994,7 @@
Allocation Step
All Sorted parse nodes:
+ ingress_intrinsic_metadata (ingress) with bits = 16 and max = 2
parse_pkt_out (ingress) with bits = 16 and max = 2
parse_ipv4 (ingress) with bits = 160 and max = 1
parse_tcp (ingress) with bits = 160 and max = 1
@@ -1237,7 +1003,6 @@
parse_ethernet (ingress) with bits = 112 and max = 1
parse_ethernet (egress) with bits = 112 and max = 1
egress_intrinsic_metadata (egress) with bits = 24 and max = 1
- ingress_intrinsic_metadata (ingress) with bits = 16 and max = 1
parse_pkt_out (egress) with bits = 16 and max = 1
start () with bits = 0 and max = 0
default_parser () with bits = 0 and max = 0
@@ -1249,6 +1014,85 @@
Total packet bits: 936
Total meta bits: 0
Total bits: 936
+Working on parse node ingress_intrinsic_metadata (9) (ingress)
+
+-------------------------------------------
+Allocating parsed header: pkt fields (5) / meta fields (0) using extraction bandwidth 224
+-------------------------------------------
+Extracted bits: 16
+Set metadata bits: 0
+Gress: ingress
+bits_will_need_to_parse = 16
+unused_metadata_container_bits = 0
+min_parse_states = 1
+bits_per_state = 16
+Parse state 0 (16 bits)
+ ig_intr_md.resubmit_flag [0:0]
+ ig_intr_md._pad1 [0:0]
+ ig_intr_md._pad2 [1:0]
+ ig_intr_md._pad3 [2:0]
+ ig_intr_md.ingress_port [8:0]
+-----------------------------------------------------------------------------------------------
+| Name | BW | Tagalong? | Req | Pref | Not Allow | MaxSplit | Group Size |
+-----------------------------------------------------------------------------------------------
+| ig_intr_md.resubmit_flag | 1 | False | - | - | - | 1 | 1 |
+| ig_intr_md._pad1 | 1 | False | - | - | - | 1 | 1 |
+| ig_intr_md._pad2 | 2 | False | - | - | - | 1 | 1 |
+| ig_intr_md._pad3 | 3 | False | - | - | - | 1 | 1 |
+| ig_intr_md.ingress_port | 9 | False | - | - | [32] | 2 | 2 |
+-----------------------------------------------------------------------------------------------
+
+min_extracts[8] = 1
+min_extracts[16] = 1
+min_extracts[32] = 1
+Packing options: 2
+MAU containers available:
+ 8-bit: 48
+ 16-bit: 80
+ 32-bit: 47
+Tagalong containers available:
+ 8-bit: 32
+ 16-bit: 48
+ 32-bit: 32
+Initial packing options: 2
+
+Packing option 0: [16]
+MAU containers after:
+ 8-bit: 48
+ 16-bit: 78
+ 32-bit: 47
++-----------------------------------+
+| ig_intr_md.resubmit_flag [0:0] |
+| ig_intr_md._pad1 [0:0] |
+| ig_intr_md._pad2 [1:0] |
+| ig_intr_md._pad3 [2:0] |
+| ig_intr_md.ingress_port [8:0] |
++-----------------------------------+
+
+Looking at ig_intr_md.resubmit_flag (ingress) [0:0], with test_alloc = True
+----> ig_intr_md.resubmit_flag (ingress) is allocated? False
+Looking at ig_intr_md._pad1 (ingress) [0:0], with test_alloc = True
+Looking at ig_intr_md._pad2 (ingress) [1:0], with test_alloc = True
+Looking at ig_intr_md._pad3 (ingress) [2:0], with test_alloc = True
+Looking at ig_intr_md.ingress_port (ingress) [8:0], with test_alloc = True
+Checking if can overlay metadata field.
+No required PHV group.
+Could not find container to overlay in.
+
+MAU groups: 5
+ Group 8 16 bits -- avail 16 -- ingress avail 16 and remain 14 and promised 2 and req 2 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv128
+ Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 14 and promised 2 and req 2 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv160
+ Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 14 and promised 2 and req 2 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv176
+ Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 14 and promised 2 and req 2 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv192
+ Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 14 and promised 2 and req 2 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
+***Allocating phv128[15:15] for ig_intr_md.resubmit_flag[0:0]
+***Allocating phv128[14:14] for ig_intr_md._pad1[0:0]
+***Allocating phv128[13:12] for ig_intr_md._pad2[1:0]
+***Allocating phv128[11:9] for ig_intr_md._pad3[2:0]
+***Allocating phv128[8:0] for ig_intr_md.ingress_port[8:0]
+Packing options tried: 1
+Packing options skipped: 0
+
Working on parse node parse_pkt_out (4) (ingress)
-------------------------------------------
@@ -1276,8 +1120,8 @@
min_extracts[32] = 1
Packing options: 2
MAU containers available:
- 8-bit: 47
- 16-bit: 79
+ 8-bit: 48
+ 16-bit: 78
32-bit: 47
Tagalong containers available:
8-bit: 32
@@ -1287,8 +1131,8 @@
Packing option 0: [16]
MAU containers after:
- 8-bit: 47
- 16-bit: 77
+ 8-bit: 48
+ 16-bit: 76
32-bit: 47
+-------------------------------------+
| packet_out_hdr.egress_port [8:0] |
@@ -1298,6 +1142,7 @@
Looking at packet_out_hdr.egress_port (ingress) [8:0], with test_alloc = True
----> packet_out_hdr.egress_port (ingress) is allocated? False
Looking at packet_out_hdr._padding (ingress) [6:0], with test_alloc = True
+$$$ initialization at table table0 will expand the table layout due to adding a default action.
MAU groups: 5
Group 8 16 bits -- avail 15 -- ingress avail 15 and remain 13 and promised 2 and req 2 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv129
@@ -1357,7 +1202,7 @@
min_extracts[32] = 1
Packing options: 5196
MAU containers available:
- 8-bit: 47
+ 8-bit: 48
16-bit: 77
32-bit: 47
Tagalong containers available:
@@ -1368,7 +1213,7 @@
Packing option 0: [8, 16, 16, 32, 32, 8, 16, 32]
MAU containers after:
- 8-bit: 46
+ 8-bit: 47
16-bit: 76
32-bit: 45
+------------------------------+
@@ -1437,10 +1282,10 @@
----> ipv4.srcAddr (ingress) is allocated? False
MAU groups: 3
- Group 4 8 bits -- avail 15 -- ingress avail 15 and remain 14 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv65
+ Group 4 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv64
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-***Allocating phv65[7:0] for ipv4.srcAddr[23:16]
+***Allocating phv64[7:0] for ipv4.srcAddr[23:16]
Looking at ipv4.srcAddr (ingress) [15:0], with test_alloc = True
----> ipv4.srcAddr (ingress) is allocated? False
@@ -1507,7 +1352,7 @@
min_extracts[32] = 1
Packing options: 5196
MAU containers available:
- 8-bit: 46
+ 8-bit: 47
16-bit: 76
32-bit: 45
Tagalong containers available:
@@ -1516,9 +1361,9 @@
32-bit: 31
Initial packing options: 5196
-Packing option 0: [8, 8, 16, 16, 16, 32, 32, 32]
+Packing option 0: [8, 8, 8, 8, 16, 16, 16, 16, 32, 32]
MAU containers after:
- 8-bit: 46
+ 8-bit: 47
16-bit: 76
32-bit: 45
+-------------------------+
@@ -1526,13 +1371,17 @@
+-------------------------+
| tcp.srcPort [7:0] |
+-------------------------+
-| tcp.dstPort [15:0] |
+| tcp.dstPort [15:8] |
++-------------------------+
+| tcp.dstPort [7:0] |
+-------------------------+
| tcp.seqNo [31:16] |
+-------------------------+
| tcp.seqNo [15:0] |
+-------------------------+
-| tcp.ackNo [31:0] |
+| tcp.ackNo [31:16] |
++-------------------------+
+| tcp.ackNo [15:0] |
+-------------------------+
| tcp.dataOffset [3:0] |
| tcp.res [2:0] |
@@ -1550,34 +1399,40 @@
Looking at tcp.srcPort (ingress) [7:0], with test_alloc = True
----> tcp.srcPort (ingress) is allocated? False
***Allocating phv290[7:0] for tcp.srcPort[7:0]
-Looking at tcp.dstPort (ingress) [15:0], with test_alloc = True
+Looking at tcp.dstPort (ingress) [15:8], with test_alloc = True
----> tcp.dstPort (ingress) is allocated? False
-***Allocating phv322[15:0] for tcp.dstPort[15:0]
+***Allocating phv291[7:0] for tcp.dstPort[15:8]
+Looking at tcp.dstPort (ingress) [7:0], with test_alloc = True
+----> tcp.dstPort (ingress) is allocated? False
+***Allocating phv292[7:0] for tcp.dstPort[7:0]
Looking at tcp.seqNo (ingress) [31:16], with test_alloc = True
----> tcp.seqNo (ingress) is allocated? False
-***Allocating phv323[15:0] for tcp.seqNo[31:16]
+***Allocating phv322[15:0] for tcp.seqNo[31:16]
Looking at tcp.seqNo (ingress) [15:0], with test_alloc = True
----> tcp.seqNo (ingress) is allocated? False
-***Allocating phv324[15:0] for tcp.seqNo[15:0]
-Looking at tcp.ackNo (ingress) [31:0], with test_alloc = True
+***Allocating phv323[15:0] for tcp.seqNo[15:0]
+Looking at tcp.ackNo (ingress) [31:16], with test_alloc = True
----> tcp.ackNo (ingress) is allocated? False
-***Allocating phv257[31:0] for tcp.ackNo[31:0]
+***Allocating phv324[15:0] for tcp.ackNo[31:16]
+Looking at tcp.ackNo (ingress) [15:0], with test_alloc = True
+----> tcp.ackNo (ingress) is allocated? False
+***Allocating phv325[15:0] for tcp.ackNo[15:0]
Looking at tcp.dataOffset (ingress) [3:0], with test_alloc = True
----> tcp.dataOffset (ingress) is allocated? False
Looking at tcp.res (ingress) [2:0], with test_alloc = True
Looking at tcp.ecn (ingress) [2:0], with test_alloc = True
Looking at tcp.ctrl (ingress) [5:0], with test_alloc = True
Looking at tcp.window (ingress) [15:0], with test_alloc = True
-***Allocating phv258[31:28] for tcp.dataOffset[3:0]
-***Allocating phv258[27:25] for tcp.res[2:0]
-***Allocating phv258[24:22] for tcp.ecn[2:0]
-***Allocating phv258[21:16] for tcp.ctrl[5:0]
-***Allocating phv258[15:0] for tcp.window[15:0]
+***Allocating phv257[31:28] for tcp.dataOffset[3:0]
+***Allocating phv257[27:25] for tcp.res[2:0]
+***Allocating phv257[24:22] for tcp.ecn[2:0]
+***Allocating phv257[21:16] for tcp.ctrl[5:0]
+***Allocating phv257[15:0] for tcp.window[15:0]
Looking at tcp.checksum (ingress) [15:0], with test_alloc = True
----> tcp.checksum (ingress) is allocated? False
Looking at tcp.urgentPtr (ingress) [15:0], with test_alloc = True
-***Allocating phv259[31:16] for tcp.checksum[15:0]
-***Allocating phv259[15:0] for tcp.urgentPtr[15:0]
+***Allocating phv258[31:16] for tcp.checksum[15:0]
+***Allocating phv258[15:0] for tcp.urgentPtr[15:0]
Packing options tried: 1
Packing options skipped: 0
@@ -1628,19 +1483,19 @@
min_extracts[32] = 1
Packing options: 5196
MAU containers available:
- 8-bit: 47
- 16-bit: 78
+ 8-bit: 48
+ 16-bit: 80
32-bit: 48
Tagalong containers available:
- 8-bit: 28
- 16-bit: 42
- 32-bit: 28
+ 8-bit: 24
+ 16-bit: 36
+ 32-bit: 24
Initial packing options: 5196
Packing option 0: [8, 8, 16, 16, 16, 32, 32, 32]
MAU containers after:
- 8-bit: 47
- 16-bit: 78
+ 8-bit: 48
+ 16-bit: 80
32-bit: 48
+------------------------------+
| ipv4.version [3:0] |
@@ -1667,35 +1522,35 @@
Looking at ipv4.version (egress) [3:0], with test_alloc = True
----> ipv4.version (egress) is allocated? False
Looking at ipv4.ihl (egress) [3:0], with test_alloc = True
-***Allocating phv292[7:4] for ipv4.version[3:0]
-***Allocating phv292[3:0] for ipv4.ihl[3:0]
+***Allocating phv296[7:4] for ipv4.version[3:0]
+***Allocating phv296[3:0] for ipv4.ihl[3:0]
Looking at ipv4.diffserv (egress) [7:0], with test_alloc = True
----> ipv4.diffserv (egress) is allocated? False
-***Allocating phv293[7:0] for ipv4.diffserv[7:0]
+***Allocating phv297[7:0] for ipv4.diffserv[7:0]
Looking at ipv4.totalLen (egress) [15:0], with test_alloc = True
----> ipv4.totalLen (egress) is allocated? False
-***Allocating phv326[15:0] for ipv4.totalLen[15:0]
+***Allocating phv332[15:0] for ipv4.totalLen[15:0]
Looking at ipv4.identification (egress) [15:0], with test_alloc = True
----> ipv4.identification (egress) is allocated? False
-***Allocating phv327[15:0] for ipv4.identification[15:0]
+***Allocating phv333[15:0] for ipv4.identification[15:0]
Looking at ipv4.flags (egress) [2:0], with test_alloc = True
----> ipv4.flags (egress) is allocated? False
Looking at ipv4.fragOffset (egress) [12:0], with test_alloc = True
-***Allocating phv328[15:13] for ipv4.flags[2:0]
-***Allocating phv328[12:0] for ipv4.fragOffset[12:0]
+***Allocating phv334[15:13] for ipv4.flags[2:0]
+***Allocating phv334[12:0] for ipv4.fragOffset[12:0]
Looking at ipv4.ttl (egress) [7:0], with test_alloc = True
----> ipv4.ttl (egress) is allocated? False
Looking at ipv4.protocol (egress) [7:0], with test_alloc = True
Looking at ipv4.hdrChecksum (egress) [15:0], with test_alloc = True
-***Allocating phv260[31:24] for ipv4.ttl[7:0]
-***Allocating phv260[23:16] for ipv4.protocol[7:0]
-***Allocating phv260[15:0] for ipv4.hdrChecksum[15:0]
+***Allocating phv264[31:24] for ipv4.ttl[7:0]
+***Allocating phv264[23:16] for ipv4.protocol[7:0]
+***Allocating phv264[15:0] for ipv4.hdrChecksum[15:0]
Looking at ipv4.srcAddr (egress) [31:0], with test_alloc = True
----> ipv4.srcAddr (egress) is allocated? False
-***Allocating phv261[31:0] for ipv4.srcAddr[31:0]
+***Allocating phv265[31:0] for ipv4.srcAddr[31:0]
Looking at ipv4.dstAddr (egress) [31:0], with test_alloc = True
----> ipv4.dstAddr (egress) is allocated? False
-***Allocating phv262[31:0] for ipv4.dstAddr[31:0]
+***Allocating phv266[31:0] for ipv4.dstAddr[31:0]
Packing options tried: 1
Packing options skipped: 0
@@ -1744,19 +1599,19 @@
min_extracts[32] = 1
Packing options: 5196
MAU containers available:
- 8-bit: 47
- 16-bit: 78
+ 8-bit: 48
+ 16-bit: 80
32-bit: 48
Tagalong containers available:
- 8-bit: 26
- 16-bit: 39
- 32-bit: 25
+ 8-bit: 22
+ 16-bit: 33
+ 32-bit: 21
Initial packing options: 5196
Packing option 0: [8, 8, 16, 16, 16, 32, 32, 32]
MAU containers after:
- 8-bit: 47
- 16-bit: 78
+ 8-bit: 48
+ 16-bit: 80
32-bit: 48
+-------------------------+
| tcp.srcPort [15:8] |
@@ -1783,38 +1638,38 @@
Looking at tcp.srcPort (egress) [15:8], with test_alloc = True
----> tcp.srcPort (egress) is allocated? False
-***Allocating phv294[7:0] for tcp.srcPort[15:8]
+***Allocating phv298[7:0] for tcp.srcPort[15:8]
Looking at tcp.srcPort (egress) [7:0], with test_alloc = True
----> tcp.srcPort (egress) is allocated? False
-***Allocating phv295[7:0] for tcp.srcPort[7:0]
+***Allocating phv299[7:0] for tcp.srcPort[7:0]
Looking at tcp.dstPort (egress) [15:0], with test_alloc = True
----> tcp.dstPort (egress) is allocated? False
-***Allocating phv329[15:0] for tcp.dstPort[15:0]
+***Allocating phv335[15:0] for tcp.dstPort[15:0]
Looking at tcp.seqNo (egress) [31:16], with test_alloc = True
----> tcp.seqNo (egress) is allocated? False
-***Allocating phv330[15:0] for tcp.seqNo[31:16]
+***Allocating phv336[15:0] for tcp.seqNo[31:16]
Looking at tcp.seqNo (egress) [15:0], with test_alloc = True
----> tcp.seqNo (egress) is allocated? False
-***Allocating phv331[15:0] for tcp.seqNo[15:0]
+***Allocating phv337[15:0] for tcp.seqNo[15:0]
Looking at tcp.ackNo (egress) [31:0], with test_alloc = True
----> tcp.ackNo (egress) is allocated? False
-***Allocating phv263[31:0] for tcp.ackNo[31:0]
+***Allocating phv267[31:0] for tcp.ackNo[31:0]
Looking at tcp.dataOffset (egress) [3:0], with test_alloc = True
----> tcp.dataOffset (egress) is allocated? False
Looking at tcp.res (egress) [2:0], with test_alloc = True
Looking at tcp.ecn (egress) [2:0], with test_alloc = True
Looking at tcp.ctrl (egress) [5:0], with test_alloc = True
Looking at tcp.window (egress) [15:0], with test_alloc = True
-***Allocating phv264[31:28] for tcp.dataOffset[3:0]
-***Allocating phv264[27:25] for tcp.res[2:0]
-***Allocating phv264[24:22] for tcp.ecn[2:0]
-***Allocating phv264[21:16] for tcp.ctrl[5:0]
-***Allocating phv264[15:0] for tcp.window[15:0]
+***Allocating phv268[31:28] for tcp.dataOffset[3:0]
+***Allocating phv268[27:25] for tcp.res[2:0]
+***Allocating phv268[24:22] for tcp.ecn[2:0]
+***Allocating phv268[21:16] for tcp.ctrl[5:0]
+***Allocating phv268[15:0] for tcp.window[15:0]
Looking at tcp.checksum (egress) [15:0], with test_alloc = True
----> tcp.checksum (egress) is allocated? False
Looking at tcp.urgentPtr (egress) [15:0], with test_alloc = True
-***Allocating phv265[31:16] for tcp.checksum[15:0]
-***Allocating phv265[15:0] for tcp.urgentPtr[15:0]
+***Allocating phv269[31:16] for tcp.checksum[15:0]
+***Allocating phv269[15:0] for tcp.urgentPtr[15:0]
Packing options tried: 1
Packing options skipped: 0
@@ -1847,18 +1702,18 @@
min_extracts[32] = 1
Packing options: 604
MAU containers available:
- 8-bit: 46
+ 8-bit: 47
16-bit: 76
32-bit: 45
Tagalong containers available:
- 8-bit: 21
- 16-bit: 31
- 32-bit: 20
+ 8-bit: 19
+ 16-bit: 30
+ 32-bit: 21
Initial packing options: 604
Packing option 0: [8, 32, 16, 8, 32, 16]
MAU containers after:
- 8-bit: 44
+ 8-bit: 45
16-bit: 74
32-bit: 43
+-----------------------------+
@@ -1880,10 +1735,10 @@
----> ethernet.dstAddr (ingress) is allocated? False
MAU groups: 3
- Group 4 8 bits -- avail 14 -- ingress avail 14 and remain 13 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv66
+ Group 4 8 bits -- avail 15 -- ingress avail 15 and remain 14 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv65
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-***Allocating phv66[7:0] for ethernet.dstAddr[47:40]
+***Allocating phv65[7:0] for ethernet.dstAddr[47:40]
Looking at ethernet.dstAddr (ingress) [39:8], with test_alloc = True
----> ethernet.dstAddr (ingress) is allocated? False
@@ -1908,10 +1763,10 @@
----> ethernet.srcAddr (ingress) is allocated? False
MAU groups: 3
- Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
+ Group 4 8 bits -- avail 14 -- ingress avail 14 and remain 13 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv66
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
-***Allocating phv67[7:0] for ethernet.srcAddr[39:32]
+***Allocating phv66[7:0] for ethernet.srcAddr[39:32]
Looking at ethernet.srcAddr (ingress) [31:0], with test_alloc = True
----> ethernet.srcAddr (ingress) is allocated? False
@@ -1962,19 +1817,19 @@
min_extracts[32] = 1
Packing options: 604
MAU containers available:
- 8-bit: 47
- 16-bit: 78
+ 8-bit: 48
+ 16-bit: 80
32-bit: 48
Tagalong containers available:
- 8-bit: 24
- 16-bit: 36
- 32-bit: 22
+ 8-bit: 20
+ 16-bit: 30
+ 32-bit: 18
Initial packing options: 604
Packing option 0: [8, 32, 16, 8, 32, 16]
MAU containers after:
- 8-bit: 47
- 16-bit: 78
+ 8-bit: 48
+ 16-bit: 80
32-bit: 48
+-----------------------------+
| ethernet.dstAddr [47:40] |
@@ -1993,24 +1848,24 @@
Looking at ethernet.dstAddr (egress) [47:40], with test_alloc = True
----> ethernet.dstAddr (egress) is allocated? False
-***Allocating phv296[7:0] for ethernet.dstAddr[47:40]
+***Allocating phv300[7:0] for ethernet.dstAddr[47:40]
Looking at ethernet.dstAddr (egress) [39:8], with test_alloc = True
----> ethernet.dstAddr (egress) is allocated? False
-***Allocating phv266[31:0] for ethernet.dstAddr[39:8]
+***Allocating phv270[31:0] for ethernet.dstAddr[39:8]
Looking at ethernet.dstAddr (egress) [7:0], with test_alloc = True
----> ethernet.dstAddr (egress) is allocated? False
Looking at ethernet.srcAddr (egress) [47:40], with test_alloc = True
-***Allocating phv332[15:8] for ethernet.dstAddr[7:0]
-***Allocating phv332[7:0] for ethernet.srcAddr[47:40]
+***Allocating phv338[15:8] for ethernet.dstAddr[7:0]
+***Allocating phv338[7:0] for ethernet.srcAddr[47:40]
Looking at ethernet.srcAddr (egress) [39:32], with test_alloc = True
----> ethernet.srcAddr (egress) is allocated? False
-***Allocating phv297[7:0] for ethernet.srcAddr[39:32]
+***Allocating phv301[7:0] for ethernet.srcAddr[39:32]
Looking at ethernet.srcAddr (egress) [31:0], with test_alloc = True
----> ethernet.srcAddr (egress) is allocated? False
-***Allocating phv267[31:0] for ethernet.srcAddr[31:0]
+***Allocating phv271[31:0] for ethernet.srcAddr[31:0]
Looking at ethernet.etherType (egress) [15:0], with test_alloc = True
----> ethernet.etherType (egress) is allocated? False
-***Allocating phv333[15:0] for ethernet.etherType[15:0]
+***Allocating phv339[15:0] for ethernet.etherType[15:0]
Packing options tried: 1
Packing options skipped: 0
@@ -2045,19 +1900,19 @@
min_extracts[32] = 1
Packing options: 3
MAU containers available:
- 8-bit: 47
- 16-bit: 78
+ 8-bit: 48
+ 16-bit: 80
32-bit: 48
Tagalong containers available:
- 8-bit: 22
- 16-bit: 34
- 32-bit: 20
+ 8-bit: 18
+ 16-bit: 28
+ 32-bit: 16
Initial packing options: 3
Packing option 1: [16, 8]
MAU containers after:
- 8-bit: 46
- 16-bit: 77
+ 8-bit: 47
+ 16-bit: 79
32-bit: 48
+---------------------------------+
| eg_intr_md._pad0 [6:0] |
@@ -2072,31 +1927,29 @@
Looking at eg_intr_md.egress_port (egress) [8:0], with test_alloc = True
Checking if can overlay metadata field.
No required PHV group.
- Group 9 16 bits -- deparsed True -- avail 15 and promised 2 -- ingress promised 0 and remain 0 and req 8 -- egress promised 2 and remain 13 and req 2 -- act like deparsed True -- container_to_use phv146 -- fails False
Could not find container to overlay in.
MAU groups: 5
- Group 9 16 bits -- avail 15 -- ingress avail 8 and remain 8 and promised 0 and req 0 -- egress avail 15 and remain 13 and promised 2 and req 2 -- as if deparsed True -- container_to_use phv146
+ Group 9 16 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 15 and promised 1 and req 1 -- as if deparsed True -- container_to_use phv144
Group 10 16 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 15 and promised 1 and req 1 -- as if deparsed True -- container_to_use phv160
Group 11 16 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 15 and promised 1 and req 1 -- as if deparsed True -- container_to_use phv176
Group 12 16 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 15 and promised 1 and req 1 -- as if deparsed True -- container_to_use phv192
Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 15 and promised 1 and req 1 -- as if deparsed True -- container_to_use phv208
-***Allocating phv146[15:9] for eg_intr_md._pad0[6:0]
-***Allocating phv146[8:0] for eg_intr_md.egress_port[8:0]
+***Allocating phv144[15:9] for eg_intr_md._pad0[6:0]
+***Allocating phv144[8:0] for eg_intr_md.egress_port[8:0]
Looking at eg_intr_md._pad7 (egress) [4:0], with test_alloc = True
----> eg_intr_md._pad7 (egress) is allocated? False
Looking at eg_intr_md.egress_cos (egress) [2:0], with test_alloc = True
Checking if can overlay metadata field.
No required PHV group.
- Group 5 8 bits -- deparsed True -- avail 15 and promised 1 -- ingress promised 0 and remain 0 and req 8 -- egress promised 1 and remain 14 and req 1 -- act like deparsed True -- container_to_use phv81 -- fails False
Could not find container to overlay in.
MAU groups: 3
- Group 5 8 bits -- avail 15 -- ingress avail 8 and remain 8 and promised 0 and req 0 -- egress avail 15 and remain 14 and promised 1 and req 1 -- as if deparsed True -- container_to_use phv81
+ Group 5 8 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 15 and promised 1 and req 1 -- as if deparsed True -- container_to_use phv80
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 15 and promised 1 and req 1 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 8 and promised 0 and req 0 -- egress avail 16 and remain 15 and promised 1 and req 1 -- as if deparsed True -- container_to_use phv112
-***Allocating phv81[7:3] for eg_intr_md._pad7[4:0]
-***Allocating phv81[2:0] for eg_intr_md.egress_cos[2:0]
+***Allocating phv80[7:3] for eg_intr_md._pad7[4:0]
+***Allocating phv80[2:0] for eg_intr_md.egress_cos[2:0]
Packing options tried: 2
Packing options skipped: 0
Failure Reasons:
@@ -2109,86 +1962,6 @@
ContainerAlignment Constraint: eg_intr_md.egress_cos <3 bits egress parsed imeta> -- field_bit: 0 -- bits_list: [0, 1, 2, 3, 4, 5, 6, 7]
]
-Working on parse node ingress_intrinsic_metadata (9) (ingress)
-
--------------------------------------------
-Allocating parsed header: pkt fields (5) / meta fields (0) using extraction bandwidth 224
--------------------------------------------
-Extracted bits: 16
-Set metadata bits: 0
-Gress: ingress
-bits_will_need_to_parse = 16
-unused_metadata_container_bits = 0
-min_parse_states = 1
-bits_per_state = 16
-Already allocated? ig_intr_md.resubmit_flag (ingress)
-Already allocated? ig_intr_md._pad1 (ingress)
-Already allocated? ig_intr_md._pad2 (ingress)
-Already allocated? ig_intr_md._pad3 (ingress)
-Already allocated? ig_intr_md.ingress_port (ingress)
-Already allocated? ig_intr_md.ingress_port (ingress)
-Parse state 0 (16 bits)
- ig_intr_md.resubmit_flag [0:0]
- ig_intr_md._pad1 [0:0]
- ig_intr_md._pad2 [1:0]
- ig_intr_md._pad3 [2:0]
- ig_intr_md.ingress_port [8:0]
------------------------------------------------------------------------------------------------------
-| Name | BW | Tagalong? | Req | Pref | Not Allow | MaxSplit | Group Size |
------------------------------------------------------------------------------------------------------
-| ig_intr_md.resubmit_flag | 1 | False | [(16, 1)] | - | - | 1 | 1 |
-| ig_intr_md._pad1 | 1 | False | [(16, 1)] | - | - | 1 | 1 |
-| ig_intr_md._pad2 | 2 | False | [(16, 2)] | - | - | 1 | 1 |
-| ig_intr_md._pad3 | 3 | False | [(16, 3)] | - | - | 1 | 1 |
-| ig_intr_md.ingress_port | 9 | False | [(16, 9)] | - | - | 2 | 1 |
------------------------------------------------------------------------------------------------------
-
-min_extracts[8] = 1
-min_extracts[16] = 6
-min_extracts[32] = 1
-Packing options: 2
-MAU containers available:
- 8-bit: 44
- 16-bit: 74
- 32-bit: 43
-Tagalong containers available:
- 8-bit: 21
- 16-bit: 31
- 32-bit: 20
-Initial packing options: 2
-
-Packing option 0: [16]
-MAU containers after:
- 8-bit: 44
- 16-bit: 74
- 32-bit: 43
-+-----------------------------------+
-| ig_intr_md.resubmit_flag [0:0] |
-| ig_intr_md._pad1 [0:0] |
-| ig_intr_md._pad2 [1:0] |
-| ig_intr_md._pad3 [2:0] |
-| ig_intr_md.ingress_port [8:0] |
-+-----------------------------------+
-
-Looking at ig_intr_md.resubmit_flag (ingress) [0:0], with test_alloc = True
-----> ig_intr_md.resubmit_flag (ingress) is allocated? True
-Looking at ig_intr_md._pad1 (ingress) [0:0], with test_alloc = True
-----> ig_intr_md._pad1 (ingress) is allocated? True
-Looking at ig_intr_md._pad2 (ingress) [1:0], with test_alloc = True
-----> ig_intr_md._pad2 (ingress) is allocated? True
-Looking at ig_intr_md._pad3 (ingress) [2:0], with test_alloc = True
-----> ig_intr_md._pad3 (ingress) is allocated? True
-Looking at ig_intr_md.ingress_port (ingress) [8:0], with test_alloc = True
-----> ig_intr_md.ingress_port (ingress) is allocated? True
-Fields for container 16 at index 0 already allocated. No need to overlay or allocate new.
- ig_intr_md.resubmit_flag[0:0]
- ig_intr_md._pad1[0:0]
- ig_intr_md._pad2[1:0]
- ig_intr_md._pad3[2:0]
- ig_intr_md.ingress_port[8:0]
-Packing options tried: 1
-Packing options skipped: 0
-
Working on parse node parse_pkt_out (4) (egress)
-------------------------------------------
@@ -2216,19 +1989,19 @@
min_extracts[32] = 1
Packing options: 2
MAU containers available:
- 8-bit: 46
- 16-bit: 77
+ 8-bit: 47
+ 16-bit: 79
32-bit: 48
Tagalong containers available:
- 8-bit: 22
- 16-bit: 34
- 32-bit: 20
+ 8-bit: 18
+ 16-bit: 28
+ 32-bit: 16
Initial packing options: 2
Packing option 0: [16]
MAU containers after:
- 8-bit: 46
- 16-bit: 77
+ 8-bit: 47
+ 16-bit: 79
32-bit: 48
+-------------------------------------+
| packet_out_hdr.egress_port [8:0] |
@@ -2238,8 +2011,8 @@
Looking at packet_out_hdr.egress_port (egress) [8:0], with test_alloc = True
----> packet_out_hdr.egress_port (egress) is allocated? False
Looking at packet_out_hdr._padding (egress) [6:0], with test_alloc = True
-***Allocating phv334[15:7] for packet_out_hdr.egress_port[8:0]
-***Allocating phv334[6:0] for packet_out_hdr._padding[6:0]
+***Allocating phv340[15:7] for packet_out_hdr.egress_port[8:0]
+***Allocating phv340[6:0] for packet_out_hdr._padding[6:0]
Packing options tried: 1
Packing options skipped: 0
@@ -2253,50 +2026,50 @@
After allocating critical parse paths:
Allocation state: Final Allocation
-------------------------------------------------------------------------------
-| PHV Group | Containers Used | Bits Used | Bits Available |
-| (container bit widths) | (% used) | (% used) | |
-------------------------------------------------------------------------------
-| 0 (32) | 5 (31.25%) | 160 (31.25%) | 512 |
-| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 5 (7.81%) | 160 (7.81%) | 2048 |
-| | | | |
-| 4 (8) | 4 (25.00%) | 32 (25.00%) | 128 |
-| 5 (8) | 2 (12.50%) | 16 (12.50%) | 128 |
-| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 6 (9.38%) | 48 (9.38%) | 512 |
-| | | | |
-| 8 (16) | 5 (31.25%) | 80 (31.25%) | 256 |
-| 9 (16) | 2 (12.50%) | 32 (12.50%) | 256 |
-| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 7 (7.29%) | 112 (7.29%) | 1536 |
-| | | | |
-| 14 (32) T | 12 (75.00%) | 384 (75.00%) | 512 |
-| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 12 (37.50%) | 384 (37.50%) | 1024 |
-| | | | |
-| 16 (8) T | 9 (56.25%) | 72 (56.25%) | 128 |
-| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 9 (28.12%) | 72 (28.12%) | 256 |
-| | | | |
-| 18 (16) T | 14 (87.50%) | 224 (87.50%) | 256 |
-| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 14 (29.17%) | 224 (29.17%) | 768 |
-| | | | |
-| MAU total | 18 (8.04%) | 320 (7.81%) | 4096 |
-| Tagalong total | 35 (31.25%) | 680 (33.20%) | 2048 |
-| Overall total | 53 (15.77%) | 1000 (16.28%) | 6144 |
-------------------------------------------------------------------------------
+-----------------------------------------------------------------------------
+| PHV Group | Containers Used | Bits Used | Bits Available |
+| (container bit widths) | (% used) | (% used) | |
+-----------------------------------------------------------------------------
+| 0 (32) | 5 (31.25%) | 160 (31.25%) | 512 |
+| 1 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 2 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
+| Total for 32 bit | 5 (7.81%) | 160 (7.81%) | 2048 |
+| | | | |
+| 4 (8) | 3 (18.75%) | 24 (18.75%) | 128 |
+| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
+| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
+| Total for 8 bit | 4 (6.25%) | 32 (6.25%) | 512 |
+| | | | |
+| 8 (16) | 5 (31.25%) | 80 (31.25%) | 256 |
+| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
+| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
+| Total for 16 bit | 6 (6.25%) | 96 (6.25%) | 1536 |
+| | | | |
+| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
+| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
+| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
+| | | | |
+| 16 (8) T | 11 (68.75%) | 88 (68.75%) | 128 |
+| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
+| Total for 8 bit | 11 (34.38%) | 88 (34.38%) | 256 |
+| | | | |
+| 18 (16) T | 10 (62.50%) | 160 (62.50%) | 256 |
+| 19 (16) T | 5 (31.25%) | 80 (31.25%) | 256 |
+| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| Total for 16 bit | 15 (31.25%) | 240 (31.25%) | 768 |
+| | | | |
+| MAU total | 15 (6.70%) | 288 (7.03%) | 4096 |
+| Tagalong total | 37 (33.04%) | 680 (33.20%) | 2048 |
+| Overall total | 52 (15.48%) | 968 (15.76%) | 6144 |
+-----------------------------------------------------------------------------
->>Event 'pa_overlay' at time 1504795741.17
- Took 9.08 seconds
+>>Event 'pa_overlay' at time 1504859126.82
+ Took 9.14 seconds
-----------------------------------------------
Allocating remaining parsed fields
@@ -2304,21 +2077,21 @@
Allocation Step
All Sorted parse nodes (non-critical):
- parse_pkt_in (egress) with bits = 16 and max = 2
+ parse_pkt_in (ingress) with bits = 16 and max = 2
parse_udp (ingress) with bits = 64 and max = 1
parse_udp (egress) with bits = 64 and max = 1
- parse_pkt_in (ingress) with bits = 16 and max = 1
+ parse_pkt_in (egress) with bits = 16 and max = 1
Total packet bits: 160
Total meta bits: 0
Total bits: 160
-Working on parse node parse_pkt_in (2) (egress)
+Working on parse node parse_pkt_in (2) (ingress)
-------------------------------------------
Overlaying parsed header: pkt fields (2) / meta fields (0) using extraction bandwidth 224
-------------------------------------------
Extracted bits: 16
Set metadata bits: 0
-Gress: egress
+Gress: ingress
bits_will_need_to_parse = 16
unused_metadata_container_bits = 0
min_parse_states = 1
@@ -2334,19 +2107,19 @@
-------------------------------------------------------------------------------------------------------
MAU containers available:
- 8-bit: 46
- 16-bit: 77
- 32-bit: 48
+ 8-bit: 45
+ 16-bit: 74
+ 32-bit: 43
Packing options: 2
Initial packing options: 2
Packing option 0: [16]
->>Can pack using [16] if open up 1 new containers.
-Packing options tried: 2
+>>Can pack using [16] if open up 0 new containers.
+Packing options tried: 1
Packing options skipped: 0
Trying to place using best packing [16]
-***Allocating phv145[15:7] for packet_in_hdr.ingress_port[8:0]
-***Allocating phv145[6:0] for packet_in_hdr._padding[6:0]
+***Allocating phv129[15:7] for packet_in_hdr.ingress_port[8:0]
+***Allocating phv129[6:0] for packet_in_hdr._padding[6:0]
Working on parse node parse_udp (8) (ingress)
-------------------------------------------
@@ -2374,7 +2147,7 @@
-----------------------------------------------------------------------------------
MAU containers available:
- 8-bit: 44
+ 8-bit: 45
16-bit: 74
32-bit: 43
Packing options: 47
@@ -2383,12 +2156,12 @@
Packing option 0: [8, 8, 16, 32]
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
MAU groups: 3
- Group 4 8 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv69
+ Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
@@ -2403,12 +2176,12 @@
Packing option 1: [8, 8, 32, 16]
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
MAU groups: 3
- Group 4 8 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv69
+ Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
@@ -2421,7 +2194,7 @@
Packing option 2: [8, 16, 8, 32]
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
@@ -2433,7 +2206,7 @@
Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
MAU groups: 3
- Group 4 8 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv69
+ Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
>>Can pack using [8, 16, 8, 32] if open up 3 new containers.
@@ -2441,7 +2214,7 @@
Packing option 3: [8, 16, 32, 8]
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
@@ -2461,7 +2234,7 @@
Packing option 4: [8, 32, 8, 16]
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
@@ -2474,7 +2247,7 @@
Packing option 5: [8, 32, 16, 8]
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
@@ -2494,12 +2267,12 @@
Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
MAU groups: 3
- Group 4 8 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv69
+ Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
>>Can pack using [16, 8, 8, 32] if open up 3 new containers.
@@ -2514,7 +2287,7 @@
Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
@@ -2606,12 +2379,12 @@
Packing option 15: [8, 8, 16, 16, 16]
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
MAU groups: 3
- Group 4 8 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv69
+ Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
@@ -2626,7 +2399,7 @@
Packing option 16: [8, 16, 8, 16, 16]
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
@@ -2638,7 +2411,7 @@
Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
MAU groups: 3
- Group 4 8 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv69
+ Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
>>Can pack using [8, 16, 8, 16, 16] if open up 3 new containers.
@@ -2646,7 +2419,7 @@
Packing option 17: [8, 16, 16, 8, 16]
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
@@ -2668,7 +2441,7 @@
Packing option 18: [8, 16, 16, 16, 8]
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
@@ -2697,12 +2470,12 @@
Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
MAU groups: 3
- Group 4 8 bits -- avail 11 -- ingress avail 11 and remain 10 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv69
+ Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
>>Can pack using [16, 8, 8, 16, 16] if open up 3 new containers.
@@ -2717,7 +2490,7 @@
Group 13 16 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv208
MAU groups: 3
- Group 4 8 bits -- avail 12 -- ingress avail 12 and remain 11 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv68
+ Group 4 8 bits -- avail 13 -- ingress avail 13 and remain 12 and promised 1 and req 1 -- egress avail 8 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv67
Group 6 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv96
Group 7 8 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 8 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv112
@@ -2769,8 +2542,8 @@
-----------------------------------------------------------------------------------
MAU containers available:
- 8-bit: 46
- 16-bit: 77
+ 8-bit: 47
+ 16-bit: 79
32-bit: 48
Packing options: 47
Initial packing options: 47
@@ -2780,19 +2553,19 @@
Packing options tried: 1
Packing options skipped: 0
Trying to place using best packing [8, 8, 16, 32]
-***Allocating phv294[7:0] for udp.srcPort[15:8]
-***Allocating phv295[7:0] for udp.srcPort[7:0]
-***Allocating phv329[15:0] for udp.dstPort[15:0]
-***Allocating phv263[31:16] for udp.length_[15:0]
-***Allocating phv263[15:0] for udp.checksum[15:0]
-Working on parse node parse_pkt_in (2) (ingress)
+***Allocating phv298[7:0] for udp.srcPort[15:8]
+***Allocating phv299[7:0] for udp.srcPort[7:0]
+***Allocating phv336[15:0] for udp.dstPort[15:0]
+***Allocating phv267[31:16] for udp.length_[15:0]
+***Allocating phv267[15:0] for udp.checksum[15:0]
+Working on parse node parse_pkt_in (2) (egress)
-------------------------------------------
Overlaying parsed header: pkt fields (2) / meta fields (0) using extraction bandwidth 224
-------------------------------------------
Extracted bits: 16
Set metadata bits: 0
-Gress: ingress
+Gress: egress
bits_will_need_to_parse = 16
unused_metadata_container_bits = 0
min_parse_states = 1
@@ -2808,9 +2581,9 @@
-------------------------------------------------------------------------------------------------
MAU containers available:
- 8-bit: 44
- 16-bit: 74
- 32-bit: 42
+ 8-bit: 47
+ 16-bit: 79
+ 32-bit: 48
Packing options: 2
Initial packing options: 2
@@ -2819,8 +2592,8 @@
Packing options tried: 1
Packing options skipped: 0
Trying to place using best packing [16]
-***Allocating phv129[15:7] for packet_in_hdr.ingress_port[8:0]
-***Allocating phv129[6:0] for packet_in_hdr._padding[6:0]
+***Allocating phv340[15:7] for packet_in_hdr.ingress_port[8:0]
+***Allocating phv340[6:0] for packet_in_hdr._padding[6:0]
After allocating remaining parse nodes:
Allocation state: Final Allocation
@@ -2834,36 +2607,36 @@
| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
| | | | |
-| 4 (8) | 4 (25.00%) | 32 (25.00%) | 128 |
-| 5 (8) | 2 (12.50%) | 16 (12.50%) | 128 |
+| 4 (8) | 3 (18.75%) | 24 (18.75%) | 128 |
+| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 6 (9.38%) | 48 (9.38%) | 512 |
+| Total for 8 bit | 4 (6.25%) | 32 (6.25%) | 512 |
| | | | |
| 8 (16) | 5 (31.25%) | 80 (31.25%) | 256 |
-| 9 (16) | 3 (18.75%) | 48 (18.75%) | 256 |
+| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 8 (8.33%) | 128 (8.33%) | 1536 |
+| Total for 16 bit | 6 (6.25%) | 96 (6.25%) | 1536 |
| | | | |
-| 14 (32) T | 12 (75.00%) | 384 (75.00%) | 512 |
+| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 12 (37.50%) | 384 (37.50%) | 1024 |
+| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
| | | | |
-| 16 (8) T | 9 (56.25%) | 72 (56.25%) | 128 |
+| 16 (8) T | 11 (68.75%) | 88 (68.75%) | 128 |
| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 9 (28.12%) | 72 (28.12%) | 256 |
+| Total for 8 bit | 11 (34.38%) | 88 (34.38%) | 256 |
| | | | |
-| 18 (16) T | 14 (87.50%) | 224 (87.50%) | 256 |
-| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| 18 (16) T | 10 (62.50%) | 160 (62.50%) | 256 |
+| 19 (16) T | 5 (31.25%) | 80 (31.25%) | 256 |
| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 14 (29.17%) | 224 (29.17%) | 768 |
+| Total for 16 bit | 15 (31.25%) | 240 (31.25%) | 768 |
| | | | |
-| MAU total | 20 (8.93%) | 368 (8.98%) | 4096 |
-| Tagalong total | 35 (31.25%) | 680 (33.20%) | 2048 |
-| Overall total | 55 (16.37%) | 1048 (17.06%) | 6144 |
+| MAU total | 16 (7.14%) | 320 (7.81%) | 4096 |
+| Tagalong total | 37 (33.04%) | 680 (33.20%) | 2048 |
+| Overall total | 53 (15.77%) | 1000 (16.28%) | 6144 |
------------------------------------------------------------------------------
@@ -2887,12 +2660,12 @@
| Total for 8 bit | 0 (0.00%) | 0 (0.00%) | 512 |
| | | | |
| 8 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
+| 9 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 1 (1.04%) | 16 (1.04%) | 1536 |
+| Total for 16 bit | 0 (0.00%) | 0 (0.00%) | 1536 |
| | | | |
| 14 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
@@ -2907,21 +2680,36 @@
| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
| Total for 16 bit | 0 (0.00%) | 0 (0.00%) | 768 |
| | | | |
-| MAU total | 2 (0.89%) | 48 (1.17%) | 4096 |
+| MAU total | 1 (0.45%) | 32 (0.78%) | 4096 |
| Tagalong total | 0 (0.00%) | 0 (0.00%) | 2048 |
-| Overall total | 2 (0.60%) | 48 (0.78%) | 6144 |
+| Overall total | 1 (0.30%) | 32 (0.52%) | 6144 |
---------------------------------------------------------------------------
->>Event 'pa_meta1' at time 1504795745.06
- Took 3.89 seconds
+>>Event 'pa_meta1' at time 1504859130.57
+ Took 3.76 seconds
-----------------------------------------------
Allocating metadata (pass 1)
-----------------------------------------------
Allocation Step
+$$$ initialization at table table0 will expand the table layout due to adding a default action.
+$$$ initialization at table table0 will expand the table layout due to adding a default action.
+$$$ initialization at table table0 will expand the table layout due to adding a default action.
+@@@ overlaying ig_intr_md_for_tm.drop_ctl (ingress) and ig_intr_md.resubmit_flag (ingress) will require table injection to initialize.
+@@@ overlaying ig_intr_md_for_tm.drop_ctl (ingress) and ig_intr_md._pad1 (ingress) will require table injection to initialize.
+@@@ overlaying ig_intr_md_for_tm.drop_ctl (ingress) and ig_intr_md._pad2 (ingress) will require table injection to initialize.
+@@@ overlaying ig_intr_md_for_tm.drop_ctl (ingress) and ig_intr_md._pad3 (ingress) will require table injection to initialize.
+$$$ initialization at table table0 will expand the table layout due to adding a default action.
+$$$ initialization at table table0 will expand the table layout due to adding a default action.
+$$$ initialization at table table0 will expand the table layout due to adding a default action.
+$$$ initialization at table table0 will expand the table layout due to adding a default action.
+$$$ initialization at table table0 will expand the table layout due to adding a default action.
+$$$ initialization at table table0 will expand the table layout due to adding a default action.
+$$$ initialization at table table0 will expand the table layout due to adding a default action.
+$$$ initialization at table table0 will expand the table layout due to adding a default action.
Total metadata field instances to allocate: 4 / 44 bits (44 ingress bits and 0 egress bits)
Promised metadata field instances to allocate: 1 / 9 bits (9 ingress bits and 0 egress bits)
- 0: ig_intr_md_for_tm.ucast_egress_port (ingress) (highly=0, mau_group_size=2, max_overlay=0, max_share=0, max_split=1, bit_width=9, initial_usage_read=3, earliest_use=0, latest_use=12)
+ 0: ig_intr_md_for_tm.ucast_egress_port (ingress) (highly=0, mau_group_size=2, max_overlay=0, max_share=0, max_split=1, bit_width=9, initial_usage_read=2, earliest_use=0, latest_use=12)
--------------
Working on:
@@ -2976,36 +2764,36 @@
| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
| | | | |
-| 4 (8) | 4 (25.00%) | 32 (25.00%) | 128 |
-| 5 (8) | 2 (12.50%) | 16 (12.50%) | 128 |
+| 4 (8) | 3 (18.75%) | 24 (18.75%) | 128 |
+| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 6 (9.38%) | 48 (9.38%) | 512 |
+| Total for 8 bit | 4 (6.25%) | 32 (6.25%) | 512 |
| | | | |
| 8 (16) | 6 (37.50%) | 89 (34.77%) | 256 |
-| 9 (16) | 3 (18.75%) | 48 (18.75%) | 256 |
+| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 9 (9.38%) | 137 (8.92%) | 1536 |
+| Total for 16 bit | 7 (7.29%) | 105 (6.84%) | 1536 |
| | | | |
-| 14 (32) T | 12 (75.00%) | 384 (75.00%) | 512 |
+| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 12 (37.50%) | 384 (37.50%) | 1024 |
+| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
| | | | |
-| 16 (8) T | 9 (56.25%) | 72 (56.25%) | 128 |
+| 16 (8) T | 11 (68.75%) | 88 (68.75%) | 128 |
| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 9 (28.12%) | 72 (28.12%) | 256 |
+| Total for 8 bit | 11 (34.38%) | 88 (34.38%) | 256 |
| | | | |
-| 18 (16) T | 14 (87.50%) | 224 (87.50%) | 256 |
-| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| 18 (16) T | 10 (62.50%) | 160 (62.50%) | 256 |
+| 19 (16) T | 5 (31.25%) | 80 (31.25%) | 256 |
| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 14 (29.17%) | 224 (29.17%) | 768 |
+| Total for 16 bit | 15 (31.25%) | 240 (31.25%) | 768 |
| | | | |
-| MAU total | 21 (9.38%) | 377 (9.20%) | 4096 |
-| Tagalong total | 35 (31.25%) | 680 (33.20%) | 2048 |
-| Overall total | 56 (16.67%) | 1057 (17.20%) | 6144 |
+| MAU total | 17 (7.59%) | 329 (8.03%) | 4096 |
+| Tagalong total | 37 (33.04%) | 680 (33.20%) | 2048 |
+| Overall total | 54 (16.07%) | 1009 (16.42%) | 6144 |
------------------------------------------------------------------------------
Allocation state difference after promised meta allocated:
@@ -3053,8 +2841,8 @@
--------------------------------------------------------------------------
Sorted metadata field instances to allocate: 0 / 0 bits (0 ingress bits and 0 egress bits)
->>Event 'pa_pov' at time 1504795745.11
- Took 0.05 seconds
+>>Event 'pa_pov' at time 1504859130.68
+ Took 0.10 seconds
-----------------------------------------------
Allocating POV
@@ -3071,36 +2859,36 @@
| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
| | | | |
-| 4 (8) | 4 (25.00%) | 32 (25.00%) | 128 |
-| 5 (8) | 2 (12.50%) | 16 (12.50%) | 128 |
+| 4 (8) | 3 (18.75%) | 24 (18.75%) | 128 |
+| 5 (8) | 1 (6.25%) | 8 (6.25%) | 128 |
| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 6 (9.38%) | 48 (9.38%) | 512 |
+| Total for 8 bit | 4 (6.25%) | 32 (6.25%) | 512 |
| | | | |
| 8 (16) | 6 (37.50%) | 89 (34.77%) | 256 |
-| 9 (16) | 3 (18.75%) | 48 (18.75%) | 256 |
+| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 9 (9.38%) | 137 (8.92%) | 1536 |
+| Total for 16 bit | 7 (7.29%) | 105 (6.84%) | 1536 |
| | | | |
-| 14 (32) T | 12 (75.00%) | 384 (75.00%) | 512 |
+| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 12 (37.50%) | 384 (37.50%) | 1024 |
+| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
| | | | |
-| 16 (8) T | 9 (56.25%) | 72 (56.25%) | 128 |
+| 16 (8) T | 11 (68.75%) | 88 (68.75%) | 128 |
| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 9 (28.12%) | 72 (28.12%) | 256 |
+| Total for 8 bit | 11 (34.38%) | 88 (34.38%) | 256 |
| | | | |
-| 18 (16) T | 14 (87.50%) | 224 (87.50%) | 256 |
-| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| 18 (16) T | 10 (62.50%) | 160 (62.50%) | 256 |
+| 19 (16) T | 5 (31.25%) | 80 (31.25%) | 256 |
| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 14 (29.17%) | 224 (29.17%) | 768 |
+| Total for 16 bit | 15 (31.25%) | 240 (31.25%) | 768 |
| | | | |
-| MAU total | 21 (9.38%) | 377 (9.20%) | 4096 |
-| Tagalong total | 35 (31.25%) | 680 (33.20%) | 2048 |
-| Overall total | 56 (16.67%) | 1057 (17.20%) | 6144 |
+| MAU total | 17 (7.59%) | 329 (8.03%) | 4096 |
+| Tagalong total | 37 (33.04%) | 680 (33.20%) | 2048 |
+| Overall total | 54 (16.07%) | 1009 (16.42%) | 6144 |
------------------------------------------------------------------------------
Sorted POV field instances to allocate (with best pack): 13
@@ -3119,25 +2907,25 @@
12: --validity_check--udp (egress) -- max pov share 5 / best pack 4
Working on
---validity_check--packet_in_hdr <1 bits ingress parsed pov>
+--validity_check--packet_in_hdr <1 bits ingress parsed pov W>
Call to _allocate_pov_helper for:
--validity_check--packet_in_hdr (ingress)
Best pack group: (6)
Looking for container to share POV bit in from already allocated containers for POV.
-Container availability (not used yet for POV): total 192 / partial 1
+Container availability (not used yet for POV): total 193 / partial 1
Looking for container to share POV bit in from already allocated containers that have not been used for POV.
->>Choose container phv68, starting at container bit 0, which results in 7 bits still available (unused = 8 and could fit = 7).
+>>Choose container phv67, starting at container bit 0, which results in 7 bits still available (unused = 8 and could fit = 7).
>> Decided to allocate new container
-Required container phv68
-***Allocating phv68[0:0] for --validity_check--packet_in_hdr[0:0]
-***Allocating phv68[1:1] for --validity_check--packet_out_hdr[0:0]
-***Allocating phv68[2:2] for --validity_check--ethernet[0:0]
-***Allocating phv68[3:3] for --validity_check--ipv4[0:0]
-***Allocating phv68[4:4] for --validity_check--tcp[0:0]
-***Allocating phv68[5:5] for --validity_check--udp[0:0]
-***Allocating phv68[6:6] for --validity_check--metadata_bridge[0:0]
+Required container phv67
+***Allocating phv67[0:0] for --validity_check--packet_in_hdr[0:0]
+***Allocating phv67[1:1] for --validity_check--packet_out_hdr[0:0]
+***Allocating phv67[2:2] for --validity_check--ethernet[0:0]
+***Allocating phv67[3:3] for --validity_check--ipv4[0:0]
+***Allocating phv67[4:4] for --validity_check--tcp[0:0]
+***Allocating phv67[5:5] for --validity_check--udp[0:0]
+***Allocating phv67[6:6] for --validity_check--metadata_bridge[0:0]
Working on
--validity_check--packet_out_hdr <1 bits ingress parsed pov R W>
@@ -3164,24 +2952,24 @@
Already allocated.
Working on
---validity_check--packet_in_hdr <1 bits egress parsed pov W>
+--validity_check--packet_in_hdr <1 bits egress parsed pov>
Call to _allocate_pov_helper for:
--validity_check--packet_in_hdr (egress)
Best pack group: (5)
Looking for container to share POV bit in from already allocated containers for POV.
-Container availability (not used yet for POV): total 195 / partial 0
+Container availability (not used yet for POV): total 198 / partial 0
Looking for container to share POV bit in from already allocated containers that have not been used for POV.
->>Choose container phv82, starting at container bit 0, which results in 7 bits still available (unused = 8 and could fit = 6).
+>>Choose container phv81, starting at container bit 0, which results in 7 bits still available (unused = 8 and could fit = 6).
>> Decided to allocate new container
-Required container phv82
-***Allocating phv82[0:0] for --validity_check--packet_in_hdr[0:0]
-***Allocating phv82[1:1] for --validity_check--packet_out_hdr[0:0]
-***Allocating phv82[2:2] for --validity_check--ethernet[0:0]
-***Allocating phv82[3:3] for --validity_check--ipv4[0:0]
-***Allocating phv82[4:4] for --validity_check--tcp[0:0]
-***Allocating phv82[5:5] for --validity_check--udp[0:0]
+Required container phv81
+***Allocating phv81[0:0] for --validity_check--packet_in_hdr[0:0]
+***Allocating phv81[1:1] for --validity_check--packet_out_hdr[0:0]
+***Allocating phv81[2:2] for --validity_check--ethernet[0:0]
+***Allocating phv81[3:3] for --validity_check--ipv4[0:0]
+***Allocating phv81[4:4] for --validity_check--tcp[0:0]
+***Allocating phv81[5:5] for --validity_check--udp[0:0]
Working on
--validity_check--packet_out_hdr <1 bits egress parsed pov>
@@ -3205,12 +2993,12 @@
Sum of container bit widths POVs found in: 16
ingress
- phv68 (8 bits)
+ phv67 (8 bits)
>> 8 total bits
egress
- phv82 (8 bits)
+ phv81 (8 bits)
>> 8 total bits
->>Event 'pa_meta2' at time 1504795745.23
+>>Event 'pa_meta2' at time 1504859130.80
Took 0.12 seconds
-----------------------------------------------
@@ -3231,36 +3019,36 @@
| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
| | | | |
-| 4 (8) | 5 (31.25%) | 39 (30.47%) | 128 |
-| 5 (8) | 3 (18.75%) | 22 (17.19%) | 128 |
+| 4 (8) | 4 (25.00%) | 31 (24.22%) | 128 |
+| 5 (8) | 2 (12.50%) | 14 (10.94%) | 128 |
| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 8 (12.50%) | 61 (11.91%) | 512 |
+| Total for 8 bit | 6 (9.38%) | 45 (8.79%) | 512 |
| | | | |
| 8 (16) | 6 (37.50%) | 89 (34.77%) | 256 |
-| 9 (16) | 3 (18.75%) | 48 (18.75%) | 256 |
+| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 9 (9.38%) | 137 (8.92%) | 1536 |
+| Total for 16 bit | 7 (7.29%) | 105 (6.84%) | 1536 |
| | | | |
-| 14 (32) T | 12 (75.00%) | 384 (75.00%) | 512 |
+| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 12 (37.50%) | 384 (37.50%) | 1024 |
+| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
| | | | |
-| 16 (8) T | 9 (56.25%) | 72 (56.25%) | 128 |
+| 16 (8) T | 11 (68.75%) | 88 (68.75%) | 128 |
| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 9 (28.12%) | 72 (28.12%) | 256 |
+| Total for 8 bit | 11 (34.38%) | 88 (34.38%) | 256 |
| | | | |
-| 18 (16) T | 14 (87.50%) | 224 (87.50%) | 256 |
-| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| 18 (16) T | 10 (62.50%) | 160 (62.50%) | 256 |
+| 19 (16) T | 5 (31.25%) | 80 (31.25%) | 256 |
| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 14 (29.17%) | 224 (29.17%) | 768 |
+| Total for 16 bit | 15 (31.25%) | 240 (31.25%) | 768 |
| | | | |
-| MAU total | 23 (10.27%) | 390 (9.52%) | 4096 |
-| Tagalong total | 35 (31.25%) | 680 (33.20%) | 2048 |
-| Overall total | 58 (17.26%) | 1070 (17.42%) | 6144 |
+| MAU total | 19 (8.48%) | 342 (8.35%) | 4096 |
+| Tagalong total | 37 (33.04%) | 680 (33.20%) | 2048 |
+| Overall total | 56 (16.67%) | 1022 (16.63%) | 6144 |
------------------------------------------------------------------------------
Allocation state difference after promised meta allocated:
@@ -3308,9 +3096,9 @@
--------------------------------------------------------------------------
Sorted metadata field instances to allocate: 3 / 35 bits (35 ingress bits and 0 egress bits)
- 0: ecmp_metadata.groupId (ingress) (highly=0, mau_group_size=1, max_overlay=0, best_overlay_pack=0, max_share=1, best_share_pack=0, max_split=16, bit_width=16, initial_usage_read=1, earliest_use=1, latest_use=2)
- 1: ecmp_metadata.selector (ingress) (highly=0, mau_group_size=1, max_overlay=0, best_overlay_pack=0, max_share=1, best_share_pack=0, max_split=16, bit_width=16, initial_usage_read=1, earliest_use=1, latest_use=2)
- 2: ig_intr_md_for_tm.drop_ctl (ingress) (highly=0, mau_group_size=1, max_overlay=0, best_overlay_pack=0, max_share=2, best_share_pack=0, max_split=1, bit_width=3, initial_usage_read=2, earliest_use=1, latest_use=12)
+ 0: ecmp_metadata.groupId (ingress) (highly=0, mau_group_size=1, max_overlay=0, best_overlay_pack=0, max_share=1, best_share_pack=0, max_split=16, bit_width=16, initial_usage_read=1, earliest_use=0, latest_use=1)
+ 1: ecmp_metadata.selector (ingress) (highly=0, mau_group_size=1, max_overlay=0, best_overlay_pack=0, max_share=1, best_share_pack=0, max_split=16, bit_width=16, initial_usage_read=1, earliest_use=0, latest_use=1)
+ 2: ig_intr_md_for_tm.drop_ctl (ingress) (highly=0, mau_group_size=1, max_overlay=0, best_overlay_pack=0, max_share=2, best_share_pack=0, max_split=1, bit_width=3, initial_usage_read=2, earliest_use=0, latest_use=12)
---------------------------------------
Working on:
@@ -3337,12 +3125,12 @@
Group 1 32 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 2 32 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv32 -- fails False
Group 3 32 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv48 -- fails False
- Group 4 8 bits -- avail 11 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
- Group 5 8 bits -- avail 13 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
+ Group 4 8 bits -- avail 12 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
+ Group 5 8 bits -- avail 14 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 6 8 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 7 8 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 8 16 bits -- avail 10 and promised 1 -- ingress promised 1 and remain 9 and req 0 -- egress promised 0 and remain 8 and req 0 -- as if deparsed False -- container_to_use phv134 -- fails False
- Group 9 16 bits -- avail 13 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
+ Group 9 16 bits -- avail 15 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 10 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv160 -- fails False
Group 11 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv176 -- fails False
Group 12 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv192 -- fails False
@@ -3378,12 +3166,12 @@
Group 1 32 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 2 32 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv32 -- fails False
Group 3 32 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv48 -- fails False
- Group 4 8 bits -- avail 11 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
- Group 5 8 bits -- avail 13 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
+ Group 4 8 bits -- avail 12 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
+ Group 5 8 bits -- avail 14 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 6 8 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 7 8 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 8 16 bits -- avail 9 and promised 1 -- ingress promised 1 and remain 8 and req 0 -- egress promised 0 and remain 8 and req 0 -- as if deparsed False -- container_to_use phv135 -- fails False
- Group 9 16 bits -- avail 13 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
+ Group 9 16 bits -- avail 15 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 10 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv160 -- fails False
Group 11 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv176 -- fails False
Group 12 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 0 -- egress promised 0 and remain 15 and req 0 -- as if deparsed False -- container_to_use phv192 -- fails False
@@ -3419,12 +3207,12 @@
Group 1 32 bits -- avail 16 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 2 32 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 12 and req 0 -- as if deparsed True -- container_to_use phv32 -- fails False
Group 3 32 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 12 and req 0 -- as if deparsed True -- container_to_use phv48 -- fails False
- Group 4 8 bits -- avail 11 and promised 1 -- ingress promised 1 and remain 10 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv69 -- fails False
- Group 5 8 bits -- avail 13 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
+ Group 4 8 bits -- avail 12 and promised 1 -- ingress promised 1 and remain 11 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv68 -- fails False
+ Group 5 8 bits -- avail 14 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 6 8 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv96 -- fails False
Group 7 8 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv112 -- fails False
Group 8 16 bits -- avail 8 and promised 1 -- ingress promised 1 and remain 7 and req 1 -- egress promised 0 and remain 0 and req 0 -- as if deparsed True -- container_to_use phv136 -- fails False
- Group 9 16 bits -- avail 13 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
+ Group 9 16 bits -- avail 15 and promised None -- ingress promised None and remain None and req None -- egress promised None and remain None and req None -- as if deparsed False -- container_to_use None -- fails True
Group 10 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv160 -- fails False
Group 11 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv176 -- fails False
Group 12 16 bits -- avail 16 and promised 1 -- ingress promised 1 and remain 15 and req 1 -- egress promised 0 and remain 8 and req 0 -- as if deparsed True -- container_to_use phv192 -- fails False
@@ -3436,8 +3224,8 @@
case 2: looking at allowed start bits [0, 1, 2, 3, 4, 5, 6, 7]
final start_bit = 5
(1) msb_offset = 8
-***Allocating phv69[7:5] for ig_intr_md_for_tm.drop_ctl[2:0]
->>Event 'pa_meta_init' at time 1504795745.39
+***Allocating phv68[7:5] for ig_intr_md_for_tm.drop_ctl[2:0]
+>>Event 'pa_meta_init' at time 1504859130.96
Took 0.16 seconds
-----------------------------------------------
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.results.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.results.log
index b15a782..e535990 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.results.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/pa.results.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: pa.results.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
Program: ecmp
@@ -17,36 +17,36 @@
| 3 (32) | 0 (0.00%) | 0 (0.00%) | 512 |
| Total for 32 bit | 6 (9.38%) | 192 (9.38%) | 2048 |
| | | | |
-| 4 (8) | 6 (37.50%) | 42 (32.81%) | 128 |
-| 5 (8) | 3 (18.75%) | 22 (17.19%) | 128 |
+| 4 (8) | 5 (31.25%) | 34 (26.56%) | 128 |
+| 5 (8) | 2 (12.50%) | 14 (10.94%) | 128 |
| 6 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
| 7 (8) | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 9 (14.06%) | 64 (12.50%) | 512 |
+| Total for 8 bit | 7 (10.94%) | 48 (9.38%) | 512 |
| | | | |
| 8 (16) | 8 (50.00%) | 121 (47.27%) | 256 |
-| 9 (16) | 3 (18.75%) | 48 (18.75%) | 256 |
+| 9 (16) | 1 (6.25%) | 16 (6.25%) | 256 |
| 10 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 11 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 12 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
| 13 (16) | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 11 (11.46%) | 169 (11.00%) | 1536 |
+| Total for 16 bit | 9 (9.38%) | 137 (8.92%) | 1536 |
| | | | |
-| 14 (32) T | 12 (75.00%) | 384 (75.00%) | 512 |
+| 14 (32) T | 11 (68.75%) | 352 (68.75%) | 512 |
| 15 (32) T | 0 (0.00%) | 0 (0.00%) | 512 |
-| Total for 32 bit | 12 (37.50%) | 384 (37.50%) | 1024 |
+| Total for 32 bit | 11 (34.38%) | 352 (34.38%) | 1024 |
| | | | |
-| 16 (8) T | 9 (56.25%) | 72 (56.25%) | 128 |
+| 16 (8) T | 11 (68.75%) | 88 (68.75%) | 128 |
| 17 (8) T | 0 (0.00%) | 0 (0.00%) | 128 |
-| Total for 8 bit | 9 (28.12%) | 72 (28.12%) | 256 |
+| Total for 8 bit | 11 (34.38%) | 88 (34.38%) | 256 |
| | | | |
-| 18 (16) T | 14 (87.50%) | 224 (87.50%) | 256 |
-| 19 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
+| 18 (16) T | 10 (62.50%) | 160 (62.50%) | 256 |
+| 19 (16) T | 5 (31.25%) | 80 (31.25%) | 256 |
| 20 (16) T | 0 (0.00%) | 0 (0.00%) | 256 |
-| Total for 16 bit | 14 (29.17%) | 224 (29.17%) | 768 |
+| Total for 16 bit | 15 (31.25%) | 240 (31.25%) | 768 |
| | | | |
-| MAU total | 26 (11.61%) | 425 (10.38%) | 4096 |
-| Tagalong total | 35 (31.25%) | 680 (33.20%) | 2048 |
-| Overall total | 61 (18.15%) | 1105 (17.99%) | 6144 |
+| MAU total | 22 (9.82%) | 377 (9.20%) | 4096 |
+| Tagalong total | 37 (33.04%) | 680 (33.20%) | 2048 |
+| Overall total | 59 (17.56%) | 1057 (17.20%) | 6144 |
------------------------------------------------------------------------------
--------------------------------------------
@@ -66,42 +66,38 @@
>> 6 in ingress and 0 in egress
Allocations in Group 4 8 bits
- 8-bit PHV 64 (ingress): phv64[7:1] = -pad-0-[6:0] (tagalong capable)
- 8-bit PHV 64 (ingress): phv64[0:0] = ig_intr_md_for_tm.copy_to_cpu[0:0] (deparsed)
- 8-bit PHV 65 (ingress): phv65[7:0] = ipv4.srcAddr[23:16] (deparsed)
- 8-bit PHV 66 (ingress): phv66[7:0] = ethernet.dstAddr[47:40] (deparsed)
- 8-bit PHV 67 (ingress): phv67[7:0] = ethernet.srcAddr[39:32] (deparsed)
- 8-bit PHV 68 (ingress): phv68[6:6] = --validity_check--metadata_bridge[0:0] (deparsed)
- 8-bit PHV 68 (ingress): phv68[5:5] = --validity_check--udp[0:0] (deparsed)
- 8-bit PHV 68 (ingress): phv68[4:4] = --validity_check--tcp[0:0] (deparsed)
- 8-bit PHV 68 (ingress): phv68[3:3] = --validity_check--ipv4[0:0] (deparsed)
- 8-bit PHV 68 (ingress): phv68[2:2] = --validity_check--ethernet[0:0] (deparsed)
- 8-bit PHV 68 (ingress): phv68[1:1] = --validity_check--packet_out_hdr[0:0] (deparsed)
- 8-bit PHV 68 (ingress): phv68[0:0] = --validity_check--packet_in_hdr[0:0] (deparsed)
- 8-bit PHV 69 (ingress): phv69[7:5] = ig_intr_md_for_tm.drop_ctl[2:0] (deparsed)
- >> 6 in ingress and 0 in egress
+ 8-bit PHV 64 (ingress): phv64[7:0] = ipv4.srcAddr[23:16] (deparsed)
+ 8-bit PHV 65 (ingress): phv65[7:0] = ethernet.dstAddr[47:40] (deparsed)
+ 8-bit PHV 66 (ingress): phv66[7:0] = ethernet.srcAddr[39:32] (deparsed)
+ 8-bit PHV 67 (ingress): phv67[6:6] = --validity_check--metadata_bridge[0:0] (deparsed)
+ 8-bit PHV 67 (ingress): phv67[5:5] = --validity_check--udp[0:0] (deparsed)
+ 8-bit PHV 67 (ingress): phv67[4:4] = --validity_check--tcp[0:0] (deparsed)
+ 8-bit PHV 67 (ingress): phv67[3:3] = --validity_check--ipv4[0:0] (deparsed)
+ 8-bit PHV 67 (ingress): phv67[2:2] = --validity_check--ethernet[0:0] (deparsed)
+ 8-bit PHV 67 (ingress): phv67[1:1] = --validity_check--packet_out_hdr[0:0] (deparsed)
+ 8-bit PHV 67 (ingress): phv67[0:0] = --validity_check--packet_in_hdr[0:0] (deparsed)
+ 8-bit PHV 68 (ingress): phv68[7:5] = ig_intr_md_for_tm.drop_ctl[2:0] (deparsed)
+ >> 5 in ingress and 0 in egress
Allocations in Group 5 8 bits
- 8-bit PHV 80 (egress): phv80[7:1] = -pad-0-[6:0] (tagalong capable)
- 8-bit PHV 80 (egress): phv80[0:0] = ig_intr_md_for_tm.copy_to_cpu[0:0] (deparsed)
- 8-bit PHV 81 (egress): phv81[7:3] = eg_intr_md._pad7[4:0]
- 8-bit PHV 81 (egress): phv81[2:0] = eg_intr_md.egress_cos[2:0] (deparsed)
- 8-bit PHV 82 (egress): phv82[5:5] = --validity_check--udp[0:0] (deparsed)
- 8-bit PHV 82 (egress): phv82[4:4] = --validity_check--tcp[0:0] (deparsed)
- 8-bit PHV 82 (egress): phv82[3:3] = --validity_check--ipv4[0:0] (deparsed)
- 8-bit PHV 82 (egress): phv82[2:2] = --validity_check--ethernet[0:0] (deparsed)
- 8-bit PHV 82 (egress): phv82[1:1] = --validity_check--packet_out_hdr[0:0] (deparsed)
- 8-bit PHV 82 (egress): phv82[0:0] = --validity_check--packet_in_hdr[0:0] (deparsed)
- >> 0 in ingress and 3 in egress
+ 8-bit PHV 80 (egress): phv80[7:3] = eg_intr_md._pad7[4:0]
+ 8-bit PHV 80 (egress): phv80[2:0] = eg_intr_md.egress_cos[2:0] (deparsed)
+ 8-bit PHV 81 (egress): phv81[5:5] = --validity_check--udp[0:0] (deparsed)
+ 8-bit PHV 81 (egress): phv81[4:4] = --validity_check--tcp[0:0] (deparsed)
+ 8-bit PHV 81 (egress): phv81[3:3] = --validity_check--ipv4[0:0] (deparsed)
+ 8-bit PHV 81 (egress): phv81[2:2] = --validity_check--ethernet[0:0] (deparsed)
+ 8-bit PHV 81 (egress): phv81[1:1] = --validity_check--packet_out_hdr[0:0] (deparsed)
+ 8-bit PHV 81 (egress): phv81[0:0] = --validity_check--packet_in_hdr[0:0] (deparsed)
+ >> 0 in ingress and 2 in egress
Allocations in Group 8 16 bits
- 16-bit PHV 128 (ingress): phv128[15:15] = ig_intr_md.resubmit_flag[0:0] (deparsed)
- 16-bit PHV 128 (ingress): phv128[14:14] = ig_intr_md._pad1[0:0] (deparsed)
- 16-bit PHV 128 (ingress): phv128[13:12] = ig_intr_md._pad2[1:0] (deparsed)
- 16-bit PHV 128 (ingress): phv128[11:9] = ig_intr_md._pad3[2:0] (deparsed)
+ 16-bit PHV 128 (ingress): phv128[15:15] = ig_intr_md.resubmit_flag[0:0]
+ 16-bit PHV 128 (ingress): phv128[14:14] = ig_intr_md._pad1[0:0]
+ 16-bit PHV 128 (ingress): phv128[13:12] = ig_intr_md._pad2[1:0]
+ 16-bit PHV 128 (ingress): phv128[11:9] = ig_intr_md._pad3[2:0]
16-bit PHV 128 (ingress): phv128[8:0] = ig_intr_md.ingress_port[8:0] (deparsed)
16-bit PHV 129 (ingress): phv129[15:7] = packet_out_hdr.egress_port[8:0] (deparsed)
- 16-bit PHV 129 (ingress): phv129[15:7] = packet_in_hdr.ingress_port[8:0] (tagalong capable) (deparsed)
+ 16-bit PHV 129 (ingress): phv129[15:7] = packet_in_hdr.ingress_port[8:0] (deparsed)
16-bit PHV 129 (ingress): phv129[6:0] = packet_out_hdr._padding[6:0] (tagalong capable) (deparsed)
16-bit PHV 129 (ingress): phv129[6:0] = packet_in_hdr._padding[6:0] (tagalong capable) (deparsed)
16-bit PHV 130 (ingress): phv130[8:0] = ig_intr_md_for_tm.ucast_egress_port[8:0] (deparsed)
@@ -114,45 +110,40 @@
>> 8 in ingress and 0 in egress
Allocations in Group 9 16 bits
- 16-bit PHV 144 (egress): phv144[15:9] = -pad-1-[6:0] (tagalong capable)
- 16-bit PHV 144 (egress): phv144[8:0] = ig_intr_md.ingress_port[8:0] (deparsed)
- 16-bit PHV 145 (egress): phv145[15:7] = packet_in_hdr.ingress_port[8:0] (deparsed)
- 16-bit PHV 145 (egress): phv145[6:0] = packet_in_hdr._padding[6:0] (tagalong capable) (deparsed)
- 16-bit PHV 146 (egress): phv146[15:9] = eg_intr_md._pad0[6:0]
- 16-bit PHV 146 (egress): phv146[8:0] = eg_intr_md.egress_port[8:0] (deparsed)
- >> 0 in ingress and 3 in egress
+ 16-bit PHV 144 (egress): phv144[15:9] = eg_intr_md._pad0[6:0]
+ 16-bit PHV 144 (egress): phv144[8:0] = eg_intr_md.egress_port[8:0] (deparsed)
+ >> 0 in ingress and 1 in egress
Allocations in Group 14 32 bits (tagalong)
32-bit PHV 256 (ingress): phv256[31:24] = ipv4.identification[7:0] (tagalong capable) (deparsed)
32-bit PHV 256 (ingress): phv256[23:21] = ipv4.flags[2:0] (tagalong capable) (deparsed)
32-bit PHV 256 (ingress): phv256[20:8] = ipv4.fragOffset[12:0] (tagalong capable) (deparsed)
32-bit PHV 256 (ingress): phv256[7:0] = ipv4.ttl[7:0] (tagalong capable) (deparsed)
- 32-bit PHV 257 (ingress): phv257[31:0] = tcp.ackNo[31:0] (tagalong capable) (deparsed)
- 32-bit PHV 258 (ingress): phv258[31:28] = tcp.dataOffset[3:0] (tagalong capable) (deparsed)
- 32-bit PHV 258 (ingress): phv258[27:25] = tcp.res[2:0] (tagalong capable) (deparsed)
- 32-bit PHV 258 (ingress): phv258[24:22] = tcp.ecn[2:0] (tagalong capable) (deparsed)
- 32-bit PHV 258 (ingress): phv258[21:16] = tcp.ctrl[5:0] (tagalong capable) (deparsed)
- 32-bit PHV 258 (ingress): phv258[15:0] = tcp.window[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 259 (ingress): phv259[31:16] = tcp.checksum[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 259 (ingress): phv259[15:0] = tcp.urgentPtr[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 260 (egress): phv260[31:24] = ipv4.ttl[7:0] (tagalong capable) (deparsed)
- 32-bit PHV 260 (egress): phv260[23:16] = ipv4.protocol[7:0] (tagalong capable) (deparsed)
- 32-bit PHV 260 (egress): phv260[15:0] = ipv4.hdrChecksum[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 261 (egress): phv261[31:0] = ipv4.srcAddr[31:0] (tagalong capable) (deparsed)
- 32-bit PHV 262 (egress): phv262[31:0] = ipv4.dstAddr[31:0] (tagalong capable) (deparsed)
- 32-bit PHV 263 (egress): phv263[31:0] = tcp.ackNo[31:0] (tagalong capable) (deparsed)
- 32-bit PHV 263 (egress): phv263[31:16] = udp.length_[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 263 (egress): phv263[15:0] = udp.checksum[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 264 (egress): phv264[31:28] = tcp.dataOffset[3:0] (tagalong capable) (deparsed)
- 32-bit PHV 264 (egress): phv264[27:25] = tcp.res[2:0] (tagalong capable) (deparsed)
- 32-bit PHV 264 (egress): phv264[24:22] = tcp.ecn[2:0] (tagalong capable) (deparsed)
- 32-bit PHV 264 (egress): phv264[21:16] = tcp.ctrl[5:0] (tagalong capable) (deparsed)
- 32-bit PHV 264 (egress): phv264[15:0] = tcp.window[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 265 (egress): phv265[31:16] = tcp.checksum[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 265 (egress): phv265[15:0] = tcp.urgentPtr[15:0] (tagalong capable) (deparsed)
- 32-bit PHV 266 (egress): phv266[31:0] = ethernet.dstAddr[39:8] (tagalong capable) (deparsed)
- 32-bit PHV 267 (egress): phv267[31:0] = ethernet.srcAddr[31:0] (tagalong capable) (deparsed)
- >> 4 in ingress and 8 in egress
+ 32-bit PHV 257 (ingress): phv257[31:28] = tcp.dataOffset[3:0] (tagalong capable) (deparsed)
+ 32-bit PHV 257 (ingress): phv257[27:25] = tcp.res[2:0] (tagalong capable) (deparsed)
+ 32-bit PHV 257 (ingress): phv257[24:22] = tcp.ecn[2:0] (tagalong capable) (deparsed)
+ 32-bit PHV 257 (ingress): phv257[21:16] = tcp.ctrl[5:0] (tagalong capable) (deparsed)
+ 32-bit PHV 257 (ingress): phv257[15:0] = tcp.window[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 258 (ingress): phv258[31:16] = tcp.checksum[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 258 (ingress): phv258[15:0] = tcp.urgentPtr[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 264 (egress): phv264[31:24] = ipv4.ttl[7:0] (tagalong capable) (deparsed)
+ 32-bit PHV 264 (egress): phv264[23:16] = ipv4.protocol[7:0] (tagalong capable) (deparsed)
+ 32-bit PHV 264 (egress): phv264[15:0] = ipv4.hdrChecksum[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 265 (egress): phv265[31:0] = ipv4.srcAddr[31:0] (tagalong capable) (deparsed)
+ 32-bit PHV 266 (egress): phv266[31:0] = ipv4.dstAddr[31:0] (tagalong capable) (deparsed)
+ 32-bit PHV 267 (egress): phv267[31:0] = tcp.ackNo[31:0] (tagalong capable) (deparsed)
+ 32-bit PHV 267 (egress): phv267[31:16] = udp.length_[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 267 (egress): phv267[15:0] = udp.checksum[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 268 (egress): phv268[31:28] = tcp.dataOffset[3:0] (tagalong capable) (deparsed)
+ 32-bit PHV 268 (egress): phv268[27:25] = tcp.res[2:0] (tagalong capable) (deparsed)
+ 32-bit PHV 268 (egress): phv268[24:22] = tcp.ecn[2:0] (tagalong capable) (deparsed)
+ 32-bit PHV 268 (egress): phv268[21:16] = tcp.ctrl[5:0] (tagalong capable) (deparsed)
+ 32-bit PHV 268 (egress): phv268[15:0] = tcp.window[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 269 (egress): phv269[31:16] = tcp.checksum[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 269 (egress): phv269[15:0] = tcp.urgentPtr[15:0] (tagalong capable) (deparsed)
+ 32-bit PHV 270 (egress): phv270[31:0] = ethernet.dstAddr[39:8] (tagalong capable) (deparsed)
+ 32-bit PHV 271 (egress): phv271[31:0] = ethernet.srcAddr[31:0] (tagalong capable) (deparsed)
+ >> 3 in ingress and 8 in egress
Allocations in Group 16 8 bits (tagalong)
8-bit PHV 288 (ingress): phv288[7:4] = ipv4.version[3:0] (tagalong capable) (deparsed)
@@ -161,74 +152,68 @@
8-bit PHV 289 (ingress): phv289[7:0] = udp.length_[15:8] (tagalong capable) (deparsed)
8-bit PHV 290 (ingress): phv290[7:0] = tcp.srcPort[7:0] (tagalong capable) (deparsed)
8-bit PHV 290 (ingress): phv290[7:0] = udp.length_[7:0] (tagalong capable) (deparsed)
- 8-bit PHV 292 (egress): phv292[7:4] = ipv4.version[3:0] (tagalong capable) (deparsed)
- 8-bit PHV 292 (egress): phv292[3:0] = ipv4.ihl[3:0] (tagalong capable) (deparsed)
- 8-bit PHV 293 (egress): phv293[7:0] = ipv4.diffserv[7:0] (tagalong capable) (deparsed)
- 8-bit PHV 294 (egress): phv294[7:0] = tcp.srcPort[15:8] (tagalong capable) (deparsed)
- 8-bit PHV 294 (egress): phv294[7:0] = udp.srcPort[15:8] (tagalong capable) (deparsed)
- 8-bit PHV 295 (egress): phv295[7:0] = tcp.srcPort[7:0] (tagalong capable) (deparsed)
- 8-bit PHV 295 (egress): phv295[7:0] = udp.srcPort[7:0] (tagalong capable) (deparsed)
- 8-bit PHV 296 (egress): phv296[7:0] = ethernet.dstAddr[47:40] (tagalong capable) (deparsed)
- 8-bit PHV 297 (egress): phv297[7:0] = ethernet.srcAddr[39:32] (tagalong capable) (deparsed)
- >> 3 in ingress and 6 in egress
+ 8-bit PHV 291 (ingress): phv291[7:0] = tcp.dstPort[15:8] (tagalong capable) (deparsed)
+ 8-bit PHV 292 (ingress): phv292[7:0] = tcp.dstPort[7:0] (tagalong capable) (deparsed)
+ 8-bit PHV 296 (egress): phv296[7:4] = ipv4.version[3:0] (tagalong capable) (deparsed)
+ 8-bit PHV 296 (egress): phv296[3:0] = ipv4.ihl[3:0] (tagalong capable) (deparsed)
+ 8-bit PHV 297 (egress): phv297[7:0] = ipv4.diffserv[7:0] (tagalong capable) (deparsed)
+ 8-bit PHV 298 (egress): phv298[7:0] = tcp.srcPort[15:8] (tagalong capable) (deparsed)
+ 8-bit PHV 298 (egress): phv298[7:0] = udp.srcPort[15:8] (tagalong capable) (deparsed)
+ 8-bit PHV 299 (egress): phv299[7:0] = tcp.srcPort[7:0] (tagalong capable) (deparsed)
+ 8-bit PHV 299 (egress): phv299[7:0] = udp.srcPort[7:0] (tagalong capable) (deparsed)
+ 8-bit PHV 300 (egress): phv300[7:0] = ethernet.dstAddr[47:40] (tagalong capable) (deparsed)
+ 8-bit PHV 301 (egress): phv301[7:0] = ethernet.srcAddr[39:32] (tagalong capable) (deparsed)
+ >> 5 in ingress and 6 in egress
Allocations in Group 18 16 bits (tagalong)
16-bit PHV 320 (ingress): phv320[15:8] = ipv4.diffserv[7:0] (tagalong capable) (deparsed)
16-bit PHV 320 (ingress): phv320[7:0] = ipv4.totalLen[15:8] (tagalong capable) (deparsed)
16-bit PHV 321 (ingress): phv321[15:8] = ipv4.totalLen[7:0] (tagalong capable) (deparsed)
16-bit PHV 321 (ingress): phv321[7:0] = ipv4.identification[15:8] (tagalong capable) (deparsed)
- 16-bit PHV 322 (ingress): phv322[15:0] = tcp.dstPort[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 322 (ingress): phv322[15:0] = tcp.seqNo[31:16] (tagalong capable) (deparsed)
16-bit PHV 322 (ingress): phv322[15:0] = udp.checksum[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 323 (ingress): phv323[15:0] = tcp.seqNo[31:16] (tagalong capable) (deparsed)
- 16-bit PHV 324 (ingress): phv324[15:0] = tcp.seqNo[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 326 (egress): phv326[15:0] = ipv4.totalLen[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 327 (egress): phv327[15:0] = ipv4.identification[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 328 (egress): phv328[15:13] = ipv4.flags[2:0] (tagalong capable) (deparsed)
- 16-bit PHV 328 (egress): phv328[12:0] = ipv4.fragOffset[12:0] (tagalong capable) (deparsed)
- 16-bit PHV 329 (egress): phv329[15:0] = tcp.dstPort[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 329 (egress): phv329[15:0] = udp.dstPort[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 330 (egress): phv330[15:0] = tcp.seqNo[31:16] (tagalong capable) (deparsed)
- 16-bit PHV 331 (egress): phv331[15:0] = tcp.seqNo[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 332 (egress): phv332[15:8] = ethernet.dstAddr[7:0] (tagalong capable) (deparsed)
- 16-bit PHV 332 (egress): phv332[7:0] = ethernet.srcAddr[47:40] (tagalong capable) (deparsed)
- 16-bit PHV 333 (egress): phv333[15:0] = ethernet.etherType[15:0] (tagalong capable) (deparsed)
- 16-bit PHV 334 (egress): phv334[15:7] = packet_out_hdr.egress_port[8:0] (tagalong capable) (deparsed)
- 16-bit PHV 334 (egress): phv334[6:0] = packet_out_hdr._padding[6:0] (tagalong capable) (deparsed)
- >> 5 in ingress and 9 in egress
+ 16-bit PHV 323 (ingress): phv323[15:0] = tcp.seqNo[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 324 (ingress): phv324[15:0] = tcp.ackNo[31:16] (tagalong capable) (deparsed)
+ 16-bit PHV 325 (ingress): phv325[15:0] = tcp.ackNo[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 332 (egress): phv332[15:0] = ipv4.totalLen[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 333 (egress): phv333[15:0] = ipv4.identification[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 334 (egress): phv334[15:13] = ipv4.flags[2:0] (tagalong capable) (deparsed)
+ 16-bit PHV 334 (egress): phv334[12:0] = ipv4.fragOffset[12:0] (tagalong capable) (deparsed)
+ 16-bit PHV 335 (egress): phv335[15:0] = tcp.dstPort[15:0] (tagalong capable) (deparsed)
+ >> 6 in ingress and 4 in egress
+
+Allocations in Group 19 16 bits (tagalong)
+ 16-bit PHV 336 (egress): phv336[15:0] = tcp.seqNo[31:16] (tagalong capable) (deparsed)
+ 16-bit PHV 336 (egress): phv336[15:0] = udp.dstPort[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 337 (egress): phv337[15:0] = tcp.seqNo[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 338 (egress): phv338[15:8] = ethernet.dstAddr[7:0] (tagalong capable) (deparsed)
+ 16-bit PHV 338 (egress): phv338[7:0] = ethernet.srcAddr[47:40] (tagalong capable) (deparsed)
+ 16-bit PHV 339 (egress): phv339[15:0] = ethernet.etherType[15:0] (tagalong capable) (deparsed)
+ 16-bit PHV 340 (egress): phv340[15:7] = packet_out_hdr.egress_port[8:0] (tagalong capable) (deparsed)
+ 16-bit PHV 340 (egress): phv340[15:7] = packet_in_hdr.ingress_port[8:0] (tagalong capable) (deparsed)
+ 16-bit PHV 340 (egress): phv340[6:0] = packet_out_hdr._padding[6:0] (tagalong capable) (deparsed)
+ 16-bit PHV 340 (egress): phv340[6:0] = packet_in_hdr._padding[6:0] (tagalong capable) (deparsed)
+ >> 0 in ingress and 5 in egress
Final POV layout (ingress):
- 32: --validity_check--packet_in_hdr (ingress) in container 68
- 33: --validity_check--packet_out_hdr (ingress) in container 68
- 34: --validity_check--ethernet (ingress) in container 68
- 35: --validity_check--ipv4 (ingress) in container 68
- 36: --validity_check--tcp (ingress) in container 68
- 37: --validity_check--udp (ingress) in container 68
- 38: --validity_check--metadata_bridge (ingress) in container 68
+ 32: --validity_check--packet_in_hdr (ingress) in container 67
+ 33: --validity_check--packet_out_hdr (ingress) in container 67
+ 34: --validity_check--ethernet (ingress) in container 67
+ 35: --validity_check--ipv4 (ingress) in container 67
+ 36: --validity_check--tcp (ingress) in container 67
+ 37: --validity_check--udp (ingress) in container 67
+ 38: --validity_check--metadata_bridge (ingress) in container 67
Final POV layout (egress):
- 0: --validity_check--packet_in_hdr (egress) in container 82
- 1: --validity_check--packet_out_hdr (egress) in container 82
- 2: --validity_check--ethernet (egress) in container 82
- 3: --validity_check--ipv4 (egress) in container 82
- 4: --validity_check--tcp (egress) in container 82
- 5: --validity_check--udp (egress) in container 82
+ 0: --validity_check--packet_in_hdr (egress) in container 81
+ 1: --validity_check--packet_out_hdr (egress) in container 81
+ 2: --validity_check--ethernet (egress) in container 81
+ 3: --validity_check--ipv4 (egress) in container 81
+ 4: --validity_check--tcp (egress) in container 81
+ 5: --validity_check--udp (egress) in container 81
--------------------------------------------
- Bridged metadata layout (9 bytes)
+ Bridged metadata layout (6 bytes)
--------------------------------------------
-Final ingress layout:
- -pad-0-[6:0]
- ig_intr_md_for_tm.copy_to_cpu[0:0]
- ig_intr_md.resubmit_flag[0:0]
- ig_intr_md._pad1[0:0]
- ig_intr_md._pad2[1:0]
- ig_intr_md._pad3[2:0]
- ig_intr_md.ingress_port[8:0]
-
-Final egress layout:
- -pad-0-[6:0]
- ig_intr_md_for_tm.copy_to_cpu[0:0]
- -pad-1-[6:0]
- ig_intr_md.ingress_port[8:0]
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.calcfields.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.calcfields.log
index 910a68e..f521d95 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.calcfields.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.calcfields.log
@@ -1,35 +1,37 @@
+---------------------------------------------------------------------+
| Log file: parde.calcfields.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
Reserving 0 16-bit ingress tphvs for residual checksums
Reserving 0 16-bit egress tphvs for residual checksums
Need 0 POV bits for checksum update control
-Number of reachable states from state parse_tcp : 1
+Number of reachable states from state parse_tcp//spilled : 1
+Number of reachable states from state parse_tcp : 2
Number of reachable states from state parse_udp : 1
-Number of reachable states from state parse_ipv4 : 3
-Number of reachable states from state parse_ethernet : 4
-Number of reachable states from state parse_pkt_in : 5
-Number of reachable states from state parse_pkt_out : 5
-Number of reachable states from state default_parser : 6
-Number of reachable states from state start : 8
-Number of reachable states from state <POV initialization>_<Ingress intrinsic metadata>_<Phase 0> : 9
-Number of reachable states from state <Shim start state> : 10
+Number of reachable states from state parse_ipv4 : 4
+Number of reachable states from state parse_ethernet : 5
+Number of reachable states from state parse_pkt_in : 6
+Number of reachable states from state parse_pkt_out : 6
+Number of reachable states from state default_parser : 7
+Number of reachable states from state start : 9
+Number of reachable states from state <POV initialization>_<Ingress intrinsic metadata>_<Phase 0> : 10
+Number of reachable states from state <Shim start state> : 11
parser_state_calculations:[
- parse_tcp_140208442752208
- parse_udp_140208440733776
- parse_ipv4_140208442749200
- parse_ethernet_140208440786256
- parse_pkt_in_140208440785552
- parse_pkt_out_140208440734864
- default_parser_140208440734672
- start_140208442750992
- <Phase 0>_140208442851280
- <Ingress intrinsic metadata>_140208442850960
- <POV initialization>_140208442802576
- <Shim start state>_140208442802896
+ parse_tcp_139953904595664
+ parse_tcp_139953905676240
+ parse_udp_139953897530320
+ parse_ipv4_139953905675408
+ parse_ethernet_139953905672592
+ parse_pkt_in_139953905675344
+ parse_pkt_out_139953897531408
+ default_parser_139953897531216
+ start_139953905674832
+ <Phase 0>_139953905422864
+ <Ingress intrinsic metadata>_139953905422544
+ <POV initialization>_139953905423248
+ <Shim start state>_139953905423568
]
parser_calculations: [
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.config.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.config.log
index 22d729d..42c8ef3 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.config.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.config.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: parde.config.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
Configuring deparser.inp.iim.ii_phv_csum.csum_cfg[0].csum_cfg_entry[0].zero_m_s_b = 1
@@ -16059,12 +16059,12 @@
63 | g1w31:
|
8 bits
- 64 | I g2w0: [ig_intr_md_for_tm.copy_to_cpu]
- 65 | I g2w1: [ipv4.srcAddr[23:16]]
- 66 | I g2w2: [ethernet.dstAddr[47:40]]
- 67 | I g2w3: [ethernet.srcAddr[39:32]]
- 68 | I g2w4: [POV[39:32]]
- 69 | I g2w5: [ig_intr_md_for_tm.drop_ctl]
+ 64 | I g2w0: [ipv4.srcAddr[23:16]]
+ 65 | I g2w1: [ethernet.dstAddr[47:40]]
+ 66 | I g2w2: [ethernet.srcAddr[39:32]]
+ 67 | I g2w3: [POV[39:32]]
+ 68 | I g2w4: [ig_intr_md_for_tm.drop_ctl]
+ 69 | g2w5:
70 | g2w6:
71 | g2w7:
72 | g2w8:
@@ -16075,9 +16075,9 @@
77 | g2w13:
78 | g2w14:
79 | g2w15:
- 80 | E g2w16: [ig_intr_md_for_tm.copy_to_cpu]
- 81 | E g2w17: [eg_intr_md._pad7, eg_intr_md.egress_cos]
- 82 | E g2w18: [POV[7:0]]
+ 80 | E g2w16: [eg_intr_md._pad7, eg_intr_md.egress_cos]
+ 81 | E g2w17: [POV[7:0]]
+ 82 | g2w18:
83 | g2w19:
84 | g2w20:
85 | g2w21:
@@ -16143,9 +16143,9 @@
141 | g4w13:
142 | g4w14:
143 | g4w15:
- 144 | E g4w16: [ig_intr_md.ingress_port]
- 145 | E g4w17: [packet_in_hdr.ingress_port, packet_in_hdr._padding]
- 146 | E g4w18: [eg_intr_md._pad0, eg_intr_md.egress_port]
+ 144 | E g4w16: [eg_intr_md._pad0, eg_intr_md.egress_port]
+ 145 | g4w17:
+ 146 | g4w18:
147 | g4w19:
148 | g4w20:
149 | g4w21:
@@ -16232,21 +16232,21 @@
|
32 bits
256 | I g8w0: [ipv4.identification[7:0], ipv4.flags, ipv4.fragOffset, ipv4.ttl]
- 257 | I g8w1: [tcp.ackNo]
- 258 | I g8w2: [tcp.dataOffset, tcp.res, tcp.ecn, tcp.ctrl, tcp.window]
- 259 | I g8w3: [tcp.checksum, tcp.urgentPtr]
- 260 | E g8w4: [ipv4.ttl, ipv4.protocol, ipv4.hdrChecksum]
- 261 | E g8w5: [ipv4.srcAddr]
- 262 | E g8w6: [ipv4.dstAddr]
- 263 | E g8w7: [tcp.ackNo, udp.length_, udp.checksum]
- 264 | E g8w8: [tcp.dataOffset, tcp.res, tcp.ecn, tcp.ctrl, tcp.window]
- 265 | E g8w9: [tcp.checksum, tcp.urgentPtr]
- 266 | E g8w10: [ethernet.dstAddr[39:8]]
- 267 | E g8w11: [ethernet.srcAddr[31:0]]
- 268 | g8w12:
- 269 | g8w13:
- 270 | g8w14:
- 271 | g8w15:
+ 257 | I g8w1: [tcp.dataOffset, tcp.res, tcp.ecn, tcp.ctrl, tcp.window]
+ 258 | I g8w2: [tcp.checksum, tcp.urgentPtr]
+ 259 | g8w3:
+ 260 | g8w4:
+ 261 | g8w5:
+ 262 | g8w6:
+ 263 | g8w7:
+ 264 | E g8w8: [ipv4.ttl, ipv4.protocol, ipv4.hdrChecksum]
+ 265 | E g8w9: [ipv4.srcAddr]
+ 266 | E g8w10: [ipv4.dstAddr]
+ 267 | E g8w11: [tcp.ackNo, udp.length_, udp.checksum]
+ 268 | E g8w12: [tcp.dataOffset, tcp.res, tcp.ecn, tcp.ctrl, tcp.window]
+ 269 | E g8w13: [tcp.checksum, tcp.urgentPtr]
+ 270 | E g8w14: [ethernet.dstAddr[39:8]]
+ 271 | E g8w15: [ethernet.srcAddr[31:0]]
272 | g8w16:
273 | g8w17:
274 | g8w18:
@@ -16268,17 +16268,17 @@
288 | I g9w0: [ipv4.version, ipv4.ihl]
289 | I g9w1: [tcp.srcPort[15:8], udp.length_[15:8]]
290 | I g9w2: [tcp.srcPort[7:0], udp.length_[7:0]]
- 291 | g9w3:
- 292 | E g9w4: [ipv4.version, ipv4.ihl]
- 293 | E g9w5: [ipv4.diffserv]
- 294 | E g9w6: [tcp.srcPort[15:8], udp.srcPort[15:8]]
- 295 | E g9w7: [tcp.srcPort[7:0], udp.srcPort[7:0]]
- 296 | E g9w8: [ethernet.dstAddr[47:40]]
- 297 | E g9w9: [ethernet.srcAddr[39:32]]
- 298 | g9w10:
- 299 | g9w11:
- 300 | g9w12:
- 301 | g9w13:
+ 291 | I g9w3: [tcp.dstPort[15:8]]
+ 292 | I g9w4: [tcp.dstPort[7:0]]
+ 293 | g9w5:
+ 294 | g9w6:
+ 295 | g9w7:
+ 296 | E g9w8: [ipv4.version, ipv4.ihl]
+ 297 | E g9w9: [ipv4.diffserv]
+ 298 | E g9w10: [tcp.srcPort[15:8], udp.srcPort[15:8]]
+ 299 | E g9w11: [tcp.srcPort[7:0], udp.srcPort[7:0]]
+ 300 | E g9w12: [ethernet.dstAddr[47:40]]
+ 301 | E g9w13: [ethernet.srcAddr[39:32]]
302 | g9w14:
303 | g9w15:
304 | g9w16:
@@ -16301,25 +16301,25 @@
16 bits
320 | I g10w0: [ipv4.diffserv, ipv4.totalLen[15:8]]
321 | I g10w1: [ipv4.totalLen[7:0], ipv4.identification[15:8]]
- 322 | I g10w2: [tcp.dstPort, udp.checksum]
- 323 | I g10w3: [tcp.seqNo[31:16]]
- 324 | I g10w4: [tcp.seqNo[15:0]]
- 325 | g10w5:
- 326 | E g10w6: [ipv4.totalLen]
- 327 | E g10w7: [ipv4.identification]
- 328 | E g10w8: [ipv4.flags, ipv4.fragOffset]
- 329 | E g10w9: [tcp.dstPort, udp.dstPort]
- 330 | E g10w10: [tcp.seqNo[31:16]]
- 331 | E g10w11: [tcp.seqNo[15:0]]
- 332 | E g10w12: [ethernet.dstAddr[7:0], ethernet.srcAddr[47:40]]
- 333 | E g10w13: [ethernet.etherType]
- 334 | E g10w14: [packet_out_hdr.egress_port, packet_out_hdr._padding]
- 335 | g10w15:
- 336 | g10w16:
- 337 | g10w17:
- 338 | g10w18:
- 339 | g10w19:
- 340 | g10w20:
+ 322 | I g10w2: [tcp.seqNo[31:16], udp.checksum]
+ 323 | I g10w3: [tcp.seqNo[15:0]]
+ 324 | I g10w4: [tcp.ackNo[31:16]]
+ 325 | I g10w5: [tcp.ackNo[15:0]]
+ 326 | g10w6:
+ 327 | g10w7:
+ 328 | g10w8:
+ 329 | g10w9:
+ 330 | g10w10:
+ 331 | g10w11:
+ 332 | E g10w12: [ipv4.totalLen]
+ 333 | E g10w13: [ipv4.identification]
+ 334 | E g10w14: [ipv4.flags, ipv4.fragOffset]
+ 335 | E g10w15: [tcp.dstPort]
+ 336 | E g10w16: [tcp.seqNo[31:16], udp.dstPort]
+ 337 | E g10w17: [tcp.seqNo[15:0]]
+ 338 | E g10w18: [ethernet.dstAddr[7:0], ethernet.srcAddr[47:40]]
+ 339 | E g10w19: [ethernet.etherType]
+ 340 | E g10w20: [packet_out_hdr.egress_port, packet_out_hdr._padding, packet_in_hdr.ingress_port, packet_in_hdr._padding]
341 | g10w21:
342 | g10w22:
343 | g10w23:
@@ -16363,6 +16363,7 @@
7: parse_pkt_out
8: <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
9: start
+ 10: parse_tcp//spilled
Egress:
0: <Shim start state>
1: parse_ethernet
@@ -16371,7 +16372,7 @@
4: parse_udp
5: default_parser
6: parse_pkt_out
- 7: <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
+ 7: <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>_start
8: parse_pkt_in
---------------
POV layout:
@@ -16395,11 +16396,8 @@
6-254 | -
---------------
Bridged metadata:
-Ingress:
-[64, 128]
-Egress:
-[80, 144]
+[None]
---------------
Deparse order:
-Ingress: ['metadata_bridge', '_bridged_intr_md_', 'packet_out_hdr', 'packet_in_hdr', 'ethernet', 'ipv4', 'tcp', 'udp']
-Egress: ['packet_out_hdr', 'packet_in_hdr', 'ethernet', 'ipv4', 'tcp', 'udp']
+Ingress: ['metadata_bridge', '_bridged_intr_md_', 'packet_out_hdr', 'packet_in_hdr', 'ethernet', 'ipv4', 'udp', 'tcp']
+Egress: ['packet_out_hdr', 'packet_in_hdr', 'ethernet', 'ipv4', 'udp', 'tcp']
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.error.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.error.log
index 34ac11a..a2284a1 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.error.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.error.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: parde.error.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.log
index 2a5c0e4..1372924 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parde.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: parde.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
># Begin digest init (pre-PHV)
@@ -14,20 +14,18 @@
># End digest PHV reservations
># Begin digest init (post-PHV)
># End digest init (post-PHV)
-Bridge-MF:ig_intr_md_for_tm.copy_to_cpu
-Bridge-MF:ig_intr_md.ingress_port
Found parser entry point: start
># Begin unroll of HLIR parse graph
>## Create shadow parse graph and find loops
>## Entrypoint 'p4_parse_state.start'
-Creating shadow state: 'p4_parse_state.start' -> 'shadow_state (start, 140208440786448)'
-Creating shadow state: 'p4_parse_state.parse_pkt_in' -> 'shadow_state (parse_pkt_in, 140208440786000)'
-Creating shadow state: 'p4_parse_state.parse_ethernet' -> 'shadow_state (parse_ethernet, 140208440785808)'
-Creating shadow state: 'p4_parse_state.parse_ipv4' -> 'shadow_state (parse_ipv4, 140208442749264)'
-Creating shadow state: 'p4_parse_state.parse_tcp' -> 'shadow_state (parse_tcp, 140208442749456)'
-Creating shadow state: 'p4_parse_state.parse_udp' -> 'shadow_state (parse_udp, 140208442749392)'
-Creating shadow state: 'p4_parse_state.default_parser' -> 'shadow_state (default_parser, 140208442749520)'
-Creating shadow state: 'p4_parse_state.parse_pkt_out' -> 'shadow_state (parse_pkt_out, 140208442749584)'
+Creating shadow state: 'p4_parse_state.start' -> 'shadow_state (start, 139953897373264)'
+Creating shadow state: 'p4_parse_state.parse_pkt_in' -> 'shadow_state (parse_pkt_in, 139953897373136)'
+Creating shadow state: 'p4_parse_state.parse_ethernet' -> 'shadow_state (parse_ethernet, 139953905673296)'
+Creating shadow state: 'p4_parse_state.parse_ipv4' -> 'shadow_state (parse_ipv4, 139953905672656)'
+Creating shadow state: 'p4_parse_state.parse_tcp' -> 'shadow_state (parse_tcp, 139953905673360)'
+Creating shadow state: 'p4_parse_state.parse_udp' -> 'shadow_state (parse_udp, 139953905672272)'
+Creating shadow state: 'p4_parse_state.default_parser' -> 'shadow_state (default_parser, 139953905673424)'
+Creating shadow state: 'p4_parse_state.parse_pkt_out' -> 'shadow_state (parse_pkt_out, 139953905673488)'
># End unroll of HLIR parse graph
># Begin deparser init
>## Create records for gress 0
@@ -50,8 +48,8 @@
>## Build field ordering for record 'packet_in_hdr'
>## Build field ordering for record 'ethernet'
>## Build field ordering for record 'ipv4'
->## Build field ordering for record 'tcp'
>## Build field ordering for record 'udp'
+>## Build field ordering for record 'tcp'
>## Create records for gress 1
Skipping metadata header 'p4_header_instance.standard_metadata'
Skipping intrinsic header 'p4_header_instance.ig_intr_md'
@@ -72,8 +70,8 @@
>## Build field ordering for record 'packet_in_hdr'
>## Build field ordering for record 'ethernet'
>## Build field ordering for record 'ipv4'
->## Build field ordering for record 'tcp'
>## Build field ordering for record 'udp'
+>## Build field ordering for record 'tcp'
Deparse bmeta_ig_intr_md header
>## Create deparser bridge_ig_intr_md record
Add container 128 for ig_intr_md.resubmit_flag to bmeta_ig_intr_md
@@ -82,7 +80,6 @@
Add container 128 for ig_intr_md._pad3 to bmeta_ig_intr_md
Add container 128 for ig_intr_md.ingress_port to bmeta_ig_intr_md
>## Create deparser bridge record
-Bridge contains user-provided data
># End deparser init
Constructing parse graph for entry point start on ingress
Constructing parse graph for entry point start on egress
@@ -92,52 +89,57 @@
Stretch extraction of ingress_port to state <Ingress intrinsic metadata> offset 7
Stretch extraction of ig_intr_md.ingress_port to state <_parse_bridged_ingress_intrinsic_metadata> offset 7
># Begin scraping deparser POV allocation from raw PHV allocation
-PHV layout: [0, 0, 0, 0, 68, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
+PHV layout: [0, 0, 0, 0, 67, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
>## Scraping individual POV records
-POV 37 -> udp
-POV 32 -> packet_in_hdr
-POV 33 -> packet_out_hdr
-POV 34 -> ethernet
-POV 38 -> pov_bmeta
POV 35 -> ipv4
POV 36 -> tcp
+POV 37 -> udp
+POV 32 -> packet_in_hdr
+POV 38 -> pov_bmeta
+POV 33 -> packet_out_hdr
+POV 34 -> ethernet
>## Setting up array bits
># End scraping deparser POV allocation from raw PHV allocation
># Begin parser POV rewrite
>## Filling in POV init state
>## Rewriting parser POV extractions
-POV for metadata_bridge -> PHV 68 |= 0x40
-POV for packet_in_hdr -> PHV 68 |= 0x1
-POV for ethernet -> PHV 68 |= 0x4
-POV for ipv4 -> PHV 68 |= 0x8
-POV for tcp -> PHV 68 |= 0x10
-POV for udp -> PHV 68 |= 0x20
-POV for packet_out_hdr -> PHV 68 |= 0x2
+POV for metadata_bridge -> PHV 67 |= 0x40
+POV for packet_in_hdr -> PHV 67 |= 0x1
+POV for ethernet -> PHV 67 |= 0x4
+POV for ipv4 -> PHV 67 |= 0x8
+POV for tcp -> PHV 67 |= 0x10
+POV for udp -> PHV 67 |= 0x20
+POV for packet_out_hdr -> PHV 67 |= 0x2
POV for ig_intr_md -> dropped (no deparser record)
POV for _bridged_intr_md_ -> PHV 0 |= 0x10000
>## Sampling not detected, deparsing at least 1 POV byte
>## Adding POV containers to metadata bridge: [0]
>## Set POV skip state's shift amount to 32
># Begin scraping deparser POV allocation from raw PHV allocation
-PHV layout: [82, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
+PHV layout: [81, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
>## Scraping individual POV records
+POV 3 -> ipv4
+POV 4 -> tcp
POV 5 -> udp
POV 0 -> packet_in_hdr
POV 1 -> packet_out_hdr
POV 2 -> ethernet
-POV 3 -> ipv4
-POV 4 -> tcp
>## Setting up array bits
># End scraping deparser POV allocation from raw PHV allocation
># Begin parser POV rewrite
>## Filling in POV init state
>## Rewriting parser POV extractions
-POV for packet_in_hdr -> PHV 82 |= 0x1
-POV for ethernet -> PHV 82 |= 0x4
-POV for ipv4 -> PHV 82 |= 0x8
-POV for tcp -> PHV 82 |= 0x10
-POV for udp -> PHV 82 |= 0x20
-POV for packet_out_hdr -> PHV 82 |= 0x2
+POV for packet_in_hdr -> PHV 81 |= 0x1
+POV for ethernet -> PHV 81 |= 0x4
+POV for ipv4 -> PHV 81 |= 0x8
+POV for tcp -> PHV 81 |= 0x10
+POV for udp -> PHV 81 |= 0x20
+POV for packet_out_hdr -> PHV 81 |= 0x2
+Linear Chain parse_tcp -> parse_tcp//spilled
+Try merge parse_tcp <- parse_tcp//spilled
+merge output at offset 24
+Ran out of 8b extractors
+states will not be partially merged since S2 is end of chain
Linear Chain parse_pkt_in -> parse_ethernet
Try merge parse_pkt_in <- parse_ethernet
Multiple paths to state S2 : parse_ethernet <- 3
@@ -197,7 +199,7 @@
Multiple paths to state S2 : start <- 2
Remove state <Ingress intrinsic metadata>
Remove state <Phase 0>
-assign ids to 10 states, dir = 0
+assign ids to 11 states, dir = 0
------
State : <Shim start state>
shift: 0B
@@ -210,7 +212,7 @@
State : parse_pkt_in
shift: 2B
match_reservations: []
-outputs[addr, width]: ([68, 8], [129, 16])
+outputs[addr, width]: ([67, 8], [129, 16])
match_extractions: []
next state parse_ethernet val 0 mask [False]
parent state start
@@ -219,7 +221,7 @@
State : parse_ethernet
shift: 14B
match_reservations: []
-outputs[addr, width]: ([68, 8], [66, 8], [3, 32], [132, 16], [67, 8], [4, 32], [133, 16])
+outputs[addr, width]: ([67, 8], [65, 8], [3, 32], [132, 16], [66, 8], [4, 32], [133, 16])
branch on = etherType, offset = 96b, dst = parse_ethernet
match_extractions: [match_window(hw_id=0, width=16)]
match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
@@ -232,7 +234,7 @@
State : parse_ipv4
shift: 20B
match_reservations: []
-outputs[addr, width]: ([68, 8], [288, 8], [320, 16], [321, 16], [256, 32], [1, 32], [65, 8], [131, 16], [2, 32])
+outputs[addr, width]: ([67, 8], [288, 8], [320, 16], [321, 16], [256, 32], [1, 32], [64, 8], [131, 16], [2, 32])
branch on = fragOffset, offset = 51b, dst = parse_ipv4
branch on = protocol, offset = 72b, dst = parse_ipv4
match_extractions: [match_window(hw_id=0, width=16), match_window(hw_id=2, width=8)]
@@ -244,17 +246,18 @@
------
State : parse_tcp
-shift: 20B
+shift: 0B
match_reservations: []
-outputs[addr, width]: ([68, 8], [289, 8], [290, 8], [322, 16], [323, 16], [324, 16], [257, 32], [258, 32], [259, 32])
+outputs[addr, width]: ([67, 8], [289, 8], [290, 8], [291, 8], [322, 16], [323, 16], [324, 16], [325, 16], [257, 32], [258, 32])
match_extractions: []
+next state parse_tcp//spilled val 0 mask [False]
parent state parse_ipv4
------
State : parse_udp
shift: 8B
match_reservations: []
-outputs[addr, width]: ([68, 8], [5, 32], [289, 8], [290, 8], [322, 16])
+outputs[addr, width]: ([67, 8], [5, 32], [289, 8], [290, 8], [322, 16])
match_extractions: []
parent state parse_ipv4
@@ -274,7 +277,7 @@
State : parse_pkt_out
shift: 2B
match_reservations: []
-outputs[addr, width]: ([68, 8], [129, 16])
+outputs[addr, width]: ([67, 8], [129, 16])
match_extractions: []
next state parse_ethernet val 0 mask [False]
parent state default_parser
@@ -297,7 +300,7 @@
State : start
shift: 0B
match_reservations: [match_window(hw_id=0, width=16)]
-outputs[addr, width]: ([68, 8],)
+outputs[addr, width]: ([67, 8],)
branch on = None, offset = 96b, dst = start
match_extractions: [match_window(hw_id=2, width=8)]
match key = [0, 1, 2, 3, 4, 5, 6, 7]
@@ -305,6 +308,14 @@
next state default_parser val 0 mask [False]
parent state <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>
+------
+State : parse_tcp//spilled
+shift: 20B
+match_reservations: []
+outputs[addr, width]: ([292, 8],)
+match_extractions: []
+parent state parse_tcp
+
Linear Chain parse_pkt_in -> parse_ethernet
Try merge parse_pkt_in <- parse_ethernet
Multiple paths to state S2 : parse_ethernet <- 3
@@ -326,7 +337,7 @@
S2: State : <Egress intrinsic metadata>
shift: 3B
match_reservations: []
-outputs[addr, width]: ([146, 16], [81, 8])
+outputs[addr, width]: ([144, 16], [80, 8])
branch on = None, offset = 24b, dst = <Egress intrinsic metadata>
match_extractions: []
next state <POV skip> val 0 mask [False]
@@ -340,7 +351,7 @@
S1: State : <POV initialization>_<Egress intrinsic metadata>
shift: 3B
match_reservations: []
-outputs[addr, width]: ([146, 16], [81, 8])
+outputs[addr, width]: ([144, 16], [80, 8])
branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>
match_extractions: []
next state <POV skip> val 0 mask [False]
@@ -352,45 +363,20 @@
match_reservations: []
outputs[addr, width]: ()
match_extractions: []
-next state <Metadata bridge> val 0 mask [False]
+next state <_parse_bridged_ingress_intrinsic_metadata> val 0 mask [False]
parent state <POV initialization>_<Egress intrinsic metadata>
Full merge done <POV initialization>_<Egress intrinsic metadata> <- <POV skip>
-Try merge <POV initialization>_<Egress intrinsic metadata>_<POV skip> <- <Metadata bridge>
-merge output at offset 0
-merge output at offset 8
-merge_offset = 24, complete_merge = True
+Try merge <POV initialization>_<Egress intrinsic metadata>_<POV skip> <- <_parse_bridged_ingress_intrinsic_metadata>
+merge_offset = 0, complete_merge = True
Before Merge ------
S1: State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>
shift: 7B
match_reservations: []
-outputs[addr, width]: ([146, 16], [81, 8])
+outputs[addr, width]: ([144, 16], [80, 8])
branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>
match_extractions: []
-next state <Metadata bridge> val 0 mask [False]
-parent state <Shim start state>
-
-
-S2: State : <Metadata bridge>
-shift: 3B
-match_reservations: []
-outputs[addr, width]: ([80, 8], [144, 16])
-match_extractions: []
-next state <_parse_bridged_ingress_intrinsic_metadata> val 0 mask [False]
-parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>
-
-
-Full merge done <POV initialization>_<Egress intrinsic metadata>_<POV skip> <- <Metadata bridge>
-Try merge <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge> <- <_parse_bridged_ingress_intrinsic_metadata>
-merge_offset = 0, complete_merge = True
-Before Merge ------
-S1: State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>
-shift: 10B
-match_reservations: []
-outputs[addr, width]: ([146, 16], [81, 8], [80, 8], [144, 16])
-branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>
-match_extractions: []
next state <_parse_bridged_ingress_intrinsic_metadata> val 0 mask [False]
parent state <Shim start state>
@@ -402,19 +388,19 @@
branch promise on = ingress_port, offset = 7b, dst = default_parser
match_extractions: []
next state start val 0 mask [False]
-parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>
+parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>
-Full merge done <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge> <- <_parse_bridged_ingress_intrinsic_metadata>
-Try merge <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata> <- start
+Full merge done <POV initialization>_<Egress intrinsic metadata>_<POV skip> <- <_parse_bridged_ingress_intrinsic_metadata>
+Try merge <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata> <- start
merge_offset = 0, complete_merge = True
Before Merge ------
-S1: State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>
-shift: 12B
+S1: State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>
+shift: 9B
match_reservations: []
-outputs[addr, width]: ([146, 16], [81, 8], [80, 8], [144, 16])
-branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>
-branch promise on = ingress_port, offset = 87b, dst = default_parser
+outputs[addr, width]: ([144, 16], [80, 8])
+branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>
+branch promise on = ingress_port, offset = 63b, dst = default_parser
match_extractions: []
next state start val 0 mask [False]
parent state <Shim start state>
@@ -428,13 +414,12 @@
match_extractions: []
next state parse_pkt_in val 0 mask [True, True, True, True, True, True, True, True]
next state default_parser val 0 mask [False]
-parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>
+parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>
-Full merge done <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata> <- start
+Full merge done <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata> <- start
Remove state <Egress intrinsic metadata>
Remove state <POV skip>
-Remove state <Metadata bridge>
Remove state <_parse_bridged_ingress_intrinsic_metadata>
Remove state start
assign ids to 9 states, dir = 1
@@ -444,13 +429,13 @@
match_reservations: []
outputs[addr, width]: ()
match_extractions: []
-next state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start val 0 mask [False]
+next state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>_start val 0 mask [False]
------
State : parse_ethernet
shift: 14B
match_reservations: []
-outputs[addr, width]: ([82, 8], [296, 8], [266, 32], [332, 16], [297, 8], [267, 32], [333, 16])
+outputs[addr, width]: ([81, 8], [300, 8], [270, 32], [338, 16], [301, 8], [271, 32], [339, 16])
branch on = etherType, offset = 96b, dst = parse_ethernet
match_extractions: [match_window(hw_id=0, width=16)]
match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
@@ -463,7 +448,7 @@
State : parse_ipv4
shift: 20B
match_reservations: []
-outputs[addr, width]: ([82, 8], [292, 8], [293, 8], [326, 16], [327, 16], [328, 16], [260, 32], [261, 32], [262, 32])
+outputs[addr, width]: ([81, 8], [296, 8], [297, 8], [332, 16], [333, 16], [334, 16], [264, 32], [265, 32], [266, 32])
branch on = fragOffset, offset = 51b, dst = parse_ipv4
branch on = protocol, offset = 72b, dst = parse_ipv4
match_extractions: [match_window(hw_id=0, width=16), match_window(hw_id=2, width=8)]
@@ -477,7 +462,7 @@
State : parse_tcp
shift: 20B
match_reservations: []
-outputs[addr, width]: ([82, 8], [294, 8], [295, 8], [329, 16], [330, 16], [331, 16], [263, 32], [264, 32], [265, 32])
+outputs[addr, width]: ([81, 8], [298, 8], [299, 8], [335, 16], [336, 16], [337, 16], [267, 32], [268, 32], [269, 32])
match_extractions: []
parent state parse_ipv4
@@ -485,7 +470,7 @@
State : parse_udp
shift: 8B
match_reservations: []
-outputs[addr, width]: ([82, 8], [294, 8], [295, 8], [329, 16], [263, 32])
+outputs[addr, width]: ([81, 8], [298, 8], [299, 8], [336, 16], [267, 32])
match_extractions: []
parent state parse_ipv4
@@ -494,30 +479,30 @@
shift: 0B
match_reservations: [match_window(hw_id=0, width=16)]
outputs[addr, width]: ()
-branch on = ingress_port, offset = 87b, dst = default_parser
+branch on = ingress_port, offset = 63b, dst = default_parser
match_extractions: [match_window(hw_id=0, width=16)]
match key = [0, 1, 2, 3, 4, 5, 6, 7, 8, None, None, None, None, None, None, None]
next state parse_pkt_out val 320 mask [True, True, True, True, True, True, True, True, True]
next state parse_ethernet val 0 mask [False]
-parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
+parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>_start
------
State : parse_pkt_out
shift: 2B
match_reservations: []
-outputs[addr, width]: ([82, 8], [334, 16])
+outputs[addr, width]: ([81, 8], [340, 16])
match_extractions: []
next state parse_ethernet val 0 mask [False]
parent state default_parser
------
-State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
-shift: 12B
+State : <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>_start
+shift: 9B
match_reservations: []
-outputs[addr, width]: ([146, 16], [81, 8], [80, 8], [144, 16])
-branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
-branch on = None, offset = 192b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
-branch promise on = ingress_port, offset = 87b, dst = default_parser
+outputs[addr, width]: ([144, 16], [80, 8])
+branch on = None, offset = 24b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>_start
+branch on = None, offset = 168b, dst = <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>_start
+branch promise on = ingress_port, offset = 63b, dst = default_parser
match_extractions: [match_window(hw_id=0, width=16), match_window(hw_id=2, width=8), match_window(hw_id=3, width=8)]
match key = [None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
match key = [8, 9, 10, 11, 12, 13, 14, 15]
@@ -530,8 +515,8 @@
State : parse_pkt_in
shift: 2B
match_reservations: []
-outputs[addr, width]: ([82, 8], [145, 16])
+outputs[addr, width]: ([81, 8], [340, 16])
match_extractions: []
next state parse_ethernet val 0 mask [False]
-parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<Metadata bridge>_<_parse_bridged_ingress_intrinsic_metadata>_start
+parent state <POV initialization>_<Egress intrinsic metadata>_<POV skip>_<_parse_bridged_ingress_intrinsic_metadata>_start
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parser.characterize.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parser.characterize.log
index 2edd52e..31fb1b8 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parser.characterize.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/parser.characterize.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: parser.characterize.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/transform.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/transform.log
index 5930344..5287027 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/transform.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/transform.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: transform.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Thu Sep 7 14:48:49 2017 |
+| Created on: Fri Sep 8 08:25:15 2017 |
+---------------------------------------------------------------------+
-------------------------------