| +---------------------------------------------------------------------+ |
| | Log file: mau.config.log | |
| | Compiler version: 5.1.0 (fca32d1) | |
| | Created on: Thu Sep 7 13:56:08 2017 | |
| +---------------------------------------------------------------------+ |
| |
| Final Stage dependencies are: |
| (0, 'ingress') : match |
| (1, 'ingress') : match |
| (2, 'ingress') : match |
| (3, 'ingress') : concurrent |
| (4, 'ingress') : concurrent |
| (5, 'ingress') : concurrent |
| (6, 'ingress') : match |
| (7, 'ingress') : concurrent |
| (8, 'ingress') : concurrent |
| (9, 'ingress') : concurrent |
| (10, 'ingress') : concurrent |
| (11, 'ingress') : concurrent |
| (0, 'egress') : match |
| (1, 'egress') : concurrent |
| (2, 'egress') : concurrent |
| (3, 'egress') : concurrent |
| (4, 'egress') : concurrent |
| (5, 'egress') : concurrent |
| (6, 'egress') : match |
| (7, 'egress') : concurrent |
| (8, 'egress') : concurrent |
| (9, 'egress') : concurrent |
| (10, 'egress') : concurrent |
| (11, 'egress') : concurrent |
| Action/Concurrent chaining in ingress consists of [3, 4, 5] |
| Action/Concurrent chaining in ingress consists of [7, 8, 9, 10, 11] |
| Action/Concurrent chaining in egress consists of [1, 2, 3, 4, 5] |
| Action/Concurrent chaining in egress consists of [7, 8, 9, 10, 11] |
| |
| +------------------------------------------------------------------------ |
| | MAU Stage 0 |
| +------------------------------------------------------------------------ |
| |
| +------------------------------------------------------------------------ |
| | Working on table _condition_0 in stage 0 --- |
| +------------------------------------------------------------------------ |
| --> Stage Gateway Table for condition _condition_0 in stage 0 |
| Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1) |
| Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 3. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 1 to come from 8-bit PHV container 3. |
| That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}. |
| Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8) |
| Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=41].byte1 to be 0x2. |
| Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x0 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xfffffd |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff |
| Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8 |
| Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x10 |
| Configuring rams.match.merge.gateway_en.gateway_en to be 0x1 |
| Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xe |
| Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1 |
| allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits |
| Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x0 |
| Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1 |
| Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2 |
| Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x1 |
| Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0 |
| Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x1 |
| Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0 |
| Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff |
| Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff |
| |
| +------------------------------------------------------------------------ |
| | Working on table _condition_3 in stage 0 --- |
| +------------------------------------------------------------------------ |
| --> Stage Gateway Table for condition _condition_3 in stage 0 |
| Configuring rams.match.merge.predication_ctl[direction_index=1].table_thread to be 0x2 (previous_value=0x0 OR new_value=0x2). |
| Configuring dp.imem_table_addr_egress to be 0x2 (previous_value = 0x0 OR new_value = 0x2). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=1][copy_index=0].adr_dist_table_thread to be 0x2 (previous_value=0x0 OR new_value=0x2). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=1][copy_index=1].adr_dist_table_thread to be 0x2 (previous_value=0x0 OR new_value=0x2). |
| Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_egress to be 0x2 (previous_value=0x0 OR new_value=0x2). |
| Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_egress to be 0x2 (previous_value=0x0 OR new_value=0x2). |
| Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_egress to be 0x2 (previous_value=0x0 OR new_value=0x2). |
| Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=1].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1) |
| Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=1].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=2][output_byte=0].match_input_xbar_816b_ctl_address to be 0. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=2][output_byte=0].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 0 to come from 8-bit PHV container 16. |
| That PHV byte contains {unused[6:0], ig_intr_md_for_tm.copy_to_cpu[0:0]}. |
| Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=6].match_input_xbar_din_power_ctl to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x1) |
| Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte0 to be 0x1. |
| Configuring dp.hashout_ctl.hash_group_egress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0. |
| Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1. |
| Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0. |
| Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1. |
| Configuring cfg_regs.mau_cfg_lt_thread.mau_cfg_lt_thread to be 0x2. (previous value = 0x0 OR new value = 0x2) |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x1 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x1 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xfffffe |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffffff |
| Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8 |
| Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0xff |
| Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2) |
| Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xf |
| Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1 |
| allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits |
| Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_logical_select to be 0x1 |
| Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_inhibit_enable to be 0x1 |
| Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x3 (previous value 0x2 OR new value 0x1) |
| Configuring rams.match.merge.gateway_payload_data[0][0][0][0].gateway_payload_data to be 0x1 |
| Configuring rams.match.merge.gateway_payload_data[0][0][1][0].gateway_payload_data to be 0x0 |
| Configuring rams.match.merge.gateway_payload_data[0][0][0][1].gateway_payload_data to be 0x1 |
| Configuring rams.match.merge.gateway_payload_data[0][0][1][1].gateway_payload_data to be 0x0 |
| Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff |
| Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff |
| |
| +------------------------------------------------------------------------ |
| | Working on table ingress_pkt__action__ in stage 0 --- |
| +------------------------------------------------------------------------ |
| --> Action Data Table ingress_pkt__action__ with logical_table_id 0 that is reference type is 'direct' |
| |
| +------------------------------------------------------------------------ |
| | Working on table ingress_pkt in stage 0 --- |
| +------------------------------------------------------------------------ |
| --> Match Table with no key ingress_pkt with logical_table_id 0 |
| allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits |
| Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1. |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1. |
| Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x0. |
| Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x1. |
| Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x10. |
| Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2080. |
| Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
| Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x74412. |
| Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1. |
| Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 0. |
| Micro instruction added in VLIW 0 for 16-bit position 2 for table ingress_pkt. |
| Assembled as 0x74412 (or decimal 476178) |
| Micro Instruction deposit-field for PHV Container 130 has bit width 23 |
| Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| Field Src1 [4:0] : 0x1 (5 bits in instruction bits [8:4]) |
| Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11]) |
| Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15]) |
| Field right_rotate [3:0] : 0x7 (4 bits in instruction bits [19:16]) |
| Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| |
| Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=0].imem_subword8_instr to be 0x74d83. |
| Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=0].imem_subword8_color to be 1. |
| Configuring dp.imem.imem_subword8[unit_number=3][vliw_instruction_number=0].imem_subword8_parity to be 1. |
| Micro instruction added in VLIW 0 for 8-bit position 3 for table ingress_pkt. |
| Assembled as 0x74d83 (or decimal 478595) |
| Micro Instruction deposit-field for PHV Container 67 has bit width 20 |
| Field Src2 [3:0] : 0x3 (4 bits in instruction bits [3:0]) |
| Field Src1 [4:0] : 0x18 (5 bits in instruction bits [8:4]) |
| Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| Field high_bit [2:0] : 0x1 (3 bits in instruction bits [13:11]) |
| Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14]) |
| Field right_rotate [2:0] : 0x7 (3 bits in instruction bits [18:16]) |
| Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19]) |
| |
| Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8) |
| Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6) |
| Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1. |
| |
| +------------------------------------------------------------------------ |
| | Working on table egress_pkt__action__ in stage 0 --- |
| +------------------------------------------------------------------------ |
| --> Action Data Table egress_pkt__action__ with logical_table_id 1 that is reference type is 'direct' |
| |
| +------------------------------------------------------------------------ |
| | Working on table egress_pkt in stage 0 --- |
| +------------------------------------------------------------------------ |
| --> Match Table with no key egress_pkt with logical_table_id 1 |
| allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits |
| Configuring dp.imem_table_addr_egress to be 0x2 (previous_value = 0x2 OR new_value = 0x2). |
| Configuring rams.match.merge.predication_ctl[direction_index=1].table_thread to be 0x2 (previous_value=0x2 OR new_value=0x2). |
| Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_egress to be 0x2 (previous_value=0x2 OR new_value=0x2). |
| Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_egress to be 0x2 (previous_value=0x2 OR new_value=0x2). |
| Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_egress to be 0x2 (previous_value=0x2 OR new_value=0x2). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=1][copy_index=0].adr_dist_table_thread to be 0x2 (previous_value=0x2 OR new_value=0x2). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=1][copy_index=1].adr_dist_table_thread to be 0x2 (previous_value=0x2 OR new_value=0x2). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_default to be 0x0. |
| Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x1. |
| Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0xff. |
| Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x2080. |
| Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
| Configuring dp.imem.imem_subword8[unit_number=18][vliw_instruction_number=0].imem_subword8_instr to be 0x592. |
| Configuring dp.imem.imem_subword8[unit_number=18][vliw_instruction_number=0].imem_subword8_color to be 1. |
| Configuring dp.imem.imem_subword8[unit_number=18][vliw_instruction_number=0].imem_subword8_parity to be 0. |
| Micro instruction added in VLIW 0 for 8-bit position 18 for table egress_pkt. |
| Assembled as 0x592 (or decimal 1426) |
| Micro Instruction deposit-field for PHV Container 82 has bit width 20 |
| Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4]) |
| Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11]) |
| Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14]) |
| Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16]) |
| Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19]) |
| |
| Configuring dp.imem.imem_subword16[unit_number=17][vliw_instruction_number=0].imem_subword16_instr to be 0x39fc01. |
| Configuring dp.imem.imem_subword16[unit_number=17][vliw_instruction_number=0].imem_subword16_color to be 1. |
| Configuring dp.imem.imem_subword16[unit_number=17][vliw_instruction_number=0].imem_subword16_parity to be 0. |
| Micro instruction added in VLIW 0 for 16-bit position 17 for table egress_pkt. |
| Assembled as 0x39fc01 (or decimal 3800065) |
| Micro Instruction deposit-field for PHV Container 145 has bit width 23 |
| Field Src2 [3:0] : 0x1 (4 bits in instruction bits [3:0]) |
| Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4]) |
| Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| Field high_bit [3:0] : 0xf (4 bits in instruction bits [14:11]) |
| Field low_bit_lo [0:0] : 0x1 (1 bits in instruction bits [15:15]) |
| Field right_rotate [3:0] : 0x9 (4 bits in instruction bits [19:16]) |
| Field low_bit_hi [2:0] : 0x3 (3 bits in instruction bits [22:20]) |
| |
| Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=6].actionmux_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4) |
| Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=10].actionmux_din_power_ctl to be 0x3. (previous value = 0x0 OR new value = 0x3) |
| Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=0].action_instruction_adr_payload_shifter_en to be 1. |
| +------------------------------------------------------------------------ |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 10. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 1. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 10. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 1. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x3. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x3. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x1. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| -------------------------------------------- |
| Configuration for unused statistics ALUs. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| +------------------------------------------------------------------------ |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| +------------------------------------------------------------------------ |
| Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0. |
| Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| |
| +------------------------------------------------------------------------ |
| | MAU Stage 1 |
| +------------------------------------------------------------------------ |
| |
| +------------------------------------------------------------------------ |
| | Working on table _condition_1 in stage 1 --- |
| +------------------------------------------------------------------------ |
| --> Stage Gateway Table for condition _condition_1 in stage 1 |
| Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1) |
| Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 3. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 0 to come from 8-bit PHV container 3. |
| That PHV byte contains {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}. |
| Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0x8. (previous value = 0x0 OR new value = 0x8) |
| Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte0 to be 0x2. |
| Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0. |
| Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1. |
| Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0. |
| Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1. |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xfffffe |
| Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x10 |
| Configuring rams.match.merge.gateway_next_table_lut[0][4] to be 0x20 |
| Configuring rams.match.merge.gateway_en.gateway_en to be 0x1 |
| Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf |
| Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1 |
| Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_logical_select to be 0x0 |
| Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].tind_inhibit_enable to be 0x1 |
| Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff |
| Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff |
| |
| +------------------------------------------------------------------------ |
| | Working on table table0__action__ in stage 1 --- |
| +------------------------------------------------------------------------ |
| --> Action Data Table table0__action__ with logical_table_id 0 that is reference type is 'direct' |
| Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_select to be 4. |
| Configuring rams.match.adrdist.immediate_data_16b_ixbar_ctl[logical_table_concat_hi_lo_half=0].enabled_4bit_muxctl_enable to be 1. |
| |
| +------------------------------------------------------------------------ |
| | Working on table table0 in stage 1 --- |
| +------------------------------------------------------------------------ |
| --> Ternary Match Table table0 with logical_table_id 0 |
| Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=1][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_select to be 0 (logical table id). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=3][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x3. |
| Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_default to be 0x0. |
| Configuring rams.match.merge.mau_action_instruction_adr_per_entry_en_mux_ctl[table_type_index=1][physical_result_bus=0].mau_action_instruction_adr_per_entry_en_mux_ctl to be 0x2. |
| Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=1].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x870a080. |
| Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=1][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
| Configuring rams.match.merge.next_table_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.next_table_map_data[logical_table_id=0][entry_index=0].next_table_map_data0 to be 0x20. |
| Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0x20. |
| Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_mask to be 0x0. |
| Configuring rams.match.merge.mau_immediate_data_mask[table_type_index=1][result_bus_number=0].mau_immediate_data_mask to be 0xffff. |
| Configuring rams.match.merge.mau_stats_adr_mask[table_type_index=1][result_bus_number=0].mau_stats_adr_mask to be 0xffffe. |
| Configuring rams.match.merge.mau_stats_adr_default[table_type_index=1][result_bus_number=0].mau_stats_adr_default to be 0x80000. |
| Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x0) |
| Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x3. (old value = 0x0 OR new value = 0x3) |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_address to be 16. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=133].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 133 to come from 16-bit PHV container 0. |
| That PHV byte contains version/valid |
| {unused[6:0], ig_intr_md.ingress_port[8:8]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_address to be 2. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=128].match_input_xbar_32b_ctl_lo_enable to be 1. |
| Configuring match input crossbar byte 128 to come from 32-bit PHV container 2. |
| That PHV byte contains {ethernet.srcAddr[7:0]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_address to be 2. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=129].match_input_xbar_32b_ctl_lo_enable to be 1. |
| Configuring match input crossbar byte 129 to come from 32-bit PHV container 2. |
| That PHV byte contains {ethernet.srcAddr[15:8]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_address to be 2. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=130].match_input_xbar_32b_ctl_lo_enable to be 1. |
| Configuring match input crossbar byte 130 to come from 32-bit PHV container 2. |
| That PHV byte contains {ethernet.srcAddr[23:16]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_address to be 2. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=131].match_input_xbar_32b_ctl_lo_enable to be 1. |
| Configuring match input crossbar byte 131 to come from 32-bit PHV container 2. |
| That PHV byte contains {ethernet.srcAddr[31:24]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_address to be 1. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=132].match_input_xbar_32b_ctl_lo_enable to be 1. |
| Configuring match input crossbar byte 132 to come from 32-bit PHV container 1. |
| That PHV byte contains {ethernet.dstAddr[15:8]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_address to be 1. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=134].match_input_xbar_32b_ctl_lo_enable to be 1. |
| Configuring match input crossbar byte 134 to come from 32-bit PHV container 1. |
| That PHV byte contains {ethernet.dstAddr[31:24]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_address to be 1. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=135].match_input_xbar_32b_ctl_lo_enable to be 1. |
| Configuring match input crossbar byte 135 to come from 32-bit PHV container 1. |
| That PHV byte contains {ethernet.dstAddr[39:32]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_address to be 20. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=136].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 136 to come from 16-bit PHV container 4. |
| That PHV byte contains {ethernet.etherType[7:0]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_address to be 1. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_32b_ctl[word_group=0][output_byte=137].match_input_xbar_32b_ctl_lo_enable to be 1. |
| Configuring match input crossbar byte 137 to come from 32-bit PHV container 1. |
| That PHV byte contains {ethernet.dstAddr[23:16]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_address to be 19. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=138].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 138 to come from 16-bit PHV container 3. |
| That PHV byte contains {ethernet.srcAddr[47:40]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_address to be 20. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=139].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 139 to come from 16-bit PHV container 4. |
| That PHV byte contains {ethernet.etherType[15:8]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_address to be 16. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=140].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 140 to come from 16-bit PHV container 0. |
| That PHV byte contains {ig_intr_md.ingress_port[7:0]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_address to be 19. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=141].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 141 to come from 16-bit PHV container 3. |
| That PHV byte contains {ethernet.dstAddr[7:0]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_address to be 2. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=142].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 142 to come from 8-bit PHV container 2. |
| That PHV byte contains {ethernet.srcAddr[39:32]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_address to be 1. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=143].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 143 to come from 8-bit PHV container 1. |
| That PHV byte contains {ethernet.dstAddr[47:40]}. |
| Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=0].match_input_xbar_din_power_ctl to be 0x6. (previous value = 0x0 OR new value = 0x6) |
| Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=4].match_input_xbar_din_power_ctl to be 0xe. (previous value = 0x8 OR new value = 0x6) |
| Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x19. (previous value = 0x0 OR new value = 0x19) |
| |
| --> Idletime Table for match table table0 in stage 1 |
| Looking at Map RAM: Row 7 Unit 0 |
| Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 0. |
| Configuring rams.map_alu.row[row=7].vh_xbars.adr_dist_idletime_adr_xbar_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be select of 1. |
| Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].two_way_idletime_notification to be 1. |
| Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].per_flow_idletime to be 1. |
| Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].idletime_bitwidth to be 2 (precision = 3 bits). |
| Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_type to be 4. |
| Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0. |
| FIXME: Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn_members to be 0. |
| Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_vpn to be 0. |
| Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| Configuring rams.map_alu.row[row=7].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 2. |
| Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| Configuring rams.map_alu.row[row=7].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].ram_stats_meter_adr_mux_select_idlet to be 1. |
| Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0. |
| Configuring rams.map_alu.row[row=7].adrmux.idletime_logical_to_physical_sweep_grant_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1. |
| Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_select to be 0. |
| Configuring rams.map_alu.row[row=7].adrmux.idletime_physical_to_logical_req_inc_ctl[map_ram_index=0].enabled_4bit_muxctl_enable to be 1. |
| Configuring rams.map_alu.row[row=7].adrmux.idletime_cfg_rd_clear_val[map_ram_index=0].idletime_cfg_rd_clear_val to be 0x36. |
| logical table ID is 0 |
| Configuring rams.match.adrdist.adr_dist_idletime_adr_oxbar_ctl.[entry_index=2].adr_dist_idletime_adr_oxbar_ctl be 0x4000 (previous value = 0x0 OR new value = 0x4000) |
| Note that rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_en must be programmed by run time. |
| Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_offset be 0x0. |
| Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_size be 0x0. |
| Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_pos be 0x0. |
| Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_remove_hole_en be 0x0. |
| Configuring rams.match.adrdist.idletime_sweep_ctl[logical_table_id=0].idletime_sweep_interval be 0x7. |
| Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_offset be 0x0. |
| Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_size be 0x0. |
| Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_pos be 0x0. |
| Configuring cfg_regs.idle_dump_ctl[logical_table=0].idletime_dump_remove_hole_en be 0. |
| Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_size be 2. |
| Configuring rams.match.adrdist.movereg_idle_ctl[logical_table=0].movereg_idle_ctl_direct be 1. |
| Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=2].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.match.merge.mau_idletime_adr_mask[table_type_index=1][result_bus_number=0].mau_idletime_adr_mask to be 0x1ffff8. |
| Configuring rams.match.merge.mau_idletime_adr_default[table_type_index=1][result_bus_number=0].idletime_adr_default to be 0x100003. |
| Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_instr to be 0x4602. |
| Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_color to be 1. |
| Configuring dp.imem.imem_subword16[unit_number=2][vliw_instruction_number=0].imem_subword16_parity to be 1. |
| Micro instruction added in VLIW 0 for 16-bit position 2 for table table0. |
| Assembled as 0x4602 (or decimal 17922) |
| Micro Instruction deposit-field for PHV Container 130 has bit width 23 |
| Field Src2 [3:0] : 0x2 (4 bits in instruction bits [3:0]) |
| Field Src1 [4:0] : 0x0 (5 bits in instruction bits [8:4]) |
| Field Src1i [0:0] : 0x1 (1 bits in instruction bits [9:9]) |
| Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| Field high_bit [3:0] : 0x8 (4 bits in instruction bits [14:11]) |
| Field low_bit_lo [0:0] : 0x0 (1 bits in instruction bits [15:15]) |
| Field right_rotate [3:0] : 0x0 (4 bits in instruction bits [19:16]) |
| Field low_bit_hi [2:0] : 0x0 (3 bits in instruction bits [22:20]) |
| |
| Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=8].actionmux_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4) |
| Configuring dp.imem.imem_subword8[unit_number=0][vliw_instruction_number=1].imem_subword8_instr to be 0x590. |
| Configuring dp.imem.imem_subword8[unit_number=0][vliw_instruction_number=1].imem_subword8_color to be 0. |
| Configuring dp.imem.imem_subword8[unit_number=0][vliw_instruction_number=1].imem_subword8_parity to be 0. |
| Micro instruction added in VLIW 1 for 8-bit position 0 for table table0. |
| Assembled as 0x590 (or decimal 1424) |
| Micro Instruction deposit-field for PHV Container 64 has bit width 20 |
| Field Src2 [3:0] : 0x0 (4 bits in instruction bits [3:0]) |
| Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4]) |
| Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| Field high_bit [2:0] : 0x0 (3 bits in instruction bits [13:11]) |
| Field low_bit_lo [1:0] : 0x0 (2 bits in instruction bits [15:14]) |
| Field right_rotate [2:0] : 0x0 (3 bits in instruction bits [18:16]) |
| Field low_bit_hi [0:0] : 0x0 (1 bits in instruction bits [19:19]) |
| |
| Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_instr to be 0xb7d94. |
| Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_color to be 1. |
| Configuring dp.imem.imem_subword8[unit_number=4][vliw_instruction_number=1].imem_subword8_parity to be 1. |
| Micro instruction added in VLIW 1 for 8-bit position 4 for table table0. |
| Assembled as 0xb7d94 (or decimal 753044) |
| Micro Instruction deposit-field for PHV Container 68 has bit width 20 |
| Field Src2 [3:0] : 0x4 (4 bits in instruction bits [3:0]) |
| Field Src1 [4:0] : 0x19 (5 bits in instruction bits [8:4]) |
| Field Src1i [0:0] : 0x0 (1 bits in instruction bits [9:9]) |
| Field opcode [0:0] : 0x1 (1 bits in instruction bits [10:10]) |
| Field high_bit [2:0] : 0x7 (3 bits in instruction bits [13:11]) |
| Field low_bit_lo [1:0] : 0x1 (2 bits in instruction bits [15:14]) |
| Field right_rotate [2:0] : 0x3 (3 bits in instruction bits [18:16]) |
| Field low_bit_hi [0:0] : 0x1 (1 bits in instruction bits [19:19]) |
| |
| Configuring dp.actionmux_din_power_ctl[14_byte_group=0][byte_position=4].actionmux_din_power_ctl to be 0x11. (previous value = 0x1 OR new value = 0x10) |
| Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].idletime_adr_payload_shifter_en to be 1. |
| Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].stats_adr_payload_shifter_en to be 1. |
| Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].action_instruction_adr_payload_shifter_en to be 1. |
| Configuring rams.match.merge.mau_payload_shifter_enable[table_type=1][result_bus=0].immediate_data_payload_shifter_en to be 1. |
| Configuring rams.match.merge.mau_table_counter_ctl[half_index=0].mau_table_counter_ctl to be 0x2. (previous value = 0x0 OR new value = 0x2) |
| dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit'] |
| Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data_dirtcam_mode to be 0x155. |
| Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vbit_dirtcam_mode to be 0x1. |
| Configuring tcams.col[col=1].tcam_mode[row=9].tcam_data1_select to be 1. |
| Configuring tcams.col[col=1].tcam_mode[row=9].tcam_chain_out_enable to be 0. |
| Configuring tcams.col[col=1].tcam_mode[row=9].tcam_ingress to be 1. |
| Configuring tcams.col[col=1].tcam_mode[row=9].tcam_match_output_enable to be 1. |
| Configuring tcams.col[col=1].tcam_mode[row=9].tcam_vpn to be 0. |
| Configuring tcams.col[col=1].tcam_mode[row=9].tcam_logical_table to be 0. |
| TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=0] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=1] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=2] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=3] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=4] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=5] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=6] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=4][valid_bit_index=7] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_select to be 0 (don't care). |
| Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=9].tcam_row_halfbyte_mux_ctl_enable to be 1. |
| Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_select to be 2. |
| Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=9].enabled_4bit_muxctl_enable to be 1. |
| dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit'] |
| Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data_dirtcam_mode to be 0x155. |
| Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vbit_dirtcam_mode to be 0x0. |
| Configuring tcams.col[col=1].tcam_mode[row=10].tcam_data1_select to be 1. |
| Configuring tcams.col[col=1].tcam_mode[row=10].tcam_chain_out_enable to be 1. |
| Configuring tcams.col[col=1].tcam_mode[row=10].tcam_ingress to be 1. |
| Configuring tcams.col[col=1].tcam_mode[row=10].tcam_match_output_enable to be 0. |
| Configuring tcams.col[col=1].tcam_mode[row=10].tcam_vpn to be 0. |
| Configuring tcams.col[col=1].tcam_mode[row=10].tcam_logical_table to be 0. |
| TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_select to be 3 (version on [3:2] and valid bits for [1:0]). |
| Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=10].tcam_row_halfbyte_mux_ctl_enable to be 1. |
| Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0. |
| Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1. |
| Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_select to be 1. |
| Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=10].enabled_4bit_muxctl_enable to be 1. |
| dirtcam_mode_list = ['2bit', '2bit', '2bit', '2bit', '2bit'] |
| Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data_dirtcam_mode to be 0x155. |
| Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vbit_dirtcam_mode to be 0x1. |
| Configuring tcams.col[col=1].tcam_mode[row=11].tcam_data1_select to be 1. |
| Configuring tcams.col[col=1].tcam_mode[row=11].tcam_chain_out_enable to be 1. |
| Configuring tcams.col[col=1].tcam_mode[row=11].tcam_ingress to be 1. |
| Configuring tcams.col[col=1].tcam_mode[row=11].tcam_match_output_enable to be 0. |
| Configuring tcams.col[col=1].tcam_mode[row=11].tcam_vpn to be 0. |
| Configuring tcams.col[col=1].tcam_mode[row=11].tcam_logical_table to be 0. |
| TODO: Currently PHV container valid bits are disabled. Matching on a valid bit will require using a POV bit. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=0] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=1] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=2] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=3] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=4] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=5] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=6] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_validbit_xbar_ctl[tcam_match_bus=1][row_pair_index=5][valid_bit_index=7] to be 15. |
| Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_select to be 0 (extra byte low nibble [3:0]). |
| Configuring tcams.vh_data_xbar.tcam_row_halfbyte_mux_ctl[tcam_match_bus=1][row=11].tcam_row_halfbyte_mux_ctl_enable to be 1. |
| Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_select to be 0. |
| Configuring tcams.vh_data_xbar.tcam_extra_byte_ctl[tcam_match_bus=1][row_pair=5].enabled_3bit_muxctl_enable to be 1. |
| Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_select to be 0. |
| Configuring tcams.vh_data_xbar.tcam_row_output_ctl[tcam_match_bus=1][row=11].enabled_4bit_muxctl_enable to be 1. |
| Configuring tcams.col[col=0].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x0. |
| Configuring tcams.col[col=1].tcam_table_map[logical_tcam_table_id=0].tcam_table_map to be 0x200. |
| --> Ternary Indirection table for Match Table table0 with logical_table_id 0 |
| Configuring tcams.tcam_match_adr_shift[tcam_table_id=0] to be left shift of 3. |
| Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_write_data_mux_select to be select of 7. |
| Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.match_ram_read_data_mux_select to be select of 7. |
| Configuring rams.array.row[row=0].ram[col=2].unit_ram_ctl.tind_result_bus_select to be select of 1. |
| Configuring rams.map_alu.row[row=0].adrmux.ram_address_mux_ctl[column_half=0][column_index=2].ram_unitram_adr_mux_select to be 2. |
| Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_type to be 6. |
| Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_vpn to be 0. |
| Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_logical_table to be 0. |
| Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_ingress to be 1. |
| Configuring rams.map_alu.row[row=0].adrmux.unitram_config[column_half=0][column_index=2].unitram_enable to be 1. |
| Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id). |
| Configuring rams.map_alu.row[row=0].adrmux.vh_xbars.adr_dist_tind_adr_xbar_ctl[tind_bus_on_row=0].enabled_3bit_muxctl_enable to be 1. |
| Configuring rams.array.row[row=0].tind_ecc_error_uram_ctl[direction=0].tind_ecc_error_uram_ctl to be select of 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.match.merge.tind_ram_data_size[tind_bus_number=0].tind_ram_data_size to be code 4. |
| Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_select to be 0 (logical tcam table id). |
| Configuring rams.match.merge.tcam_match_adr_to_physical_oxbar_outputmap[tind_bus_number=0].enabled_3bit_muxctl_enable to be 1. |
| TODO: rams.match.merge.tind_bus_prop[tind_bus_number=0] is currently always set to 1. |
| Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].tcam_piped to be 1. |
| Configuring rams.match.merge.tind_bus_prop[tind_bus_number=0].enabled to be 1. |
| Configuring rams.match.merge.mau_action_instruction_adr_tcam_shiftcount[physical_result_bus=0].mau_action_instruction_adr_tcam_shiftcount to be 0. |
| Configuring rams.match.merge.mau_immediate_data_tcam_shiftcount[tind_bus_number=0].mau_immediate_data_tcam_shiftcount to be 3. |
| Configuring rams.match.merge.mau_idletime_adr_tcam_shiftcount[result_bus_number=0].mau_idletime_adr_tcam_shiftcount to be 0x44. |
| Configuring rams.match.merge.mau_stats_adr_tcam_shiftcount[result_bus_index=0].mau_stats_adr_tcam_shiftcount to be 0x49. |
| Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_select to be 0 (logical table id). |
| Configuring rams.match.merge.tcam_hit_to_logical_table_ixbar_outputmap[tcam_table_id=0].enabled_4bit_muxctl_enable to be 1. |
| TODO: rams.match.merge.tcam_table_prop[tcam_table_id=0] is currently always set to 1. |
| Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].tcam_piped to be 1. |
| Configuring rams.match.merge.tcam_table_prop[tcam_table_id=0].enabled to be 1. |
| Configuring tcams.tcam_output_table_thread[tcam_table_id=0].tcam_output_table_thread to be 1. |
| TODO: tcams.tcam_piped is currently always set to True for ingress and egress. |
| Configuring tcams.tcam_piped to be 3. |
| Configuring cfg_regs.mau_cfg_movereg_tcam_only.mau_cfg_movereg_tcam_only to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| |
| +------------------------------------------------------------------------ |
| | Working on table table0_counter in stage 1 --- |
| +------------------------------------------------------------------------ |
| Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3. |
| Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1. |
| Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3. |
| Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1. |
| Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1. |
| Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2) |
| Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| Stat table table0_counter is used by match table table0. |
| Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8) |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0. |
| Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0. |
| Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1. |
| For counter width 32 and N = 4096 |
| number iterations = 32 |
| b_cur = 379488672.0 |
| eqn(b_cur) = 4294964039.26 |
| max_counter_value = 4294967295 |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1. |
| TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x0. |
| Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4. |
| Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1. |
| Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0. |
| Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0. |
| Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0. |
| Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0. |
| Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0. |
| Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0. |
| Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0. |
| Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1. |
| Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3. |
| Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_direct be 1. |
| Configuring rams.match.adrdist.movereg_ad_direct[movereg_index=0].movereg_ad_direct be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_tcam be 1. |
| Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x0. |
| Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x7. ( previous value = 0x0 OR new value = 0x7) |
| Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x1. |
| +------------------------------------------------------------------------ |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 21. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3. |
| Configuring rams.match.merge.exact_match_delay_thread[copy_index=0].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.match.merge.exact_match_delay_thread[copy_index=1].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.match.merge.exact_match_delay_thread[copy_index=2].exact_match_delay_thread to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x1. |
| Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 16. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 21. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| -------------------------------------------- |
| Configuration for unused statistics ALUs. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| +------------------------------------------------------------------------ |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 1. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| +------------------------------------------------------------------------ |
| Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 19. |
| Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 2. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0. |
| Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1. |
| Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| |
| +------------------------------------------------------------------------ |
| | MAU Stage 2 |
| +------------------------------------------------------------------------ |
| |
| +------------------------------------------------------------------------ |
| | Working on table _condition_2 in stage 2 --- |
| +------------------------------------------------------------------------ |
| --> Stage Gateway Table for condition _condition_2 in stage 2 |
| Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1) |
| Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 18. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 0 to come from 16-bit PHV container 2. |
| That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 18. |
| Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1. |
| Configuring match input crossbar byte 1 to come from 16-bit PHV container 2. |
| That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}. |
| Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4) |
| Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte1 to be 0x1. |
| Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=41].byte0 to be 0x1. |
| Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=42].byte0 to be 0x2. |
| Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=43].byte0 to be 0x4. |
| Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=44].byte0 to be 0x8. |
| Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=45].byte0 to be 0x10. |
| Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=46].byte0 to be 0x20. |
| Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=47].byte0 to be 0x40. |
| Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=48].byte0 to be 0x80. |
| Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0. |
| Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1. |
| Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_select to be 0. |
| Configuring rams.array.row[row=7].vh_adr_xbar.exactmatch_row_hashadr_xbar_ctl[search_bus_index=0].enabled_3bit_muxctl_enable to be 1. |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_logical_table to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_thread to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_mode to be 0x2 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff3f |
| Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8 |
| Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x21 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid0 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid1 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][0] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][1] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff7fff |
| Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xc (previous value 0x8 OR new value 0x4) |
| Configuring rams.match.merge.gateway_next_table_lut[0][2] to be 0x21 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid0 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid1 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][0] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][1] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0xffff |
| Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][1] to be 0xffff |
| Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xe (previous value 0xc OR new value 0x2) |
| Configuring rams.match.merge.gateway_next_table_lut[0][1] to be 0x21 |
| Configuring rams.match.merge.gateway_en.gateway_en to be 0x1 |
| Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_select to be 0xf |
| Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[0].enabled_4bit_muxctl_enable to be 0x1 |
| allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits |
| Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_logical_select to be 0x0 |
| Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[1].exact_inhibit_enable to be 0x1 |
| Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x2 |
| Configuring rams.match.merge.gateway_payload_data[0][1][0][0].gateway_payload_data to be 0x1 |
| Configuring rams.match.merge.gateway_payload_data[0][1][1][0].gateway_payload_data to be 0x0 |
| Configuring rams.match.merge.gateway_payload_data[0][1][0][1].gateway_payload_data to be 0x1 |
| Configuring rams.match.merge.gateway_payload_data[0][1][1][1].gateway_payload_data to be 0x0 |
| Configuring rams.match.merge.gateway_payload_match_adr[0][1][0].gateway_payload_match_adr to be 0x7ffff |
| Configuring rams.match.merge.gateway_payload_match_adr[0][1][1].gateway_payload_match_adr to be 0x7ffff |
| |
| +------------------------------------------------------------------------ |
| | Working on table ingress_port_count_table__action__ in stage 2 --- |
| +------------------------------------------------------------------------ |
| --> Action Data Table ingress_port_count_table__action__ with logical_table_id 0 that is reference type is 'direct' |
| |
| +------------------------------------------------------------------------ |
| | Working on table ingress_port_count_table in stage 2 --- |
| +------------------------------------------------------------------------ |
| --> Match Table with no key ingress_port_count_table with logical_table_id 0 |
| allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits |
| Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=1].enabled_4bit_muxctl_enable to be 1. |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_select to be 0 (logical table id). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=1].enabled_4bit_muxctl_enable to be 1. |
| Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_default to be 0x0. |
| Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=1].mau_action_instruction_adr_mask to be 0x1. |
| Configuring rams.match.merge.next_table_format_data[logical_table_id=0].match_next_table_adr_miss_value to be 0xff. |
| Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=1].mau_stats_adr_default to be 0x0. |
| Configuring rams.match.merge.mau_stats_adr_per_entry_en_mux_ctl[table_type_index=0][result_bus_number=1].mau_stats_adr_per_entry_en_mux_ctl to be 0x7. |
| Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1). |
| Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2000. |
| Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
| Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].stats_adr_payload_shifter_en to be 1. |
| Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1. |
| |
| +------------------------------------------------------------------------ |
| | Working on table egress_port_count_table__action__ in stage 2 --- |
| +------------------------------------------------------------------------ |
| --> Action Data Table egress_port_count_table__action__ with logical_table_id 1 that is reference type is 'direct' |
| |
| +------------------------------------------------------------------------ |
| | Working on table egress_port_count_table in stage 2 --- |
| +------------------------------------------------------------------------ |
| --> Match Table with no key egress_port_count_table with logical_table_id 1 |
| allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits |
| Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=0][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_select to be 1 (logical table id). |
| Configuring rams.match.merge.match_to_logical_table_ixbar_outputmap[match_index=2][result_bus_number=0].enabled_4bit_muxctl_enable to be 1. |
| Configuring rams.match.merge.mau_action_instruction_adr_default[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_default to be 0x40. |
| Configuring rams.match.merge.mau_action_instruction_adr_mask[table_type_index=0][physical_result_bus=0].mau_action_instruction_adr_mask to be 0x0. |
| Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_miss_value to be 0xff. |
| Configuring rams.match.merge.next_table_format_data[logical_table_id=1].match_next_table_adr_default to be 0xff. |
| Configuring rams.match.merge.mau_stats_adr_default[table_type_index=0][result_bus_number=0].mau_stats_adr_default to be 0x80000. |
| Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2). |
| Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x40. |
| Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0. |
| --> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 2 |
| Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=1].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2). |
| Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x0) |
| Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0) |
| Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x0) |
| Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0) |
| Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1) |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash1_select to be 0x0 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_logical_table to be 0x1 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_thread to be 0x0 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_matchdata_xor_en.gateway_table_matchdata_xor_en to be 0x0 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid0 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_vv_entry[3].gateway_table_entry_versionvalid1 to be 0x3 |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][0] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_entry_matchdata[3][1] to be 0xffffffff |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][0] to be 0xffffff |
| Configuring rams.array.row[7].gateway_table[0].gateway_table_data_entry[3][1] to be 0xffffff |
| Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x8 |
| Configuring rams.match.merge.gateway_next_table_lut[1][3] to be 0xff |
| Configuring rams.match.merge.gateway_inhibit_lut[1] to be 0x18 (previous value 0x8 OR new value 0x10) |
| Configuring rams.match.merge.gateway_next_table_lut[1][4] to be 0xff |
| Configuring rams.match.merge.gateway_en.gateway_en to be 0x3 (previous value 0x1 OR new value 0x2) |
| Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_select to be 0xe |
| Configuring rams.match.merge.gateway_to_logicaltable_xbar_ctl[1].enabled_4bit_muxctl_enable to be 0x1 |
| allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits |
| Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_logical_select to be 0x1 |
| Configuring rams.match.merge.gateway_to_pbus_xbar_ctl[0].exact_inhibit_enable to be 0x1 |
| Configuring rams.match.merge.gateway_payload_exact_pbus[0].gateway_payload_exact_pbus to be 0x3 (previous value 0x2 OR new value 0x1) |
| Configuring rams.match.merge.gateway_payload_data[0][0][0][0].gateway_payload_data to be 0x0 |
| Configuring rams.match.merge.gateway_payload_data[0][0][1][0].gateway_payload_data to be 0x0 |
| Configuring rams.match.merge.gateway_payload_data[0][0][0][1].gateway_payload_data to be 0x0 |
| Configuring rams.match.merge.gateway_payload_data[0][0][1][1].gateway_payload_data to be 0x0 |
| Configuring rams.match.merge.gateway_payload_match_adr[0][0][0].gateway_payload_match_adr to be 0x7ffff |
| Configuring rams.match.merge.gateway_payload_match_adr[0][0][1].gateway_payload_match_adr to be 0x7ffff |
| Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=0].action_instruction_adr_payload_shifter_en to be 1. |
| |
| +------------------------------------------------------------------------ |
| | Working on table ingress_port_counter in stage 2 --- |
| +------------------------------------------------------------------------ |
| Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| Configuring rams.array.row[row=4].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3. |
| Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 0. |
| Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1. |
| Configuring rams.array.switchbox.row[row=4].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| Configuring rams.array.row[row=4].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3. |
| Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 0. |
| Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1. |
| Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1. |
| Configuring rams.map_alu.row[row=4].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2) |
| Configuring rams.map_alu.row[row=4].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| Stat table ingress_port_counter is used by match table ingress_port_count_table. |
| Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=0].adr_dist_stats_adr_icxbar_ctl to be 0x4. (previous value = 0x0 OR new value =0x4) |
| Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 0. |
| Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 0. |
| Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1. |
| Configuring rams.map_alu.row[row=4].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1. |
| For counter width 32 and N = 4096 |
| number iterations = 32 |
| b_cur = 379488672.0 |
| eqn(b_cur) = 4294964039.26 |
| max_counter_value = 4294967295 |
| Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_entries_per_word to be 4. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_process_packets to be 1. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.lrt_enable to be 1. |
| TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=2].stats.statistics_ctl.stats_alu_error_enable to be 0. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0x0. |
| Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_entries_per_word be 0x4. |
| Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_has_packets be 0x1. |
| Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_offset be 0x0. |
| Configuring cfg_regs.stats_dump_ctl[logical_table=0].stats_dump_size be 0x0. |
| Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=2].stats_lrt_fsm_sweep_size to be 0x0. |
| Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=2].stats_lrt_fsm_sweep_offset to be 0x0. |
| Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=2].stats_lrt_sweep_adr to be 0x0. |
| Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0. |
| Configuring rams.map_alu.row[row=4].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0. |
| Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=2].packet_action_at_headertime be 1. |
| Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_size be 3. |
| Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=2].movereg_stats_ctl_lt be 0x0. |
| Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=0].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x6. ( previous value = 0x0 OR new value = 0x6) |
| Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=2].mau_ad_stats_virt_lt be 0x1. |
| |
| +------------------------------------------------------------------------ |
| | Working on table egress_port_counter in stage 2 --- |
| +------------------------------------------------------------------------ |
| Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| Configuring rams.array.row[row=6].ram[col=6].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_type to be 3. |
| Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_logical_table to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_ingress to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=0].unitram_enable to be 1. |
| Configuring rams.array.switchbox.row[row=6].ctl.r_stats_alu_o_mux_select.r_stats_alu_o_sel_stats_rd_r_i to be 1. |
| Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_write_data_mux_select to be select of 0. |
| Configuring rams.array.row[row=6].ram[col=7].unit_ram_ctl.match_ram_read_data_mux_select to be select of 0. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_type to be 3. |
| Note that unitram_vpn does not need to be programmed for synthetic two port rams. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_logical_table to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_ingress to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.unitram_config[column_half=1][column_index=1].unitram_enable to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_unitram_adr_mux_select to be 5. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_stats_meter_adr_mux_select_meter to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].ram_ofo_stats_mux_select_statsmeter to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=0].synth2port_radr_mux_select_home_row to be 1. |
| Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x1. (previous value = 0x0 OR new value = 0x1) |
| Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_unitram_adr_mux_select to be 5. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_stats_meter_adr_mux_select_meter to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].ram_ofo_stats_mux_select_statsmeter to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[column_half=1][column_index=1].synth2port_radr_mux_select_home_row to be 1. |
| Configuring rams.map_alu.row[row=6].i2portctl.synth2port_hbus_members[bus_index=0][array_half_index=1].synth2port_hbus_members to be 0x3. (previous value = 0x1 OR new value = 0x2) |
| Configuring rams.map_alu.row[row=6].i2portctl.synth2port_ctl.synth2port_enable to be 1. |
| Stat table egress_port_counter is used by match table egress_port_count_table. |
| Configuring rams.match.adrdist.adr_dist_stats_adr_icxbar_ctl[match_logical_table_id=1].adr_dist_stats_adr_icxbar_ctl to be 0x8. (previous value = 0x0 OR new value =0x8) |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_type to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_logical_table to be 1. |
| Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_generate to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ecc_check to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_ingress to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=0].mapram_enable to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_select to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_wadr_mux_enable to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=0].map_ram_radr_mux_select_smoflo to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_type to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_logical_table to be 1. |
| Note that map ram vpn does not need to be configured for synthetic two port map rams. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_generate to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ecc_check to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_ingress to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.mapram_config[map_ram_index=1].mapram_enable to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_select to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_wadr_mux_enable to be 1. |
| Configuring rams.map_alu.row[row=6].adrmux.ram_address_mux_ctl[array_half_index=1][map_ram_half_index=1].map_ram_radr_mux_select_smoflo to be 1. |
| For counter width 32 and N = 4096 |
| number iterations = 32 |
| b_cur = 379488672.0 |
| eqn(b_cur) = 4294964039.26 |
| max_counter_value = 4294967295 |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=0].lrt_threshold to be 0x169e89a. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=0].lrt_update_interval to be 0xfffffff. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=1].lrt_threshold to be 0x169e89a. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=1].lrt_update_interval to be 0xfffffff. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_threshold[threshold_index=2].lrt_threshold to be 0x169e89a. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.lrt_update_interval[threshold_index=2].lrt_update_interval to be 0xfffffff. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_entries_per_word to be 4. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_process_packets to be 1. |
| Configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.lrt_enable to be 1. |
| TODO: Temporarily configuring rams.map_alu.stats_wrap[stats_group_index=3].stats.statistics_ctl.stats_alu_error_enable to be 0. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0x1. |
| Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_entries_per_word be 0x4. |
| Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_has_packets be 0x1. |
| Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_offset be 0x0. |
| Configuring cfg_regs.stats_dump_ctl[logical_table=1].stats_dump_size be 0x0. |
| Configuring rams.match.adrdist.stats_lrt_fsm_sweep_size[stats_group_index=3].stats_lrt_fsm_sweep_size to be 0x0. |
| Configuring rams.match.adrdist.stats_lrt_fsm_sweep_offset[stats_group_index=3].stats_lrt_fsm_sweep_offset to be 0x0. |
| Configuring rams.match.adrdist.stats_lrt_sweep_adr[stats_group_index=3].stats_lrt_sweep_adr to be 0x0. |
| Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_base to be 0x0. |
| Configuring rams.map_alu.row[row=6].i2portctl.synth2port_vpn_ctl.synth2port_vpn_limit to be 0x0. |
| Configuring rams.match.adrdist.packet_action_at_headertime[type_index=0][alu_index=3].packet_action_at_headertime be 1. |
| Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_size be 3. |
| Configuring rams.match.adrdist.movereg_stats_ctl[stat_alu_index=3].movereg_stats_ctl_lt be 0x1. |
| Configuring rams.match.adrdist.movereg_ad_stats_alu_to_logical_xbar_ctl[logical_index=3].movereg_ad_stats_alu_to_logical_xbar_ctl be 0x3e. ( previous value = 0x6 OR new value = 0x38) |
| Configuring rams.match.adrdist.mau_ad_stats_virt_lt[meter_alu_index=3].mau_ad_stats_virt_lt be 0x2. |
| +------------------------------------------------------------------------ |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x3. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x3. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| -------------------------------------------- |
| Configuration for unused statistics ALUs. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| +------------------------------------------------------------------------ |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| +------------------------------------------------------------------------ |
| Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 1. |
| Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 2. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| |
| +------------------------------------------------------------------------ |
| | MAU Stage 3 |
| +------------------------------------------------------------------------ |
| +------------------------------------------------------------------------ |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| -------------------------------------------- |
| Configuration for unused statistics ALUs. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| +------------------------------------------------------------------------ |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| +------------------------------------------------------------------------ |
| Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| |
| +------------------------------------------------------------------------ |
| | MAU Stage 4 |
| +------------------------------------------------------------------------ |
| +------------------------------------------------------------------------ |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| -------------------------------------------- |
| Configuration for unused statistics ALUs. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| +------------------------------------------------------------------------ |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| +------------------------------------------------------------------------ |
| Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| |
| +------------------------------------------------------------------------ |
| | MAU Stage 5 |
| +------------------------------------------------------------------------ |
| +------------------------------------------------------------------------ |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| -------------------------------------------- |
| Configuration for unused statistics ALUs. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| +------------------------------------------------------------------------ |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| +------------------------------------------------------------------------ |
| Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0. |
| Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0. |
| Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| |
| +------------------------------------------------------------------------ |
| | MAU Stage 6 |
| +------------------------------------------------------------------------ |
| +------------------------------------------------------------------------ |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 19. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 9. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 3. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 19. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 9. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 3. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| -------------------------------------------- |
| Configuration for unused statistics ALUs. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| +------------------------------------------------------------------------ |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| +------------------------------------------------------------------------ |
| Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 0. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 0. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 3. |
| Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| |
| +------------------------------------------------------------------------ |
| | MAU Stage 7 |
| +------------------------------------------------------------------------ |
| +------------------------------------------------------------------------ |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| -------------------------------------------- |
| Configuration for unused statistics ALUs. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| +------------------------------------------------------------------------ |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| +------------------------------------------------------------------------ |
| Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| |
| +------------------------------------------------------------------------ |
| | MAU Stage 8 |
| +------------------------------------------------------------------------ |
| +------------------------------------------------------------------------ |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| -------------------------------------------- |
| Configuration for unused statistics ALUs. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| +------------------------------------------------------------------------ |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| +------------------------------------------------------------------------ |
| Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| |
| +------------------------------------------------------------------------ |
| | MAU Stage 9 |
| +------------------------------------------------------------------------ |
| +------------------------------------------------------------------------ |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| -------------------------------------------- |
| Configuration for unused statistics ALUs. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| +------------------------------------------------------------------------ |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| +------------------------------------------------------------------------ |
| Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| |
| +------------------------------------------------------------------------ |
| | MAU Stage 10 |
| +------------------------------------------------------------------------ |
| +------------------------------------------------------------------------ |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| -------------------------------------------- |
| Configuration for unused statistics ALUs. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| +------------------------------------------------------------------------ |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| +------------------------------------------------------------------------ |
| Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 2. |
| Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 2. |
| Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| |
| +------------------------------------------------------------------------ |
| | MAU Stage 11 |
| +------------------------------------------------------------------------ |
| +------------------------------------------------------------------------ |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=0].start_table_fifo_enable to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay0 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_delay1 to be 0. |
| Configuring rams.match.merge.predication_ctl[direction_index=1].start_table_fifo_enable to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=0][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=0].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.adrdist.adr_dist_pipe_delay[direction_index=1][copy_index=1].adr_dist_pipe_delay to be 0. |
| Configuring rams.match.merge.exact_match_logical_result_delay.exact_match_logical_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_logical_result_en.exact_match_logical_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=0].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_delay[array_half_index=1].exact_match_phys_result_delay to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=0].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_en[array_half_index=1].exact_match_phys_result_en to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=0].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.merge.exact_match_phys_result_thread[array_half_index=1].exact_match_phys_result_thread to be 0x0. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_output_delay_fifo to be 19. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=0].eop_delay_fifo_en to be 1. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_internal_delay_fifo to be 14. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_output_delay_fifo to be 19. |
| Configuring rams.match.adrdist.deferred_eop_bus_delay[direction_index=1].eop_delay_fifo_en to be 1. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=0].meter_alu_thread_egress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_ingress to be 0x0. |
| Configuring rams.match.merge.meter_alu_thread[duplication_index=1].meter_alu_thread_egress to be 0x0. |
| -------------------------------------------- |
| Configuration for unused statistics ALUs. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=0].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=1].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=2].mau_cfg_stats_alu_lt to be 0xf. |
| Configuring cfg_regs.mau_cfg_stats_alu_lt.[stats_group_index=3].mau_cfg_stats_alu_lt to be 0xf. |
| +------------------------------------------------------------------------ |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=0].phv_ingress_thread to be 0x7. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=0].phv_ingress_thread_alu to be 0x7. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=0].phv_ingress_thread_imem to be 0x7. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=4].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=4].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=4].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_ingress_thread[14_byte_group=0][byte_position=8].phv_ingress_thread to be 0x1f. |
| Configuring dp.phv_ingress_thread_alu[14_byte_group=0][byte_position=8].phv_ingress_thread_alu to be 0x1f. |
| Configuring dp.phv_ingress_thread_imem[14_byte_group=0][byte_position=8].phv_ingress_thread_imem to be 0x1f. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=6].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=6].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=6].phv_egress_thread_imem to be 0x7. |
| Configuring dp.phv_egress_thread[14_byte_group=0][byte_position=10].phv_egress_thread to be 0x7. |
| Configuring dp.phv_egress_thread_alu[14_byte_group=0][byte_position=10].phv_egress_thread_alu to be 0x7. |
| Configuring dp.phv_egress_thread_imem[14_byte_group=0][byte_position=10].phv_egress_thread_imem to be 0x7. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=0].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=0].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=0].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=0].emm_ecc_error_ctl_delay to be 0. |
| Configuring rams.match.merge.tcam_match_error_ctl[dir=1].tcam_match_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.tind_ecc_error_ctl[dir=1].tind_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_o_err_en to be 1. |
| Configuring rams.match.merge.gfm_parity_error_ctl[dir=1].gfm_parity_error_ctl_delay to be 0. |
| Configuring rams.match.merge.emm_ecc_error_ctl[dir=1].emm_ecc_error_ctl_delay to be 0. |
| +------------------------------------------------------------------------ |
| Configuring dp.action_output_delay[direction_index=0].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=0].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=0].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=0].next_stage_dependency_on_cur to be 0. |
| Configuring dp.action_output_delay[direction_index=1].action_output_delay to be 17. |
| Configuring dp.pipelength_added_stages[direction_index=1].pipelength_added_stages to be 0. |
| Configuring dp.cur_stage_dependency_on_prev[direction_index=1].cur_stage_dependency_on_prev to be 2. |
| Configuring dp.next_stage_dependency_on_cur[direction_index=1].next_stage_dependency_on_cur to be 0. |
| Configuring dp.match_ie_input_mux_sel.match_ie_input_mux_sel to be 0. |
| Configuring dp.stage_concurrent_with_prev.stage_concurrent_with_prev to be 3. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_ingress_final_output_enable to be 0. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_action_output_enable to be 1. |
| Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0. |
| |
| +------------------------------------------------------------------------ |
| | Number of configuration field values set in Match-Action Stages: 1635 |
| +------------------------------------------------------------------------ |
| |
| +------------------------------------------------------------------------ |
| | MAU Feature Characteristics: |
| +------------------------------------------------------------------------ |
| |
| |
| Features per Stage for ingress: |
| ----------------------------------------------------------------------------------------------- |
| | Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency | |
| | | | | | LPF | (max words) | | to Previous | |
| ----------------------------------------------------------------------------------------------- |
| | 0 | Yes | No | No | No | No (0) | No | match | |
| | 1 | No | Yes | Yes | No | No (0) | No | match | |
| | 2 | Yes | No | Yes | No | No (0) | No | match | |
| | 3 | Yes* | No | Yes* | No | No (0) | No | concurrent | |
| | 4 | Yes* | No | Yes* | No | No (0) | No | concurrent | |
| | 5 | Yes* | No | Yes* | No | No (0) | No | concurrent | |
| | 6 | No | No | No | No | No (0) | No | match | |
| | 7 | No | No | No | No | No (0) | No | concurrent | |
| | 8 | No | No | No | No | No (0) | No | concurrent | |
| | 9 | No | No | No | No | No (0) | No | concurrent | |
| | 10 | No | No | No | No | No (0) | No | concurrent | |
| | 11 | No | No | No | No | No (0) | No | concurrent | |
| ----------------------------------------------------------------------------------------------- |
| |
| A '*' denotes that this feature was added to balance an action/concurrent chain. |
| |
| |
| Features per Stage for egress: |
| ----------------------------------------------------------------------------------------------- |
| | Stage Number | Exact | Ternary | Statistics | Meter | Selector | Stateful | Dependency | |
| | | | | | LPF | (max words) | | to Previous | |
| ----------------------------------------------------------------------------------------------- |
| | 0 | Yes | No | No | No | No (0) | No | match | |
| | 1 | Yes* | No | No | No | No (0) | No | concurrent | |
| | 2 | Yes* | No | No | No | No (0) | No | concurrent | |
| | 3 | Yes* | No | No | No | No (0) | No | concurrent | |
| | 4 | Yes* | No | No | No | No (0) | No | concurrent | |
| | 5 | Yes* | No | No | No | No (0) | No | concurrent | |
| | 6 | No | No | No | No | No (0) | No | match | |
| | 7 | No | No | No | No | No (0) | No | concurrent | |
| | 8 | No | No | No | No | No (0) | No | concurrent | |
| | 9 | No | No | No | No | No (0) | No | concurrent | |
| | 10 | No | No | No | No | No (0) | No | concurrent | |
| | 11 | No | No | No | No | No (0) | No | concurrent | |
| ----------------------------------------------------------------------------------------------- |
| |
| A '*' denotes that this feature was added to balance an action/concurrent chain. |
| |
| +------------------------------------------------------------------------ |
| | MAU Latency Characteristics: |
| +------------------------------------------------------------------------ |
| |
| |
| Clock Cycles Per Stage For ingress: |
| ----------------------------------------------------------------------------------------------------- |
| | Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency | |
| ----------------------------------------------------------------------------------------------------- |
| | 0 | 20 | 11 | match | 20 | |
| | 1 | 22 | 13 | match | 22 | |
| | 2 | 20 | 11 | match | 20 | |
| | 3 | 20 | 11 | concurrent | 1 | |
| | 4 | 20 | 11 | concurrent | 1 | |
| | 5 | 20 | 11 | concurrent | 1 | |
| | 6 | 20 | 11 | match | 20 | |
| | 7 | 20 | 11 | concurrent | 1 | |
| | 8 | 20 | 11 | concurrent | 1 | |
| | 9 | 20 | 11 | concurrent | 1 | |
| | 10 | 20 | 11 | concurrent | 1 | |
| | 11 | 20 | 11 | concurrent | 1 | |
| ----------------------------------------------------------------------------------------------------- |
| |
| Total latency for ingress: 94 |
| |
| |
| Clock Cycles Per Stage For egress: |
| ----------------------------------------------------------------------------------------------------- |
| | Stage Number | Clock Cycles | Predication Cycle | Dependency To Previous | Cycles Add To Latency | |
| ----------------------------------------------------------------------------------------------------- |
| | 0 | 20 | 11 | match | 20 | |
| | 1 | 20 | 11 | concurrent | 1 | |
| | 2 | 20 | 11 | concurrent | 1 | |
| | 3 | 20 | 11 | concurrent | 1 | |
| | 4 | 20 | 11 | concurrent | 1 | |
| | 5 | 20 | 11 | concurrent | 1 | |
| | 6 | 20 | 11 | match | 20 | |
| | 7 | 20 | 11 | concurrent | 1 | |
| | 8 | 20 | 11 | concurrent | 1 | |
| | 9 | 20 | 11 | concurrent | 1 | |
| | 10 | 20 | 11 | concurrent | 1 | |
| | 11 | 20 | 11 | concurrent | 1 | |
| ----------------------------------------------------------------------------------------------------- |
| |
| Total latency for egress: 54 |