| +---------------------------------------------------------------------+ |
| | Log file: mau.gw.log | |
| | Compiler version: 5.1.0 (fca32d1) | |
| | Created on: Wed Sep 13 12:57:41 2017 | |
| +---------------------------------------------------------------------+ |
| |
| cond _condition_0: not valid packet_out_hdr |
| not valid packet_out_hdr |
| ! not not valid packet_out_hdr |
| cond _condition_0 can be gateway (1+0)x1 |
| cond !_condition_0 can be gateway (1+0)x1 |
| _condition_0 is gateway for table0 |
| cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 512 |
| ig_intr_md_for_tm.ucast_egress_port < 512 |
| ! ig_intr_md_for_tm.ucast_egress_port >= 512 |
| cond _condition_2 can be gateway (9+0)x1 |
| cond !_condition_2 can be gateway (9+0)x1 |
| _condition_2 is gateway for ingress_port_count_table |
| fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7fe022d0bc50>]) and and xor_fields is OrderedSet() |
| fields = OrderedSet() and and xor_fields is OrderedSet() |
| cond _condition_0: not valid packet_out_hdr |
| not valid packet_out_hdr |
| ! not not valid packet_out_hdr |
| cond _condition_0 can be gateway (1+0)x1 |
| cond !_condition_0 can be gateway (1+0)x1 |
| _condition_0 is gateway for table0 |
| cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 512 |
| ig_intr_md_for_tm.ucast_egress_port < 512 |
| ! ig_intr_md_for_tm.ucast_egress_port >= 512 |
| cond _condition_2 can be gateway (9+0)x1 |
| cond !_condition_2 can be gateway (9+0)x1 |
| _condition_2 is gateway for ingress_port_count_table |
| fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7fe022d0bc50>]) and and xor_fields is OrderedSet() |
| fields = OrderedSet() and and xor_fields is OrderedSet() |
| cond _condition_0: not valid packet_out_hdr |
| not valid packet_out_hdr |
| ! not not valid packet_out_hdr |
| cond _condition_0 can be gateway (1+0)x1 |
| cond !_condition_0 can be gateway (1+0)x1 |
| _condition_0 is gateway for table0 |
| cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 512 |
| ig_intr_md_for_tm.ucast_egress_port < 512 |
| ! ig_intr_md_for_tm.ucast_egress_port >= 512 |
| cond _condition_2 can be gateway (9+0)x1 |
| cond !_condition_2 can be gateway (9+0)x1 |
| _condition_2 is gateway for ingress_port_count_table |
| fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7fe022d0bc50>]) and and xor_fields is OrderedSet() |
| fields = OrderedSet() and and xor_fields is OrderedSet() |
| cond _always_true: True == True |
| True |
| ! False |
| cond _always_true: True == True |
| True |
| ! False |
| --> Stage Gateway Table for condition _condition_0 in stage 0 |
| T -> table0(0), F -> process_packet_out_table(1) |
| building tcam for GatewayTest('not valid packet_out_hdr') |
| adding line (match=0 mask=100000000 T) |
| tcam data: [(match=0 mask=100000000 T)] |
| final.tcam: [(match=0 mask=100000000 T)], miss=False |
| --> Stage Gateway Table for condition process_packet_out_table_always_true_condition in stage 0 |
| T -> process_packet_out_table(1), F -> process_packet_out_table(1) |
| building tcam for GatewayTest('True') |
| adding line (match=0 mask=0 T) |
| tcam data: [(match=0 mask=0 T)] |
| final.tcam: [(match=0 mask=0 T)], miss=False |
| --> Stage Gateway Table for condition _condition_2 in stage 2 |
| T -> ingress_port_count_table(32), F -> None(255) |
| building tcam for GatewayTest('ig_intr_md_for_tm.ucast_egress_port < 512') |
| adding line (range=[ffff ffff 0] match=0 mask=0 T) |
| adding line (range=[ffff 0 ffff] match=0 mask=0 T) |
| adding line (range=[3 ffff ffff] match=0 mask=0 T) |
| tcam data: [(range=[ffff ffff 0] match=0 mask=0 T), (range=[ffff 0 ffff] match=0 mask=0 T), (range=[3 ffff ffff] match=0 mask=0 T)] |
| final.tcam: [(range=[ffff ffff 0] match=0 mask=0 T), (range=[ffff 0 ffff] match=0 mask=0 T), (range=[3 ffff ffff] match=0 mask=0 T)], miss=False |
| --> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 2 |
| T -> egress_port_count_table(33), F -> egress_port_count_table(33) |
| building tcam for GatewayTest('True') |
| adding line (match=0 mask=0 T) |
| tcam data: [(match=0 mask=0 T)] |
| final.tcam: [(match=0 mask=0 T)], miss=False |