Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 4 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
| 38 | OFP_TCP_PORT = 6633, |
| 39 | OFP_SSL_PORT = 6633, |
| 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFP_VLAN_NONE = 0, |
| 46 | |
| 47 | OFP_FLOW_PERMANENT = 0, |
| 48 | |
| 49 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 50 | |
| 51 | OFP_NO_BUFFER = 0xffffffff, |
| 52 | |
| 53 | DESC_STR_LEN = 256, |
| 54 | SERIAL_NUM_LEN = 32, |
| 55 | |
| 56 | OFPQ_ALL = 0xffffffff, |
| 57 | OFPQ_MAX_RATE_UNCFG = 0xffff, |
| 58 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 59 | }; |
| 60 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 61 | enum ofp_port_no(wire_type=uint32_t, complete=no) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 62 | OFPP_ANY = 0xffffffff, |
| 63 | }; |
| 64 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 65 | enum ofp_port(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 66 | OFPP_MAX = 0xffffff00, |
| 67 | OFPP_IN_PORT = 0xfffffff8, |
| 68 | OFPP_TABLE = 0xfffffff9, |
| 69 | OFPP_NORMAL = 0xfffffffa, |
| 70 | OFPP_FLOOD = 0xfffffffb, |
| 71 | OFPP_ALL = 0xfffffffc, |
| 72 | OFPP_CONTROLLER = 0xfffffffd, |
| 73 | OFPP_LOCAL = 0xfffffffe, |
| 74 | }; |
| 75 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 76 | enum ofp_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 77 | OFPT_HELLO = 0, |
| 78 | OFPT_ERROR = 1, |
| 79 | OFPT_ECHO_REQUEST = 2, |
| 80 | OFPT_ECHO_REPLY = 3, |
| 81 | OFPT_EXPERIMENTER = 4, |
| 82 | OFPT_FEATURES_REQUEST = 5, |
| 83 | OFPT_FEATURES_REPLY = 6, |
| 84 | OFPT_GET_CONFIG_REQUEST = 7, |
| 85 | OFPT_GET_CONFIG_REPLY = 8, |
| 86 | OFPT_SET_CONFIG = 9, |
| 87 | OFPT_PACKET_IN = 10, |
| 88 | OFPT_FLOW_REMOVED = 11, |
| 89 | OFPT_PORT_STATUS = 12, |
| 90 | OFPT_PACKET_OUT = 13, |
| 91 | OFPT_FLOW_MOD = 14, |
| 92 | OFPT_GROUP_MOD = 15, |
| 93 | OFPT_PORT_MOD = 16, |
| 94 | OFPT_TABLE_MOD = 17, |
| 95 | OFPT_MULTIPART_REQUEST = 18, |
| 96 | OFPT_MULTIPART_REPLY = 19, |
| 97 | OFPT_BARRIER_REQUEST = 20, |
| 98 | OFPT_BARRIER_REPLY = 21, |
| 99 | OFPT_QUEUE_GET_CONFIG_REQUEST = 22, |
| 100 | OFPT_QUEUE_GET_CONFIG_REPLY = 23, |
| 101 | OFPT_ROLE_REQUEST = 24, |
| 102 | OFPT_ROLE_REPLY = 25, |
| 103 | OFPT_GET_ASYNC_REQUEST = 26, |
| 104 | OFPT_GET_ASYNC_REPLY = 27, |
| 105 | OFPT_SET_ASYNC = 28, |
| 106 | OFPT_METER_MOD = 29, |
| 107 | }; |
| 108 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 109 | enum ofp_config_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 110 | OFPC_FRAG_NORMAL = 0, |
| 111 | OFPC_FRAG_DROP = 1, |
| 112 | OFPC_FRAG_REASM = 2, |
| 113 | OFPC_FRAG_MASK = 3, |
| 114 | }; |
| 115 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 116 | enum ofp_table_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 117 | OFPTC_DEPRECATED_MASK = 0x3, |
| 118 | }; |
| 119 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 120 | enum ofp_table(wire_type=uint8_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 121 | OFPTT_MAX = 0xfe, |
| 122 | OFPTT_ALL = 0xff, |
| 123 | }; |
| 124 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 125 | enum ofp_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 126 | OFPC_FLOW_STATS = 0x1, |
| 127 | OFPC_TABLE_STATS = 0x2, |
| 128 | OFPC_PORT_STATS = 0x4, |
| 129 | OFPC_GROUP_STATS = 0x8, |
| 130 | OFPC_IP_REASM = 0x20, |
| 131 | OFPC_QUEUE_STATS = 0x40, |
| 132 | OFPC_PORT_BLOCKED = 0x100, |
| 133 | }; |
| 134 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 135 | enum ofp_port_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 136 | OFPPC_PORT_DOWN = 0x1, |
| 137 | OFPPC_NO_RECV = 0x4, |
| 138 | OFPPC_NO_FWD = 0x20, |
| 139 | OFPPC_NO_PACKET_IN = 0x40, |
| 140 | }; |
| 141 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 142 | enum ofp_port_state(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 143 | OFPPS_LINK_DOWN = 0x1, |
| 144 | OFPPS_BLOCKED = 0x2, |
| 145 | OFPPS_LIVE = 0x4, |
| 146 | }; |
| 147 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 148 | enum ofp_port_features(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 149 | OFPPF_10MB_HD = 0x1, |
| 150 | OFPPF_10MB_FD = 0x2, |
| 151 | OFPPF_100MB_HD = 0x4, |
| 152 | OFPPF_100MB_FD = 0x8, |
| 153 | OFPPF_1GB_HD = 0x10, |
| 154 | OFPPF_1GB_FD = 0x20, |
| 155 | OFPPF_10GB_FD = 0x40, |
| 156 | OFPPF_40GB_FD = 0x80, |
| 157 | OFPPF_100GB_FD = 0x100, |
| 158 | OFPPF_1TB_FD = 0x200, |
| 159 | OFPPF_OTHER = 0x400, |
| 160 | OFPPF_COPPER = 0x800, |
| 161 | OFPPF_FIBER = 0x1000, |
| 162 | OFPPF_AUTONEG = 0x2000, |
| 163 | OFPPF_PAUSE = 0x4000, |
| 164 | OFPPF_PAUSE_ASYM = 0x8000, |
| 165 | }; |
| 166 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 167 | enum ofp_port_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 168 | OFPPR_ADD = 0, |
| 169 | OFPPR_DELETE = 1, |
| 170 | OFPPR_MODIFY = 2, |
| 171 | }; |
| 172 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 173 | enum ofp_match_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 174 | OFPMT_STANDARD = 0, |
| 175 | OFPMT_OXM = 1, |
| 176 | }; |
| 177 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 178 | enum ofp_oxm_class(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 179 | OFPXMC_NXM_0 = 0, |
| 180 | OFPXMC_NXM_1 = 1, |
| 181 | OFPXMC_OPENFLOW_BASIC = 0x8000, |
| 182 | OFPXMC_EXPERIMENTER = 0xffff, |
| 183 | }; |
| 184 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 185 | enum ofp_vlan_id(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 186 | OFPVID_NONE = 0, |
| 187 | OFPVID_PRESENT = 0x1000, |
| 188 | }; |
| 189 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 190 | // FIXME: OF spec specified this as '9' bits, implicitly adding |
| 191 | // to full byte |
| 192 | enum ofp_ipv6exthdr_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 193 | OFPIEH_NONEXT = 0x1, |
| 194 | OFPIEH_ESP = 0x2, |
| 195 | OFPIEH_AUTH = 0x4, |
| 196 | OFPIEH_DEST = 0x8, |
| 197 | OFPIEH_FRAG = 0x10, |
| 198 | OFPIEH_ROUTER = 0x20, |
| 199 | OFPIEH_HOP = 0x40, |
| 200 | OFPIEH_UNREP = 0x80, |
| 201 | OFPIEH_UNSEQ = 0x100, |
| 202 | }; |
| 203 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 204 | enum ofp_action_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 205 | OFPAT_OUTPUT = 0, |
| 206 | OFPAT_COPY_TTL_OUT = 0xb, |
| 207 | OFPAT_COPY_TTL_IN = 0xc, |
| 208 | OFPAT_SET_MPLS_TTL = 0xf, |
| 209 | OFPAT_DEC_MPLS_TTL = 0x10, |
| 210 | OFPAT_PUSH_VLAN = 0x11, |
| 211 | OFPAT_POP_VLAN = 0x12, |
| 212 | OFPAT_PUSH_MPLS = 0x13, |
| 213 | OFPAT_POP_MPLS = 0x14, |
| 214 | OFPAT_SET_QUEUE = 0x15, |
| 215 | OFPAT_GROUP = 0x16, |
| 216 | OFPAT_SET_NW_TTL = 0x17, |
| 217 | OFPAT_DEC_NW_TTL = 0x18, |
| 218 | OFPAT_SET_FIELD = 0x19, |
| 219 | OFPAT_PUSH_PBB = 0x1a, |
| 220 | OFPAT_POP_PBB = 0x1b, |
| 221 | OFPAT_EXPERIMENTER = 0xffff, |
| 222 | }; |
| 223 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 224 | enum ofp_controller_max_len(wire_type=uint16_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 225 | OFPCML_MAX = 0xffe5, |
| 226 | OFPCML_NO_BUFFER = 0xffff, |
| 227 | }; |
| 228 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 229 | enum ofp_instruction_type(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 230 | OFPIT_GOTO_TABLE = 0x1, |
| 231 | OFPIT_WRITE_METADATA = 0x2, |
| 232 | OFPIT_WRITE_ACTIONS = 0x3, |
| 233 | OFPIT_APPLY_ACTIONS = 0x4, |
| 234 | OFPIT_CLEAR_ACTIONS = 0x5, |
| 235 | OFPIT_METER = 0x6, |
| 236 | OFPIT_EXPERIMENTER = 0xffff, |
| 237 | }; |
| 238 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 239 | enum ofp_flow_mod_command(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 240 | OFPFC_ADD = 0, |
| 241 | OFPFC_MODIFY = 1, |
| 242 | OFPFC_MODIFY_STRICT = 2, |
| 243 | OFPFC_DELETE = 3, |
| 244 | OFPFC_DELETE_STRICT = 4, |
| 245 | }; |
| 246 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 247 | enum ofp_flow_mod_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 248 | OFPFF_SEND_FLOW_REM = 0x1, |
| 249 | OFPFF_CHECK_OVERLAP = 0x2, |
| 250 | OFPFF_RESET_COUNTS = 0x4, |
| 251 | OFPFF_NO_PKT_COUNTS = 0x8, |
| 252 | OFPFF_NO_BYT_COUNTS = 0x10, |
| 253 | }; |
| 254 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 255 | enum ofp_group(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 256 | OFPG_MAX = 0xffffff00, |
| 257 | OFPG_ALL = 0xfffffffc, |
| 258 | OFPG_ANY = 0xffffffff, |
| 259 | }; |
| 260 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 261 | enum ofp_group_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 262 | OFPGC_ADD = 0, |
| 263 | OFPGC_MODIFY = 1, |
| 264 | OFPGC_DELETE = 2, |
| 265 | }; |
| 266 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 267 | enum ofp_group_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 268 | OFPGT_ALL = 0, |
| 269 | OFPGT_SELECT = 1, |
| 270 | OFPGT_INDIRECT = 2, |
| 271 | OFPGT_FF = 3, |
| 272 | }; |
| 273 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 274 | enum ofp_packet_in_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 275 | OFPR_NO_MATCH = 0, |
| 276 | OFPR_ACTION = 1, |
| 277 | OFPR_INVALID_TTL = 2, |
| 278 | }; |
| 279 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 280 | enum ofp_flow_removed_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 281 | OFPRR_IDLE_TIMEOUT = 0, |
| 282 | OFPRR_HARD_TIMEOUT = 1, |
| 283 | OFPRR_DELETE = 2, |
| 284 | OFPRR_GROUP_DELETE = 3, |
| 285 | }; |
| 286 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 287 | enum ofp_meter(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 288 | OFPM_MAX = 0xffff0000, |
| 289 | OFPM_SLOWPATH = 0xfffffffd, |
| 290 | OFPM_CONTROLLER = 0xfffffffe, |
| 291 | OFPM_ALL = 0xffffffff, |
| 292 | }; |
| 293 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 294 | enum ofp_meter_band_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 295 | OFPMBT_DROP = 0x1, |
| 296 | OFPMBT_DSCP_REMARK = 0x2, |
| 297 | OFPMBT_EXPERIMENTER = 0xffff, |
| 298 | }; |
| 299 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 300 | enum ofp_meter_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 301 | OFPMC_ADD = 0, |
| 302 | OFPMC_MODIFY = 1, |
| 303 | OFPMC_DELETE = 2, |
| 304 | }; |
| 305 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 306 | enum ofp_meter_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 307 | OFPMF_KBPS = 0x1, |
| 308 | OFPMF_PKTPS = 0x2, |
| 309 | OFPMF_BURST = 0x4, |
| 310 | OFPMF_STATS = 0x8, |
| 311 | }; |
| 312 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 313 | enum ofp_error_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 314 | OFPET_HELLO_FAILED = 0, |
| 315 | OFPET_BAD_REQUEST = 1, |
| 316 | OFPET_BAD_ACTION = 2, |
| 317 | OFPET_BAD_INSTRUCTION = 3, |
| 318 | OFPET_BAD_MATCH = 4, |
| 319 | OFPET_FLOW_MOD_FAILED = 5, |
| 320 | OFPET_GROUP_MOD_FAILED = 6, |
| 321 | OFPET_PORT_MOD_FAILED = 7, |
| 322 | OFPET_TABLE_MOD_FAILED = 8, |
| 323 | OFPET_QUEUE_OP_FAILED = 9, |
| 324 | OFPET_SWITCH_CONFIG_FAILED = 10, |
| 325 | OFPET_ROLE_REQUEST_FAILED = 11, |
| 326 | OFPET_METER_MOD_FAILED = 12, |
| 327 | OFPET_TABLE_FEATURES_FAILED = 13, |
| 328 | OFPET_EXPERIMENTER = 0xffff, |
| 329 | }; |
| 330 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 331 | enum ofp_hello_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 332 | OFPHFC_INCOMPATIBLE = 0, |
| 333 | OFPHFC_EPERM = 1, |
| 334 | }; |
| 335 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 336 | enum ofp_bad_request_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 337 | OFPBRC_BAD_VERSION = 0, |
| 338 | OFPBRC_BAD_TYPE = 1, |
| 339 | OFPBRC_BAD_MULTIPART = 2, |
| 340 | OFPBRC_BAD_EXPERIMENTER = 3, |
| 341 | OFPBRC_BAD_EXP_TYPE = 4, |
| 342 | OFPBRC_EPERM = 5, |
| 343 | OFPBRC_BAD_LEN = 6, |
| 344 | OFPBRC_BUFFER_EMPTY = 7, |
| 345 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 346 | OFPBRC_BAD_TABLE_ID = 9, |
| 347 | OFPBRC_IS_SLAVE = 10, |
| 348 | OFPBRC_BAD_PORT = 11, |
| 349 | OFPBRC_BAD_PACKET = 12, |
| 350 | OFPBRC_MULTIPART_BUFFER_OVERFLOW = 13, |
| 351 | }; |
| 352 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 353 | enum ofp_bad_action_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 354 | OFPBAC_BAD_TYPE = 0, |
| 355 | OFPBAC_BAD_LEN = 1, |
| 356 | OFPBAC_BAD_EXPERIMENTER = 2, |
| 357 | OFPBAC_BAD_EXP_TYPE = 3, |
| 358 | OFPBAC_BAD_OUT_PORT = 4, |
| 359 | OFPBAC_BAD_ARGUMENT = 5, |
| 360 | OFPBAC_EPERM = 6, |
| 361 | OFPBAC_TOO_MANY = 7, |
| 362 | OFPBAC_BAD_QUEUE = 8, |
| 363 | OFPBAC_BAD_OUT_GROUP = 9, |
| 364 | OFPBAC_MATCH_INCONSISTENT = 10, |
| 365 | OFPBAC_UNSUPPORTED_ORDER = 11, |
| 366 | OFPBAC_BAD_TAG = 12, |
| 367 | OFPBAC_BAD_SET_TYPE = 13, |
| 368 | OFPBAC_BAD_SET_LEN = 14, |
| 369 | OFPBAC_BAD_SET_ARGUMENT = 15, |
| 370 | }; |
| 371 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 372 | enum ofp_bad_instruction_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 373 | OFPBIC_UNKNOWN_INST = 0, |
| 374 | OFPBIC_UNSUP_INST = 1, |
| 375 | OFPBIC_BAD_TABLE_ID = 2, |
| 376 | OFPBIC_UNSUP_METADATA = 3, |
| 377 | OFPBIC_UNSUP_METADATA_MASK = 4, |
| 378 | OFPBIC_BAD_EXPERIMENTER = 5, |
| 379 | OFPBIC_BAD_EXP_TYPE = 6, |
| 380 | OFPBIC_BAD_LEN = 7, |
| 381 | OFPBIC_EPERM = 8, |
| 382 | }; |
| 383 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 384 | enum ofp_bad_match_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 385 | OFPBMC_BAD_TYPE = 0, |
| 386 | OFPBMC_BAD_LEN = 1, |
| 387 | OFPBMC_BAD_TAG = 2, |
| 388 | OFPBMC_BAD_DL_ADDR_MASK = 3, |
| 389 | OFPBMC_BAD_NW_ADDR_MASK = 4, |
| 390 | OFPBMC_BAD_WILDCARDS = 5, |
| 391 | OFPBMC_BAD_FIELD = 6, |
| 392 | OFPBMC_BAD_VALUE = 7, |
| 393 | OFPBMC_BAD_MASK = 8, |
| 394 | OFPBMC_BAD_PREREQ = 9, |
| 395 | OFPBMC_DUP_FIELD = 10, |
| 396 | OFPBMC_EPERM = 11, |
| 397 | }; |
| 398 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 399 | enum ofp_flow_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 400 | OFPFMFC_UNKNOWN = 0, |
| 401 | OFPFMFC_TABLE_FULL = 1, |
| 402 | OFPFMFC_BAD_TABLE_ID = 2, |
| 403 | OFPFMFC_OVERLAP = 3, |
| 404 | OFPFMFC_EPERM = 4, |
| 405 | OFPFMFC_BAD_TIMEOUT = 5, |
| 406 | OFPFMFC_BAD_COMMAND = 6, |
| 407 | OFPFMFC_BAD_FLAGS = 7, |
| 408 | }; |
| 409 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 410 | enum ofp_group_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 411 | OFPGMFC_GROUP_EXISTS = 0, |
| 412 | OFPGMFC_INVALID_GROUP = 1, |
| 413 | OFPGMFC_WEIGHT_UNSUPPORTED = 2, |
| 414 | OFPGMFC_OUT_OF_GROUPS = 3, |
| 415 | OFPGMFC_OUT_OF_BUCKETS = 4, |
| 416 | OFPGMFC_CHAINING_UNSUPPORTED = 5, |
| 417 | OFPGMFC_WATCH_UNSUPPORTED = 6, |
| 418 | OFPGMFC_LOOP = 7, |
| 419 | OFPGMFC_UNKNOWN_GROUP = 8, |
| 420 | OFPGMFC_CHAINED_GROUP = 9, |
| 421 | OFPGMFC_BAD_TYPE = 10, |
| 422 | OFPGMFC_BAD_COMMAND = 11, |
| 423 | OFPGMFC_BAD_BUCKET = 12, |
| 424 | OFPGMFC_BAD_WATCH = 13, |
| 425 | OFPGMFC_EPERM = 14, |
| 426 | }; |
| 427 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 428 | enum ofp_port_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 429 | OFPPMFC_BAD_PORT = 0, |
| 430 | OFPPMFC_BAD_HW_ADDR = 1, |
| 431 | OFPPMFC_BAD_CONFIG = 2, |
| 432 | OFPPMFC_BAD_ADVERTISE = 3, |
| 433 | OFPPMFC_EPERM = 4, |
| 434 | }; |
| 435 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 436 | enum ofp_table_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 437 | OFPTMFC_BAD_TABLE = 0, |
| 438 | OFPTMFC_BAD_CONFIG = 1, |
| 439 | OFPTMFC_EPERM = 2, |
| 440 | }; |
| 441 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 442 | enum ofp_queue_op_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 443 | OFPQOFC_BAD_PORT = 0, |
| 444 | OFPQOFC_BAD_QUEUE = 1, |
| 445 | OFPQOFC_EPERM = 2, |
| 446 | }; |
| 447 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 448 | enum ofp_switch_config_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 449 | OFPSCFC_BAD_FLAGS = 0, |
| 450 | OFPSCFC_BAD_LEN = 1, |
| 451 | OFPSCFC_EPERM = 2, |
| 452 | }; |
| 453 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 454 | enum ofp_role_request_failed_code(wire_type=uint16_t){ |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 455 | OFPRRFC_STALE = 0, |
| 456 | OFPRRFC_UNSUP = 1, |
| 457 | OFPRRFC_BAD_ROLE = 2, |
| 458 | }; |
| 459 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 460 | enum ofp_meter_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 461 | OFPMMFC_UNKNOWN = 0, |
| 462 | OFPMMFC_METER_EXISTS = 1, |
| 463 | OFPMMFC_INVALID_METER = 2, |
| 464 | OFPMMFC_UNKNOWN_METER = 3, |
| 465 | OFPMMFC_BAD_COMMAND = 4, |
| 466 | OFPMMFC_BAD_FLAGS = 5, |
| 467 | OFPMMFC_BAD_RATE = 6, |
| 468 | OFPMMFC_BAD_BURST = 7, |
| 469 | OFPMMFC_BAD_BAND = 8, |
| 470 | OFPMMFC_BAD_BAND_VALUE = 9, |
| 471 | OFPMMFC_OUT_OF_METERS = 10, |
| 472 | OFPMMFC_OUT_OF_BANDS = 11, |
| 473 | }; |
| 474 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 475 | enum ofp_table_features_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 476 | OFPTFFC_BAD_TABLE = 0, |
| 477 | OFPTFFC_BAD_METADATA = 1, |
| 478 | OFPTFFC_BAD_TYPE = 2, |
| 479 | OFPTFFC_BAD_LEN = 3, |
| 480 | OFPTFFC_BAD_ARGUMENT = 4, |
| 481 | OFPTFFC_EPERM = 5, |
| 482 | }; |
| 483 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 484 | enum ofp_multipart_types(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 485 | OFPMP_DESC = 0, |
| 486 | OFPMP_FLOW = 1, |
| 487 | OFPMP_AGGREGATE = 2, |
| 488 | OFPMP_TABLE = 3, |
| 489 | OFPMP_PORT_STATS = 4, |
| 490 | OFPMP_QUEUE = 5, |
| 491 | OFPMP_GROUP = 6, |
| 492 | OFPMP_GROUP_DESC = 7, |
| 493 | OFPMP_GROUP_FEATURES = 8, |
| 494 | OFPMP_METER = 9, |
| 495 | OFPMP_METER_CONFIG = 10, |
| 496 | OFPMP_METER_FEATURES = 11, |
| 497 | OFPMP_TABLE_FEATURES = 12, |
| 498 | OFPMP_PORT_DESC = 13, |
| 499 | OFPMP_EXPERIMENTER = 0xffff, |
| 500 | }; |
| 501 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 502 | enum ofp_multipart_request_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 503 | OFPMPF_REQ_MORE = 0x1, |
| 504 | }; |
| 505 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 506 | enum ofp_multipart_reply_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 507 | OFPMPF_REPLY_MORE = 0x1, |
| 508 | }; |
| 509 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 510 | enum ofp_table_feature_prop_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 511 | OFPTFPT_INSTRUCTIONS = 0, |
| 512 | OFPTFPT_INSTRUCTIONS_MISS = 1, |
| 513 | OFPTFPT_NEXT_TABLES = 2, |
| 514 | OFPTFPT_NEXT_TABLES_MISS = 3, |
| 515 | OFPTFPT_WRITE_ACTIONS = 4, |
| 516 | OFPTFPT_WRITE_ACTIONS_MISS = 5, |
| 517 | OFPTFPT_APPLY_ACTIONS = 6, |
| 518 | OFPTFPT_APPLY_ACTIONS_MISS = 7, |
| 519 | OFPTFPT_MATCH = 8, |
| 520 | OFPTFPT_WILDCARDS = 0xa, |
| 521 | OFPTFPT_WRITE_SETFIELD = 0xc, |
| 522 | OFPTFPT_WRITE_SETFIELD_MISS = 0xd, |
| 523 | OFPTFPT_APPLY_SETFIELD = 0xe, |
| 524 | OFPTFPT_APPLY_SETFIELD_MISS = 0xf, |
| 525 | OFPTFPT_EXPERIMENTER = 0xfffe, |
| 526 | OFPTFPT_EXPERIMENTER_MISS = 0xffff, |
| 527 | }; |
| 528 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 529 | enum ofp_group_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 530 | OFPGFC_SELECT_WEIGHT = 0x1, |
| 531 | OFPGFC_SELECT_LIVENESS = 0x2, |
| 532 | OFPGFC_CHAINING = 0x4, |
| 533 | OFPGFC_CHAINING_CHECKS = 0x8, |
| 534 | }; |
| 535 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 536 | enum ofp_queue_properties(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 537 | OFPQT_MIN_RATE = 0x1, |
| 538 | OFPQT_MAX_RATE = 0x2, |
| 539 | OFPQT_EXPERIMENTER = 0xffff, |
| 540 | }; |
| 541 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 542 | enum ofp_controller_role(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 543 | OFPCR_ROLE_NOCHANGE = 0, |
| 544 | OFPCR_ROLE_EQUAL = 1, |
| 545 | OFPCR_ROLE_MASTER = 2, |
| 546 | OFPCR_ROLE_SLAVE = 3, |
| 547 | }; |
| 548 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 549 | enum ofp_hello_elem_type(wire_type=uint16_t) { |
Rich Lane | 0733cd6 | 2013-04-18 21:14:42 -0700 | [diff] [blame] | 550 | OFPHET_VERSIONBITMAP = 1, |
| 551 | }; |
| 552 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 553 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 554 | uint8_t version; |
| 555 | uint8_t type; |
| 556 | uint16_t length; |
| 557 | uint32_t xid; |
| 558 | }; |
| 559 | |
| 560 | // Special structures used for managing scalar list elements |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 561 | struct of_uint32 { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 562 | uint32_t value; |
| 563 | }; |
| 564 | |
| 565 | // Special structures used for managing scalar list elements |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 566 | struct of_uint8 { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 567 | uint8_t value; |
| 568 | }; |
| 569 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 570 | struct of_hello_elem { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 571 | uint16_t type; |
| 572 | uint16_t length; |
| 573 | }; |
| 574 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 575 | struct of_hello_elem_versionbitmap { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 576 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 577 | uint16_t length; |
| 578 | list(of_uint32_t) bitmaps; |
| 579 | }; |
| 580 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 581 | struct of_hello { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 582 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 583 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 584 | uint16_t length; |
| 585 | uint32_t xid; |
| 586 | list(of_hello_elem_t) elements; |
| 587 | }; |
| 588 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 589 | struct of_echo_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 590 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 591 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 592 | uint16_t length; |
| 593 | uint32_t xid; |
| 594 | of_octets_t data; |
| 595 | }; |
| 596 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 597 | struct of_echo_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 598 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 599 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 600 | uint16_t length; |
| 601 | uint32_t xid; |
| 602 | of_octets_t data; |
| 603 | }; |
| 604 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 605 | struct of_experimenter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 606 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 607 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 608 | uint16_t length; |
| 609 | uint32_t xid; |
| 610 | uint32_t experimenter; |
| 611 | uint32_t subtype; |
| 612 | of_octets_t data; |
| 613 | }; |
| 614 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 615 | struct of_barrier_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 616 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 617 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 618 | uint16_t length; |
| 619 | uint32_t xid; |
| 620 | }; |
| 621 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 622 | struct of_barrier_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 623 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 624 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 625 | uint16_t length; |
| 626 | uint32_t xid; |
| 627 | }; |
| 628 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 629 | struct of_get_config_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 630 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 631 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 632 | uint16_t length; |
| 633 | uint32_t xid; |
| 634 | }; |
| 635 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 636 | struct of_get_config_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 637 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 638 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 639 | uint16_t length; |
| 640 | uint32_t xid; |
| 641 | uint16_t flags; |
| 642 | uint16_t miss_send_len; |
| 643 | }; |
| 644 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 645 | struct of_set_config { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 646 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 647 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 648 | uint16_t length; |
| 649 | uint32_t xid; |
| 650 | uint16_t flags; |
| 651 | uint16_t miss_send_len; |
| 652 | }; |
| 653 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 654 | struct of_table_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 655 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 656 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 657 | uint16_t length; |
| 658 | uint32_t xid; |
| 659 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 660 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 661 | uint32_t config; |
| 662 | }; |
| 663 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 664 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 665 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 666 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 667 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 668 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 669 | of_port_name_t name; |
| 670 | uint32_t config; |
| 671 | uint32_t state; |
| 672 | uint32_t curr; |
| 673 | uint32_t advertised; |
| 674 | uint32_t supported; |
| 675 | uint32_t peer; |
| 676 | uint32_t curr_speed; |
| 677 | uint32_t max_speed; |
| 678 | }; |
| 679 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 680 | struct of_features_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 681 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 682 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 683 | uint16_t length; |
| 684 | uint32_t xid; |
| 685 | }; |
| 686 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 687 | struct of_features_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 688 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 689 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 690 | uint16_t length; |
| 691 | uint32_t xid; |
| 692 | uint64_t datapath_id; |
| 693 | uint32_t n_buffers; |
| 694 | uint8_t n_tables; |
| 695 | uint8_t auxiliary_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 696 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 697 | uint32_t capabilities; |
| 698 | uint32_t reserved; |
| 699 | }; |
| 700 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 701 | struct of_port_status { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 702 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 703 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 704 | uint16_t length; |
| 705 | uint32_t xid; |
| 706 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 707 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 708 | of_port_desc_t desc; |
| 709 | }; |
| 710 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 711 | struct of_port_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 712 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 713 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 714 | uint16_t length; |
| 715 | uint32_t xid; |
| 716 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 717 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 718 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 719 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 720 | uint32_t config; |
| 721 | uint32_t mask; |
| 722 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 723 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 724 | }; |
| 725 | |
| 726 | // FIXME Does this need to be v4? |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 727 | struct of_match_v3 { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 728 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 729 | uint16_t length; |
| 730 | list(of_oxm_t) oxm_list; |
| 731 | }; |
| 732 | |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 733 | // This looks like an action header, but is standalone. See |
| 734 | // ofp_table_features_prop_actions |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 735 | struct of_action_id { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 736 | uint16_t type; |
| 737 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 738 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 739 | }; |
| 740 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 741 | struct of_action_output { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 742 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 743 | uint16_t len; |
| 744 | of_port_no_t port; |
| 745 | uint16_t max_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 746 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 747 | }; |
| 748 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 749 | struct of_action_copy_ttl_out { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 750 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 751 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 752 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 753 | }; |
| 754 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 755 | struct of_action_copy_ttl_in { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 756 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 757 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 758 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 759 | }; |
| 760 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 761 | struct of_action_set_mpls_ttl { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 762 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 763 | uint16_t len; |
| 764 | uint8_t mpls_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 765 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 766 | }; |
| 767 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 768 | struct of_action_dec_mpls_ttl { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 769 | uint16_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 770 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 771 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 772 | }; |
| 773 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 774 | struct of_action_push_vlan { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 775 | uint16_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 776 | uint16_t len; |
| 777 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 778 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 779 | }; |
| 780 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 781 | struct of_action_pop_vlan { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 782 | uint16_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 783 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 784 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 785 | }; |
| 786 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 787 | struct of_action_push_mpls { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 788 | uint16_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 789 | uint16_t len; |
| 790 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 791 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 792 | }; |
| 793 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 794 | struct of_action_pop_mpls { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 795 | uint16_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 796 | uint16_t len; |
| 797 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 798 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 799 | }; |
| 800 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 801 | struct of_action_set_queue { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 802 | uint16_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 803 | uint16_t len; |
| 804 | uint32_t queue_id; |
| 805 | }; |
| 806 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 807 | struct of_action_group { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 808 | uint16_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 809 | uint16_t len; |
| 810 | uint32_t group_id; |
| 811 | }; |
| 812 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 813 | struct of_action_set_nw_ttl { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 814 | uint16_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 815 | uint16_t len; |
| 816 | uint8_t nw_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 817 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 818 | }; |
| 819 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 820 | struct of_action_dec_nw_ttl { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 821 | uint16_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 822 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 823 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 824 | }; |
| 825 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 826 | struct of_action_set_field { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 827 | uint16_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 828 | uint16_t len; |
Rich Lane | be90eae | 2013-07-22 16:44:26 -0700 | [diff] [blame] | 829 | of_oxm_t field; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 830 | }; |
| 831 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 832 | struct of_action_experimenter { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 833 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 834 | uint16_t len; |
| 835 | uint32_t experimenter; |
| 836 | of_octets_t data; |
| 837 | }; |
| 838 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 839 | struct of_action_pop_pbb { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 840 | uint16_t type == 27; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 841 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 842 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 843 | }; |
| 844 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 845 | struct of_action_push_pbb { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 846 | uint16_t type == 26; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 847 | uint16_t len; |
| 848 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 849 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 850 | }; |
| 851 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 852 | struct of_action { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 853 | uint16_t type; |
| 854 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 855 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 856 | }; |
| 857 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 858 | struct of_instruction { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 859 | uint16_t type; |
| 860 | uint16_t len; |
| 861 | }; |
| 862 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 863 | struct of_instruction_goto_table { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 864 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 865 | uint16_t len; |
| 866 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 867 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 868 | }; |
| 869 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 870 | struct of_instruction_write_metadata { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 871 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 872 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 873 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 874 | uint64_t metadata; |
| 875 | uint64_t metadata_mask; |
| 876 | }; |
| 877 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 878 | struct of_instruction_write_actions { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 879 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 880 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 881 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 882 | list(of_action_t) actions; |
| 883 | }; |
| 884 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 885 | struct of_instruction_apply_actions { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 886 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 887 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 888 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 889 | list(of_action_t) actions; |
| 890 | }; |
| 891 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 892 | struct of_instruction_clear_actions { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 893 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 894 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 895 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 896 | }; |
| 897 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 898 | struct of_instruction_meter { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 899 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 900 | uint16_t len; |
| 901 | uint32_t meter_id; |
| 902 | }; |
| 903 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 904 | struct of_instruction_experimenter { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 905 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 906 | uint16_t len; |
| 907 | uint32_t experimenter; |
| 908 | of_octets_t data; |
| 909 | }; |
| 910 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 911 | struct of_flow_add { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 912 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 913 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 914 | uint16_t length; |
| 915 | uint32_t xid; |
| 916 | uint64_t cookie; |
| 917 | uint64_t cookie_mask; |
| 918 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 919 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 920 | uint16_t idle_timeout; |
| 921 | uint16_t hard_timeout; |
| 922 | uint16_t priority; |
| 923 | uint32_t buffer_id; |
| 924 | of_port_no_t out_port; |
| 925 | uint32_t out_group; |
| 926 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 927 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 928 | of_match_t match; |
| 929 | list(of_instruction_t) instructions; |
| 930 | }; |
| 931 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 932 | struct of_flow_modify { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 933 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 934 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 935 | uint16_t length; |
| 936 | uint32_t xid; |
| 937 | uint64_t cookie; |
| 938 | uint64_t cookie_mask; |
| 939 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 940 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 941 | uint16_t idle_timeout; |
| 942 | uint16_t hard_timeout; |
| 943 | uint16_t priority; |
| 944 | uint32_t buffer_id; |
| 945 | of_port_no_t out_port; |
| 946 | uint32_t out_group; |
| 947 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 948 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 949 | of_match_t match; |
| 950 | list(of_instruction_t) instructions; |
| 951 | }; |
| 952 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 953 | struct of_flow_modify_strict { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 954 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 955 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 956 | uint16_t length; |
| 957 | uint32_t xid; |
| 958 | uint64_t cookie; |
| 959 | uint64_t cookie_mask; |
| 960 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 961 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 962 | uint16_t idle_timeout; |
| 963 | uint16_t hard_timeout; |
| 964 | uint16_t priority; |
| 965 | uint32_t buffer_id; |
| 966 | of_port_no_t out_port; |
| 967 | uint32_t out_group; |
| 968 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 969 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 970 | of_match_t match; |
| 971 | list(of_instruction_t) instructions; |
| 972 | }; |
| 973 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 974 | struct of_flow_delete { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 975 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 976 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 977 | uint16_t length; |
| 978 | uint32_t xid; |
| 979 | uint64_t cookie; |
| 980 | uint64_t cookie_mask; |
| 981 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 982 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 983 | uint16_t idle_timeout; |
| 984 | uint16_t hard_timeout; |
| 985 | uint16_t priority; |
| 986 | uint32_t buffer_id; |
| 987 | of_port_no_t out_port; |
| 988 | uint32_t out_group; |
| 989 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 990 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 991 | of_match_t match; |
| 992 | list(of_instruction_t) instructions; |
| 993 | }; |
| 994 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 995 | struct of_flow_delete_strict { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 996 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 997 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 998 | uint16_t length; |
| 999 | uint32_t xid; |
| 1000 | uint64_t cookie; |
| 1001 | uint64_t cookie_mask; |
| 1002 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1003 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1004 | uint16_t idle_timeout; |
| 1005 | uint16_t hard_timeout; |
| 1006 | uint16_t priority; |
| 1007 | uint32_t buffer_id; |
| 1008 | of_port_no_t out_port; |
| 1009 | uint32_t out_group; |
| 1010 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1011 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1012 | of_match_t match; |
| 1013 | list(of_instruction_t) instructions; |
| 1014 | }; |
| 1015 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1016 | struct of_bucket { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1017 | uint16_t len; |
| 1018 | uint16_t weight; |
| 1019 | of_port_no_t watch_port; |
| 1020 | uint32_t watch_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1021 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1022 | list(of_action_t) actions; |
| 1023 | }; |
| 1024 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1025 | struct of_group_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1026 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1027 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1028 | uint16_t length; |
| 1029 | uint32_t xid; |
| 1030 | uint16_t command; |
| 1031 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1032 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1033 | uint32_t group_id; |
| 1034 | list(of_bucket_t) buckets; |
| 1035 | }; |
| 1036 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1037 | struct of_packet_out { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1038 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1039 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1040 | uint16_t length; |
| 1041 | uint32_t xid; |
| 1042 | uint32_t buffer_id; |
| 1043 | of_port_no_t in_port; |
| 1044 | uint16_t actions_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1045 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1046 | list(of_action_t) actions; |
| 1047 | of_octets_t data; |
| 1048 | }; |
| 1049 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1050 | struct of_packet_in { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1051 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1052 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1053 | uint16_t length; |
| 1054 | uint32_t xid; |
| 1055 | uint32_t buffer_id; |
| 1056 | uint16_t total_len; |
| 1057 | uint8_t reason; |
| 1058 | uint8_t table_id; |
| 1059 | uint64_t cookie; |
| 1060 | of_match_t match; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1061 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1062 | of_octets_t data; /* FIXME: Ensure total_len gets updated */ |
| 1063 | }; |
| 1064 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1065 | struct of_flow_removed { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1066 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1067 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1068 | uint16_t length; |
| 1069 | uint32_t xid; |
| 1070 | uint64_t cookie; |
| 1071 | uint16_t priority; |
| 1072 | uint8_t reason; |
| 1073 | uint8_t table_id; |
| 1074 | uint32_t duration_sec; |
| 1075 | uint32_t duration_nsec; |
| 1076 | uint16_t idle_timeout; |
| 1077 | uint16_t hard_timeout; |
| 1078 | uint64_t packet_count; |
| 1079 | uint64_t byte_count; |
| 1080 | of_match_t match; |
| 1081 | }; |
| 1082 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1083 | struct of_meter_band { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1084 | uint16_t type; |
| 1085 | uint16_t len; |
| 1086 | // uint32_t rate; // These are excluded b/c this is the header |
| 1087 | // uint32_t burst_size; // These are excluded b/c this is the header |
| 1088 | }; |
| 1089 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1090 | struct of_meter_band_drop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1091 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1092 | uint16_t len; |
| 1093 | uint32_t rate; |
| 1094 | uint32_t burst_size; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1095 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1096 | }; |
| 1097 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1098 | struct of_meter_band_dscp_remark { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1099 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1100 | uint16_t len; |
| 1101 | uint32_t rate; |
| 1102 | uint32_t burst_size; |
| 1103 | uint8_t prec_level; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1104 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1105 | }; |
| 1106 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1107 | struct of_meter_band_experimenter { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1108 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1109 | uint16_t len; |
| 1110 | uint32_t rate; |
| 1111 | uint32_t burst_size; |
| 1112 | uint32_t experimenter; |
| 1113 | }; |
| 1114 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1115 | struct of_meter_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1116 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1117 | uint8_t type == 29; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1118 | uint16_t length; |
| 1119 | uint32_t xid; |
| 1120 | uint16_t command; |
| 1121 | uint16_t flags; |
| 1122 | uint32_t meter_id; |
| 1123 | list(of_meter_band_t) meters; |
| 1124 | }; |
| 1125 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1126 | struct of_error_msg { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1127 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1128 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1129 | uint16_t length; |
| 1130 | uint32_t xid; |
| 1131 | uint16_t err_type; |
| 1132 | uint16_t code; |
| 1133 | of_octets_t data; |
| 1134 | }; |
| 1135 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1136 | //struct of_error_experimenter_msg { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1137 | // uint8_t version; |
| 1138 | // uint8_t type; |
| 1139 | // uint16_t length; |
| 1140 | // uint32_t xid; |
| 1141 | // uint16_t err_type; |
| 1142 | // uint16_t subtype; |
| 1143 | // uint32_t experimenter; |
| 1144 | // of_octets_t data; |
| 1145 | //}; |
| 1146 | |
| 1147 | // STATS ENTRIES: flow, table, port, queue, group stats, group desc stats |
| 1148 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1149 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1150 | uint16_t length; |
| 1151 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1152 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1153 | uint32_t duration_sec; |
| 1154 | uint32_t duration_nsec; |
| 1155 | uint16_t priority; |
| 1156 | uint16_t idle_timeout; |
| 1157 | uint16_t hard_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1158 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1159 | uint64_t cookie; |
| 1160 | uint64_t packet_count; |
| 1161 | uint64_t byte_count; |
| 1162 | of_match_t match; |
| 1163 | list(of_instruction_t) instructions; |
| 1164 | }; |
| 1165 | |
| 1166 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1167 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1168 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1169 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1170 | uint32_t active_count; |
| 1171 | uint64_t lookup_count; |
| 1172 | uint64_t matched_count; |
| 1173 | }; |
| 1174 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1175 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1176 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1177 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1178 | uint64_t rx_packets; |
| 1179 | uint64_t tx_packets; |
| 1180 | uint64_t rx_bytes; |
| 1181 | uint64_t tx_bytes; |
| 1182 | uint64_t rx_dropped; |
| 1183 | uint64_t tx_dropped; |
| 1184 | uint64_t rx_errors; |
| 1185 | uint64_t tx_errors; |
| 1186 | uint64_t rx_frame_err; |
| 1187 | uint64_t rx_over_err; |
| 1188 | uint64_t rx_crc_err; |
| 1189 | uint64_t collisions; |
| 1190 | uint32_t duration_sec; |
| 1191 | uint32_t duration_nsec; |
| 1192 | }; |
| 1193 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1194 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1195 | of_port_no_t port_no; |
| 1196 | uint32_t queue_id; |
| 1197 | uint64_t tx_bytes; |
| 1198 | uint64_t tx_packets; |
| 1199 | uint64_t tx_errors; |
| 1200 | uint32_t duration_sec; |
| 1201 | uint32_t duration_nsec; |
| 1202 | }; |
| 1203 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1204 | struct of_bucket_counter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1205 | uint64_t packet_count; |
| 1206 | uint64_t byte_count; |
| 1207 | }; |
| 1208 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1209 | struct of_group_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1210 | uint16_t length; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1211 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1212 | uint32_t group_id; |
| 1213 | uint32_t ref_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1214 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1215 | uint64_t packet_count; |
| 1216 | uint64_t byte_count; |
| 1217 | uint32_t duration_sec; |
| 1218 | uint32_t duration_nsec; |
| 1219 | list(of_bucket_counter_t) bucket_stats; |
| 1220 | }; |
| 1221 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1222 | struct of_group_desc_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1223 | uint16_t length; |
| 1224 | uint8_t type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1225 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1226 | uint32_t group_id; |
| 1227 | list(of_bucket_t) buckets; |
| 1228 | }; |
| 1229 | |
| 1230 | // STATS: |
| 1231 | // Desc, flow, agg, table, port, queue, group, group_desc, group_feat, experi |
| 1232 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1233 | struct of_desc_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1234 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1235 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1236 | uint16_t length; |
| 1237 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1238 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1239 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1240 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1241 | }; |
| 1242 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1243 | struct of_desc_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1244 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1245 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1246 | uint16_t length; |
| 1247 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1248 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1249 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1250 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1251 | of_desc_str_t mfr_desc; |
| 1252 | of_desc_str_t hw_desc; |
| 1253 | of_desc_str_t sw_desc; |
| 1254 | of_serial_num_t serial_num; |
| 1255 | of_desc_str_t dp_desc; |
| 1256 | }; |
| 1257 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1258 | struct of_flow_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1259 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1260 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1261 | uint16_t length; |
| 1262 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1263 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1264 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1265 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1266 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1267 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1268 | of_port_no_t out_port; |
| 1269 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1270 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1271 | uint64_t cookie; |
| 1272 | uint64_t cookie_mask; |
| 1273 | of_match_t match; |
| 1274 | }; |
| 1275 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1276 | struct of_flow_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1277 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1278 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1279 | uint16_t length; |
| 1280 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1281 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1282 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1283 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1284 | list(of_flow_stats_entry_t) entries; |
| 1285 | }; |
| 1286 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1287 | struct of_aggregate_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1288 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1289 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1290 | uint16_t length; |
| 1291 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1292 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1293 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1294 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1295 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1296 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1297 | of_port_no_t out_port; |
| 1298 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1299 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1300 | uint64_t cookie; |
| 1301 | uint64_t cookie_mask; |
| 1302 | of_match_t match; |
| 1303 | }; |
| 1304 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1305 | struct of_aggregate_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1306 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1307 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1308 | uint16_t length; |
| 1309 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1310 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1311 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1312 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1313 | uint64_t packet_count; |
| 1314 | uint64_t byte_count; |
| 1315 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1316 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1317 | }; |
| 1318 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1319 | struct of_table_stats_request { |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1320 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1321 | uint8_t type == 18; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1322 | uint16_t length; |
| 1323 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1324 | uint16_t stats_type == 3; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1325 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1326 | pad(4); |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1327 | }; |
| 1328 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1329 | struct of_table_stats_reply { |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1330 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1331 | uint8_t type == 19; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1332 | uint16_t length; |
| 1333 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1334 | uint16_t stats_type == 3; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1335 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1336 | pad(4); |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1337 | list(of_table_stats_entry_t) entries; |
| 1338 | }; |
| 1339 | |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1340 | // FIXME: These are padded to 8 byte align beyond the length indicated |
| 1341 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1342 | struct of_table_feature_prop { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1343 | uint16_t type; |
| 1344 | uint16_t length; |
| 1345 | }; |
| 1346 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1347 | struct of_table_feature_prop_instructions { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1348 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1349 | uint16_t length; |
| 1350 | // FIXME Check if instruction_t is right for ids here |
| 1351 | list(of_instruction_t) instruction_ids; |
| 1352 | }; |
| 1353 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1354 | struct of_table_feature_prop_instructions_miss { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1355 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1356 | uint16_t length; |
| 1357 | list(of_instruction_t) instruction_ids; |
| 1358 | }; |
| 1359 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1360 | struct of_table_feature_prop_next_tables { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1361 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1362 | uint16_t length; |
| 1363 | list(of_uint8_t) next_table_ids; |
| 1364 | }; |
| 1365 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1366 | struct of_table_feature_prop_next_tables_miss { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1367 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1368 | uint16_t length; |
| 1369 | list(of_uint8_t) next_table_ids; |
| 1370 | }; |
| 1371 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1372 | struct of_table_feature_prop_write_actions { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1373 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1374 | uint16_t length; |
| 1375 | list(of_action_id_t) action_ids; |
| 1376 | }; |
| 1377 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1378 | struct of_table_feature_prop_write_actions_miss { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1379 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1380 | uint16_t length; |
| 1381 | list(of_action_id_t) action_ids; |
| 1382 | }; |
| 1383 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1384 | struct of_table_feature_prop_apply_actions { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1385 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1386 | uint16_t length; |
| 1387 | list(of_action_id_t) action_ids; |
| 1388 | }; |
| 1389 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1390 | struct of_table_feature_prop_apply_actions_miss { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1391 | uint16_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1392 | uint16_t length; |
| 1393 | list(of_action_id_t) action_ids; |
| 1394 | }; |
| 1395 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1396 | struct of_table_feature_prop_match { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1397 | uint16_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1398 | uint16_t length; |
| 1399 | list(of_uint32_t) oxm_ids; |
| 1400 | }; |
| 1401 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1402 | struct of_table_feature_prop_wildcards { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1403 | uint16_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1404 | uint16_t length; |
| 1405 | list(of_uint32_t) oxm_ids; |
| 1406 | }; |
| 1407 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1408 | struct of_table_feature_prop_write_setfield { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1409 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1410 | uint16_t length; |
| 1411 | list(of_uint32_t) oxm_ids; |
| 1412 | }; |
| 1413 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1414 | struct of_table_feature_prop_write_setfield_miss { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1415 | uint16_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1416 | uint16_t length; |
| 1417 | list(of_uint32_t) oxm_ids; |
| 1418 | }; |
| 1419 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1420 | struct of_table_feature_prop_apply_setfield { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1421 | uint16_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1422 | uint16_t length; |
| 1423 | list(of_uint32_t) oxm_ids; |
| 1424 | }; |
| 1425 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1426 | struct of_table_feature_prop_apply_setfield_miss { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1427 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1428 | uint16_t length; |
| 1429 | list(of_uint32_t) oxm_ids; |
| 1430 | }; |
| 1431 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1432 | struct of_table_feature_prop_experimenter { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1433 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1434 | uint16_t length; |
| 1435 | uint32_t experimenter; |
| 1436 | uint32_t subtype; |
| 1437 | of_octets_t experimenter_data; |
| 1438 | }; |
| 1439 | |
| 1440 | // Not yet supported |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1441 | // struct of_table_feature_prop_experimenter_miss { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1442 | // uint16_t type; |
| 1443 | // uint16_t length; |
| 1444 | // uint32_t experimenter; |
| 1445 | // uint32_t subtype; |
| 1446 | // of_octets_t experimenter_data; |
| 1447 | // }; |
| 1448 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1449 | struct of_table_features { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1450 | uint16_t length; |
| 1451 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1452 | pad(5); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1453 | of_table_name_t name; |
| 1454 | uint64_t metadata_match; |
| 1455 | uint64_t metadata_write; |
| 1456 | uint32_t config; |
| 1457 | uint32_t max_entries; |
| 1458 | list(of_table_feature_prop_t) properties; |
| 1459 | }; |
| 1460 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1461 | struct of_meter_features { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1462 | uint32_t max_meter; |
| 1463 | uint32_t band_types; |
| 1464 | uint32_t capabilities; |
| 1465 | uint8_t max_bands; |
| 1466 | uint8_t max_color; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1467 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1468 | }; |
| 1469 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1470 | struct of_port_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1471 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1472 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1473 | uint16_t length; |
| 1474 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1475 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1476 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1477 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1478 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1479 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1480 | }; |
| 1481 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1482 | struct of_port_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1483 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1484 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1485 | uint16_t length; |
| 1486 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1487 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1488 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1489 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1490 | list(of_port_stats_entry_t) entries; |
| 1491 | }; |
| 1492 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1493 | struct of_queue_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1494 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1495 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1496 | uint16_t length; |
| 1497 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1498 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1499 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1500 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1501 | of_port_no_t port_no; |
| 1502 | uint32_t queue_id; |
| 1503 | }; |
| 1504 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1505 | struct of_queue_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1506 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1507 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1508 | uint16_t length; |
| 1509 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1510 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1511 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1512 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1513 | list(of_queue_stats_entry_t) entries; |
| 1514 | }; |
| 1515 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1516 | struct of_group_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1517 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1518 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1519 | uint16_t length; |
| 1520 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1521 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1522 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1523 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1524 | uint32_t group_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1525 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1526 | }; |
| 1527 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1528 | struct of_group_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1529 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1530 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1531 | uint16_t length; |
| 1532 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1533 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1534 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1535 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1536 | list(of_group_stats_entry_t) entries; |
| 1537 | }; |
| 1538 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1539 | struct of_group_desc_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1540 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1541 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1542 | uint16_t length; |
| 1543 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1544 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1545 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1546 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1547 | }; |
| 1548 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1549 | struct of_group_desc_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1550 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1551 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1552 | uint16_t length; |
| 1553 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1554 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1555 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1556 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1557 | list(of_group_desc_stats_entry_t) entries; |
| 1558 | }; |
| 1559 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1560 | struct of_group_features_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1561 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1562 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1563 | uint16_t length; |
| 1564 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1565 | uint16_t stats_type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1566 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1567 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1568 | }; |
| 1569 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1570 | struct of_group_features_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1571 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1572 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1573 | uint16_t length; |
| 1574 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1575 | uint16_t stats_type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1576 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1577 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1578 | uint32_t types; |
| 1579 | uint32_t capabilities; |
| 1580 | uint32_t max_groups_all; |
| 1581 | uint32_t max_groups_select; |
| 1582 | uint32_t max_groups_indirect; |
| 1583 | uint32_t max_groups_ff; |
| 1584 | uint32_t actions_all; |
| 1585 | uint32_t actions_select; |
| 1586 | uint32_t actions_indirect; |
| 1587 | uint32_t actions_ff; |
| 1588 | }; |
| 1589 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1590 | struct of_meter_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1591 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1592 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1593 | uint16_t length; |
| 1594 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1595 | uint16_t stats_type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1596 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1597 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1598 | uint32_t meter_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1599 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1600 | }; |
| 1601 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1602 | struct of_meter_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1603 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1604 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1605 | uint16_t length; |
| 1606 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1607 | uint16_t stats_type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1608 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1609 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1610 | list(of_meter_stats_t) entries; |
| 1611 | }; |
| 1612 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1613 | struct of_meter_config_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1614 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1615 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1616 | uint16_t length; |
| 1617 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1618 | uint16_t stats_type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1619 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1620 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1621 | uint32_t meter_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1622 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1623 | }; |
| 1624 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1625 | struct of_meter_config_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1626 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1627 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1628 | uint16_t length; |
| 1629 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1630 | uint16_t stats_type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1631 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1632 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1633 | list(of_meter_band_t) entries; |
| 1634 | }; |
| 1635 | |
| 1636 | // FIXME stats added to get things working |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1637 | struct of_meter_features_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1638 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1639 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1640 | uint16_t length; |
| 1641 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1642 | uint16_t stats_type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1643 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1644 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1645 | }; |
| 1646 | |
| 1647 | // FIXME stats added to get things working |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1648 | struct of_meter_features_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1649 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1650 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1651 | uint16_t length; |
| 1652 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1653 | uint16_t stats_type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1654 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1655 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1656 | of_meter_features_t features; |
| 1657 | }; |
| 1658 | |
| 1659 | // FIXME stats added to get things working |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1660 | struct of_table_features_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1661 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1662 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1663 | uint16_t length; |
| 1664 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1665 | uint16_t stats_type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1666 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1667 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1668 | list(of_table_features_t) entries; |
| 1669 | }; |
| 1670 | |
| 1671 | // FIXME stats added to get things working |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1672 | struct of_table_features_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1673 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1674 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1675 | uint16_t length; |
| 1676 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1677 | uint16_t stats_type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1678 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1679 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1680 | list(of_table_features_t) entries; |
| 1681 | }; |
| 1682 | |
| 1683 | // FIXME stats added to get things working |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1684 | struct of_port_desc_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1685 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1686 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1687 | uint16_t length; |
| 1688 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1689 | uint16_t stats_type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1690 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1691 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1692 | }; |
| 1693 | |
| 1694 | // FIXME stats added to get things working |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1695 | struct of_port_desc_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1696 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1697 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1698 | uint16_t length; |
| 1699 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1700 | uint16_t stats_type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1701 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1702 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1703 | list(of_port_desc_t) entries; |
| 1704 | }; |
| 1705 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1706 | struct of_meter_band_stats { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1707 | uint64_t packet_band_count; |
| 1708 | uint64_t byte_band_count; |
| 1709 | }; |
| 1710 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1711 | struct of_meter_stats { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1712 | uint32_t meter_id; |
| 1713 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1714 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1715 | uint32_t flow_count; |
| 1716 | uint64_t packet_in_count; |
| 1717 | uint64_t byte_in_count; |
| 1718 | uint32_t duration_sec; |
| 1719 | uint32_t duration_nsec; |
| 1720 | list(of_meter_band_stats_t) band_stats; |
| 1721 | }; |
| 1722 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1723 | struct of_meter_config { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1724 | uint16_t length; |
| 1725 | uint16_t flags; |
| 1726 | uint32_t meter_id; |
| 1727 | list(of_meter_band_t) entries; |
| 1728 | }; |
| 1729 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1730 | struct of_experimenter_multipart_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1731 | uint32_t experimenter; |
| 1732 | uint32_t subtype; |
| 1733 | }; |
| 1734 | |
| 1735 | // END OF STATS OBJECTS |
| 1736 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1737 | struct of_queue_prop { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1738 | uint16_t type; |
| 1739 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1740 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1741 | }; |
| 1742 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1743 | struct of_queue_prop_min_rate { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1744 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1745 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1746 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1747 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1748 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1749 | }; |
| 1750 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1751 | struct of_queue_prop_max_rate { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1752 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1753 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1754 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1755 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1756 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1757 | }; |
| 1758 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1759 | struct of_queue_prop_experimenter { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1760 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1761 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1762 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1763 | uint32_t experimenter; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1764 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1765 | of_octets_t data; |
| 1766 | }; |
| 1767 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1768 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1769 | uint32_t queue_id; |
| 1770 | of_port_no_t port; |
| 1771 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1772 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1773 | list(of_queue_prop_t) properties; |
| 1774 | }; |
| 1775 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1776 | struct of_queue_get_config_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1777 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1778 | uint8_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1779 | uint16_t length; |
| 1780 | uint32_t xid; |
| 1781 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1782 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1783 | }; |
| 1784 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1785 | struct of_queue_get_config_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1786 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1787 | uint8_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1788 | uint16_t length; |
| 1789 | uint32_t xid; |
| 1790 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1791 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1792 | list(of_packet_queue_t) queues; |
| 1793 | }; |
| 1794 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1795 | struct of_role_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1796 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1797 | uint8_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1798 | uint16_t length; |
| 1799 | uint32_t xid; |
| 1800 | uint32_t role; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1801 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1802 | uint64_t generation_id; |
| 1803 | }; |
| 1804 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1805 | struct of_role_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1806 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1807 | uint8_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1808 | uint16_t length; |
| 1809 | uint32_t xid; |
| 1810 | of_octets_t data; |
| 1811 | }; |
| 1812 | |
| 1813 | //////////////////////////////////////////////////////////////// |
| 1814 | // FIXME understand async; where do bitmasks live? |
| 1815 | // Determine bitmap type for masks below. |
| 1816 | // DOCUMENT masks where uint32_t[0] is interest for equal/master |
| 1817 | // while uint32_t[1] is interest for slave |
| 1818 | //////////////////////////////////////////////////////////////// |
| 1819 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1820 | struct of_async_get_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1821 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1822 | uint8_t type == 26; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1823 | uint16_t length; |
| 1824 | uint32_t xid; |
| 1825 | uint32_t packet_in_mask_equal_master; |
| 1826 | uint32_t packet_in_mask_slave; |
| 1827 | uint32_t port_status_mask_equal_master; |
| 1828 | uint32_t port_status_mask_slave; |
| 1829 | uint32_t flow_removed_mask_equal_master; |
| 1830 | uint32_t flow_removed_mask_slave; |
| 1831 | }; |
| 1832 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1833 | struct of_async_get_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1834 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1835 | uint8_t type == 27; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1836 | uint16_t length; |
| 1837 | uint32_t xid; |
| 1838 | uint32_t packet_in_mask_equal_master; |
| 1839 | uint32_t packet_in_mask_slave; |
| 1840 | uint32_t port_status_mask_equal_master; |
| 1841 | uint32_t port_status_mask_slave; |
| 1842 | uint32_t flow_removed_mask_equal_master; |
| 1843 | uint32_t flow_removed_mask_slave; |
| 1844 | }; |
| 1845 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1846 | struct of_async_set { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1847 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1848 | uint8_t type == 28; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1849 | uint16_t length; |
| 1850 | uint32_t xid; |
| 1851 | uint32_t packet_in_mask_equal_master; |
| 1852 | uint32_t packet_in_mask_slave; |
| 1853 | uint32_t port_status_mask_equal_master; |
| 1854 | uint32_t port_status_mask_slave; |
| 1855 | uint32_t flow_removed_mask_equal_master; |
| 1856 | uint32_t flow_removed_mask_slave; |
| 1857 | }; |