Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 1 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
| 38 | OFP_TCP_PORT = 6633, |
| 39 | OFP_SSL_PORT = 6633, |
| 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFP_VLAN_NONE = 0xffff, |
| 46 | |
| 47 | OFPFW_ICMP_TYPE = 0x40, |
| 48 | OFPFW_ICMP_CODE = 0x80, |
| 49 | |
| 50 | OFP_DL_TYPE_ETH2_CUTOFF = 0x600, |
| 51 | OFP_DL_TYPE_NOT_ETH_TYPE = 0x5ff, |
| 52 | |
| 53 | OFP_FLOW_PERMANENT = 0, |
| 54 | |
| 55 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 56 | |
| 57 | DESC_STR_LEN = 256, |
| 58 | SERIAL_NUM_LEN = 32, |
| 59 | |
| 60 | OFPQ_ALL = 0xffffffff, |
| 61 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 62 | }; |
| 63 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 64 | enum ofp_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 65 | OFPT_HELLO = 0, |
| 66 | OFPT_ERROR = 1, |
| 67 | OFPT_ECHO_REQUEST = 2, |
| 68 | OFPT_ECHO_REPLY = 3, |
| 69 | OFPT_VENDOR = 4, |
| 70 | OFPT_FEATURES_REQUEST = 5, |
| 71 | OFPT_FEATURES_REPLY = 6, |
| 72 | OFPT_GET_CONFIG_REQUEST = 7, |
| 73 | OFPT_GET_CONFIG_REPLY = 8, |
| 74 | OFPT_SET_CONFIG = 9, |
| 75 | OFPT_PACKET_IN = 10, |
| 76 | OFPT_FLOW_REMOVED = 11, |
| 77 | OFPT_PORT_STATUS = 12, |
| 78 | OFPT_PACKET_OUT = 13, |
| 79 | OFPT_FLOW_MOD = 14, |
| 80 | OFPT_PORT_MOD = 15, |
| 81 | OFPT_STATS_REQUEST = 16, |
| 82 | OFPT_STATS_REPLY = 17, |
| 83 | OFPT_BARRIER_REQUEST = 18, |
| 84 | OFPT_BARRIER_REPLY = 19, |
| 85 | OFPT_QUEUE_GET_CONFIG_REQUEST = 20, |
| 86 | OFPT_QUEUE_GET_CONFIG_REPLY = 21, |
| 87 | }; |
| 88 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 89 | enum ofp_port_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 90 | OFPPC_PORT_DOWN = 0x1, |
| 91 | OFPPC_NO_STP = 0x2, |
| 92 | OFPPC_NO_RECV = 0x4, |
| 93 | OFPPC_NO_RECV_STP = 0x8, |
| 94 | OFPPC_NO_FLOOD = 0x10, |
| 95 | OFPPC_NO_FWD = 0x20, |
| 96 | OFPPC_NO_PACKET_IN = 0x40, |
| 97 | }; |
| 98 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 99 | enum ofp_port_state(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 100 | OFPPS_STP_LISTEN = 0, |
| 101 | OFPPS_LINK_DOWN = 1, |
| 102 | OFPPS_STP_LEARN = 0x100, |
| 103 | OFPPS_STP_FORWARD = 0x200, |
| 104 | OFPPS_STP_BLOCK = 0x300, |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 105 | OFPPS_STP_MASK(virtual=True) = 0x300, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 106 | }; |
| 107 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 108 | // FIXME: these constants are currently 32 bit due to implementation |
| 109 | // details of loci, which is in violation of the OpenFlow spec. |
| 110 | // Should recast to 32 bits and fix/glue the c backend |
| 111 | enum ofp_port(wire_type=uint16_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 112 | OFPP_MAX = 0xffffff00, |
| 113 | OFPP_IN_PORT = 0xfffffff8, |
| 114 | OFPP_TABLE = 0xfffffff9, |
| 115 | OFPP_NORMAL = 0xfffffffa, |
| 116 | OFPP_FLOOD = 0xfffffffb, |
| 117 | OFPP_ALL = 0xfffffffc, |
| 118 | OFPP_CONTROLLER = 0xfffffffd, |
| 119 | OFPP_LOCAL = 0xfffffffe, |
| 120 | OFPP_NONE = 0xffffffff, |
| 121 | }; |
| 122 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 123 | enum ofp_port_features(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 124 | OFPPF_10MB_HD = 0x1, |
| 125 | OFPPF_10MB_FD = 0x2, |
| 126 | OFPPF_100MB_HD = 0x4, |
| 127 | OFPPF_100MB_FD = 0x8, |
| 128 | OFPPF_1GB_HD = 0x10, |
| 129 | OFPPF_1GB_FD = 0x20, |
| 130 | OFPPF_10GB_FD = 0x40, |
| 131 | OFPPF_COPPER = 0x80, |
| 132 | OFPPF_FIBER = 0x100, |
| 133 | OFPPF_AUTONEG = 0x200, |
| 134 | OFPPF_PAUSE = 0x400, |
| 135 | OFPPF_PAUSE_ASYM = 0x800, |
| 136 | }; |
| 137 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 138 | enum ofp_queue_properties(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 139 | OFPQT_NONE = 0, |
| 140 | OFPQT_MIN_RATE = 1, |
| 141 | }; |
| 142 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 143 | enum ofp_flow_wildcards(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 144 | OFPFW_IN_PORT = 0x1, |
| 145 | OFPFW_DL_VLAN = 0x2, |
| 146 | OFPFW_DL_SRC = 0x4, |
| 147 | OFPFW_NW_DST_BITS = 0x6, |
| 148 | OFPFW_NW_SRC_BITS = 0x6, |
| 149 | OFPFW_NW_SRC_SHIFT = 0x8, |
| 150 | OFPFW_DL_DST = 0x8, |
| 151 | OFPFW_NW_DST_SHIFT = 0xe, |
| 152 | OFPFW_DL_TYPE = 0x10, |
| 153 | OFPFW_NW_PROTO = 0x20, |
| 154 | OFPFW_TP_SRC = 0x40, |
| 155 | OFPFW_TP_DST = 0x80, |
| 156 | OFPFW_NW_SRC_ALL = 0x2000, |
| 157 | OFPFW_NW_SRC_MASK = 0x3f00, |
| 158 | OFPFW_NW_DST_ALL = 0x80000, |
| 159 | OFPFW_NW_DST_MASK = 0xfc000, |
| 160 | OFPFW_DL_VLAN_PCP = 0x100000, |
| 161 | OFPFW_NW_TOS = 0x200000, |
| 162 | OFPFW_ALL = 0x3fffff, |
| 163 | }; |
| 164 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 165 | enum ofp_action_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 166 | OFPAT_OUTPUT = 0, |
| 167 | OFPAT_SET_VLAN_VID = 1, |
| 168 | OFPAT_SET_VLAN_PCP = 2, |
| 169 | OFPAT_STRIP_VLAN = 3, |
| 170 | OFPAT_SET_DL_SRC = 4, |
| 171 | OFPAT_SET_DL_DST = 5, |
| 172 | OFPAT_SET_NW_SRC = 6, |
| 173 | OFPAT_SET_NW_DST = 7, |
| 174 | OFPAT_SET_NW_TOS = 8, |
| 175 | OFPAT_SET_TP_SRC = 9, |
| 176 | OFPAT_SET_TP_DST = 10, |
| 177 | OFPAT_ENQUEUE = 11, |
| 178 | OFPAT_VENDOR = 0xffff, |
| 179 | }; |
| 180 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 181 | enum ofp_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 182 | OFPC_FLOW_STATS = 0x1, |
| 183 | OFPC_TABLE_STATS = 0x2, |
| 184 | OFPC_PORT_STATS = 0x4, |
| 185 | OFPC_STP = 0x8, |
| 186 | OFPC_RESERVED = 0x10, |
| 187 | OFPC_IP_REASM = 0x20, |
| 188 | OFPC_QUEUE_STATS = 0x40, |
| 189 | OFPC_ARP_MATCH_IP = 0x80, |
| 190 | }; |
| 191 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 192 | enum ofp_config_flags(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 193 | OFPC_FRAG_NORMAL = 0x0, |
| 194 | OFPC_FRAG_DROP = 0x1, |
| 195 | OFPC_FRAG_REASM = 0x2, |
| 196 | OFPC_FRAG_MASK = 0x3, |
| 197 | }; |
| 198 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 199 | enum ofp_flow_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 200 | OFPFC_ADD = 0, |
| 201 | OFPFC_MODIFY = 1, |
| 202 | OFPFC_MODIFY_STRICT = 2, |
| 203 | OFPFC_DELETE = 3, |
| 204 | OFPFC_DELETE_STRICT = 4, |
| 205 | }; |
| 206 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 207 | enum ofp_flow_mod_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 208 | OFPFF_SEND_FLOW_REM = 0x1, |
| 209 | OFPFF_CHECK_OVERLAP = 0x2, |
| 210 | OFPFF_EMERG = 0x4, |
| 211 | }; |
| 212 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 213 | enum ofp_stats_reply_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 214 | OFPSF_REPLY_MORE = 0x1, |
| 215 | }; |
| 216 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 217 | enum ofp_stats_types(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 218 | OFPST_DESC = 0, |
| 219 | OFPST_FLOW = 1, |
| 220 | OFPST_AGGREGATE = 2, |
| 221 | OFPST_TABLE = 3, |
| 222 | OFPST_PORT = 4, |
| 223 | OFPST_QUEUE = 5, |
| 224 | OFPST_VENDOR = 0xffff, |
| 225 | }; |
| 226 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 227 | enum ofp_packet_in_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 228 | OFPR_NO_MATCH = 0, |
| 229 | OFPR_ACTION = 1, |
| 230 | }; |
| 231 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 232 | enum ofp_flow_removed_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 233 | OFPRR_IDLE_TIMEOUT = 0, |
| 234 | OFPRR_HARD_TIMEOUT = 1, |
| 235 | OFPRR_DELETE = 2, |
| 236 | }; |
| 237 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 238 | enum ofp_port_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 239 | OFPPR_ADD = 0, |
| 240 | OFPPR_DELETE = 1, |
| 241 | OFPPR_MODIFY = 2, |
| 242 | }; |
| 243 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 244 | enum ofp_error_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 245 | OFPET_HELLO_FAILED = 0, |
| 246 | OFPET_BAD_REQUEST = 1, |
| 247 | OFPET_BAD_ACTION = 2, |
| 248 | OFPET_FLOW_MOD_FAILED = 3, |
| 249 | OFPET_PORT_MOD_FAILED = 4, |
| 250 | OFPET_QUEUE_OP_FAILED = 5, |
| 251 | }; |
| 252 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 253 | enum ofp_hello_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 254 | OFPHFC_INCOMPATIBLE = 0, |
| 255 | OFPHFC_EPERM = 1, |
| 256 | }; |
| 257 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 258 | enum ofp_bad_request_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 259 | OFPBRC_BAD_VERSION = 0, |
| 260 | OFPBRC_BAD_TYPE = 1, |
| 261 | OFPBRC_BAD_STAT = 2, |
| 262 | OFPBRC_BAD_VENDOR = 3, |
| 263 | OFPBRC_BAD_SUBTYPE = 4, |
| 264 | OFPBRC_EPERM = 5, |
| 265 | OFPBRC_BAD_LEN = 6, |
| 266 | OFPBRC_BUFFER_EMPTY = 7, |
| 267 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 268 | }; |
| 269 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 270 | enum ofp_bad_action_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 271 | OFPBAC_BAD_TYPE = 0, |
| 272 | OFPBAC_BAD_LEN = 1, |
| 273 | OFPBAC_BAD_VENDOR = 2, |
| 274 | OFPBAC_BAD_VENDOR_TYPE = 3, |
| 275 | OFPBAC_BAD_OUT_PORT = 4, |
| 276 | OFPBAC_BAD_ARGUMENT = 5, |
| 277 | OFPBAC_EPERM = 6, |
| 278 | OFPBAC_TOO_MANY = 7, |
| 279 | OFPBAC_BAD_QUEUE = 8, |
| 280 | }; |
| 281 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 282 | enum ofp_flow_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 283 | OFPFMFC_ALL_TABLES_FULL = 0, |
| 284 | OFPFMFC_OVERLAP = 1, |
| 285 | OFPFMFC_EPERM = 2, |
| 286 | OFPFMFC_BAD_EMERG_TIMEOUT = 3, |
| 287 | OFPFMFC_BAD_COMMAND = 4, |
| 288 | OFPFMFC_UNSUPPORTED = 5, |
| 289 | }; |
| 290 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 291 | enum ofp_port_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 292 | OFPPMFC_BAD_PORT = 0, |
| 293 | OFPPMFC_BAD_HW_ADDR = 1, |
| 294 | }; |
| 295 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 296 | enum ofp_queue_op_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 297 | OFPQOFC_BAD_PORT = 0, |
| 298 | OFPQOFC_BAD_QUEUE = 1, |
| 299 | OFPQOFC_EPERM = 2, |
| 300 | }; |
| 301 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 302 | /* XXX rename to of_message */ |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 303 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 304 | uint8_t version; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 305 | uint8_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 306 | uint16_t length; |
| 307 | uint32_t xid; |
| 308 | }; |
| 309 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 310 | struct of_hello : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 311 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 312 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 313 | uint16_t length; |
| 314 | uint32_t xid; |
| 315 | }; |
| 316 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 317 | struct of_echo_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 318 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 319 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 320 | uint16_t length; |
| 321 | uint32_t xid; |
| 322 | of_octets_t data; |
| 323 | }; |
| 324 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 325 | struct of_echo_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 326 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 327 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 328 | uint16_t length; |
| 329 | uint32_t xid; |
| 330 | of_octets_t data; |
| 331 | }; |
| 332 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 333 | struct of_experimenter : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 334 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 335 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 336 | uint16_t length; |
| 337 | uint32_t xid; |
| 338 | uint32_t experimenter; |
| 339 | uint32_t subtype; |
| 340 | of_octets_t data; |
| 341 | }; |
| 342 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 343 | struct of_barrier_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 344 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 345 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 346 | uint16_t length; |
| 347 | uint32_t xid; |
| 348 | }; |
| 349 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 350 | struct of_barrier_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 351 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 352 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 353 | uint16_t length; |
| 354 | uint32_t xid; |
| 355 | }; |
| 356 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 357 | struct of_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 358 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 359 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 360 | uint16_t length; |
| 361 | uint32_t xid; |
| 362 | }; |
| 363 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 364 | struct of_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 365 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 366 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 367 | uint16_t length; |
| 368 | uint32_t xid; |
| 369 | uint16_t flags; |
| 370 | uint16_t miss_send_len; |
| 371 | }; |
| 372 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 373 | struct of_set_config : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 374 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 375 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 376 | uint16_t length; |
| 377 | uint32_t xid; |
| 378 | uint16_t flags; |
| 379 | uint16_t miss_send_len; |
| 380 | }; |
| 381 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 382 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 383 | of_port_no_t port_no; |
| 384 | of_mac_addr_t hw_addr; |
| 385 | of_port_name_t name; |
| 386 | uint32_t config; |
| 387 | uint32_t state; |
| 388 | uint32_t curr; |
| 389 | uint32_t advertised; |
| 390 | uint32_t supported; |
| 391 | uint32_t peer; |
| 392 | }; |
| 393 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 394 | struct of_features_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 395 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 396 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 397 | uint16_t length; |
| 398 | uint32_t xid; |
| 399 | }; |
| 400 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 401 | struct of_features_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 402 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 403 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 404 | uint16_t length; |
| 405 | uint32_t xid; |
| 406 | uint64_t datapath_id; |
| 407 | uint32_t n_buffers; |
| 408 | uint8_t n_tables; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 409 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 410 | uint32_t capabilities; |
| 411 | uint32_t actions; |
| 412 | list(of_port_desc_t) ports; |
| 413 | }; |
| 414 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 415 | struct of_port_status : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 416 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 417 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 418 | uint16_t length; |
| 419 | uint32_t xid; |
| 420 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 421 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 422 | of_port_desc_t desc; |
| 423 | }; |
| 424 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 425 | struct of_port_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 426 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 427 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 428 | uint16_t length; |
| 429 | uint32_t xid; |
| 430 | of_port_no_t port_no; |
| 431 | of_mac_addr_t hw_addr; |
| 432 | uint32_t config; |
| 433 | uint32_t mask; |
| 434 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 435 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 436 | }; |
| 437 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 438 | struct of_packet_in : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 439 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 440 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 441 | uint16_t length; |
| 442 | uint32_t xid; |
| 443 | uint32_t buffer_id; |
| 444 | uint16_t total_len; |
| 445 | of_port_no_t in_port; |
| 446 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 447 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 448 | of_octets_t data; |
| 449 | }; |
| 450 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 451 | struct of_action_output : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 452 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 453 | uint16_t len; |
| 454 | of_port_no_t port; |
| 455 | uint16_t max_len; |
| 456 | }; |
| 457 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 458 | struct of_action_set_vlan_vid : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 459 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 460 | uint16_t len; |
| 461 | uint16_t vlan_vid; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 462 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 463 | }; |
| 464 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 465 | struct of_action_strip_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 466 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 467 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 468 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 469 | }; |
| 470 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 471 | struct of_action_set_vlan_pcp : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 472 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 473 | uint16_t len; |
| 474 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 475 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 476 | }; |
| 477 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 478 | struct of_action_set_dl_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 479 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 480 | uint16_t len; |
| 481 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 482 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 483 | }; |
| 484 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 485 | struct of_action_set_dl_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 486 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 487 | uint16_t len; |
| 488 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 489 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 490 | }; |
| 491 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 492 | struct of_action_set_nw_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 493 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 494 | uint16_t len; |
| 495 | uint32_t nw_addr; |
| 496 | }; |
| 497 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 498 | struct of_action_set_nw_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 499 | uint16_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 500 | uint16_t len; |
| 501 | uint32_t nw_addr; |
| 502 | }; |
| 503 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 504 | struct of_action_set_tp_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 505 | uint16_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 506 | uint16_t len; |
| 507 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 508 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 509 | }; |
| 510 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 511 | struct of_action_set_tp_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 512 | uint16_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 513 | uint16_t len; |
| 514 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 515 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 516 | }; |
| 517 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 518 | struct of_action_set_nw_tos : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 519 | uint16_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 520 | uint16_t len; |
| 521 | uint8_t nw_tos; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 522 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 523 | }; |
| 524 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 525 | struct of_action_experimenter : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 526 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 527 | uint16_t len; |
| 528 | uint32_t experimenter; |
| 529 | of_octets_t data; |
| 530 | }; |
| 531 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 532 | struct of_action_enqueue : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 533 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 534 | uint16_t len; |
| 535 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 536 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 537 | uint32_t queue_id; |
| 538 | }; |
| 539 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 540 | struct of_action { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 541 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 542 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 543 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 544 | }; |
| 545 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 546 | struct of_packet_out : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 547 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 548 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 549 | uint16_t length; |
| 550 | uint32_t xid; |
| 551 | uint32_t buffer_id; |
| 552 | of_port_no_t in_port; |
| 553 | uint16_t actions_len; |
| 554 | list(of_action_t) actions; |
| 555 | of_octets_t data; |
| 556 | }; |
| 557 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 558 | struct of_match_v1 { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 559 | of_wc_bmap_t wildcards; |
| 560 | of_port_no_t in_port; |
| 561 | of_mac_addr_t eth_src; |
| 562 | of_mac_addr_t eth_dst; |
| 563 | uint16_t vlan_vid; |
| 564 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 565 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 566 | uint16_t eth_type; |
| 567 | uint8_t ip_dscp; |
| 568 | uint8_t ip_proto; |
Rob Sherwood | 53989c8 | 2013-07-03 16:49:50 -0700 | [diff] [blame] | 569 | pad(2); |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 570 | of_ipv4_t ipv4_src; |
| 571 | of_ipv4_t ipv4_dst; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 572 | uint16_t tcp_src; |
| 573 | uint16_t tcp_dst; |
| 574 | }; |
| 575 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 576 | struct of_flow_mod : of_header { |
| 577 | uint8_t version; |
| 578 | uint8_t type == 14; |
| 579 | uint16_t length; |
| 580 | uint32_t xid; |
| 581 | of_match_t match; |
| 582 | uint64_t cookie; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 583 | of_fm_cmd_t _command == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 584 | uint16_t idle_timeout; |
| 585 | uint16_t hard_timeout; |
| 586 | uint16_t priority; |
| 587 | uint32_t buffer_id; |
| 588 | of_port_no_t out_port; |
| 589 | uint16_t flags; |
| 590 | list(of_action_t) actions; |
| 591 | }; |
| 592 | |
| 593 | struct of_flow_add : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 594 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 595 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 596 | uint16_t length; |
| 597 | uint32_t xid; |
| 598 | of_match_t match; |
| 599 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 600 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 601 | uint16_t idle_timeout; |
| 602 | uint16_t hard_timeout; |
| 603 | uint16_t priority; |
| 604 | uint32_t buffer_id; |
| 605 | of_port_no_t out_port; |
| 606 | uint16_t flags; |
| 607 | list(of_action_t) actions; |
| 608 | }; |
| 609 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 610 | struct of_flow_modify : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 611 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 612 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 613 | uint16_t length; |
| 614 | uint32_t xid; |
| 615 | of_match_t match; |
| 616 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 617 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 618 | uint16_t idle_timeout; |
| 619 | uint16_t hard_timeout; |
| 620 | uint16_t priority; |
| 621 | uint32_t buffer_id; |
| 622 | of_port_no_t out_port; |
| 623 | uint16_t flags; |
| 624 | list(of_action_t) actions; |
| 625 | }; |
| 626 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 627 | struct of_flow_modify_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 628 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 629 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 630 | uint16_t length; |
| 631 | uint32_t xid; |
| 632 | of_match_t match; |
| 633 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 634 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 635 | uint16_t idle_timeout; |
| 636 | uint16_t hard_timeout; |
| 637 | uint16_t priority; |
| 638 | uint32_t buffer_id; |
| 639 | of_port_no_t out_port; |
| 640 | uint16_t flags; |
| 641 | list(of_action_t) actions; |
| 642 | }; |
| 643 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 644 | struct of_flow_delete : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 645 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 646 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 647 | uint16_t length; |
| 648 | uint32_t xid; |
| 649 | of_match_t match; |
| 650 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 651 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 652 | uint16_t idle_timeout; |
| 653 | uint16_t hard_timeout; |
| 654 | uint16_t priority; |
| 655 | uint32_t buffer_id; |
| 656 | of_port_no_t out_port; |
| 657 | uint16_t flags; |
| 658 | list(of_action_t) actions; |
| 659 | }; |
| 660 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 661 | struct of_flow_delete_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 662 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 663 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 664 | uint16_t length; |
| 665 | uint32_t xid; |
| 666 | of_match_t match; |
| 667 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 668 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 669 | uint16_t idle_timeout; |
| 670 | uint16_t hard_timeout; |
| 671 | uint16_t priority; |
| 672 | uint32_t buffer_id; |
| 673 | of_port_no_t out_port; |
| 674 | uint16_t flags; |
| 675 | list(of_action_t) actions; |
| 676 | }; |
| 677 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 678 | struct of_flow_removed : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 679 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 680 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 681 | uint16_t length; |
| 682 | uint32_t xid; |
| 683 | of_match_t match; |
| 684 | uint64_t cookie; |
| 685 | uint16_t priority; |
| 686 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 687 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 688 | uint32_t duration_sec; |
| 689 | uint32_t duration_nsec; |
| 690 | uint16_t idle_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 691 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 692 | uint64_t packet_count; |
| 693 | uint64_t byte_count; |
| 694 | }; |
| 695 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 696 | struct of_error_msg : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 697 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 698 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 699 | uint16_t length; |
| 700 | uint32_t xid; |
| 701 | uint16_t err_type; |
| 702 | uint16_t code; |
| 703 | of_octets_t data; |
| 704 | }; |
| 705 | |
| 706 | // STATS ENTRIES: flow, table, port, queue, |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 707 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 708 | uint16_t length; |
| 709 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 710 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 711 | of_match_t match; |
| 712 | uint32_t duration_sec; |
| 713 | uint32_t duration_nsec; |
| 714 | uint16_t priority; |
| 715 | uint16_t idle_timeout; |
| 716 | uint16_t hard_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 717 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 718 | uint64_t cookie; |
| 719 | uint64_t packet_count; |
| 720 | uint64_t byte_count; |
| 721 | list(of_action_t) actions; |
| 722 | }; |
| 723 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 724 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 725 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 726 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 727 | of_table_name_t name; |
| 728 | of_wc_bmap_t wildcards; |
| 729 | uint32_t max_entries; |
| 730 | uint32_t active_count; |
| 731 | uint64_t lookup_count; |
| 732 | uint64_t matched_count; |
| 733 | }; |
| 734 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 735 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 736 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 737 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 738 | uint64_t rx_packets; |
| 739 | uint64_t tx_packets; |
| 740 | uint64_t rx_bytes; |
| 741 | uint64_t tx_bytes; |
| 742 | uint64_t rx_dropped; |
| 743 | uint64_t tx_dropped; |
| 744 | uint64_t rx_errors; |
| 745 | uint64_t tx_errors; |
| 746 | uint64_t rx_frame_err; |
| 747 | uint64_t rx_over_err; |
| 748 | uint64_t rx_crc_err; |
| 749 | uint64_t collisions; |
| 750 | }; |
| 751 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 752 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 753 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 754 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 755 | uint32_t queue_id; |
| 756 | uint64_t tx_bytes; |
| 757 | uint64_t tx_packets; |
| 758 | uint64_t tx_errors; |
| 759 | }; |
| 760 | |
| 761 | // STATS request/reply: Desc, flow, agg, table, port, queue |
| 762 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 763 | struct of_stats_request : of_header { |
| 764 | uint8_t version; |
| 765 | uint8_t type == 16; |
| 766 | uint16_t length; |
| 767 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 768 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 769 | uint16_t flags; |
| 770 | }; |
| 771 | |
| 772 | struct of_stats_reply : of_header { |
| 773 | uint8_t version; |
| 774 | uint8_t type == 17; |
| 775 | uint16_t length; |
| 776 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 777 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 778 | uint16_t flags; |
| 779 | }; |
| 780 | |
| 781 | struct of_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 782 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 783 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 784 | uint16_t length; |
| 785 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 786 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 787 | uint16_t flags; |
| 788 | }; |
| 789 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 790 | struct of_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 791 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 792 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 793 | uint16_t length; |
| 794 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 795 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 796 | uint16_t flags; |
| 797 | of_desc_str_t mfr_desc; |
| 798 | of_desc_str_t hw_desc; |
| 799 | of_desc_str_t sw_desc; |
| 800 | of_serial_num_t serial_num; |
| 801 | of_desc_str_t dp_desc; |
| 802 | }; |
| 803 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 804 | struct of_flow_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 805 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 806 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 807 | uint16_t length; |
| 808 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 809 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 810 | uint16_t flags; |
| 811 | of_match_t match; |
| 812 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 813 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 814 | of_port_no_t out_port; |
| 815 | }; |
| 816 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 817 | struct of_flow_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 818 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 819 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 820 | uint16_t length; |
| 821 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 822 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 823 | uint16_t flags; |
| 824 | list(of_flow_stats_entry_t) entries; |
| 825 | }; |
| 826 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 827 | struct of_aggregate_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 828 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 829 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 830 | uint16_t length; |
| 831 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 832 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 833 | uint16_t flags; |
| 834 | of_match_t match; |
| 835 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 836 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 837 | of_port_no_t out_port; |
| 838 | }; |
| 839 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 840 | struct of_aggregate_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 841 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 842 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 843 | uint16_t length; |
| 844 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 845 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 846 | uint16_t flags; |
| 847 | uint64_t packet_count; |
| 848 | uint64_t byte_count; |
| 849 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 850 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 851 | }; |
| 852 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 853 | struct of_table_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 854 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 855 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 856 | uint16_t length; |
| 857 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 858 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 859 | uint16_t flags; |
| 860 | }; |
| 861 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 862 | struct of_table_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 863 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 864 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 865 | uint16_t length; |
| 866 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 867 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 868 | uint16_t flags; |
| 869 | list(of_table_stats_entry_t) entries; |
| 870 | }; |
| 871 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 872 | struct of_port_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 873 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 874 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 875 | uint16_t length; |
| 876 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 877 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 878 | uint16_t flags; |
| 879 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 880 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 881 | }; |
| 882 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 883 | struct of_port_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 884 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 885 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 886 | uint16_t length; |
| 887 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 888 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 889 | uint16_t flags; |
| 890 | list(of_port_stats_entry_t) entries; |
| 891 | }; |
| 892 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 893 | struct of_queue_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 894 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 895 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 896 | uint16_t length; |
| 897 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 898 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 899 | uint16_t flags; |
| 900 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 901 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 902 | uint32_t queue_id; |
| 903 | }; |
| 904 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 905 | struct of_queue_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 906 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 907 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 908 | uint16_t length; |
| 909 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 910 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 911 | uint16_t flags; |
| 912 | list(of_queue_stats_entry_t) entries; |
| 913 | }; |
| 914 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 915 | struct of_experimenter_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 916 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 917 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 918 | uint16_t length; |
| 919 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 920 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 921 | uint16_t flags; |
| 922 | uint32_t experimenter; |
| 923 | of_octets_t data; |
| 924 | }; |
| 925 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 926 | struct of_experimenter_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 927 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 928 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 929 | uint16_t length; |
| 930 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 931 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 932 | uint16_t flags; |
| 933 | uint32_t experimenter; |
| 934 | of_octets_t data; |
| 935 | }; |
| 936 | |
| 937 | // END OF STATS OBJECTS |
| 938 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 939 | struct of_queue_prop { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 940 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 941 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 942 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 943 | }; |
| 944 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 945 | struct of_queue_prop_min_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 946 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 947 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 948 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 949 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 950 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 951 | }; |
| 952 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 953 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 954 | uint32_t queue_id; |
| 955 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 956 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 957 | list(of_queue_prop_t) properties; |
| 958 | }; |
| 959 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 960 | struct of_queue_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 961 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 962 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 963 | uint16_t length; |
| 964 | uint32_t xid; |
| 965 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 966 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 967 | }; |
| 968 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 969 | struct of_queue_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 970 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 971 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 972 | uint16_t length; |
| 973 | uint32_t xid; |
| 974 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 975 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 976 | list(of_packet_queue_t) queues; |
| 977 | }; |