Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
| 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
| 31 | |
| 32 | #version 3 |
| 33 | #version 4 |
| 34 | |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 35 | struct of_oxm { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 36 | uint32_t type_len == ?; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 37 | }; |
| 38 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 39 | struct of_oxm_arp_op : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 40 | uint32_t type_len == 0x80002a02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 41 | uint16_t value; |
| 42 | }; |
| 43 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 44 | struct of_oxm_arp_op_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 45 | uint32_t type_len == 0x80002b04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 46 | uint16_t value; |
| 47 | uint16_t value_mask; |
| 48 | }; |
| 49 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 50 | struct of_oxm_arp_sha : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 51 | uint32_t type_len == 0x80003006; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 52 | of_mac_addr_t value; |
| 53 | }; |
| 54 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 55 | struct of_oxm_arp_sha_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 56 | uint32_t type_len == 0x8000310c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 57 | of_mac_addr_t value; |
| 58 | of_mac_addr_t value_mask; |
| 59 | }; |
| 60 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 61 | struct of_oxm_arp_spa : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 62 | uint32_t type_len == 0x80002c04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 63 | uint32_t value; |
| 64 | }; |
| 65 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 66 | struct of_oxm_arp_spa_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 67 | uint32_t type_len == 0x80002d08; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 68 | uint32_t value; |
| 69 | uint32_t value_mask; |
| 70 | }; |
| 71 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 72 | struct of_oxm_arp_tha : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 73 | uint32_t type_len == 0x80003206; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 74 | of_mac_addr_t value; |
| 75 | }; |
| 76 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 77 | struct of_oxm_arp_tha_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 78 | uint32_t type_len == 0x8000330c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 79 | of_mac_addr_t value; |
| 80 | of_mac_addr_t value_mask; |
| 81 | }; |
| 82 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 83 | struct of_oxm_arp_tpa : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 84 | uint32_t type_len == 0x80002e04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 85 | uint32_t value; |
| 86 | }; |
| 87 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 88 | struct of_oxm_arp_tpa_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 89 | uint32_t type_len == 0x80002f08; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 90 | uint32_t value; |
| 91 | uint32_t value_mask; |
| 92 | }; |
| 93 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 94 | struct of_oxm_eth_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 95 | uint32_t type_len == 0x80000606; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 96 | of_mac_addr_t value; |
| 97 | }; |
| 98 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 99 | struct of_oxm_eth_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 100 | uint32_t type_len == 0x8000070c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 101 | of_mac_addr_t value; |
| 102 | of_mac_addr_t value_mask; |
| 103 | }; |
| 104 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 105 | struct of_oxm_eth_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 106 | uint32_t type_len == 0x80000806; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 107 | of_mac_addr_t value; |
| 108 | }; |
| 109 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 110 | struct of_oxm_eth_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 111 | uint32_t type_len == 0x8000090c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 112 | of_mac_addr_t value; |
| 113 | of_mac_addr_t value_mask; |
| 114 | }; |
| 115 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 116 | struct of_oxm_eth_type : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 117 | uint32_t type_len == 0x80000a02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 118 | uint16_t value; |
| 119 | }; |
| 120 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 121 | struct of_oxm_eth_type_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 122 | uint32_t type_len == 0x80000b04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 123 | uint16_t value; |
| 124 | uint16_t value_mask; |
| 125 | }; |
| 126 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 127 | struct of_oxm_icmpv4_code : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 128 | uint32_t type_len == 0x80002801; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 129 | uint8_t value; |
| 130 | }; |
| 131 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 132 | struct of_oxm_icmpv4_code_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 133 | uint32_t type_len == 0x80002902; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 134 | uint8_t value; |
| 135 | uint8_t value_mask; |
| 136 | }; |
| 137 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 138 | struct of_oxm_icmpv4_type : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 139 | uint32_t type_len == 0x80002601; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 140 | uint8_t value; |
| 141 | }; |
| 142 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 143 | struct of_oxm_icmpv4_type_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 144 | uint32_t type_len == 0x80002702; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 145 | uint8_t value; |
| 146 | uint8_t value_mask; |
| 147 | }; |
| 148 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 149 | struct of_oxm_icmpv6_code : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 150 | uint32_t type_len == 0x80003c01; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 151 | uint8_t value; |
| 152 | }; |
| 153 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 154 | struct of_oxm_icmpv6_code_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 155 | uint32_t type_len == 0x80003d02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 156 | uint8_t value; |
| 157 | uint8_t value_mask; |
| 158 | }; |
| 159 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 160 | struct of_oxm_icmpv6_type : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 161 | uint32_t type_len == 0x80003a01; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 162 | uint8_t value; |
| 163 | }; |
| 164 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 165 | struct of_oxm_icmpv6_type_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 166 | uint32_t type_len == 0x80003b02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 167 | uint8_t value; |
| 168 | uint8_t value_mask; |
| 169 | }; |
| 170 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 171 | struct of_oxm_in_phy_port : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 172 | uint32_t type_len == 0x80000204; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 173 | of_port_no_t value; |
| 174 | }; |
| 175 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 176 | struct of_oxm_in_phy_port_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 177 | uint32_t type_len == 0x80000308; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 178 | of_port_no_t value; |
| 179 | of_port_no_t value_mask; |
| 180 | }; |
| 181 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 182 | struct of_oxm_in_port : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 183 | uint32_t type_len == 0x80000004; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 184 | of_port_no_t value; |
| 185 | }; |
| 186 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 187 | struct of_oxm_in_port_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 188 | uint32_t type_len == 0x80000108; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 189 | of_port_no_t value; |
| 190 | of_port_no_t value_mask; |
| 191 | }; |
| 192 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 193 | struct of_oxm_ip_dscp : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 194 | uint32_t type_len == 0x80001001; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 195 | uint8_t value; |
| 196 | }; |
| 197 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 198 | struct of_oxm_ip_dscp_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 199 | uint32_t type_len == 0x80001102; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 200 | uint8_t value; |
| 201 | uint8_t value_mask; |
| 202 | }; |
| 203 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 204 | struct of_oxm_ip_ecn : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 205 | uint32_t type_len == 0x80001201; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 206 | uint8_t value; |
| 207 | }; |
| 208 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 209 | struct of_oxm_ip_ecn_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 210 | uint32_t type_len == 0x80001302; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 211 | uint8_t value; |
| 212 | uint8_t value_mask; |
| 213 | }; |
| 214 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 215 | struct of_oxm_ip_proto : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 216 | uint32_t type_len == 0x80001401; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 217 | uint8_t value; |
| 218 | }; |
| 219 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 220 | struct of_oxm_ip_proto_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 221 | uint32_t type_len == 0x80001502; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 222 | uint8_t value; |
| 223 | uint8_t value_mask; |
| 224 | }; |
| 225 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 226 | struct of_oxm_ipv4_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 227 | uint32_t type_len == 0x80001804; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 228 | of_ipv4_t value; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 229 | }; |
| 230 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 231 | struct of_oxm_ipv4_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 232 | uint32_t type_len == 0x80001908; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 233 | of_ipv4_t value; |
| 234 | of_ipv4_t value_mask; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 235 | }; |
| 236 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 237 | struct of_oxm_ipv4_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 238 | uint32_t type_len == 0x80001604; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 239 | of_ipv4_t value; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 240 | }; |
| 241 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 242 | struct of_oxm_ipv4_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 243 | uint32_t type_len == 0x80001708; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 244 | of_ipv4_t value; |
| 245 | of_ipv4_t value_mask; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 246 | }; |
| 247 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 248 | struct of_oxm_ipv6_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 249 | uint32_t type_len == 0x80003610; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 250 | of_ipv6_t value; |
| 251 | }; |
| 252 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 253 | struct of_oxm_ipv6_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 254 | uint32_t type_len == 0x80003720; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 255 | of_ipv6_t value; |
| 256 | of_ipv6_t value_mask; |
| 257 | }; |
| 258 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 259 | struct of_oxm_ipv6_flabel : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 260 | uint32_t type_len == 0x80003804; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 261 | uint32_t value; |
| 262 | }; |
| 263 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 264 | struct of_oxm_ipv6_flabel_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 265 | uint32_t type_len == 0x80003908; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 266 | uint32_t value; |
| 267 | uint32_t value_mask; |
| 268 | }; |
| 269 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 270 | struct of_oxm_ipv6_nd_sll : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 271 | uint32_t type_len == 0x80004006; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 272 | of_mac_addr_t value; |
| 273 | }; |
| 274 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 275 | struct of_oxm_ipv6_nd_sll_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 276 | uint32_t type_len == 0x8000410c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 277 | of_mac_addr_t value; |
| 278 | of_mac_addr_t value_mask; |
| 279 | }; |
| 280 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 281 | struct of_oxm_ipv6_nd_target : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 282 | uint32_t type_len == 0x80003e10; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 283 | of_ipv6_t value; |
| 284 | }; |
| 285 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 286 | struct of_oxm_ipv6_nd_target_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 287 | uint32_t type_len == 0x80003f20; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 288 | of_ipv6_t value; |
| 289 | of_ipv6_t value_mask; |
| 290 | }; |
| 291 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 292 | struct of_oxm_ipv6_nd_tll : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 293 | uint32_t type_len == 0x80004206; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 294 | of_mac_addr_t value; |
| 295 | }; |
| 296 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 297 | struct of_oxm_ipv6_nd_tll_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 298 | uint32_t type_len == 0x8000430c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 299 | of_mac_addr_t value; |
| 300 | of_mac_addr_t value_mask; |
| 301 | }; |
| 302 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 303 | struct of_oxm_ipv6_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 304 | uint32_t type_len == 0x80003410; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 305 | of_ipv6_t value; |
| 306 | }; |
| 307 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 308 | struct of_oxm_ipv6_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 309 | uint32_t type_len == 0x80003520; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 310 | of_ipv6_t value; |
| 311 | of_ipv6_t value_mask; |
| 312 | }; |
| 313 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 314 | struct of_oxm_metadata : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 315 | uint32_t type_len == 0x80000408; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 316 | uint64_t value; |
| 317 | }; |
| 318 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 319 | struct of_oxm_metadata_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 320 | uint32_t type_len == 0x80000510; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 321 | uint64_t value; |
| 322 | uint64_t value_mask; |
| 323 | }; |
| 324 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 325 | struct of_oxm_mpls_label : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 326 | uint32_t type_len == 0x80004404; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 327 | uint32_t value; |
| 328 | }; |
| 329 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 330 | struct of_oxm_mpls_label_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 331 | uint32_t type_len == 0x80004508; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 332 | uint32_t value; |
| 333 | uint32_t value_mask; |
| 334 | }; |
| 335 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 336 | struct of_oxm_mpls_tc : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 337 | uint32_t type_len == 0x80004601; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 338 | uint8_t value; |
| 339 | }; |
| 340 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 341 | struct of_oxm_mpls_tc_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 342 | uint32_t type_len == 0x80004702; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 343 | uint8_t value; |
| 344 | uint8_t value_mask; |
| 345 | }; |
| 346 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 347 | struct of_oxm_sctp_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 348 | uint32_t type_len == 0x80002402; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 349 | uint16_t value; |
| 350 | }; |
| 351 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 352 | struct of_oxm_sctp_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 353 | uint32_t type_len == 0x80002504; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 354 | uint16_t value; |
| 355 | uint16_t value_mask; |
| 356 | }; |
| 357 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 358 | struct of_oxm_sctp_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 359 | uint32_t type_len == 0x80002202; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 360 | uint16_t value; |
| 361 | }; |
| 362 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 363 | struct of_oxm_sctp_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 364 | uint32_t type_len == 0x80002304; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 365 | uint16_t value; |
| 366 | uint16_t value_mask; |
| 367 | }; |
| 368 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 369 | struct of_oxm_tcp_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 370 | uint32_t type_len == 0x80001c02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 371 | uint16_t value; |
| 372 | }; |
| 373 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 374 | struct of_oxm_tcp_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 375 | uint32_t type_len == 0x80001d04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 376 | uint16_t value; |
| 377 | uint16_t value_mask; |
| 378 | }; |
| 379 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 380 | struct of_oxm_tcp_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 381 | uint32_t type_len == 0x80001a02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 382 | uint16_t value; |
| 383 | }; |
| 384 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 385 | struct of_oxm_tcp_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 386 | uint32_t type_len == 0x80001b04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 387 | uint16_t value; |
| 388 | uint16_t value_mask; |
| 389 | }; |
| 390 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 391 | struct of_oxm_udp_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 392 | uint32_t type_len == 0x80002002; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 393 | uint16_t value; |
| 394 | }; |
| 395 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 396 | struct of_oxm_udp_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 397 | uint32_t type_len == 0x80002104; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 398 | uint16_t value; |
| 399 | uint16_t value_mask; |
| 400 | }; |
| 401 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 402 | struct of_oxm_udp_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 403 | uint32_t type_len == 0x80001e02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 404 | uint16_t value; |
| 405 | }; |
| 406 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 407 | struct of_oxm_udp_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 408 | uint32_t type_len == 0x80001f04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 409 | uint16_t value; |
| 410 | uint16_t value_mask; |
| 411 | }; |
| 412 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 413 | struct of_oxm_vlan_pcp : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 414 | uint32_t type_len == 0x80000e01; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 415 | uint8_t value; |
| 416 | }; |
| 417 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 418 | struct of_oxm_vlan_pcp_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 419 | uint32_t type_len == 0x80000f02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 420 | uint8_t value; |
| 421 | uint8_t value_mask; |
| 422 | }; |
| 423 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 424 | struct of_oxm_vlan_vid : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 425 | uint32_t type_len == 0x80000c02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 426 | uint16_t value; |
| 427 | }; |
| 428 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 429 | struct of_oxm_vlan_vid_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 430 | uint32_t type_len == 0x80000d04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 431 | uint16_t value; |
| 432 | uint16_t value_mask; |
| 433 | }; |