Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 4 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
| 38 | OFP_TCP_PORT = 6633, |
| 39 | OFP_SSL_PORT = 6633, |
| 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFP_VLAN_NONE = 0, |
| 46 | |
| 47 | OFP_FLOW_PERMANENT = 0, |
| 48 | |
| 49 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 50 | |
| 51 | OFP_NO_BUFFER = 0xffffffff, |
| 52 | |
| 53 | DESC_STR_LEN = 256, |
| 54 | SERIAL_NUM_LEN = 32, |
| 55 | |
| 56 | OFPQ_ALL = 0xffffffff, |
| 57 | OFPQ_MAX_RATE_UNCFG = 0xffff, |
| 58 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 59 | }; |
| 60 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 61 | enum ofp_port_no(wire_type=uint32_t, complete=no) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 62 | OFPP_ANY = 0xffffffff, |
| 63 | }; |
| 64 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 65 | enum ofp_port(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 66 | OFPP_MAX = 0xffffff00, |
| 67 | OFPP_IN_PORT = 0xfffffff8, |
| 68 | OFPP_TABLE = 0xfffffff9, |
| 69 | OFPP_NORMAL = 0xfffffffa, |
| 70 | OFPP_FLOOD = 0xfffffffb, |
| 71 | OFPP_ALL = 0xfffffffc, |
| 72 | OFPP_CONTROLLER = 0xfffffffd, |
| 73 | OFPP_LOCAL = 0xfffffffe, |
| 74 | }; |
| 75 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 76 | enum ofp_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 77 | OFPT_HELLO = 0, |
| 78 | OFPT_ERROR = 1, |
| 79 | OFPT_ECHO_REQUEST = 2, |
| 80 | OFPT_ECHO_REPLY = 3, |
| 81 | OFPT_EXPERIMENTER = 4, |
| 82 | OFPT_FEATURES_REQUEST = 5, |
| 83 | OFPT_FEATURES_REPLY = 6, |
| 84 | OFPT_GET_CONFIG_REQUEST = 7, |
| 85 | OFPT_GET_CONFIG_REPLY = 8, |
| 86 | OFPT_SET_CONFIG = 9, |
| 87 | OFPT_PACKET_IN = 10, |
| 88 | OFPT_FLOW_REMOVED = 11, |
| 89 | OFPT_PORT_STATUS = 12, |
| 90 | OFPT_PACKET_OUT = 13, |
| 91 | OFPT_FLOW_MOD = 14, |
| 92 | OFPT_GROUP_MOD = 15, |
| 93 | OFPT_PORT_MOD = 16, |
| 94 | OFPT_TABLE_MOD = 17, |
| 95 | OFPT_MULTIPART_REQUEST = 18, |
| 96 | OFPT_MULTIPART_REPLY = 19, |
| 97 | OFPT_BARRIER_REQUEST = 20, |
| 98 | OFPT_BARRIER_REPLY = 21, |
| 99 | OFPT_QUEUE_GET_CONFIG_REQUEST = 22, |
| 100 | OFPT_QUEUE_GET_CONFIG_REPLY = 23, |
| 101 | OFPT_ROLE_REQUEST = 24, |
| 102 | OFPT_ROLE_REPLY = 25, |
| 103 | OFPT_GET_ASYNC_REQUEST = 26, |
| 104 | OFPT_GET_ASYNC_REPLY = 27, |
| 105 | OFPT_SET_ASYNC = 28, |
| 106 | OFPT_METER_MOD = 29, |
| 107 | }; |
| 108 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 109 | enum ofp_config_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 110 | OFPC_FRAG_NORMAL = 0, |
| 111 | OFPC_FRAG_DROP = 1, |
| 112 | OFPC_FRAG_REASM = 2, |
| 113 | OFPC_FRAG_MASK = 3, |
| 114 | }; |
| 115 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 116 | enum ofp_table_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 117 | OFPTC_DEPRECATED_MASK = 0x3, |
| 118 | }; |
| 119 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 120 | enum ofp_table(wire_type=uint8_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 121 | OFPTT_MAX = 0xfe, |
| 122 | OFPTT_ALL = 0xff, |
| 123 | }; |
| 124 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 125 | enum ofp_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 126 | OFPC_FLOW_STATS = 0x1, |
| 127 | OFPC_TABLE_STATS = 0x2, |
| 128 | OFPC_PORT_STATS = 0x4, |
| 129 | OFPC_GROUP_STATS = 0x8, |
| 130 | OFPC_IP_REASM = 0x20, |
| 131 | OFPC_QUEUE_STATS = 0x40, |
| 132 | OFPC_PORT_BLOCKED = 0x100, |
| 133 | }; |
| 134 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 135 | enum ofp_port_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 136 | OFPPC_PORT_DOWN = 0x1, |
| 137 | OFPPC_NO_RECV = 0x4, |
| 138 | OFPPC_NO_FWD = 0x20, |
| 139 | OFPPC_NO_PACKET_IN = 0x40, |
| 140 | }; |
| 141 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 142 | enum ofp_port_state(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 143 | OFPPS_LINK_DOWN = 0x1, |
| 144 | OFPPS_BLOCKED = 0x2, |
| 145 | OFPPS_LIVE = 0x4, |
| 146 | }; |
| 147 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 148 | enum ofp_port_features(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 149 | OFPPF_10MB_HD = 0x1, |
| 150 | OFPPF_10MB_FD = 0x2, |
| 151 | OFPPF_100MB_HD = 0x4, |
| 152 | OFPPF_100MB_FD = 0x8, |
| 153 | OFPPF_1GB_HD = 0x10, |
| 154 | OFPPF_1GB_FD = 0x20, |
| 155 | OFPPF_10GB_FD = 0x40, |
| 156 | OFPPF_40GB_FD = 0x80, |
| 157 | OFPPF_100GB_FD = 0x100, |
| 158 | OFPPF_1TB_FD = 0x200, |
| 159 | OFPPF_OTHER = 0x400, |
| 160 | OFPPF_COPPER = 0x800, |
| 161 | OFPPF_FIBER = 0x1000, |
| 162 | OFPPF_AUTONEG = 0x2000, |
| 163 | OFPPF_PAUSE = 0x4000, |
| 164 | OFPPF_PAUSE_ASYM = 0x8000, |
| 165 | }; |
| 166 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 167 | enum ofp_port_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 168 | OFPPR_ADD = 0, |
| 169 | OFPPR_DELETE = 1, |
| 170 | OFPPR_MODIFY = 2, |
| 171 | }; |
| 172 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 173 | enum ofp_match_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 174 | OFPMT_STANDARD = 0, |
| 175 | OFPMT_OXM = 1, |
| 176 | }; |
| 177 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 178 | enum ofp_oxm_class(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 179 | OFPXMC_NXM_0 = 0, |
| 180 | OFPXMC_NXM_1 = 1, |
| 181 | OFPXMC_OPENFLOW_BASIC = 0x8000, |
| 182 | OFPXMC_EXPERIMENTER = 0xffff, |
| 183 | }; |
| 184 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 185 | enum ofp_vlan_id(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 186 | OFPVID_NONE = 0, |
| 187 | OFPVID_PRESENT = 0x1000, |
| 188 | }; |
| 189 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 190 | // FIXME: OF spec specified this as '9' bits, implicitly adding |
| 191 | // to full byte |
| 192 | enum ofp_ipv6exthdr_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 193 | OFPIEH_NONEXT = 0x1, |
| 194 | OFPIEH_ESP = 0x2, |
| 195 | OFPIEH_AUTH = 0x4, |
| 196 | OFPIEH_DEST = 0x8, |
| 197 | OFPIEH_FRAG = 0x10, |
| 198 | OFPIEH_ROUTER = 0x20, |
| 199 | OFPIEH_HOP = 0x40, |
| 200 | OFPIEH_UNREP = 0x80, |
| 201 | OFPIEH_UNSEQ = 0x100, |
| 202 | }; |
| 203 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 204 | enum ofp_action_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 205 | OFPAT_OUTPUT = 0, |
| 206 | OFPAT_COPY_TTL_OUT = 0xb, |
| 207 | OFPAT_COPY_TTL_IN = 0xc, |
| 208 | OFPAT_SET_MPLS_TTL = 0xf, |
| 209 | OFPAT_DEC_MPLS_TTL = 0x10, |
| 210 | OFPAT_PUSH_VLAN = 0x11, |
| 211 | OFPAT_POP_VLAN = 0x12, |
| 212 | OFPAT_PUSH_MPLS = 0x13, |
| 213 | OFPAT_POP_MPLS = 0x14, |
| 214 | OFPAT_SET_QUEUE = 0x15, |
| 215 | OFPAT_GROUP = 0x16, |
| 216 | OFPAT_SET_NW_TTL = 0x17, |
| 217 | OFPAT_DEC_NW_TTL = 0x18, |
| 218 | OFPAT_SET_FIELD = 0x19, |
| 219 | OFPAT_PUSH_PBB = 0x1a, |
| 220 | OFPAT_POP_PBB = 0x1b, |
| 221 | OFPAT_EXPERIMENTER = 0xffff, |
| 222 | }; |
| 223 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 224 | enum ofp_controller_max_len(wire_type=uint16_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 225 | OFPCML_MAX = 0xffe5, |
| 226 | OFPCML_NO_BUFFER = 0xffff, |
| 227 | }; |
| 228 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 229 | enum ofp_instruction_type(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 230 | OFPIT_GOTO_TABLE = 0x1, |
| 231 | OFPIT_WRITE_METADATA = 0x2, |
| 232 | OFPIT_WRITE_ACTIONS = 0x3, |
| 233 | OFPIT_APPLY_ACTIONS = 0x4, |
| 234 | OFPIT_CLEAR_ACTIONS = 0x5, |
| 235 | OFPIT_METER = 0x6, |
| 236 | OFPIT_EXPERIMENTER = 0xffff, |
| 237 | }; |
| 238 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 239 | enum ofp_flow_mod_command(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 240 | OFPFC_ADD = 0, |
| 241 | OFPFC_MODIFY = 1, |
| 242 | OFPFC_MODIFY_STRICT = 2, |
| 243 | OFPFC_DELETE = 3, |
| 244 | OFPFC_DELETE_STRICT = 4, |
| 245 | }; |
| 246 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 247 | enum ofp_flow_mod_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 248 | OFPFF_SEND_FLOW_REM = 0x1, |
| 249 | OFPFF_CHECK_OVERLAP = 0x2, |
| 250 | OFPFF_RESET_COUNTS = 0x4, |
| 251 | OFPFF_NO_PKT_COUNTS = 0x8, |
| 252 | OFPFF_NO_BYT_COUNTS = 0x10, |
| 253 | }; |
| 254 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 255 | enum ofp_group(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 256 | OFPG_MAX = 0xffffff00, |
| 257 | OFPG_ALL = 0xfffffffc, |
| 258 | OFPG_ANY = 0xffffffff, |
| 259 | }; |
| 260 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 261 | enum ofp_group_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 262 | OFPGC_ADD = 0, |
| 263 | OFPGC_MODIFY = 1, |
| 264 | OFPGC_DELETE = 2, |
| 265 | }; |
| 266 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 267 | enum ofp_group_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 268 | OFPGT_ALL = 0, |
| 269 | OFPGT_SELECT = 1, |
| 270 | OFPGT_INDIRECT = 2, |
| 271 | OFPGT_FF = 3, |
| 272 | }; |
| 273 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 274 | enum ofp_packet_in_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 275 | OFPR_NO_MATCH = 0, |
| 276 | OFPR_ACTION = 1, |
| 277 | OFPR_INVALID_TTL = 2, |
| 278 | }; |
| 279 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 280 | enum ofp_flow_removed_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 281 | OFPRR_IDLE_TIMEOUT = 0, |
| 282 | OFPRR_HARD_TIMEOUT = 1, |
| 283 | OFPRR_DELETE = 2, |
| 284 | OFPRR_GROUP_DELETE = 3, |
| 285 | }; |
| 286 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 287 | enum ofp_meter(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 288 | OFPM_MAX = 0xffff0000, |
| 289 | OFPM_SLOWPATH = 0xfffffffd, |
| 290 | OFPM_CONTROLLER = 0xfffffffe, |
| 291 | OFPM_ALL = 0xffffffff, |
| 292 | }; |
| 293 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 294 | enum ofp_meter_band_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 295 | OFPMBT_DROP = 0x1, |
| 296 | OFPMBT_DSCP_REMARK = 0x2, |
| 297 | OFPMBT_EXPERIMENTER = 0xffff, |
| 298 | }; |
| 299 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 300 | enum ofp_meter_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 301 | OFPMC_ADD = 0, |
| 302 | OFPMC_MODIFY = 1, |
| 303 | OFPMC_DELETE = 2, |
| 304 | }; |
| 305 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 306 | enum ofp_meter_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 307 | OFPMF_KBPS = 0x1, |
| 308 | OFPMF_PKTPS = 0x2, |
| 309 | OFPMF_BURST = 0x4, |
| 310 | OFPMF_STATS = 0x8, |
| 311 | }; |
| 312 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 313 | enum ofp_error_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 314 | OFPET_HELLO_FAILED = 0, |
| 315 | OFPET_BAD_REQUEST = 1, |
| 316 | OFPET_BAD_ACTION = 2, |
| 317 | OFPET_BAD_INSTRUCTION = 3, |
| 318 | OFPET_BAD_MATCH = 4, |
| 319 | OFPET_FLOW_MOD_FAILED = 5, |
| 320 | OFPET_GROUP_MOD_FAILED = 6, |
| 321 | OFPET_PORT_MOD_FAILED = 7, |
| 322 | OFPET_TABLE_MOD_FAILED = 8, |
| 323 | OFPET_QUEUE_OP_FAILED = 9, |
| 324 | OFPET_SWITCH_CONFIG_FAILED = 10, |
| 325 | OFPET_ROLE_REQUEST_FAILED = 11, |
| 326 | OFPET_METER_MOD_FAILED = 12, |
| 327 | OFPET_TABLE_FEATURES_FAILED = 13, |
| 328 | OFPET_EXPERIMENTER = 0xffff, |
| 329 | }; |
| 330 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 331 | enum ofp_hello_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 332 | OFPHFC_INCOMPATIBLE = 0, |
| 333 | OFPHFC_EPERM = 1, |
| 334 | }; |
| 335 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 336 | enum ofp_bad_request_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 337 | OFPBRC_BAD_VERSION = 0, |
| 338 | OFPBRC_BAD_TYPE = 1, |
| 339 | OFPBRC_BAD_MULTIPART = 2, |
| 340 | OFPBRC_BAD_EXPERIMENTER = 3, |
| 341 | OFPBRC_BAD_EXP_TYPE = 4, |
| 342 | OFPBRC_EPERM = 5, |
| 343 | OFPBRC_BAD_LEN = 6, |
| 344 | OFPBRC_BUFFER_EMPTY = 7, |
| 345 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 346 | OFPBRC_BAD_TABLE_ID = 9, |
| 347 | OFPBRC_IS_SLAVE = 10, |
| 348 | OFPBRC_BAD_PORT = 11, |
| 349 | OFPBRC_BAD_PACKET = 12, |
| 350 | OFPBRC_MULTIPART_BUFFER_OVERFLOW = 13, |
| 351 | }; |
| 352 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 353 | enum ofp_bad_action_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 354 | OFPBAC_BAD_TYPE = 0, |
| 355 | OFPBAC_BAD_LEN = 1, |
| 356 | OFPBAC_BAD_EXPERIMENTER = 2, |
| 357 | OFPBAC_BAD_EXP_TYPE = 3, |
| 358 | OFPBAC_BAD_OUT_PORT = 4, |
| 359 | OFPBAC_BAD_ARGUMENT = 5, |
| 360 | OFPBAC_EPERM = 6, |
| 361 | OFPBAC_TOO_MANY = 7, |
| 362 | OFPBAC_BAD_QUEUE = 8, |
| 363 | OFPBAC_BAD_OUT_GROUP = 9, |
| 364 | OFPBAC_MATCH_INCONSISTENT = 10, |
| 365 | OFPBAC_UNSUPPORTED_ORDER = 11, |
| 366 | OFPBAC_BAD_TAG = 12, |
| 367 | OFPBAC_BAD_SET_TYPE = 13, |
| 368 | OFPBAC_BAD_SET_LEN = 14, |
| 369 | OFPBAC_BAD_SET_ARGUMENT = 15, |
| 370 | }; |
| 371 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 372 | enum ofp_bad_instruction_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 373 | OFPBIC_UNKNOWN_INST = 0, |
| 374 | OFPBIC_UNSUP_INST = 1, |
| 375 | OFPBIC_BAD_TABLE_ID = 2, |
| 376 | OFPBIC_UNSUP_METADATA = 3, |
| 377 | OFPBIC_UNSUP_METADATA_MASK = 4, |
| 378 | OFPBIC_BAD_EXPERIMENTER = 5, |
| 379 | OFPBIC_BAD_EXP_TYPE = 6, |
| 380 | OFPBIC_BAD_LEN = 7, |
| 381 | OFPBIC_EPERM = 8, |
| 382 | }; |
| 383 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 384 | enum ofp_bad_match_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 385 | OFPBMC_BAD_TYPE = 0, |
| 386 | OFPBMC_BAD_LEN = 1, |
| 387 | OFPBMC_BAD_TAG = 2, |
| 388 | OFPBMC_BAD_DL_ADDR_MASK = 3, |
| 389 | OFPBMC_BAD_NW_ADDR_MASK = 4, |
| 390 | OFPBMC_BAD_WILDCARDS = 5, |
| 391 | OFPBMC_BAD_FIELD = 6, |
| 392 | OFPBMC_BAD_VALUE = 7, |
| 393 | OFPBMC_BAD_MASK = 8, |
| 394 | OFPBMC_BAD_PREREQ = 9, |
| 395 | OFPBMC_DUP_FIELD = 10, |
| 396 | OFPBMC_EPERM = 11, |
| 397 | }; |
| 398 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 399 | enum ofp_flow_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 400 | OFPFMFC_UNKNOWN = 0, |
| 401 | OFPFMFC_TABLE_FULL = 1, |
| 402 | OFPFMFC_BAD_TABLE_ID = 2, |
| 403 | OFPFMFC_OVERLAP = 3, |
| 404 | OFPFMFC_EPERM = 4, |
| 405 | OFPFMFC_BAD_TIMEOUT = 5, |
| 406 | OFPFMFC_BAD_COMMAND = 6, |
| 407 | OFPFMFC_BAD_FLAGS = 7, |
| 408 | }; |
| 409 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 410 | enum ofp_group_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 411 | OFPGMFC_GROUP_EXISTS = 0, |
| 412 | OFPGMFC_INVALID_GROUP = 1, |
| 413 | OFPGMFC_WEIGHT_UNSUPPORTED = 2, |
| 414 | OFPGMFC_OUT_OF_GROUPS = 3, |
| 415 | OFPGMFC_OUT_OF_BUCKETS = 4, |
| 416 | OFPGMFC_CHAINING_UNSUPPORTED = 5, |
| 417 | OFPGMFC_WATCH_UNSUPPORTED = 6, |
| 418 | OFPGMFC_LOOP = 7, |
| 419 | OFPGMFC_UNKNOWN_GROUP = 8, |
| 420 | OFPGMFC_CHAINED_GROUP = 9, |
| 421 | OFPGMFC_BAD_TYPE = 10, |
| 422 | OFPGMFC_BAD_COMMAND = 11, |
| 423 | OFPGMFC_BAD_BUCKET = 12, |
| 424 | OFPGMFC_BAD_WATCH = 13, |
| 425 | OFPGMFC_EPERM = 14, |
| 426 | }; |
| 427 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 428 | enum ofp_port_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 429 | OFPPMFC_BAD_PORT = 0, |
| 430 | OFPPMFC_BAD_HW_ADDR = 1, |
| 431 | OFPPMFC_BAD_CONFIG = 2, |
| 432 | OFPPMFC_BAD_ADVERTISE = 3, |
| 433 | OFPPMFC_EPERM = 4, |
| 434 | }; |
| 435 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 436 | enum ofp_table_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 437 | OFPTMFC_BAD_TABLE = 0, |
| 438 | OFPTMFC_BAD_CONFIG = 1, |
| 439 | OFPTMFC_EPERM = 2, |
| 440 | }; |
| 441 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 442 | enum ofp_queue_op_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 443 | OFPQOFC_BAD_PORT = 0, |
| 444 | OFPQOFC_BAD_QUEUE = 1, |
| 445 | OFPQOFC_EPERM = 2, |
| 446 | }; |
| 447 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 448 | enum ofp_switch_config_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 449 | OFPSCFC_BAD_FLAGS = 0, |
| 450 | OFPSCFC_BAD_LEN = 1, |
| 451 | OFPSCFC_EPERM = 2, |
| 452 | }; |
| 453 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 454 | enum ofp_role_request_failed_code(wire_type=uint16_t){ |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 455 | OFPRRFC_STALE = 0, |
| 456 | OFPRRFC_UNSUP = 1, |
| 457 | OFPRRFC_BAD_ROLE = 2, |
| 458 | }; |
| 459 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 460 | enum ofp_meter_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 461 | OFPMMFC_UNKNOWN = 0, |
| 462 | OFPMMFC_METER_EXISTS = 1, |
| 463 | OFPMMFC_INVALID_METER = 2, |
| 464 | OFPMMFC_UNKNOWN_METER = 3, |
| 465 | OFPMMFC_BAD_COMMAND = 4, |
| 466 | OFPMMFC_BAD_FLAGS = 5, |
| 467 | OFPMMFC_BAD_RATE = 6, |
| 468 | OFPMMFC_BAD_BURST = 7, |
| 469 | OFPMMFC_BAD_BAND = 8, |
| 470 | OFPMMFC_BAD_BAND_VALUE = 9, |
| 471 | OFPMMFC_OUT_OF_METERS = 10, |
| 472 | OFPMMFC_OUT_OF_BANDS = 11, |
| 473 | }; |
| 474 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 475 | enum ofp_table_features_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 476 | OFPTFFC_BAD_TABLE = 0, |
| 477 | OFPTFFC_BAD_METADATA = 1, |
| 478 | OFPTFFC_BAD_TYPE = 2, |
| 479 | OFPTFFC_BAD_LEN = 3, |
| 480 | OFPTFFC_BAD_ARGUMENT = 4, |
| 481 | OFPTFFC_EPERM = 5, |
| 482 | }; |
| 483 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 484 | enum ofp_multipart_types(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 485 | OFPMP_DESC = 0, |
| 486 | OFPMP_FLOW = 1, |
| 487 | OFPMP_AGGREGATE = 2, |
| 488 | OFPMP_TABLE = 3, |
| 489 | OFPMP_PORT_STATS = 4, |
| 490 | OFPMP_QUEUE = 5, |
| 491 | OFPMP_GROUP = 6, |
| 492 | OFPMP_GROUP_DESC = 7, |
| 493 | OFPMP_GROUP_FEATURES = 8, |
| 494 | OFPMP_METER = 9, |
| 495 | OFPMP_METER_CONFIG = 10, |
| 496 | OFPMP_METER_FEATURES = 11, |
| 497 | OFPMP_TABLE_FEATURES = 12, |
| 498 | OFPMP_PORT_DESC = 13, |
| 499 | OFPMP_EXPERIMENTER = 0xffff, |
| 500 | }; |
| 501 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 502 | enum ofp_multipart_request_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 503 | OFPMPF_REQ_MORE = 0x1, |
| 504 | }; |
| 505 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 506 | enum ofp_multipart_reply_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 507 | OFPMPF_REPLY_MORE = 0x1, |
| 508 | }; |
| 509 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 510 | enum ofp_table_feature_prop_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 511 | OFPTFPT_INSTRUCTIONS = 0, |
| 512 | OFPTFPT_INSTRUCTIONS_MISS = 1, |
| 513 | OFPTFPT_NEXT_TABLES = 2, |
| 514 | OFPTFPT_NEXT_TABLES_MISS = 3, |
| 515 | OFPTFPT_WRITE_ACTIONS = 4, |
| 516 | OFPTFPT_WRITE_ACTIONS_MISS = 5, |
| 517 | OFPTFPT_APPLY_ACTIONS = 6, |
| 518 | OFPTFPT_APPLY_ACTIONS_MISS = 7, |
| 519 | OFPTFPT_MATCH = 8, |
| 520 | OFPTFPT_WILDCARDS = 0xa, |
| 521 | OFPTFPT_WRITE_SETFIELD = 0xc, |
| 522 | OFPTFPT_WRITE_SETFIELD_MISS = 0xd, |
| 523 | OFPTFPT_APPLY_SETFIELD = 0xe, |
| 524 | OFPTFPT_APPLY_SETFIELD_MISS = 0xf, |
| 525 | OFPTFPT_EXPERIMENTER = 0xfffe, |
| 526 | OFPTFPT_EXPERIMENTER_MISS = 0xffff, |
| 527 | }; |
| 528 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 529 | enum ofp_group_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 530 | OFPGFC_SELECT_WEIGHT = 0x1, |
| 531 | OFPGFC_SELECT_LIVENESS = 0x2, |
| 532 | OFPGFC_CHAINING = 0x4, |
| 533 | OFPGFC_CHAINING_CHECKS = 0x8, |
| 534 | }; |
| 535 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 536 | enum ofp_queue_properties(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 537 | OFPQT_MIN_RATE = 0x1, |
| 538 | OFPQT_MAX_RATE = 0x2, |
| 539 | OFPQT_EXPERIMENTER = 0xffff, |
| 540 | }; |
| 541 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 542 | enum ofp_controller_role(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 543 | OFPCR_ROLE_NOCHANGE = 0, |
| 544 | OFPCR_ROLE_EQUAL = 1, |
| 545 | OFPCR_ROLE_MASTER = 2, |
| 546 | OFPCR_ROLE_SLAVE = 3, |
| 547 | }; |
| 548 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 549 | enum ofp_hello_elem_type(wire_type=uint16_t) { |
Rich Lane | 0733cd6 | 2013-04-18 21:14:42 -0700 | [diff] [blame] | 550 | OFPHET_VERSIONBITMAP = 1, |
| 551 | }; |
| 552 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 553 | /* XXX rename to of_message */ |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 554 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 555 | uint8_t version; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 556 | uint8_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 557 | uint16_t length; |
| 558 | uint32_t xid; |
| 559 | }; |
| 560 | |
| 561 | // Special structures used for managing scalar list elements |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 562 | struct of_uint32 { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 563 | uint32_t value; |
| 564 | }; |
| 565 | |
| 566 | // Special structures used for managing scalar list elements |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 567 | struct of_uint8 { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 568 | uint8_t value; |
| 569 | }; |
| 570 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 571 | struct of_hello_elem { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 572 | uint16_t type; |
| 573 | uint16_t length; |
| 574 | }; |
| 575 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 576 | struct of_hello_elem_versionbitmap : of_hello_elem { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 577 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 578 | uint16_t length; |
| 579 | list(of_uint32_t) bitmaps; |
| 580 | }; |
| 581 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 582 | struct of_hello : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 583 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 584 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 585 | uint16_t length; |
| 586 | uint32_t xid; |
| 587 | list(of_hello_elem_t) elements; |
| 588 | }; |
| 589 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 590 | struct of_echo_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 591 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 592 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 593 | uint16_t length; |
| 594 | uint32_t xid; |
| 595 | of_octets_t data; |
| 596 | }; |
| 597 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 598 | struct of_echo_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 599 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 600 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 601 | uint16_t length; |
| 602 | uint32_t xid; |
| 603 | of_octets_t data; |
| 604 | }; |
| 605 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 606 | struct of_experimenter : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 607 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 608 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 609 | uint16_t length; |
| 610 | uint32_t xid; |
| 611 | uint32_t experimenter; |
| 612 | uint32_t subtype; |
| 613 | of_octets_t data; |
| 614 | }; |
| 615 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 616 | struct of_barrier_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 617 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 618 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 619 | uint16_t length; |
| 620 | uint32_t xid; |
| 621 | }; |
| 622 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 623 | struct of_barrier_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 624 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 625 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 626 | uint16_t length; |
| 627 | uint32_t xid; |
| 628 | }; |
| 629 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 630 | struct of_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 631 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 632 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 633 | uint16_t length; |
| 634 | uint32_t xid; |
| 635 | }; |
| 636 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 637 | struct of_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 638 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 639 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 640 | uint16_t length; |
| 641 | uint32_t xid; |
| 642 | uint16_t flags; |
| 643 | uint16_t miss_send_len; |
| 644 | }; |
| 645 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 646 | struct of_set_config : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 647 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 648 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 649 | uint16_t length; |
| 650 | uint32_t xid; |
| 651 | uint16_t flags; |
| 652 | uint16_t miss_send_len; |
| 653 | }; |
| 654 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 655 | struct of_table_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 656 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 657 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 658 | uint16_t length; |
| 659 | uint32_t xid; |
| 660 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 661 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 662 | uint32_t config; |
| 663 | }; |
| 664 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 665 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 666 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 667 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 668 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 669 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 670 | of_port_name_t name; |
| 671 | uint32_t config; |
| 672 | uint32_t state; |
| 673 | uint32_t curr; |
| 674 | uint32_t advertised; |
| 675 | uint32_t supported; |
| 676 | uint32_t peer; |
| 677 | uint32_t curr_speed; |
| 678 | uint32_t max_speed; |
| 679 | }; |
| 680 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 681 | struct of_features_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 682 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 683 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 684 | uint16_t length; |
| 685 | uint32_t xid; |
| 686 | }; |
| 687 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 688 | struct of_features_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 689 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 690 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 691 | uint16_t length; |
| 692 | uint32_t xid; |
| 693 | uint64_t datapath_id; |
| 694 | uint32_t n_buffers; |
| 695 | uint8_t n_tables; |
| 696 | uint8_t auxiliary_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 697 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 698 | uint32_t capabilities; |
| 699 | uint32_t reserved; |
| 700 | }; |
| 701 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 702 | struct of_port_status : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 703 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 704 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 705 | uint16_t length; |
| 706 | uint32_t xid; |
| 707 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 708 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 709 | of_port_desc_t desc; |
| 710 | }; |
| 711 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 712 | struct of_port_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 713 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 714 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 715 | uint16_t length; |
| 716 | uint32_t xid; |
| 717 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 718 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 719 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 720 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 721 | uint32_t config; |
| 722 | uint32_t mask; |
| 723 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 724 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 725 | }; |
| 726 | |
| 727 | // FIXME Does this need to be v4? |
Andreas Wundsam | fef7d5f | 2013-08-01 22:15:44 -0700 | [diff] [blame] | 728 | struct of_match_v3(align=8) { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 729 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 730 | uint16_t length; |
| 731 | list(of_oxm_t) oxm_list; |
| 732 | }; |
| 733 | |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 734 | // This looks like an action header, but is standalone. See |
| 735 | // ofp_table_features_prop_actions |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 736 | struct of_action_id { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 737 | uint16_t type; |
| 738 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 739 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 740 | }; |
| 741 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 742 | struct of_action_output : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 743 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 744 | uint16_t len; |
| 745 | of_port_no_t port; |
| 746 | uint16_t max_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 747 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 748 | }; |
| 749 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 750 | struct of_action_copy_ttl_out : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 751 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 752 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 753 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 754 | }; |
| 755 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 756 | struct of_action_copy_ttl_in : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 757 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 758 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 759 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 760 | }; |
| 761 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 762 | struct of_action_set_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 763 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 764 | uint16_t len; |
| 765 | uint8_t mpls_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 766 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 767 | }; |
| 768 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 769 | struct of_action_dec_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 770 | uint16_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 771 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 772 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 773 | }; |
| 774 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 775 | struct of_action_push_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 776 | uint16_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 777 | uint16_t len; |
| 778 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 779 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 780 | }; |
| 781 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 782 | struct of_action_pop_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 783 | uint16_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 784 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 785 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 786 | }; |
| 787 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 788 | struct of_action_push_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 789 | uint16_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 790 | uint16_t len; |
| 791 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 792 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 793 | }; |
| 794 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 795 | struct of_action_pop_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 796 | uint16_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 797 | uint16_t len; |
| 798 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 799 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 800 | }; |
| 801 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 802 | struct of_action_set_queue : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 803 | uint16_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 804 | uint16_t len; |
| 805 | uint32_t queue_id; |
| 806 | }; |
| 807 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 808 | struct of_action_group : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 809 | uint16_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 810 | uint16_t len; |
| 811 | uint32_t group_id; |
| 812 | }; |
| 813 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 814 | struct of_action_set_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 815 | uint16_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 816 | uint16_t len; |
| 817 | uint8_t nw_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 818 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 819 | }; |
| 820 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 821 | struct of_action_dec_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 822 | uint16_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 823 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 824 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 825 | }; |
| 826 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 827 | struct of_action_set_field : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 828 | uint16_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 829 | uint16_t len; |
Rich Lane | be90eae | 2013-07-22 16:44:26 -0700 | [diff] [blame] | 830 | of_oxm_t field; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 831 | }; |
| 832 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 833 | struct of_action_experimenter : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 834 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 835 | uint16_t len; |
| 836 | uint32_t experimenter; |
| 837 | of_octets_t data; |
| 838 | }; |
| 839 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 840 | struct of_action_pop_pbb : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 841 | uint16_t type == 27; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 842 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 843 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 844 | }; |
| 845 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 846 | struct of_action_push_pbb : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 847 | uint16_t type == 26; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 848 | uint16_t len; |
| 849 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 850 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 851 | }; |
| 852 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 853 | struct of_action { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 854 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 855 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 856 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 857 | }; |
| 858 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 859 | struct of_instruction { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 860 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 861 | uint16_t len; |
| 862 | }; |
| 863 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 864 | struct of_instruction_goto_table : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 865 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 866 | uint16_t len; |
| 867 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 868 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 869 | }; |
| 870 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 871 | struct of_instruction_write_metadata : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 872 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 873 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 874 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 875 | uint64_t metadata; |
| 876 | uint64_t metadata_mask; |
| 877 | }; |
| 878 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 879 | struct of_instruction_write_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 880 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 881 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 882 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 883 | list(of_action_t) actions; |
| 884 | }; |
| 885 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 886 | struct of_instruction_apply_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 887 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 888 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 889 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 890 | list(of_action_t) actions; |
| 891 | }; |
| 892 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 893 | struct of_instruction_clear_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 894 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 895 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 896 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 897 | }; |
| 898 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 899 | struct of_instruction_meter : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 900 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 901 | uint16_t len; |
| 902 | uint32_t meter_id; |
| 903 | }; |
| 904 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 905 | struct of_instruction_experimenter : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 906 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 907 | uint16_t len; |
| 908 | uint32_t experimenter; |
| 909 | of_octets_t data; |
| 910 | }; |
| 911 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 912 | struct of_flow_mod : of_header { |
| 913 | uint8_t version; |
| 914 | uint8_t type == 14; |
| 915 | uint16_t length; |
| 916 | uint32_t xid; |
| 917 | uint64_t cookie; |
| 918 | uint64_t cookie_mask; |
| 919 | uint8_t table_id; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 920 | of_fm_cmd_t _command == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 921 | uint16_t idle_timeout; |
| 922 | uint16_t hard_timeout; |
| 923 | uint16_t priority; |
| 924 | uint32_t buffer_id; |
| 925 | of_port_no_t out_port; |
| 926 | uint32_t out_group; |
| 927 | uint16_t flags; |
| 928 | pad(2); |
| 929 | of_match_t match; |
| 930 | list(of_instruction_t) instructions; |
| 931 | }; |
| 932 | |
| 933 | struct of_flow_add : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 934 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 935 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 936 | uint16_t length; |
| 937 | uint32_t xid; |
| 938 | uint64_t cookie; |
| 939 | uint64_t cookie_mask; |
| 940 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 941 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 942 | uint16_t idle_timeout; |
| 943 | uint16_t hard_timeout; |
| 944 | uint16_t priority; |
| 945 | uint32_t buffer_id; |
| 946 | of_port_no_t out_port; |
| 947 | uint32_t out_group; |
| 948 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 949 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 950 | of_match_t match; |
| 951 | list(of_instruction_t) instructions; |
| 952 | }; |
| 953 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 954 | struct of_flow_modify : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 955 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 956 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 957 | uint16_t length; |
| 958 | uint32_t xid; |
| 959 | uint64_t cookie; |
| 960 | uint64_t cookie_mask; |
| 961 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 962 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 963 | uint16_t idle_timeout; |
| 964 | uint16_t hard_timeout; |
| 965 | uint16_t priority; |
| 966 | uint32_t buffer_id; |
| 967 | of_port_no_t out_port; |
| 968 | uint32_t out_group; |
| 969 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 970 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 971 | of_match_t match; |
| 972 | list(of_instruction_t) instructions; |
| 973 | }; |
| 974 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 975 | struct of_flow_modify_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 976 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 977 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 978 | uint16_t length; |
| 979 | uint32_t xid; |
| 980 | uint64_t cookie; |
| 981 | uint64_t cookie_mask; |
| 982 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 983 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 984 | uint16_t idle_timeout; |
| 985 | uint16_t hard_timeout; |
| 986 | uint16_t priority; |
| 987 | uint32_t buffer_id; |
| 988 | of_port_no_t out_port; |
| 989 | uint32_t out_group; |
| 990 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 991 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 992 | of_match_t match; |
| 993 | list(of_instruction_t) instructions; |
| 994 | }; |
| 995 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 996 | struct of_flow_delete : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 997 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 998 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 999 | uint16_t length; |
| 1000 | uint32_t xid; |
| 1001 | uint64_t cookie; |
| 1002 | uint64_t cookie_mask; |
| 1003 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1004 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1005 | uint16_t idle_timeout; |
| 1006 | uint16_t hard_timeout; |
| 1007 | uint16_t priority; |
| 1008 | uint32_t buffer_id; |
| 1009 | of_port_no_t out_port; |
| 1010 | uint32_t out_group; |
| 1011 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1012 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1013 | of_match_t match; |
| 1014 | list(of_instruction_t) instructions; |
| 1015 | }; |
| 1016 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1017 | struct of_flow_delete_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1018 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1019 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1020 | uint16_t length; |
| 1021 | uint32_t xid; |
| 1022 | uint64_t cookie; |
| 1023 | uint64_t cookie_mask; |
| 1024 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1025 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1026 | uint16_t idle_timeout; |
| 1027 | uint16_t hard_timeout; |
| 1028 | uint16_t priority; |
| 1029 | uint32_t buffer_id; |
| 1030 | of_port_no_t out_port; |
| 1031 | uint32_t out_group; |
| 1032 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1033 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1034 | of_match_t match; |
| 1035 | list(of_instruction_t) instructions; |
| 1036 | }; |
| 1037 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1038 | struct of_bucket { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1039 | uint16_t len; |
| 1040 | uint16_t weight; |
| 1041 | of_port_no_t watch_port; |
| 1042 | uint32_t watch_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1043 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1044 | list(of_action_t) actions; |
| 1045 | }; |
| 1046 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1047 | struct of_group_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1048 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1049 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1050 | uint16_t length; |
| 1051 | uint32_t xid; |
| 1052 | uint16_t command; |
| 1053 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1054 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1055 | uint32_t group_id; |
| 1056 | list(of_bucket_t) buckets; |
| 1057 | }; |
| 1058 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1059 | struct of_packet_out : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1060 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1061 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1062 | uint16_t length; |
| 1063 | uint32_t xid; |
| 1064 | uint32_t buffer_id; |
| 1065 | of_port_no_t in_port; |
| 1066 | uint16_t actions_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1067 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1068 | list(of_action_t) actions; |
| 1069 | of_octets_t data; |
| 1070 | }; |
| 1071 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1072 | struct of_packet_in : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1073 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1074 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1075 | uint16_t length; |
| 1076 | uint32_t xid; |
| 1077 | uint32_t buffer_id; |
| 1078 | uint16_t total_len; |
| 1079 | uint8_t reason; |
| 1080 | uint8_t table_id; |
| 1081 | uint64_t cookie; |
| 1082 | of_match_t match; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1083 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1084 | of_octets_t data; /* FIXME: Ensure total_len gets updated */ |
| 1085 | }; |
| 1086 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1087 | struct of_flow_removed : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1088 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1089 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1090 | uint16_t length; |
| 1091 | uint32_t xid; |
| 1092 | uint64_t cookie; |
| 1093 | uint16_t priority; |
| 1094 | uint8_t reason; |
| 1095 | uint8_t table_id; |
| 1096 | uint32_t duration_sec; |
| 1097 | uint32_t duration_nsec; |
| 1098 | uint16_t idle_timeout; |
| 1099 | uint16_t hard_timeout; |
| 1100 | uint64_t packet_count; |
| 1101 | uint64_t byte_count; |
| 1102 | of_match_t match; |
| 1103 | }; |
| 1104 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1105 | struct of_meter_band { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1106 | uint16_t type; |
| 1107 | uint16_t len; |
| 1108 | // uint32_t rate; // These are excluded b/c this is the header |
| 1109 | // uint32_t burst_size; // These are excluded b/c this is the header |
| 1110 | }; |
| 1111 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1112 | struct of_meter_band_drop : of_meter_band { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1113 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1114 | uint16_t len; |
| 1115 | uint32_t rate; |
| 1116 | uint32_t burst_size; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1117 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1118 | }; |
| 1119 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1120 | struct of_meter_band_dscp_remark : of_meter_band { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1121 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1122 | uint16_t len; |
| 1123 | uint32_t rate; |
| 1124 | uint32_t burst_size; |
| 1125 | uint8_t prec_level; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1126 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1127 | }; |
| 1128 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1129 | struct of_meter_band_experimenter : of_meter_band { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1130 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1131 | uint16_t len; |
| 1132 | uint32_t rate; |
| 1133 | uint32_t burst_size; |
| 1134 | uint32_t experimenter; |
| 1135 | }; |
| 1136 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1137 | struct of_meter_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1138 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1139 | uint8_t type == 29; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1140 | uint16_t length; |
| 1141 | uint32_t xid; |
| 1142 | uint16_t command; |
| 1143 | uint16_t flags; |
| 1144 | uint32_t meter_id; |
| 1145 | list(of_meter_band_t) meters; |
| 1146 | }; |
| 1147 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1148 | struct of_error_msg : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1149 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1150 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1151 | uint16_t length; |
| 1152 | uint32_t xid; |
| 1153 | uint16_t err_type; |
| 1154 | uint16_t code; |
| 1155 | of_octets_t data; |
| 1156 | }; |
| 1157 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1158 | //struct of_error_experimenter_msg { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1159 | // uint8_t version; |
| 1160 | // uint8_t type; |
| 1161 | // uint16_t length; |
| 1162 | // uint32_t xid; |
| 1163 | // uint16_t err_type; |
| 1164 | // uint16_t subtype; |
| 1165 | // uint32_t experimenter; |
| 1166 | // of_octets_t data; |
| 1167 | //}; |
| 1168 | |
| 1169 | // STATS ENTRIES: flow, table, port, queue, group stats, group desc stats |
| 1170 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1171 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1172 | uint16_t length; |
| 1173 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1174 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1175 | uint32_t duration_sec; |
| 1176 | uint32_t duration_nsec; |
| 1177 | uint16_t priority; |
| 1178 | uint16_t idle_timeout; |
| 1179 | uint16_t hard_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1180 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1181 | uint64_t cookie; |
| 1182 | uint64_t packet_count; |
| 1183 | uint64_t byte_count; |
| 1184 | of_match_t match; |
| 1185 | list(of_instruction_t) instructions; |
| 1186 | }; |
| 1187 | |
| 1188 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1189 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1190 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1191 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1192 | uint32_t active_count; |
| 1193 | uint64_t lookup_count; |
| 1194 | uint64_t matched_count; |
| 1195 | }; |
| 1196 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1197 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1198 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1199 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1200 | uint64_t rx_packets; |
| 1201 | uint64_t tx_packets; |
| 1202 | uint64_t rx_bytes; |
| 1203 | uint64_t tx_bytes; |
| 1204 | uint64_t rx_dropped; |
| 1205 | uint64_t tx_dropped; |
| 1206 | uint64_t rx_errors; |
| 1207 | uint64_t tx_errors; |
| 1208 | uint64_t rx_frame_err; |
| 1209 | uint64_t rx_over_err; |
| 1210 | uint64_t rx_crc_err; |
| 1211 | uint64_t collisions; |
| 1212 | uint32_t duration_sec; |
| 1213 | uint32_t duration_nsec; |
| 1214 | }; |
| 1215 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1216 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1217 | of_port_no_t port_no; |
| 1218 | uint32_t queue_id; |
| 1219 | uint64_t tx_bytes; |
| 1220 | uint64_t tx_packets; |
| 1221 | uint64_t tx_errors; |
| 1222 | uint32_t duration_sec; |
| 1223 | uint32_t duration_nsec; |
| 1224 | }; |
| 1225 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1226 | struct of_bucket_counter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1227 | uint64_t packet_count; |
| 1228 | uint64_t byte_count; |
| 1229 | }; |
| 1230 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1231 | struct of_group_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1232 | uint16_t length; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1233 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1234 | uint32_t group_id; |
| 1235 | uint32_t ref_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1236 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1237 | uint64_t packet_count; |
| 1238 | uint64_t byte_count; |
| 1239 | uint32_t duration_sec; |
| 1240 | uint32_t duration_nsec; |
| 1241 | list(of_bucket_counter_t) bucket_stats; |
| 1242 | }; |
| 1243 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1244 | struct of_group_desc_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1245 | uint16_t length; |
| 1246 | uint8_t type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1247 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1248 | uint32_t group_id; |
| 1249 | list(of_bucket_t) buckets; |
| 1250 | }; |
| 1251 | |
| 1252 | // STATS: |
| 1253 | // Desc, flow, agg, table, port, queue, group, group_desc, group_feat, experi |
| 1254 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1255 | struct of_stats_request : of_header { |
| 1256 | uint8_t version; |
| 1257 | uint8_t type == 18; |
| 1258 | uint16_t length; |
| 1259 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1260 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1261 | uint16_t flags; |
| 1262 | pad(4); |
| 1263 | }; |
| 1264 | |
| 1265 | struct of_stats_reply : of_header { |
| 1266 | uint8_t version; |
| 1267 | uint8_t type == 19; |
| 1268 | uint16_t length; |
| 1269 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1270 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1271 | uint16_t flags; |
| 1272 | pad(4); |
| 1273 | }; |
| 1274 | |
| 1275 | struct of_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1276 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1277 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1278 | uint16_t length; |
| 1279 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1280 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1281 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1282 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1283 | }; |
| 1284 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1285 | struct of_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1286 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1287 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1288 | uint16_t length; |
| 1289 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1290 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1291 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1292 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1293 | of_desc_str_t mfr_desc; |
| 1294 | of_desc_str_t hw_desc; |
| 1295 | of_desc_str_t sw_desc; |
| 1296 | of_serial_num_t serial_num; |
| 1297 | of_desc_str_t dp_desc; |
| 1298 | }; |
| 1299 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1300 | struct of_flow_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1301 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1302 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1303 | uint16_t length; |
| 1304 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1305 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1306 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1307 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1308 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1309 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1310 | of_port_no_t out_port; |
| 1311 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1312 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1313 | uint64_t cookie; |
| 1314 | uint64_t cookie_mask; |
| 1315 | of_match_t match; |
| 1316 | }; |
| 1317 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1318 | struct of_flow_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1319 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1320 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1321 | uint16_t length; |
| 1322 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1323 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1324 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1325 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1326 | list(of_flow_stats_entry_t) entries; |
| 1327 | }; |
| 1328 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1329 | struct of_aggregate_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1330 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1331 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1332 | uint16_t length; |
| 1333 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1334 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1335 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1336 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1337 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1338 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1339 | of_port_no_t out_port; |
| 1340 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1341 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1342 | uint64_t cookie; |
| 1343 | uint64_t cookie_mask; |
| 1344 | of_match_t match; |
| 1345 | }; |
| 1346 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1347 | struct of_aggregate_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1348 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1349 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1350 | uint16_t length; |
| 1351 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1352 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1353 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1354 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1355 | uint64_t packet_count; |
| 1356 | uint64_t byte_count; |
| 1357 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1358 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1359 | }; |
| 1360 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1361 | struct of_table_stats_request : of_stats_request { |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1362 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1363 | uint8_t type == 18; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1364 | uint16_t length; |
| 1365 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1366 | uint16_t stats_type == 3; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1367 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1368 | pad(4); |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1369 | }; |
| 1370 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1371 | struct of_table_stats_reply : of_stats_reply { |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1372 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1373 | uint8_t type == 19; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1374 | uint16_t length; |
| 1375 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1376 | uint16_t stats_type == 3; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1377 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1378 | pad(4); |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1379 | list(of_table_stats_entry_t) entries; |
| 1380 | }; |
| 1381 | |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1382 | // FIXME: These are padded to 8 byte align beyond the length indicated |
| 1383 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1384 | struct of_table_feature_prop { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1385 | uint16_t type; |
| 1386 | uint16_t length; |
| 1387 | }; |
| 1388 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1389 | struct of_table_feature_prop_instructions : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1390 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1391 | uint16_t length; |
| 1392 | // FIXME Check if instruction_t is right for ids here |
| 1393 | list(of_instruction_t) instruction_ids; |
| 1394 | }; |
| 1395 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1396 | struct of_table_feature_prop_instructions_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1397 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1398 | uint16_t length; |
| 1399 | list(of_instruction_t) instruction_ids; |
| 1400 | }; |
| 1401 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1402 | struct of_table_feature_prop_next_tables : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1403 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1404 | uint16_t length; |
| 1405 | list(of_uint8_t) next_table_ids; |
| 1406 | }; |
| 1407 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1408 | struct of_table_feature_prop_next_tables_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1409 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1410 | uint16_t length; |
| 1411 | list(of_uint8_t) next_table_ids; |
| 1412 | }; |
| 1413 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1414 | struct of_table_feature_prop_write_actions : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1415 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1416 | uint16_t length; |
| 1417 | list(of_action_id_t) action_ids; |
| 1418 | }; |
| 1419 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1420 | struct of_table_feature_prop_write_actions_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1421 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1422 | uint16_t length; |
| 1423 | list(of_action_id_t) action_ids; |
| 1424 | }; |
| 1425 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1426 | struct of_table_feature_prop_apply_actions : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1427 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1428 | uint16_t length; |
| 1429 | list(of_action_id_t) action_ids; |
| 1430 | }; |
| 1431 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1432 | struct of_table_feature_prop_apply_actions_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1433 | uint16_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1434 | uint16_t length; |
| 1435 | list(of_action_id_t) action_ids; |
| 1436 | }; |
| 1437 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1438 | struct of_table_feature_prop_match : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1439 | uint16_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1440 | uint16_t length; |
| 1441 | list(of_uint32_t) oxm_ids; |
| 1442 | }; |
| 1443 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1444 | struct of_table_feature_prop_wildcards : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1445 | uint16_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1446 | uint16_t length; |
| 1447 | list(of_uint32_t) oxm_ids; |
| 1448 | }; |
| 1449 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1450 | struct of_table_feature_prop_write_setfield : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1451 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1452 | uint16_t length; |
| 1453 | list(of_uint32_t) oxm_ids; |
| 1454 | }; |
| 1455 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1456 | struct of_table_feature_prop_write_setfield_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1457 | uint16_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1458 | uint16_t length; |
| 1459 | list(of_uint32_t) oxm_ids; |
| 1460 | }; |
| 1461 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1462 | struct of_table_feature_prop_apply_setfield : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1463 | uint16_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1464 | uint16_t length; |
| 1465 | list(of_uint32_t) oxm_ids; |
| 1466 | }; |
| 1467 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1468 | struct of_table_feature_prop_apply_setfield_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1469 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1470 | uint16_t length; |
| 1471 | list(of_uint32_t) oxm_ids; |
| 1472 | }; |
| 1473 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1474 | struct of_table_feature_prop_experimenter : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1475 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1476 | uint16_t length; |
| 1477 | uint32_t experimenter; |
| 1478 | uint32_t subtype; |
| 1479 | of_octets_t experimenter_data; |
| 1480 | }; |
| 1481 | |
| 1482 | // Not yet supported |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1483 | // struct of_table_feature_prop_experimenter_miss : of_table_feature_prop { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1484 | // uint16_t type; |
| 1485 | // uint16_t length; |
| 1486 | // uint32_t experimenter; |
| 1487 | // uint32_t subtype; |
| 1488 | // of_octets_t experimenter_data; |
| 1489 | // }; |
| 1490 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1491 | struct of_table_features { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1492 | uint16_t length; |
| 1493 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1494 | pad(5); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1495 | of_table_name_t name; |
| 1496 | uint64_t metadata_match; |
| 1497 | uint64_t metadata_write; |
| 1498 | uint32_t config; |
| 1499 | uint32_t max_entries; |
| 1500 | list(of_table_feature_prop_t) properties; |
| 1501 | }; |
| 1502 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1503 | struct of_meter_features { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1504 | uint32_t max_meter; |
| 1505 | uint32_t band_types; |
| 1506 | uint32_t capabilities; |
| 1507 | uint8_t max_bands; |
| 1508 | uint8_t max_color; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1509 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1510 | }; |
| 1511 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1512 | struct of_port_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1513 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1514 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1515 | uint16_t length; |
| 1516 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1517 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1518 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1519 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1520 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1521 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1522 | }; |
| 1523 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1524 | struct of_port_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1525 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1526 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1527 | uint16_t length; |
| 1528 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1529 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1530 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1531 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1532 | list(of_port_stats_entry_t) entries; |
| 1533 | }; |
| 1534 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1535 | struct of_queue_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1536 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1537 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1538 | uint16_t length; |
| 1539 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1540 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1541 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1542 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1543 | of_port_no_t port_no; |
| 1544 | uint32_t queue_id; |
| 1545 | }; |
| 1546 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1547 | struct of_queue_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1548 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1549 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1550 | uint16_t length; |
| 1551 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1552 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1553 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1554 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1555 | list(of_queue_stats_entry_t) entries; |
| 1556 | }; |
| 1557 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1558 | struct of_group_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1559 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1560 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1561 | uint16_t length; |
| 1562 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1563 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1564 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1565 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1566 | uint32_t group_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1567 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1568 | }; |
| 1569 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1570 | struct of_group_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1571 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1572 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1573 | uint16_t length; |
| 1574 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1575 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1576 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1577 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1578 | list(of_group_stats_entry_t) entries; |
| 1579 | }; |
| 1580 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1581 | struct of_group_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1582 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1583 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1584 | uint16_t length; |
| 1585 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1586 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1587 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1588 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1589 | }; |
| 1590 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1591 | struct of_group_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1592 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1593 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1594 | uint16_t length; |
| 1595 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1596 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1597 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1598 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1599 | list(of_group_desc_stats_entry_t) entries; |
| 1600 | }; |
| 1601 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1602 | struct of_group_features_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1603 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1604 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1605 | uint16_t length; |
| 1606 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1607 | uint16_t stats_type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1608 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1609 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1610 | }; |
| 1611 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1612 | struct of_group_features_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1613 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1614 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1615 | uint16_t length; |
| 1616 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1617 | uint16_t stats_type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1618 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1619 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1620 | uint32_t types; |
| 1621 | uint32_t capabilities; |
| 1622 | uint32_t max_groups_all; |
| 1623 | uint32_t max_groups_select; |
| 1624 | uint32_t max_groups_indirect; |
| 1625 | uint32_t max_groups_ff; |
| 1626 | uint32_t actions_all; |
| 1627 | uint32_t actions_select; |
| 1628 | uint32_t actions_indirect; |
| 1629 | uint32_t actions_ff; |
| 1630 | }; |
| 1631 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1632 | struct of_meter_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1633 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1634 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1635 | uint16_t length; |
| 1636 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1637 | uint16_t stats_type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1638 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1639 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1640 | uint32_t meter_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1641 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1642 | }; |
| 1643 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1644 | struct of_meter_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1645 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1646 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1647 | uint16_t length; |
| 1648 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1649 | uint16_t stats_type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1650 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1651 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1652 | list(of_meter_stats_t) entries; |
| 1653 | }; |
| 1654 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1655 | struct of_meter_config_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1656 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1657 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1658 | uint16_t length; |
| 1659 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1660 | uint16_t stats_type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1661 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1662 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1663 | uint32_t meter_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1664 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1665 | }; |
| 1666 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1667 | struct of_meter_config_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1668 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1669 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1670 | uint16_t length; |
| 1671 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1672 | uint16_t stats_type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1673 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1674 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1675 | list(of_meter_band_t) entries; |
| 1676 | }; |
| 1677 | |
| 1678 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1679 | struct of_meter_features_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1680 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1681 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1682 | uint16_t length; |
| 1683 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1684 | uint16_t stats_type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1685 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1686 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1687 | }; |
| 1688 | |
| 1689 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1690 | struct of_meter_features_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1691 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1692 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1693 | uint16_t length; |
| 1694 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1695 | uint16_t stats_type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1696 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1697 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1698 | of_meter_features_t features; |
| 1699 | }; |
| 1700 | |
| 1701 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1702 | struct of_table_features_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1703 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1704 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1705 | uint16_t length; |
| 1706 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1707 | uint16_t stats_type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1708 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1709 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1710 | list(of_table_features_t) entries; |
| 1711 | }; |
| 1712 | |
| 1713 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1714 | struct of_table_features_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1715 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1716 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1717 | uint16_t length; |
| 1718 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1719 | uint16_t stats_type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1720 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1721 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1722 | list(of_table_features_t) entries; |
| 1723 | }; |
| 1724 | |
| 1725 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1726 | struct of_port_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1727 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1728 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1729 | uint16_t length; |
| 1730 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1731 | uint16_t stats_type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1732 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1733 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1734 | }; |
| 1735 | |
| 1736 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1737 | struct of_port_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1738 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1739 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1740 | uint16_t length; |
| 1741 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1742 | uint16_t stats_type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1743 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1744 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1745 | list(of_port_desc_t) entries; |
| 1746 | }; |
| 1747 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1748 | struct of_meter_band_stats { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1749 | uint64_t packet_band_count; |
| 1750 | uint64_t byte_band_count; |
| 1751 | }; |
| 1752 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1753 | struct of_meter_stats { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1754 | uint32_t meter_id; |
| 1755 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1756 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1757 | uint32_t flow_count; |
| 1758 | uint64_t packet_in_count; |
| 1759 | uint64_t byte_in_count; |
| 1760 | uint32_t duration_sec; |
| 1761 | uint32_t duration_nsec; |
| 1762 | list(of_meter_band_stats_t) band_stats; |
| 1763 | }; |
| 1764 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1765 | struct of_meter_config { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1766 | uint16_t length; |
| 1767 | uint16_t flags; |
| 1768 | uint32_t meter_id; |
| 1769 | list(of_meter_band_t) entries; |
| 1770 | }; |
| 1771 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1772 | struct of_experimenter_multipart_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1773 | uint32_t experimenter; |
| 1774 | uint32_t subtype; |
| 1775 | }; |
| 1776 | |
| 1777 | // END OF STATS OBJECTS |
| 1778 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1779 | struct of_queue_prop { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1780 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1781 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1782 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1783 | }; |
| 1784 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1785 | struct of_queue_prop_min_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1786 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1787 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1788 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1789 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1790 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1791 | }; |
| 1792 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1793 | struct of_queue_prop_max_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1794 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1795 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1796 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1797 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1798 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1799 | }; |
| 1800 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1801 | struct of_queue_prop_experimenter : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1802 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1803 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1804 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1805 | uint32_t experimenter; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1806 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1807 | of_octets_t data; |
| 1808 | }; |
| 1809 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1810 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1811 | uint32_t queue_id; |
| 1812 | of_port_no_t port; |
| 1813 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1814 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1815 | list(of_queue_prop_t) properties; |
| 1816 | }; |
| 1817 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1818 | struct of_queue_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1819 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1820 | uint8_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1821 | uint16_t length; |
| 1822 | uint32_t xid; |
| 1823 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1824 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1825 | }; |
| 1826 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1827 | struct of_queue_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1828 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1829 | uint8_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1830 | uint16_t length; |
| 1831 | uint32_t xid; |
| 1832 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1833 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1834 | list(of_packet_queue_t) queues; |
| 1835 | }; |
| 1836 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1837 | struct of_role_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1838 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1839 | uint8_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1840 | uint16_t length; |
| 1841 | uint32_t xid; |
| 1842 | uint32_t role; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1843 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1844 | uint64_t generation_id; |
| 1845 | }; |
| 1846 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1847 | struct of_role_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1848 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1849 | uint8_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1850 | uint16_t length; |
| 1851 | uint32_t xid; |
| 1852 | of_octets_t data; |
| 1853 | }; |
| 1854 | |
| 1855 | //////////////////////////////////////////////////////////////// |
| 1856 | // FIXME understand async; where do bitmasks live? |
| 1857 | // Determine bitmap type for masks below. |
| 1858 | // DOCUMENT masks where uint32_t[0] is interest for equal/master |
| 1859 | // while uint32_t[1] is interest for slave |
| 1860 | //////////////////////////////////////////////////////////////// |
| 1861 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1862 | struct of_async_get_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1863 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1864 | uint8_t type == 26; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1865 | uint16_t length; |
| 1866 | uint32_t xid; |
| 1867 | uint32_t packet_in_mask_equal_master; |
| 1868 | uint32_t packet_in_mask_slave; |
| 1869 | uint32_t port_status_mask_equal_master; |
| 1870 | uint32_t port_status_mask_slave; |
| 1871 | uint32_t flow_removed_mask_equal_master; |
| 1872 | uint32_t flow_removed_mask_slave; |
| 1873 | }; |
| 1874 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1875 | struct of_async_get_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1876 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1877 | uint8_t type == 27; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1878 | uint16_t length; |
| 1879 | uint32_t xid; |
| 1880 | uint32_t packet_in_mask_equal_master; |
| 1881 | uint32_t packet_in_mask_slave; |
| 1882 | uint32_t port_status_mask_equal_master; |
| 1883 | uint32_t port_status_mask_slave; |
| 1884 | uint32_t flow_removed_mask_equal_master; |
| 1885 | uint32_t flow_removed_mask_slave; |
| 1886 | }; |
| 1887 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1888 | struct of_async_set : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1889 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1890 | uint8_t type == 28; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1891 | uint16_t length; |
| 1892 | uint32_t xid; |
| 1893 | uint32_t packet_in_mask_equal_master; |
| 1894 | uint32_t packet_in_mask_slave; |
| 1895 | uint32_t port_status_mask_equal_master; |
| 1896 | uint32_t port_status_mask_slave; |
| 1897 | uint32_t flow_removed_mask_equal_master; |
| 1898 | uint32_t flow_removed_mask_slave; |
| 1899 | }; |