Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 1 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
Wilson Ng | d72013d | 2013-09-29 10:21:48 -0700 | [diff] [blame] | 38 | OFP_TCP_PORT = 6653, |
| 39 | OFP_SSL_PORT = 6653, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFP_VLAN_NONE = 0xffff, |
| 46 | |
| 47 | OFPFW_ICMP_TYPE = 0x40, |
| 48 | OFPFW_ICMP_CODE = 0x80, |
| 49 | |
| 50 | OFP_DL_TYPE_ETH2_CUTOFF = 0x600, |
| 51 | OFP_DL_TYPE_NOT_ETH_TYPE = 0x5ff, |
| 52 | |
| 53 | OFP_FLOW_PERMANENT = 0, |
| 54 | |
| 55 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 56 | |
| 57 | DESC_STR_LEN = 256, |
| 58 | SERIAL_NUM_LEN = 32, |
| 59 | |
| 60 | OFPQ_ALL = 0xffffffff, |
| 61 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 62 | }; |
| 63 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 64 | enum ofp_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 65 | OFPT_HELLO = 0, |
| 66 | OFPT_ERROR = 1, |
| 67 | OFPT_ECHO_REQUEST = 2, |
| 68 | OFPT_ECHO_REPLY = 3, |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 69 | OFPT_EXPERIMENTER = 4, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 70 | OFPT_FEATURES_REQUEST = 5, |
| 71 | OFPT_FEATURES_REPLY = 6, |
| 72 | OFPT_GET_CONFIG_REQUEST = 7, |
| 73 | OFPT_GET_CONFIG_REPLY = 8, |
| 74 | OFPT_SET_CONFIG = 9, |
| 75 | OFPT_PACKET_IN = 10, |
| 76 | OFPT_FLOW_REMOVED = 11, |
| 77 | OFPT_PORT_STATUS = 12, |
| 78 | OFPT_PACKET_OUT = 13, |
| 79 | OFPT_FLOW_MOD = 14, |
| 80 | OFPT_PORT_MOD = 15, |
| 81 | OFPT_STATS_REQUEST = 16, |
| 82 | OFPT_STATS_REPLY = 17, |
| 83 | OFPT_BARRIER_REQUEST = 18, |
| 84 | OFPT_BARRIER_REPLY = 19, |
| 85 | OFPT_QUEUE_GET_CONFIG_REQUEST = 20, |
| 86 | OFPT_QUEUE_GET_CONFIG_REPLY = 21, |
| 87 | }; |
| 88 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 89 | enum ofp_port_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 90 | OFPPC_PORT_DOWN = 0x1, |
| 91 | OFPPC_NO_STP = 0x2, |
| 92 | OFPPC_NO_RECV = 0x4, |
| 93 | OFPPC_NO_RECV_STP = 0x8, |
| 94 | OFPPC_NO_FLOOD = 0x10, |
| 95 | OFPPC_NO_FWD = 0x20, |
| 96 | OFPPC_NO_PACKET_IN = 0x40, |
Rob Vaterlaus | 0a8ec14 | 2013-10-10 13:27:14 -0700 | [diff] [blame] | 97 | OFPPC_BSN_MIRROR_DEST = 0x80000000, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 98 | }; |
| 99 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 100 | enum ofp_port_state(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 101 | OFPPS_LINK_DOWN = 1, |
Andreas Wundsam | c1acfcc | 2013-09-20 13:10:20 -0700 | [diff] [blame] | 102 | OFPPS_STP_LISTEN = 0, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 103 | OFPPS_STP_LEARN = 0x100, |
| 104 | OFPPS_STP_FORWARD = 0x200, |
| 105 | OFPPS_STP_BLOCK = 0x300, |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 106 | OFPPS_STP_MASK(virtual=True) = 0x300, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 107 | }; |
| 108 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 109 | // FIXME: these constants are currently 32 bit due to implementation |
| 110 | // details of loci, which is in violation of the OpenFlow spec. |
| 111 | // Should recast to 32 bits and fix/glue the c backend |
| 112 | enum ofp_port(wire_type=uint16_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 113 | OFPP_MAX = 0xffffff00, |
| 114 | OFPP_IN_PORT = 0xfffffff8, |
| 115 | OFPP_TABLE = 0xfffffff9, |
| 116 | OFPP_NORMAL = 0xfffffffa, |
| 117 | OFPP_FLOOD = 0xfffffffb, |
| 118 | OFPP_ALL = 0xfffffffc, |
| 119 | OFPP_CONTROLLER = 0xfffffffd, |
| 120 | OFPP_LOCAL = 0xfffffffe, |
| 121 | OFPP_NONE = 0xffffffff, |
| 122 | }; |
| 123 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 124 | enum ofp_port_features(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 125 | OFPPF_10MB_HD = 0x1, |
| 126 | OFPPF_10MB_FD = 0x2, |
| 127 | OFPPF_100MB_HD = 0x4, |
| 128 | OFPPF_100MB_FD = 0x8, |
| 129 | OFPPF_1GB_HD = 0x10, |
| 130 | OFPPF_1GB_FD = 0x20, |
| 131 | OFPPF_10GB_FD = 0x40, |
| 132 | OFPPF_COPPER = 0x80, |
| 133 | OFPPF_FIBER = 0x100, |
| 134 | OFPPF_AUTONEG = 0x200, |
| 135 | OFPPF_PAUSE = 0x400, |
| 136 | OFPPF_PAUSE_ASYM = 0x800, |
| 137 | }; |
| 138 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 139 | enum ofp_queue_properties(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 140 | OFPQT_NONE = 0, |
| 141 | OFPQT_MIN_RATE = 1, |
| 142 | }; |
| 143 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 144 | enum ofp_flow_wildcards(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 145 | OFPFW_IN_PORT = 0x1, |
| 146 | OFPFW_DL_VLAN = 0x2, |
| 147 | OFPFW_DL_SRC = 0x4, |
| 148 | OFPFW_NW_DST_BITS = 0x6, |
| 149 | OFPFW_NW_SRC_BITS = 0x6, |
| 150 | OFPFW_NW_SRC_SHIFT = 0x8, |
| 151 | OFPFW_DL_DST = 0x8, |
| 152 | OFPFW_NW_DST_SHIFT = 0xe, |
| 153 | OFPFW_DL_TYPE = 0x10, |
| 154 | OFPFW_NW_PROTO = 0x20, |
| 155 | OFPFW_TP_SRC = 0x40, |
| 156 | OFPFW_TP_DST = 0x80, |
| 157 | OFPFW_NW_SRC_ALL = 0x2000, |
| 158 | OFPFW_NW_SRC_MASK = 0x3f00, |
| 159 | OFPFW_NW_DST_ALL = 0x80000, |
| 160 | OFPFW_NW_DST_MASK = 0xfc000, |
| 161 | OFPFW_DL_VLAN_PCP = 0x100000, |
| 162 | OFPFW_NW_TOS = 0x200000, |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 163 | OFPFW_ALL(virtual=True) = 0x3fffff, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 164 | }; |
| 165 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 166 | enum ofp_action_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 167 | OFPAT_OUTPUT = 0, |
| 168 | OFPAT_SET_VLAN_VID = 1, |
| 169 | OFPAT_SET_VLAN_PCP = 2, |
| 170 | OFPAT_STRIP_VLAN = 3, |
| 171 | OFPAT_SET_DL_SRC = 4, |
| 172 | OFPAT_SET_DL_DST = 5, |
| 173 | OFPAT_SET_NW_SRC = 6, |
| 174 | OFPAT_SET_NW_DST = 7, |
| 175 | OFPAT_SET_NW_TOS = 8, |
| 176 | OFPAT_SET_TP_SRC = 9, |
| 177 | OFPAT_SET_TP_DST = 10, |
| 178 | OFPAT_ENQUEUE = 11, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 179 | OFPAT_EXPERIMENTER = 0xffff, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 180 | }; |
| 181 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 182 | enum ofp_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 183 | OFPC_FLOW_STATS = 0x1, |
| 184 | OFPC_TABLE_STATS = 0x2, |
| 185 | OFPC_PORT_STATS = 0x4, |
| 186 | OFPC_STP = 0x8, |
| 187 | OFPC_RESERVED = 0x10, |
| 188 | OFPC_IP_REASM = 0x20, |
| 189 | OFPC_QUEUE_STATS = 0x40, |
| 190 | OFPC_ARP_MATCH_IP = 0x80, |
| 191 | }; |
| 192 | |
Andreas Wundsam | 057540b | 2013-11-19 16:51:36 -0800 | [diff] [blame] | 193 | enum ofp_config_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 194 | OFPC_FRAG_NORMAL = 0x0, |
| 195 | OFPC_FRAG_DROP = 0x1, |
| 196 | OFPC_FRAG_REASM = 0x2, |
| 197 | OFPC_FRAG_MASK = 0x3, |
| 198 | }; |
| 199 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 200 | enum ofp_flow_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 201 | OFPFC_ADD = 0, |
| 202 | OFPFC_MODIFY = 1, |
| 203 | OFPFC_MODIFY_STRICT = 2, |
| 204 | OFPFC_DELETE = 3, |
| 205 | OFPFC_DELETE_STRICT = 4, |
| 206 | }; |
| 207 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 208 | enum ofp_flow_mod_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 209 | OFPFF_SEND_FLOW_REM = 0x1, |
| 210 | OFPFF_CHECK_OVERLAP = 0x2, |
| 211 | OFPFF_EMERG = 0x4, |
| 212 | }; |
| 213 | |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 214 | enum ofp_stats_request_flags(wire_type=uint16_t, bitmask=True) { |
| 215 | }; |
| 216 | |
| 217 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 218 | enum ofp_stats_reply_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 219 | OFPSF_REPLY_MORE = 0x1, |
| 220 | }; |
| 221 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 222 | enum ofp_stats_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 223 | OFPST_DESC = 0, |
| 224 | OFPST_FLOW = 1, |
| 225 | OFPST_AGGREGATE = 2, |
| 226 | OFPST_TABLE = 3, |
| 227 | OFPST_PORT = 4, |
| 228 | OFPST_QUEUE = 5, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 229 | OFPST_EXPERIMENTER = 0xffff, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 230 | }; |
| 231 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 232 | enum ofp_packet_in_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 233 | OFPR_NO_MATCH = 0, |
| 234 | OFPR_ACTION = 1, |
| 235 | }; |
| 236 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 237 | enum ofp_flow_removed_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 238 | OFPRR_IDLE_TIMEOUT = 0, |
| 239 | OFPRR_HARD_TIMEOUT = 1, |
| 240 | OFPRR_DELETE = 2, |
| 241 | }; |
| 242 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 243 | enum ofp_port_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 244 | OFPPR_ADD = 0, |
| 245 | OFPPR_DELETE = 1, |
| 246 | OFPPR_MODIFY = 2, |
| 247 | }; |
| 248 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 249 | enum ofp_error_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 250 | OFPET_HELLO_FAILED = 0, |
| 251 | OFPET_BAD_REQUEST = 1, |
| 252 | OFPET_BAD_ACTION = 2, |
| 253 | OFPET_FLOW_MOD_FAILED = 3, |
| 254 | OFPET_PORT_MOD_FAILED = 4, |
| 255 | OFPET_QUEUE_OP_FAILED = 5, |
| 256 | }; |
| 257 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 258 | enum ofp_hello_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 259 | OFPHFC_INCOMPATIBLE = 0, |
| 260 | OFPHFC_EPERM = 1, |
| 261 | }; |
| 262 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 263 | enum ofp_bad_request_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 264 | OFPBRC_BAD_VERSION = 0, |
| 265 | OFPBRC_BAD_TYPE = 1, |
| 266 | OFPBRC_BAD_STAT = 2, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 267 | OFPBRC_BAD_EXPERIMENTER = 3, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 268 | OFPBRC_BAD_SUBTYPE = 4, |
| 269 | OFPBRC_EPERM = 5, |
| 270 | OFPBRC_BAD_LEN = 6, |
| 271 | OFPBRC_BUFFER_EMPTY = 7, |
| 272 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 273 | }; |
| 274 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 275 | enum ofp_bad_action_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 276 | OFPBAC_BAD_TYPE = 0, |
| 277 | OFPBAC_BAD_LEN = 1, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 278 | OFPBAC_BAD_EXPERIMENTER = 2, |
| 279 | OFPBAC_BAD_EXPERIMENTER_TYPE = 3, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 280 | OFPBAC_BAD_OUT_PORT = 4, |
| 281 | OFPBAC_BAD_ARGUMENT = 5, |
| 282 | OFPBAC_EPERM = 6, |
| 283 | OFPBAC_TOO_MANY = 7, |
| 284 | OFPBAC_BAD_QUEUE = 8, |
| 285 | }; |
| 286 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 287 | enum ofp_flow_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 288 | OFPFMFC_ALL_TABLES_FULL = 0, |
| 289 | OFPFMFC_OVERLAP = 1, |
| 290 | OFPFMFC_EPERM = 2, |
| 291 | OFPFMFC_BAD_EMERG_TIMEOUT = 3, |
| 292 | OFPFMFC_BAD_COMMAND = 4, |
| 293 | OFPFMFC_UNSUPPORTED = 5, |
| 294 | }; |
| 295 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 296 | enum ofp_port_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 297 | OFPPMFC_BAD_PORT = 0, |
| 298 | OFPPMFC_BAD_HW_ADDR = 1, |
| 299 | }; |
| 300 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 301 | enum ofp_queue_op_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 302 | OFPQOFC_BAD_PORT = 0, |
| 303 | OFPQOFC_BAD_QUEUE = 1, |
| 304 | OFPQOFC_EPERM = 2, |
| 305 | }; |
| 306 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 307 | /* XXX rename to of_message */ |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 308 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 309 | uint8_t version; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 310 | uint8_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 311 | uint16_t length; |
| 312 | uint32_t xid; |
| 313 | }; |
| 314 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 315 | struct of_hello : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 316 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 317 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 318 | uint16_t length; |
| 319 | uint32_t xid; |
| 320 | }; |
| 321 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 322 | struct of_echo_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 323 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 324 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 325 | uint16_t length; |
| 326 | uint32_t xid; |
| 327 | of_octets_t data; |
| 328 | }; |
| 329 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 330 | struct of_echo_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 331 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 332 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 333 | uint16_t length; |
| 334 | uint32_t xid; |
| 335 | of_octets_t data; |
| 336 | }; |
| 337 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 338 | struct of_experimenter : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 339 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 340 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 341 | uint16_t length; |
| 342 | uint32_t xid; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 343 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 344 | uint32_t subtype; |
| 345 | of_octets_t data; |
| 346 | }; |
| 347 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 348 | struct of_barrier_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 349 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 350 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 351 | uint16_t length; |
| 352 | uint32_t xid; |
| 353 | }; |
| 354 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 355 | struct of_barrier_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 356 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 357 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 358 | uint16_t length; |
| 359 | uint32_t xid; |
| 360 | }; |
| 361 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 362 | struct of_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 363 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 364 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 365 | uint16_t length; |
| 366 | uint32_t xid; |
| 367 | }; |
| 368 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 369 | struct of_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 370 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 371 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 372 | uint16_t length; |
| 373 | uint32_t xid; |
Andreas Wundsam | 057540b | 2013-11-19 16:51:36 -0800 | [diff] [blame] | 374 | enum ofp_config_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 375 | uint16_t miss_send_len; |
| 376 | }; |
| 377 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 378 | struct of_set_config : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 379 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 380 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 381 | uint16_t length; |
| 382 | uint32_t xid; |
Andreas Wundsam | 057540b | 2013-11-19 16:51:36 -0800 | [diff] [blame] | 383 | enum ofp_config_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 384 | uint16_t miss_send_len; |
| 385 | }; |
| 386 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 387 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 388 | of_port_no_t port_no; |
| 389 | of_mac_addr_t hw_addr; |
| 390 | of_port_name_t name; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 391 | enum ofp_port_config config; |
| 392 | enum ofp_port_state state; |
| 393 | enum ofp_port_features curr; |
| 394 | enum ofp_port_features advertised; |
| 395 | enum ofp_port_features supported; |
| 396 | enum ofp_port_features peer; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 397 | }; |
| 398 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 399 | struct of_features_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 400 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 401 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 402 | uint16_t length; |
| 403 | uint32_t xid; |
| 404 | }; |
| 405 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 406 | struct of_features_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 407 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 408 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 409 | uint16_t length; |
| 410 | uint32_t xid; |
| 411 | uint64_t datapath_id; |
| 412 | uint32_t n_buffers; |
| 413 | uint8_t n_tables; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 414 | pad(3); |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 415 | enum ofp_capabilities capabilities; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 416 | uint32_t actions; |
| 417 | list(of_port_desc_t) ports; |
| 418 | }; |
| 419 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 420 | struct of_port_status : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 421 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 422 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 423 | uint16_t length; |
| 424 | uint32_t xid; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 425 | enum ofp_port_reason reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 426 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 427 | of_port_desc_t desc; |
| 428 | }; |
| 429 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 430 | struct of_port_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 431 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 432 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 433 | uint16_t length; |
| 434 | uint32_t xid; |
| 435 | of_port_no_t port_no; |
| 436 | of_mac_addr_t hw_addr; |
| 437 | uint32_t config; |
| 438 | uint32_t mask; |
| 439 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 440 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 441 | }; |
| 442 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 443 | struct of_packet_in : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 444 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 445 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 446 | uint16_t length; |
| 447 | uint32_t xid; |
| 448 | uint32_t buffer_id; |
| 449 | uint16_t total_len; |
| 450 | of_port_no_t in_port; |
| 451 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 452 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 453 | of_octets_t data; |
| 454 | }; |
| 455 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 456 | struct of_action_output : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 457 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 458 | uint16_t len; |
| 459 | of_port_no_t port; |
| 460 | uint16_t max_len; |
| 461 | }; |
| 462 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 463 | struct of_action_set_vlan_vid : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 464 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 465 | uint16_t len; |
| 466 | uint16_t vlan_vid; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 467 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 468 | }; |
| 469 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 470 | struct of_action_strip_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 471 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 472 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 473 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 474 | }; |
| 475 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 476 | struct of_action_set_vlan_pcp : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 477 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 478 | uint16_t len; |
| 479 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 480 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 481 | }; |
| 482 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 483 | struct of_action_set_dl_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 484 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 485 | uint16_t len; |
| 486 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 487 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 488 | }; |
| 489 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 490 | struct of_action_set_dl_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 491 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 492 | uint16_t len; |
| 493 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 494 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 495 | }; |
| 496 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 497 | struct of_action_set_nw_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 498 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 499 | uint16_t len; |
| 500 | uint32_t nw_addr; |
| 501 | }; |
| 502 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 503 | struct of_action_set_nw_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 504 | uint16_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 505 | uint16_t len; |
| 506 | uint32_t nw_addr; |
| 507 | }; |
| 508 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 509 | struct of_action_set_tp_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 510 | uint16_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 511 | uint16_t len; |
| 512 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 513 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 514 | }; |
| 515 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 516 | struct of_action_set_tp_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 517 | uint16_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 518 | uint16_t len; |
| 519 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 520 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 521 | }; |
| 522 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 523 | struct of_action_set_nw_tos : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 524 | uint16_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 525 | uint16_t len; |
| 526 | uint8_t nw_tos; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 527 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 528 | }; |
| 529 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 530 | struct of_action_experimenter : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 531 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 532 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 533 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 534 | of_octets_t data; |
| 535 | }; |
| 536 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 537 | struct of_action_enqueue : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 538 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 539 | uint16_t len; |
| 540 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 541 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 542 | uint32_t queue_id; |
| 543 | }; |
| 544 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 545 | struct of_action { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 546 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 547 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 548 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 549 | }; |
| 550 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 551 | struct of_packet_out : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 552 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 553 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 554 | uint16_t length; |
| 555 | uint32_t xid; |
| 556 | uint32_t buffer_id; |
| 557 | of_port_no_t in_port; |
| 558 | uint16_t actions_len; |
| 559 | list(of_action_t) actions; |
| 560 | of_octets_t data; |
| 561 | }; |
| 562 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 563 | struct of_match_v1 { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 564 | of_wc_bmap_t wildcards; |
| 565 | of_port_no_t in_port; |
| 566 | of_mac_addr_t eth_src; |
| 567 | of_mac_addr_t eth_dst; |
| 568 | uint16_t vlan_vid; |
| 569 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 570 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 571 | uint16_t eth_type; |
| 572 | uint8_t ip_dscp; |
| 573 | uint8_t ip_proto; |
Rob Sherwood | 53989c8 | 2013-07-03 16:49:50 -0700 | [diff] [blame] | 574 | pad(2); |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 575 | of_ipv4_t ipv4_src; |
| 576 | of_ipv4_t ipv4_dst; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 577 | uint16_t tcp_src; |
| 578 | uint16_t tcp_dst; |
| 579 | }; |
| 580 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 581 | struct of_flow_mod : of_header { |
| 582 | uint8_t version; |
| 583 | uint8_t type == 14; |
| 584 | uint16_t length; |
| 585 | uint32_t xid; |
| 586 | of_match_t match; |
| 587 | uint64_t cookie; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 588 | of_fm_cmd_t _command == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 589 | uint16_t idle_timeout; |
| 590 | uint16_t hard_timeout; |
| 591 | uint16_t priority; |
| 592 | uint32_t buffer_id; |
| 593 | of_port_no_t out_port; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 594 | enum ofp_flow_mod_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 595 | list(of_action_t) actions; |
| 596 | }; |
| 597 | |
| 598 | struct of_flow_add : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 599 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 600 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 601 | uint16_t length; |
| 602 | uint32_t xid; |
| 603 | of_match_t match; |
| 604 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 605 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 606 | uint16_t idle_timeout; |
| 607 | uint16_t hard_timeout; |
| 608 | uint16_t priority; |
| 609 | uint32_t buffer_id; |
| 610 | of_port_no_t out_port; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 611 | enum ofp_flow_mod_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 612 | list(of_action_t) actions; |
| 613 | }; |
| 614 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 615 | struct of_flow_modify : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 616 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 617 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 618 | uint16_t length; |
| 619 | uint32_t xid; |
| 620 | of_match_t match; |
| 621 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 622 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 623 | uint16_t idle_timeout; |
| 624 | uint16_t hard_timeout; |
| 625 | uint16_t priority; |
| 626 | uint32_t buffer_id; |
| 627 | of_port_no_t out_port; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 628 | enum ofp_flow_mod_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 629 | list(of_action_t) actions; |
| 630 | }; |
| 631 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 632 | struct of_flow_modify_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 633 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 634 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 635 | uint16_t length; |
| 636 | uint32_t xid; |
| 637 | of_match_t match; |
| 638 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 639 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 640 | uint16_t idle_timeout; |
| 641 | uint16_t hard_timeout; |
| 642 | uint16_t priority; |
| 643 | uint32_t buffer_id; |
| 644 | of_port_no_t out_port; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 645 | enum ofp_flow_mod_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 646 | list(of_action_t) actions; |
| 647 | }; |
| 648 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 649 | struct of_flow_delete : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 650 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 651 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 652 | uint16_t length; |
| 653 | uint32_t xid; |
| 654 | of_match_t match; |
| 655 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 656 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 657 | uint16_t idle_timeout; |
| 658 | uint16_t hard_timeout; |
| 659 | uint16_t priority; |
| 660 | uint32_t buffer_id; |
| 661 | of_port_no_t out_port; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 662 | enum ofp_flow_mod_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 663 | list(of_action_t) actions; |
| 664 | }; |
| 665 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 666 | struct of_flow_delete_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 667 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 668 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 669 | uint16_t length; |
| 670 | uint32_t xid; |
| 671 | of_match_t match; |
| 672 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 673 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 674 | uint16_t idle_timeout; |
| 675 | uint16_t hard_timeout; |
| 676 | uint16_t priority; |
| 677 | uint32_t buffer_id; |
| 678 | of_port_no_t out_port; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 679 | enum ofp_flow_mod_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 680 | list(of_action_t) actions; |
| 681 | }; |
| 682 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 683 | struct of_flow_removed : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 684 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 685 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 686 | uint16_t length; |
| 687 | uint32_t xid; |
| 688 | of_match_t match; |
| 689 | uint64_t cookie; |
| 690 | uint16_t priority; |
| 691 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 692 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 693 | uint32_t duration_sec; |
| 694 | uint32_t duration_nsec; |
| 695 | uint16_t idle_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 696 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 697 | uint64_t packet_count; |
| 698 | uint64_t byte_count; |
| 699 | }; |
| 700 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 701 | struct of_error_msg : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 702 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 703 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 704 | uint16_t length; |
| 705 | uint32_t xid; |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 706 | uint16_t err_type == ?; |
| 707 | }; |
| 708 | |
| 709 | struct of_hello_failed_error_msg : of_error_msg { |
| 710 | uint8_t version; |
| 711 | uint8_t type == 1; |
| 712 | uint16_t length; |
| 713 | uint32_t xid; |
| 714 | uint16_t err_type == 0; |
| 715 | enum ofp_hello_failed_code code; |
| 716 | of_octets_t data; |
| 717 | }; |
| 718 | |
| 719 | struct of_bad_request_error_msg : of_error_msg { |
| 720 | uint8_t version; |
| 721 | uint8_t type == 1; |
| 722 | uint16_t length; |
| 723 | uint32_t xid; |
| 724 | uint16_t err_type == 1; |
| 725 | enum ofp_bad_request_code code; |
| 726 | of_octets_t data; |
| 727 | }; |
| 728 | |
| 729 | struct of_bad_action_error_msg : of_error_msg { |
| 730 | uint8_t version; |
| 731 | uint8_t type == 1; |
| 732 | uint16_t length; |
| 733 | uint32_t xid; |
| 734 | uint16_t err_type == 2; |
| 735 | enum ofp_bad_action_code code; |
| 736 | of_octets_t data; |
| 737 | }; |
| 738 | |
| 739 | struct of_flow_mod_failed_error_msg : of_error_msg { |
| 740 | uint8_t version; |
| 741 | uint8_t type == 1; |
| 742 | uint16_t length; |
| 743 | uint32_t xid; |
| 744 | uint16_t err_type == 3; |
| 745 | enum ofp_flow_mod_failed_code code; |
| 746 | of_octets_t data; |
| 747 | }; |
| 748 | |
| 749 | struct of_port_mod_failed_error_msg : of_error_msg { |
| 750 | uint8_t version; |
| 751 | uint8_t type == 1; |
| 752 | uint16_t length; |
| 753 | uint32_t xid; |
| 754 | uint16_t err_type == 4; |
| 755 | enum ofp_port_mod_failed_code code; |
| 756 | of_octets_t data; |
| 757 | }; |
| 758 | |
| 759 | struct of_queue_op_failed_error_msg : of_error_msg { |
| 760 | uint8_t version; |
| 761 | uint8_t type == 1; |
| 762 | uint16_t length; |
| 763 | uint32_t xid; |
| 764 | uint16_t err_type == 5; |
| 765 | enum ofp_queue_op_failed_code code; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 766 | of_octets_t data; |
| 767 | }; |
| 768 | |
| 769 | // STATS ENTRIES: flow, table, port, queue, |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 770 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 771 | uint16_t length; |
| 772 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 773 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 774 | of_match_t match; |
| 775 | uint32_t duration_sec; |
| 776 | uint32_t duration_nsec; |
| 777 | uint16_t priority; |
| 778 | uint16_t idle_timeout; |
| 779 | uint16_t hard_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 780 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 781 | uint64_t cookie; |
| 782 | uint64_t packet_count; |
| 783 | uint64_t byte_count; |
| 784 | list(of_action_t) actions; |
| 785 | }; |
| 786 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 787 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 788 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 789 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 790 | of_table_name_t name; |
| 791 | of_wc_bmap_t wildcards; |
| 792 | uint32_t max_entries; |
| 793 | uint32_t active_count; |
| 794 | uint64_t lookup_count; |
| 795 | uint64_t matched_count; |
| 796 | }; |
| 797 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 798 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 799 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 800 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 801 | uint64_t rx_packets; |
| 802 | uint64_t tx_packets; |
| 803 | uint64_t rx_bytes; |
| 804 | uint64_t tx_bytes; |
| 805 | uint64_t rx_dropped; |
| 806 | uint64_t tx_dropped; |
| 807 | uint64_t rx_errors; |
| 808 | uint64_t tx_errors; |
| 809 | uint64_t rx_frame_err; |
| 810 | uint64_t rx_over_err; |
| 811 | uint64_t rx_crc_err; |
| 812 | uint64_t collisions; |
| 813 | }; |
| 814 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 815 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 816 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 817 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 818 | uint32_t queue_id; |
| 819 | uint64_t tx_bytes; |
| 820 | uint64_t tx_packets; |
| 821 | uint64_t tx_errors; |
| 822 | }; |
| 823 | |
| 824 | // STATS request/reply: Desc, flow, agg, table, port, queue |
| 825 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 826 | struct of_stats_request : of_header { |
| 827 | uint8_t version; |
| 828 | uint8_t type == 16; |
| 829 | uint16_t length; |
| 830 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 831 | uint16_t stats_type == ?; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 832 | enum ofp_stats_request_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 833 | }; |
| 834 | |
| 835 | struct of_stats_reply : of_header { |
| 836 | uint8_t version; |
| 837 | uint8_t type == 17; |
| 838 | uint16_t length; |
| 839 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 840 | uint16_t stats_type == ?; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 841 | enum ofp_stats_reply_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 842 | }; |
| 843 | |
| 844 | struct of_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 845 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 846 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 847 | uint16_t length; |
| 848 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 849 | uint16_t stats_type == 0; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 850 | enum ofp_stats_request_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 851 | }; |
| 852 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 853 | struct of_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 854 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 855 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 856 | uint16_t length; |
| 857 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 858 | uint16_t stats_type == 0; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 859 | enum ofp_stats_reply_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 860 | of_desc_str_t mfr_desc; |
| 861 | of_desc_str_t hw_desc; |
| 862 | of_desc_str_t sw_desc; |
| 863 | of_serial_num_t serial_num; |
| 864 | of_desc_str_t dp_desc; |
| 865 | }; |
| 866 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 867 | struct of_flow_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 868 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 869 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 870 | uint16_t length; |
| 871 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 872 | uint16_t stats_type == 1; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 873 | enum ofp_stats_request_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 874 | of_match_t match; |
| 875 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 876 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 877 | of_port_no_t out_port; |
| 878 | }; |
| 879 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 880 | struct of_flow_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 881 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 882 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 883 | uint16_t length; |
| 884 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 885 | uint16_t stats_type == 1; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 886 | enum ofp_stats_reply_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 887 | list(of_flow_stats_entry_t) entries; |
| 888 | }; |
| 889 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 890 | struct of_aggregate_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 891 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 892 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 893 | uint16_t length; |
| 894 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 895 | uint16_t stats_type == 2; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 896 | enum ofp_stats_request_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 897 | of_match_t match; |
| 898 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 899 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 900 | of_port_no_t out_port; |
| 901 | }; |
| 902 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 903 | struct of_aggregate_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 904 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 905 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 906 | uint16_t length; |
| 907 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 908 | uint16_t stats_type == 2; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 909 | enum ofp_stats_reply_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 910 | uint64_t packet_count; |
| 911 | uint64_t byte_count; |
| 912 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 913 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 914 | }; |
| 915 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 916 | struct of_table_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 917 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 918 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 919 | uint16_t length; |
| 920 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 921 | uint16_t stats_type == 3; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 922 | enum ofp_stats_request_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 923 | }; |
| 924 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 925 | struct of_table_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 926 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 927 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 928 | uint16_t length; |
| 929 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 930 | uint16_t stats_type == 3; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 931 | enum ofp_stats_reply_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 932 | list(of_table_stats_entry_t) entries; |
| 933 | }; |
| 934 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 935 | struct of_port_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 936 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 937 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 938 | uint16_t length; |
| 939 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 940 | uint16_t stats_type == 4; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 941 | enum ofp_stats_request_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 942 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 943 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 944 | }; |
| 945 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 946 | struct of_port_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 947 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 948 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 949 | uint16_t length; |
| 950 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 951 | uint16_t stats_type == 4; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 952 | enum ofp_stats_reply_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 953 | list(of_port_stats_entry_t) entries; |
| 954 | }; |
| 955 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 956 | struct of_queue_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 957 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 958 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 959 | uint16_t length; |
| 960 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 961 | uint16_t stats_type == 5; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 962 | enum ofp_stats_request_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 963 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 964 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 965 | uint32_t queue_id; |
| 966 | }; |
| 967 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 968 | struct of_queue_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 969 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 970 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 971 | uint16_t length; |
| 972 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 973 | uint16_t stats_type == 5; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 974 | enum ofp_stats_reply_flags flags; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 975 | list(of_queue_stats_entry_t) entries; |
| 976 | }; |
| 977 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 978 | struct of_experimenter_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 979 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 980 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 981 | uint16_t length; |
| 982 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 983 | uint16_t stats_type == 0xffff; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 984 | enum ofp_stats_request_flags flags; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 985 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 986 | of_octets_t data; |
| 987 | }; |
| 988 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 989 | struct of_experimenter_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 990 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 991 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 992 | uint16_t length; |
| 993 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 994 | uint16_t stats_type == 0xffff; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 995 | enum ofp_stats_reply_flags flags; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 996 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 997 | of_octets_t data; |
| 998 | }; |
| 999 | |
| 1000 | // END OF STATS OBJECTS |
| 1001 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1002 | struct of_queue_prop { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1003 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1004 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1005 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1006 | }; |
| 1007 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1008 | struct of_queue_prop_min_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1009 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1010 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1011 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1012 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1013 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1014 | }; |
| 1015 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1016 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1017 | uint32_t queue_id; |
| 1018 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1019 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1020 | list(of_queue_prop_t) properties; |
| 1021 | }; |
| 1022 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1023 | struct of_queue_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1024 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1025 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1026 | uint16_t length; |
| 1027 | uint32_t xid; |
| 1028 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1029 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1030 | }; |
| 1031 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1032 | struct of_queue_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1033 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1034 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1035 | uint16_t length; |
| 1036 | uint32_t xid; |
| 1037 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1038 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1039 | list(of_packet_queue_t) queues; |
| 1040 | }; |