Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 4 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
Wilson Ng | d72013d | 2013-09-29 10:21:48 -0700 | [diff] [blame] | 38 | OFP_TCP_PORT = 6653, |
| 39 | OFP_SSL_PORT = 6653, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFP_VLAN_NONE = 0, |
| 46 | |
| 47 | OFP_FLOW_PERMANENT = 0, |
| 48 | |
| 49 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 50 | |
| 51 | OFP_NO_BUFFER = 0xffffffff, |
| 52 | |
| 53 | DESC_STR_LEN = 256, |
| 54 | SERIAL_NUM_LEN = 32, |
| 55 | |
| 56 | OFPQ_ALL = 0xffffffff, |
| 57 | OFPQ_MAX_RATE_UNCFG = 0xffff, |
| 58 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 59 | }; |
| 60 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 61 | enum ofp_port(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 62 | OFPP_MAX = 0xffffff00, |
| 63 | OFPP_IN_PORT = 0xfffffff8, |
| 64 | OFPP_TABLE = 0xfffffff9, |
| 65 | OFPP_NORMAL = 0xfffffffa, |
| 66 | OFPP_FLOOD = 0xfffffffb, |
| 67 | OFPP_ALL = 0xfffffffc, |
| 68 | OFPP_CONTROLLER = 0xfffffffd, |
| 69 | OFPP_LOCAL = 0xfffffffe, |
Tomasz | 949aa52 | 2013-10-23 16:12:27 -0700 | [diff] [blame^] | 70 | OFPP_ANY = 0xffffffff, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 71 | }; |
| 72 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 73 | enum ofp_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 74 | OFPT_HELLO = 0, |
| 75 | OFPT_ERROR = 1, |
| 76 | OFPT_ECHO_REQUEST = 2, |
| 77 | OFPT_ECHO_REPLY = 3, |
| 78 | OFPT_EXPERIMENTER = 4, |
| 79 | OFPT_FEATURES_REQUEST = 5, |
| 80 | OFPT_FEATURES_REPLY = 6, |
| 81 | OFPT_GET_CONFIG_REQUEST = 7, |
| 82 | OFPT_GET_CONFIG_REPLY = 8, |
| 83 | OFPT_SET_CONFIG = 9, |
| 84 | OFPT_PACKET_IN = 10, |
| 85 | OFPT_FLOW_REMOVED = 11, |
| 86 | OFPT_PORT_STATUS = 12, |
| 87 | OFPT_PACKET_OUT = 13, |
| 88 | OFPT_FLOW_MOD = 14, |
| 89 | OFPT_GROUP_MOD = 15, |
| 90 | OFPT_PORT_MOD = 16, |
| 91 | OFPT_TABLE_MOD = 17, |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 92 | OFPT_STATS_REQUEST = 18, |
| 93 | OFPT_STATS_REPLY = 19, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 94 | OFPT_BARRIER_REQUEST = 20, |
| 95 | OFPT_BARRIER_REPLY = 21, |
| 96 | OFPT_QUEUE_GET_CONFIG_REQUEST = 22, |
| 97 | OFPT_QUEUE_GET_CONFIG_REPLY = 23, |
| 98 | OFPT_ROLE_REQUEST = 24, |
| 99 | OFPT_ROLE_REPLY = 25, |
| 100 | OFPT_GET_ASYNC_REQUEST = 26, |
| 101 | OFPT_GET_ASYNC_REPLY = 27, |
| 102 | OFPT_SET_ASYNC = 28, |
| 103 | OFPT_METER_MOD = 29, |
| 104 | }; |
| 105 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 106 | enum ofp_config_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 107 | OFPC_FRAG_NORMAL = 0, |
| 108 | OFPC_FRAG_DROP = 1, |
| 109 | OFPC_FRAG_REASM = 2, |
| 110 | OFPC_FRAG_MASK = 3, |
| 111 | }; |
| 112 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 113 | enum ofp_table_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 114 | OFPTC_DEPRECATED_MASK = 0x3, |
| 115 | }; |
| 116 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 117 | enum ofp_table(wire_type=uint8_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 118 | OFPTT_MAX = 0xfe, |
| 119 | OFPTT_ALL = 0xff, |
| 120 | }; |
| 121 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 122 | enum ofp_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 123 | OFPC_FLOW_STATS = 0x1, |
| 124 | OFPC_TABLE_STATS = 0x2, |
| 125 | OFPC_PORT_STATS = 0x4, |
| 126 | OFPC_GROUP_STATS = 0x8, |
| 127 | OFPC_IP_REASM = 0x20, |
| 128 | OFPC_QUEUE_STATS = 0x40, |
| 129 | OFPC_PORT_BLOCKED = 0x100, |
| 130 | }; |
| 131 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 132 | enum ofp_port_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 133 | OFPPC_PORT_DOWN = 0x1, |
| 134 | OFPPC_NO_RECV = 0x4, |
| 135 | OFPPC_NO_FWD = 0x20, |
| 136 | OFPPC_NO_PACKET_IN = 0x40, |
| 137 | }; |
| 138 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 139 | enum ofp_port_state(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 140 | OFPPS_LINK_DOWN = 0x1, |
| 141 | OFPPS_BLOCKED = 0x2, |
| 142 | OFPPS_LIVE = 0x4, |
| 143 | }; |
| 144 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 145 | enum ofp_port_features(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 146 | OFPPF_10MB_HD = 0x1, |
| 147 | OFPPF_10MB_FD = 0x2, |
| 148 | OFPPF_100MB_HD = 0x4, |
| 149 | OFPPF_100MB_FD = 0x8, |
| 150 | OFPPF_1GB_HD = 0x10, |
| 151 | OFPPF_1GB_FD = 0x20, |
| 152 | OFPPF_10GB_FD = 0x40, |
| 153 | OFPPF_40GB_FD = 0x80, |
| 154 | OFPPF_100GB_FD = 0x100, |
| 155 | OFPPF_1TB_FD = 0x200, |
| 156 | OFPPF_OTHER = 0x400, |
| 157 | OFPPF_COPPER = 0x800, |
| 158 | OFPPF_FIBER = 0x1000, |
| 159 | OFPPF_AUTONEG = 0x2000, |
| 160 | OFPPF_PAUSE = 0x4000, |
| 161 | OFPPF_PAUSE_ASYM = 0x8000, |
| 162 | }; |
| 163 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 164 | enum ofp_port_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 165 | OFPPR_ADD = 0, |
| 166 | OFPPR_DELETE = 1, |
| 167 | OFPPR_MODIFY = 2, |
| 168 | }; |
| 169 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 170 | enum ofp_match_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 171 | OFPMT_STANDARD = 0, |
| 172 | OFPMT_OXM = 1, |
| 173 | }; |
| 174 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 175 | enum ofp_oxm_class(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 176 | OFPXMC_NXM_0 = 0, |
| 177 | OFPXMC_NXM_1 = 1, |
| 178 | OFPXMC_OPENFLOW_BASIC = 0x8000, |
| 179 | OFPXMC_EXPERIMENTER = 0xffff, |
| 180 | }; |
| 181 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 182 | enum ofp_vlan_id(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 183 | OFPVID_NONE = 0, |
| 184 | OFPVID_PRESENT = 0x1000, |
| 185 | }; |
| 186 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 187 | // FIXME: OF spec specified this as '9' bits, implicitly adding |
| 188 | // to full byte |
| 189 | enum ofp_ipv6exthdr_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 190 | OFPIEH_NONEXT = 0x1, |
| 191 | OFPIEH_ESP = 0x2, |
| 192 | OFPIEH_AUTH = 0x4, |
| 193 | OFPIEH_DEST = 0x8, |
| 194 | OFPIEH_FRAG = 0x10, |
| 195 | OFPIEH_ROUTER = 0x20, |
| 196 | OFPIEH_HOP = 0x40, |
| 197 | OFPIEH_UNREP = 0x80, |
| 198 | OFPIEH_UNSEQ = 0x100, |
| 199 | }; |
| 200 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 201 | enum ofp_action_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 202 | OFPAT_OUTPUT = 0, |
| 203 | OFPAT_COPY_TTL_OUT = 0xb, |
| 204 | OFPAT_COPY_TTL_IN = 0xc, |
| 205 | OFPAT_SET_MPLS_TTL = 0xf, |
| 206 | OFPAT_DEC_MPLS_TTL = 0x10, |
| 207 | OFPAT_PUSH_VLAN = 0x11, |
| 208 | OFPAT_POP_VLAN = 0x12, |
| 209 | OFPAT_PUSH_MPLS = 0x13, |
| 210 | OFPAT_POP_MPLS = 0x14, |
| 211 | OFPAT_SET_QUEUE = 0x15, |
| 212 | OFPAT_GROUP = 0x16, |
| 213 | OFPAT_SET_NW_TTL = 0x17, |
| 214 | OFPAT_DEC_NW_TTL = 0x18, |
| 215 | OFPAT_SET_FIELD = 0x19, |
| 216 | OFPAT_PUSH_PBB = 0x1a, |
| 217 | OFPAT_POP_PBB = 0x1b, |
| 218 | OFPAT_EXPERIMENTER = 0xffff, |
| 219 | }; |
| 220 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 221 | enum ofp_controller_max_len(wire_type=uint16_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 222 | OFPCML_MAX = 0xffe5, |
| 223 | OFPCML_NO_BUFFER = 0xffff, |
| 224 | }; |
| 225 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 226 | enum ofp_instruction_type(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 227 | OFPIT_GOTO_TABLE = 0x1, |
| 228 | OFPIT_WRITE_METADATA = 0x2, |
| 229 | OFPIT_WRITE_ACTIONS = 0x3, |
| 230 | OFPIT_APPLY_ACTIONS = 0x4, |
| 231 | OFPIT_CLEAR_ACTIONS = 0x5, |
| 232 | OFPIT_METER = 0x6, |
| 233 | OFPIT_EXPERIMENTER = 0xffff, |
| 234 | }; |
| 235 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 236 | enum ofp_flow_mod_command(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 237 | OFPFC_ADD = 0, |
| 238 | OFPFC_MODIFY = 1, |
| 239 | OFPFC_MODIFY_STRICT = 2, |
| 240 | OFPFC_DELETE = 3, |
| 241 | OFPFC_DELETE_STRICT = 4, |
| 242 | }; |
| 243 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 244 | enum ofp_flow_mod_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 245 | OFPFF_SEND_FLOW_REM = 0x1, |
| 246 | OFPFF_CHECK_OVERLAP = 0x2, |
| 247 | OFPFF_RESET_COUNTS = 0x4, |
| 248 | OFPFF_NO_PKT_COUNTS = 0x8, |
| 249 | OFPFF_NO_BYT_COUNTS = 0x10, |
| 250 | }; |
| 251 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 252 | enum ofp_group(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 253 | OFPG_MAX = 0xffffff00, |
| 254 | OFPG_ALL = 0xfffffffc, |
| 255 | OFPG_ANY = 0xffffffff, |
| 256 | }; |
| 257 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 258 | enum ofp_group_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 259 | OFPGC_ADD = 0, |
| 260 | OFPGC_MODIFY = 1, |
| 261 | OFPGC_DELETE = 2, |
| 262 | }; |
| 263 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 264 | enum ofp_group_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 265 | OFPGT_ALL = 0, |
| 266 | OFPGT_SELECT = 1, |
| 267 | OFPGT_INDIRECT = 2, |
| 268 | OFPGT_FF = 3, |
| 269 | }; |
| 270 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 271 | enum ofp_packet_in_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 272 | OFPR_NO_MATCH = 0, |
| 273 | OFPR_ACTION = 1, |
| 274 | OFPR_INVALID_TTL = 2, |
| 275 | }; |
| 276 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 277 | enum ofp_flow_removed_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 278 | OFPRR_IDLE_TIMEOUT = 0, |
| 279 | OFPRR_HARD_TIMEOUT = 1, |
| 280 | OFPRR_DELETE = 2, |
| 281 | OFPRR_GROUP_DELETE = 3, |
| 282 | }; |
| 283 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 284 | enum ofp_meter(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 285 | OFPM_MAX = 0xffff0000, |
| 286 | OFPM_SLOWPATH = 0xfffffffd, |
| 287 | OFPM_CONTROLLER = 0xfffffffe, |
| 288 | OFPM_ALL = 0xffffffff, |
| 289 | }; |
| 290 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 291 | enum ofp_meter_band_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 292 | OFPMBT_DROP = 0x1, |
| 293 | OFPMBT_DSCP_REMARK = 0x2, |
| 294 | OFPMBT_EXPERIMENTER = 0xffff, |
| 295 | }; |
| 296 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 297 | enum ofp_meter_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 298 | OFPMC_ADD = 0, |
| 299 | OFPMC_MODIFY = 1, |
| 300 | OFPMC_DELETE = 2, |
| 301 | }; |
| 302 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 303 | enum ofp_meter_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 304 | OFPMF_KBPS = 0x1, |
| 305 | OFPMF_PKTPS = 0x2, |
| 306 | OFPMF_BURST = 0x4, |
| 307 | OFPMF_STATS = 0x8, |
| 308 | }; |
| 309 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 310 | enum ofp_error_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 311 | OFPET_HELLO_FAILED = 0, |
| 312 | OFPET_BAD_REQUEST = 1, |
| 313 | OFPET_BAD_ACTION = 2, |
| 314 | OFPET_BAD_INSTRUCTION = 3, |
| 315 | OFPET_BAD_MATCH = 4, |
| 316 | OFPET_FLOW_MOD_FAILED = 5, |
| 317 | OFPET_GROUP_MOD_FAILED = 6, |
| 318 | OFPET_PORT_MOD_FAILED = 7, |
| 319 | OFPET_TABLE_MOD_FAILED = 8, |
| 320 | OFPET_QUEUE_OP_FAILED = 9, |
| 321 | OFPET_SWITCH_CONFIG_FAILED = 10, |
| 322 | OFPET_ROLE_REQUEST_FAILED = 11, |
| 323 | OFPET_METER_MOD_FAILED = 12, |
| 324 | OFPET_TABLE_FEATURES_FAILED = 13, |
| 325 | OFPET_EXPERIMENTER = 0xffff, |
| 326 | }; |
| 327 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 328 | enum ofp_hello_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 329 | OFPHFC_INCOMPATIBLE = 0, |
| 330 | OFPHFC_EPERM = 1, |
| 331 | }; |
| 332 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 333 | enum ofp_bad_request_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 334 | OFPBRC_BAD_VERSION = 0, |
| 335 | OFPBRC_BAD_TYPE = 1, |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 336 | OFPBRC_BAD_STAT = 2, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 337 | OFPBRC_BAD_EXPERIMENTER = 3, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 338 | OFPBRC_BAD_EXPERIMENTER_TYPE = 4, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 339 | OFPBRC_EPERM = 5, |
| 340 | OFPBRC_BAD_LEN = 6, |
| 341 | OFPBRC_BUFFER_EMPTY = 7, |
| 342 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 343 | OFPBRC_BAD_TABLE_ID = 9, |
| 344 | OFPBRC_IS_SLAVE = 10, |
| 345 | OFPBRC_BAD_PORT = 11, |
| 346 | OFPBRC_BAD_PACKET = 12, |
| 347 | OFPBRC_MULTIPART_BUFFER_OVERFLOW = 13, |
| 348 | }; |
| 349 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 350 | enum ofp_bad_action_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 351 | OFPBAC_BAD_TYPE = 0, |
| 352 | OFPBAC_BAD_LEN = 1, |
| 353 | OFPBAC_BAD_EXPERIMENTER = 2, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 354 | OFPBAC_BAD_EXPERIMENTER_TYPE = 3, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 355 | OFPBAC_BAD_OUT_PORT = 4, |
| 356 | OFPBAC_BAD_ARGUMENT = 5, |
| 357 | OFPBAC_EPERM = 6, |
| 358 | OFPBAC_TOO_MANY = 7, |
| 359 | OFPBAC_BAD_QUEUE = 8, |
| 360 | OFPBAC_BAD_OUT_GROUP = 9, |
| 361 | OFPBAC_MATCH_INCONSISTENT = 10, |
| 362 | OFPBAC_UNSUPPORTED_ORDER = 11, |
| 363 | OFPBAC_BAD_TAG = 12, |
| 364 | OFPBAC_BAD_SET_TYPE = 13, |
| 365 | OFPBAC_BAD_SET_LEN = 14, |
| 366 | OFPBAC_BAD_SET_ARGUMENT = 15, |
| 367 | }; |
| 368 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 369 | enum ofp_bad_instruction_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 370 | OFPBIC_UNKNOWN_INST = 0, |
| 371 | OFPBIC_UNSUP_INST = 1, |
| 372 | OFPBIC_BAD_TABLE_ID = 2, |
| 373 | OFPBIC_UNSUP_METADATA = 3, |
| 374 | OFPBIC_UNSUP_METADATA_MASK = 4, |
| 375 | OFPBIC_BAD_EXPERIMENTER = 5, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 376 | OFPBIC_BAD_EXPERIMENTER_TYPE = 6, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 377 | OFPBIC_BAD_LEN = 7, |
| 378 | OFPBIC_EPERM = 8, |
| 379 | }; |
| 380 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 381 | enum ofp_bad_match_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 382 | OFPBMC_BAD_TYPE = 0, |
| 383 | OFPBMC_BAD_LEN = 1, |
| 384 | OFPBMC_BAD_TAG = 2, |
| 385 | OFPBMC_BAD_DL_ADDR_MASK = 3, |
| 386 | OFPBMC_BAD_NW_ADDR_MASK = 4, |
| 387 | OFPBMC_BAD_WILDCARDS = 5, |
| 388 | OFPBMC_BAD_FIELD = 6, |
| 389 | OFPBMC_BAD_VALUE = 7, |
| 390 | OFPBMC_BAD_MASK = 8, |
| 391 | OFPBMC_BAD_PREREQ = 9, |
| 392 | OFPBMC_DUP_FIELD = 10, |
| 393 | OFPBMC_EPERM = 11, |
| 394 | }; |
| 395 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 396 | enum ofp_flow_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 397 | OFPFMFC_UNKNOWN = 0, |
| 398 | OFPFMFC_TABLE_FULL = 1, |
| 399 | OFPFMFC_BAD_TABLE_ID = 2, |
| 400 | OFPFMFC_OVERLAP = 3, |
| 401 | OFPFMFC_EPERM = 4, |
| 402 | OFPFMFC_BAD_TIMEOUT = 5, |
| 403 | OFPFMFC_BAD_COMMAND = 6, |
| 404 | OFPFMFC_BAD_FLAGS = 7, |
| 405 | }; |
| 406 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 407 | enum ofp_group_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 408 | OFPGMFC_GROUP_EXISTS = 0, |
| 409 | OFPGMFC_INVALID_GROUP = 1, |
| 410 | OFPGMFC_WEIGHT_UNSUPPORTED = 2, |
| 411 | OFPGMFC_OUT_OF_GROUPS = 3, |
| 412 | OFPGMFC_OUT_OF_BUCKETS = 4, |
| 413 | OFPGMFC_CHAINING_UNSUPPORTED = 5, |
| 414 | OFPGMFC_WATCH_UNSUPPORTED = 6, |
| 415 | OFPGMFC_LOOP = 7, |
| 416 | OFPGMFC_UNKNOWN_GROUP = 8, |
| 417 | OFPGMFC_CHAINED_GROUP = 9, |
| 418 | OFPGMFC_BAD_TYPE = 10, |
| 419 | OFPGMFC_BAD_COMMAND = 11, |
| 420 | OFPGMFC_BAD_BUCKET = 12, |
| 421 | OFPGMFC_BAD_WATCH = 13, |
| 422 | OFPGMFC_EPERM = 14, |
| 423 | }; |
| 424 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 425 | enum ofp_port_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 426 | OFPPMFC_BAD_PORT = 0, |
| 427 | OFPPMFC_BAD_HW_ADDR = 1, |
| 428 | OFPPMFC_BAD_CONFIG = 2, |
| 429 | OFPPMFC_BAD_ADVERTISE = 3, |
| 430 | OFPPMFC_EPERM = 4, |
| 431 | }; |
| 432 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 433 | enum ofp_table_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 434 | OFPTMFC_BAD_TABLE = 0, |
| 435 | OFPTMFC_BAD_CONFIG = 1, |
| 436 | OFPTMFC_EPERM = 2, |
| 437 | }; |
| 438 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 439 | enum ofp_queue_op_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 440 | OFPQOFC_BAD_PORT = 0, |
| 441 | OFPQOFC_BAD_QUEUE = 1, |
| 442 | OFPQOFC_EPERM = 2, |
| 443 | }; |
| 444 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 445 | enum ofp_switch_config_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 446 | OFPSCFC_BAD_FLAGS = 0, |
| 447 | OFPSCFC_BAD_LEN = 1, |
| 448 | OFPSCFC_EPERM = 2, |
| 449 | }; |
| 450 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 451 | enum ofp_role_request_failed_code(wire_type=uint16_t){ |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 452 | OFPRRFC_STALE = 0, |
| 453 | OFPRRFC_UNSUP = 1, |
| 454 | OFPRRFC_BAD_ROLE = 2, |
| 455 | }; |
| 456 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 457 | enum ofp_meter_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 458 | OFPMMFC_UNKNOWN = 0, |
| 459 | OFPMMFC_METER_EXISTS = 1, |
| 460 | OFPMMFC_INVALID_METER = 2, |
| 461 | OFPMMFC_UNKNOWN_METER = 3, |
| 462 | OFPMMFC_BAD_COMMAND = 4, |
| 463 | OFPMMFC_BAD_FLAGS = 5, |
| 464 | OFPMMFC_BAD_RATE = 6, |
| 465 | OFPMMFC_BAD_BURST = 7, |
| 466 | OFPMMFC_BAD_BAND = 8, |
| 467 | OFPMMFC_BAD_BAND_VALUE = 9, |
| 468 | OFPMMFC_OUT_OF_METERS = 10, |
| 469 | OFPMMFC_OUT_OF_BANDS = 11, |
| 470 | }; |
| 471 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 472 | enum ofp_table_features_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 473 | OFPTFFC_BAD_TABLE = 0, |
| 474 | OFPTFFC_BAD_METADATA = 1, |
| 475 | OFPTFFC_BAD_TYPE = 2, |
| 476 | OFPTFFC_BAD_LEN = 3, |
| 477 | OFPTFFC_BAD_ARGUMENT = 4, |
| 478 | OFPTFFC_EPERM = 5, |
| 479 | }; |
| 480 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 481 | enum ofp_stats_type(wire_type=uint16_t) { |
| 482 | OFPST_DESC = 0, |
| 483 | OFPST_FLOW = 1, |
| 484 | OFPST_AGGREGATE = 2, |
| 485 | OFPST_TABLE = 3, |
| 486 | OFPST_PORT = 4, |
| 487 | OFPST_QUEUE = 5, |
| 488 | OFPST_GROUP = 6, |
| 489 | OFPST_GROUP_DESC = 7, |
| 490 | OFPST_GROUP_FEATURES = 8, |
| 491 | OFPST_METER = 9, |
| 492 | OFPST_METER_CONFIG = 10, |
| 493 | OFPST_METER_FEATURES = 11, |
| 494 | OFPST_TABLE_FEATURES = 12, |
| 495 | OFPST_PORT_DESC = 13, |
| 496 | OFPST_EXPERIMENTER = 0xffff, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 497 | }; |
| 498 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 499 | enum ofp_stats_request_flags(wire_type=uint16_t, bitmask=True) { |
| 500 | OFPSF_REQ_MORE = 0x1, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 501 | }; |
| 502 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 503 | enum ofp_stats_reply_flags(wire_type=uint16_t, bitmask=True) { |
| 504 | OFPSF_REPLY_MORE = 0x1, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 505 | }; |
| 506 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 507 | enum ofp_table_feature_prop_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 508 | OFPTFPT_INSTRUCTIONS = 0, |
| 509 | OFPTFPT_INSTRUCTIONS_MISS = 1, |
| 510 | OFPTFPT_NEXT_TABLES = 2, |
| 511 | OFPTFPT_NEXT_TABLES_MISS = 3, |
| 512 | OFPTFPT_WRITE_ACTIONS = 4, |
| 513 | OFPTFPT_WRITE_ACTIONS_MISS = 5, |
| 514 | OFPTFPT_APPLY_ACTIONS = 6, |
| 515 | OFPTFPT_APPLY_ACTIONS_MISS = 7, |
| 516 | OFPTFPT_MATCH = 8, |
| 517 | OFPTFPT_WILDCARDS = 0xa, |
| 518 | OFPTFPT_WRITE_SETFIELD = 0xc, |
| 519 | OFPTFPT_WRITE_SETFIELD_MISS = 0xd, |
| 520 | OFPTFPT_APPLY_SETFIELD = 0xe, |
| 521 | OFPTFPT_APPLY_SETFIELD_MISS = 0xf, |
| 522 | OFPTFPT_EXPERIMENTER = 0xfffe, |
| 523 | OFPTFPT_EXPERIMENTER_MISS = 0xffff, |
| 524 | }; |
| 525 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 526 | enum ofp_group_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 527 | OFPGFC_SELECT_WEIGHT = 0x1, |
| 528 | OFPGFC_SELECT_LIVENESS = 0x2, |
| 529 | OFPGFC_CHAINING = 0x4, |
| 530 | OFPGFC_CHAINING_CHECKS = 0x8, |
| 531 | }; |
| 532 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 533 | enum ofp_queue_properties(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 534 | OFPQT_MIN_RATE = 0x1, |
| 535 | OFPQT_MAX_RATE = 0x2, |
| 536 | OFPQT_EXPERIMENTER = 0xffff, |
| 537 | }; |
| 538 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 539 | enum ofp_controller_role(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 540 | OFPCR_ROLE_NOCHANGE = 0, |
| 541 | OFPCR_ROLE_EQUAL = 1, |
| 542 | OFPCR_ROLE_MASTER = 2, |
| 543 | OFPCR_ROLE_SLAVE = 3, |
| 544 | }; |
| 545 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 546 | enum ofp_hello_elem_type(wire_type=uint16_t) { |
Rich Lane | 0733cd6 | 2013-04-18 21:14:42 -0700 | [diff] [blame] | 547 | OFPHET_VERSIONBITMAP = 1, |
| 548 | }; |
| 549 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 550 | /* XXX rename to of_message */ |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 551 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 552 | uint8_t version; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 553 | uint8_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 554 | uint16_t length; |
| 555 | uint32_t xid; |
| 556 | }; |
| 557 | |
| 558 | // Special structures used for managing scalar list elements |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 559 | struct of_uint32 { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 560 | uint32_t value; |
| 561 | }; |
| 562 | |
| 563 | // Special structures used for managing scalar list elements |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 564 | struct of_uint8 { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 565 | uint8_t value; |
| 566 | }; |
| 567 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 568 | struct of_hello_elem { |
Andreas Wundsam | 70411bf | 2013-08-02 22:26:38 -0700 | [diff] [blame] | 569 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 570 | uint16_t length; |
| 571 | }; |
| 572 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 573 | struct of_hello_elem_versionbitmap : of_hello_elem { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 574 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 575 | uint16_t length; |
| 576 | list(of_uint32_t) bitmaps; |
| 577 | }; |
| 578 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 579 | struct of_hello : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 580 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 581 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 582 | uint16_t length; |
| 583 | uint32_t xid; |
| 584 | list(of_hello_elem_t) elements; |
| 585 | }; |
| 586 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 587 | struct of_echo_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 588 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 589 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 590 | uint16_t length; |
| 591 | uint32_t xid; |
| 592 | of_octets_t data; |
| 593 | }; |
| 594 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 595 | struct of_echo_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 596 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 597 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 598 | uint16_t length; |
| 599 | uint32_t xid; |
| 600 | of_octets_t data; |
| 601 | }; |
| 602 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 603 | struct of_experimenter : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 604 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 605 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 606 | uint16_t length; |
| 607 | uint32_t xid; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 608 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 609 | uint32_t subtype; |
| 610 | of_octets_t data; |
| 611 | }; |
| 612 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 613 | struct of_barrier_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 614 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 615 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 616 | uint16_t length; |
| 617 | uint32_t xid; |
| 618 | }; |
| 619 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 620 | struct of_barrier_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 621 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 622 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 623 | uint16_t length; |
| 624 | uint32_t xid; |
| 625 | }; |
| 626 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 627 | struct of_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 628 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 629 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 630 | uint16_t length; |
| 631 | uint32_t xid; |
| 632 | }; |
| 633 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 634 | struct of_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 635 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 636 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 637 | uint16_t length; |
| 638 | uint32_t xid; |
| 639 | uint16_t flags; |
| 640 | uint16_t miss_send_len; |
| 641 | }; |
| 642 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 643 | struct of_set_config : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 644 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 645 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 646 | uint16_t length; |
| 647 | uint32_t xid; |
| 648 | uint16_t flags; |
| 649 | uint16_t miss_send_len; |
| 650 | }; |
| 651 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 652 | struct of_table_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 653 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 654 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 655 | uint16_t length; |
| 656 | uint32_t xid; |
| 657 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 658 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 659 | uint32_t config; |
| 660 | }; |
| 661 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 662 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 663 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 664 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 665 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 666 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 667 | of_port_name_t name; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 668 | enum ofp_port_config config; |
| 669 | enum ofp_port_state state; |
| 670 | enum ofp_port_features curr; |
| 671 | enum ofp_port_features advertised; |
| 672 | enum ofp_port_features supported; |
| 673 | enum ofp_port_features peer; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 674 | uint32_t curr_speed; |
| 675 | uint32_t max_speed; |
| 676 | }; |
| 677 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 678 | struct of_features_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 679 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 680 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 681 | uint16_t length; |
| 682 | uint32_t xid; |
| 683 | }; |
| 684 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 685 | struct of_features_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 686 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 687 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 688 | uint16_t length; |
| 689 | uint32_t xid; |
| 690 | uint64_t datapath_id; |
| 691 | uint32_t n_buffers; |
| 692 | uint8_t n_tables; |
| 693 | uint8_t auxiliary_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 694 | pad(2); |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 695 | enum ofp_capabilities capabilities; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 696 | uint32_t reserved; |
| 697 | }; |
| 698 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 699 | struct of_port_status : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 700 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 701 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 702 | uint16_t length; |
| 703 | uint32_t xid; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 704 | enum ofp_port_reason reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 705 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 706 | of_port_desc_t desc; |
| 707 | }; |
| 708 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 709 | struct of_port_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 710 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 711 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 712 | uint16_t length; |
| 713 | uint32_t xid; |
| 714 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 715 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 716 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 717 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 718 | uint32_t config; |
| 719 | uint32_t mask; |
| 720 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 721 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 722 | }; |
| 723 | |
| 724 | // FIXME Does this need to be v4? |
Andreas Wundsam | fef7d5f | 2013-08-01 22:15:44 -0700 | [diff] [blame] | 725 | struct of_match_v3(align=8) { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 726 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 727 | uint16_t length; |
| 728 | list(of_oxm_t) oxm_list; |
| 729 | }; |
| 730 | |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 731 | // This looks like an action header, but is standalone. See |
| 732 | // ofp_table_features_prop_actions |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 733 | struct of_action_id { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 734 | uint16_t type; |
| 735 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 736 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 737 | }; |
| 738 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 739 | struct of_action_output : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 740 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 741 | uint16_t len; |
| 742 | of_port_no_t port; |
| 743 | uint16_t max_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 744 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 745 | }; |
| 746 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 747 | struct of_action_copy_ttl_out : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 748 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 749 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 750 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 751 | }; |
| 752 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 753 | struct of_action_copy_ttl_in : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 754 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 755 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 756 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 757 | }; |
| 758 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 759 | struct of_action_set_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 760 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 761 | uint16_t len; |
| 762 | uint8_t mpls_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 763 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 764 | }; |
| 765 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 766 | struct of_action_dec_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 767 | uint16_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 768 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 769 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 770 | }; |
| 771 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 772 | struct of_action_push_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 773 | uint16_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 774 | uint16_t len; |
| 775 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 776 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 777 | }; |
| 778 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 779 | struct of_action_pop_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 780 | uint16_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 781 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 782 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 783 | }; |
| 784 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 785 | struct of_action_push_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 786 | uint16_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 787 | uint16_t len; |
| 788 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 789 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 790 | }; |
| 791 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 792 | struct of_action_pop_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 793 | uint16_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 794 | uint16_t len; |
| 795 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 796 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 797 | }; |
| 798 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 799 | struct of_action_set_queue : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 800 | uint16_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 801 | uint16_t len; |
| 802 | uint32_t queue_id; |
| 803 | }; |
| 804 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 805 | struct of_action_group : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 806 | uint16_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 807 | uint16_t len; |
| 808 | uint32_t group_id; |
| 809 | }; |
| 810 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 811 | struct of_action_set_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 812 | uint16_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 813 | uint16_t len; |
| 814 | uint8_t nw_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 815 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 816 | }; |
| 817 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 818 | struct of_action_dec_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 819 | uint16_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 820 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 821 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 822 | }; |
| 823 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 824 | struct of_action_set_field : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 825 | uint16_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 826 | uint16_t len; |
Rich Lane | be90eae | 2013-07-22 16:44:26 -0700 | [diff] [blame] | 827 | of_oxm_t field; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 828 | }; |
| 829 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 830 | struct of_action_experimenter : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 831 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 832 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 833 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 834 | of_octets_t data; |
| 835 | }; |
| 836 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 837 | struct of_action_pop_pbb : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 838 | uint16_t type == 27; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 839 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 840 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 841 | }; |
| 842 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 843 | struct of_action_push_pbb : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 844 | uint16_t type == 26; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 845 | uint16_t len; |
| 846 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 847 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 848 | }; |
| 849 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 850 | struct of_action { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 851 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 852 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 853 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 854 | }; |
| 855 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 856 | struct of_instruction { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 857 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 858 | uint16_t len; |
| 859 | }; |
| 860 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 861 | struct of_instruction_goto_table : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 862 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 863 | uint16_t len; |
| 864 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 865 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 866 | }; |
| 867 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 868 | struct of_instruction_write_metadata : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 869 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 870 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 871 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 872 | uint64_t metadata; |
| 873 | uint64_t metadata_mask; |
| 874 | }; |
| 875 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 876 | struct of_instruction_write_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 877 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 878 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 879 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 880 | list(of_action_t) actions; |
| 881 | }; |
| 882 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 883 | struct of_instruction_apply_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 884 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 885 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 886 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 887 | list(of_action_t) actions; |
| 888 | }; |
| 889 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 890 | struct of_instruction_clear_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 891 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 892 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 893 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 894 | }; |
| 895 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 896 | struct of_instruction_meter : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 897 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 898 | uint16_t len; |
| 899 | uint32_t meter_id; |
| 900 | }; |
| 901 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 902 | struct of_instruction_experimenter : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 903 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 904 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 905 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 906 | of_octets_t data; |
| 907 | }; |
| 908 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 909 | struct of_flow_mod : of_header { |
| 910 | uint8_t version; |
| 911 | uint8_t type == 14; |
| 912 | uint16_t length; |
| 913 | uint32_t xid; |
| 914 | uint64_t cookie; |
| 915 | uint64_t cookie_mask; |
| 916 | uint8_t table_id; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 917 | of_fm_cmd_t _command == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 918 | uint16_t idle_timeout; |
| 919 | uint16_t hard_timeout; |
| 920 | uint16_t priority; |
| 921 | uint32_t buffer_id; |
| 922 | of_port_no_t out_port; |
| 923 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 924 | enum ofp_flow_mod_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 925 | pad(2); |
| 926 | of_match_t match; |
| 927 | list(of_instruction_t) instructions; |
| 928 | }; |
| 929 | |
| 930 | struct of_flow_add : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 931 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 932 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 933 | uint16_t length; |
| 934 | uint32_t xid; |
| 935 | uint64_t cookie; |
| 936 | uint64_t cookie_mask; |
| 937 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 938 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 939 | uint16_t idle_timeout; |
| 940 | uint16_t hard_timeout; |
| 941 | uint16_t priority; |
| 942 | uint32_t buffer_id; |
| 943 | of_port_no_t out_port; |
| 944 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 945 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 946 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 947 | of_match_t match; |
| 948 | list(of_instruction_t) instructions; |
| 949 | }; |
| 950 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 951 | struct of_flow_modify : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 952 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 953 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 954 | uint16_t length; |
| 955 | uint32_t xid; |
| 956 | uint64_t cookie; |
| 957 | uint64_t cookie_mask; |
| 958 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 959 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 960 | uint16_t idle_timeout; |
| 961 | uint16_t hard_timeout; |
| 962 | uint16_t priority; |
| 963 | uint32_t buffer_id; |
| 964 | of_port_no_t out_port; |
| 965 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 966 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 967 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 968 | of_match_t match; |
| 969 | list(of_instruction_t) instructions; |
| 970 | }; |
| 971 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 972 | struct of_flow_modify_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 973 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 974 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 975 | uint16_t length; |
| 976 | uint32_t xid; |
| 977 | uint64_t cookie; |
| 978 | uint64_t cookie_mask; |
| 979 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 980 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 981 | uint16_t idle_timeout; |
| 982 | uint16_t hard_timeout; |
| 983 | uint16_t priority; |
| 984 | uint32_t buffer_id; |
| 985 | of_port_no_t out_port; |
| 986 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 987 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 988 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 989 | of_match_t match; |
| 990 | list(of_instruction_t) instructions; |
| 991 | }; |
| 992 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 993 | struct of_flow_delete : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 994 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 995 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 996 | uint16_t length; |
| 997 | uint32_t xid; |
| 998 | uint64_t cookie; |
| 999 | uint64_t cookie_mask; |
| 1000 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1001 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1002 | uint16_t idle_timeout; |
| 1003 | uint16_t hard_timeout; |
| 1004 | uint16_t priority; |
| 1005 | uint32_t buffer_id; |
| 1006 | of_port_no_t out_port; |
| 1007 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 1008 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1009 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1010 | of_match_t match; |
| 1011 | list(of_instruction_t) instructions; |
| 1012 | }; |
| 1013 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1014 | struct of_flow_delete_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1015 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1016 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1017 | uint16_t length; |
| 1018 | uint32_t xid; |
| 1019 | uint64_t cookie; |
| 1020 | uint64_t cookie_mask; |
| 1021 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1022 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1023 | uint16_t idle_timeout; |
| 1024 | uint16_t hard_timeout; |
| 1025 | uint16_t priority; |
| 1026 | uint32_t buffer_id; |
| 1027 | of_port_no_t out_port; |
| 1028 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 1029 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1030 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1031 | of_match_t match; |
| 1032 | list(of_instruction_t) instructions; |
| 1033 | }; |
| 1034 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1035 | struct of_bucket { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1036 | uint16_t len; |
| 1037 | uint16_t weight; |
| 1038 | of_port_no_t watch_port; |
| 1039 | uint32_t watch_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1040 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1041 | list(of_action_t) actions; |
| 1042 | }; |
| 1043 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1044 | struct of_group_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1045 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1046 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1047 | uint16_t length; |
| 1048 | uint32_t xid; |
| 1049 | uint16_t command; |
| 1050 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1051 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1052 | uint32_t group_id; |
| 1053 | list(of_bucket_t) buckets; |
| 1054 | }; |
| 1055 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1056 | struct of_packet_out : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1057 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1058 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1059 | uint16_t length; |
| 1060 | uint32_t xid; |
| 1061 | uint32_t buffer_id; |
| 1062 | of_port_no_t in_port; |
| 1063 | uint16_t actions_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1064 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1065 | list(of_action_t) actions; |
| 1066 | of_octets_t data; |
| 1067 | }; |
| 1068 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1069 | struct of_packet_in : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1070 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1071 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1072 | uint16_t length; |
| 1073 | uint32_t xid; |
| 1074 | uint32_t buffer_id; |
| 1075 | uint16_t total_len; |
| 1076 | uint8_t reason; |
| 1077 | uint8_t table_id; |
| 1078 | uint64_t cookie; |
| 1079 | of_match_t match; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1080 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1081 | of_octets_t data; /* FIXME: Ensure total_len gets updated */ |
| 1082 | }; |
| 1083 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1084 | struct of_flow_removed : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1085 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1086 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1087 | uint16_t length; |
| 1088 | uint32_t xid; |
| 1089 | uint64_t cookie; |
| 1090 | uint16_t priority; |
| 1091 | uint8_t reason; |
| 1092 | uint8_t table_id; |
| 1093 | uint32_t duration_sec; |
| 1094 | uint32_t duration_nsec; |
| 1095 | uint16_t idle_timeout; |
| 1096 | uint16_t hard_timeout; |
| 1097 | uint64_t packet_count; |
| 1098 | uint64_t byte_count; |
| 1099 | of_match_t match; |
| 1100 | }; |
| 1101 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1102 | struct of_meter_band { |
Andreas Wundsam | 9ba6536 | 2013-08-02 19:14:42 -0700 | [diff] [blame] | 1103 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1104 | uint16_t len; |
| 1105 | // uint32_t rate; // These are excluded b/c this is the header |
| 1106 | // uint32_t burst_size; // These are excluded b/c this is the header |
| 1107 | }; |
| 1108 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1109 | struct of_meter_band_drop : of_meter_band { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1110 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1111 | uint16_t len; |
| 1112 | uint32_t rate; |
| 1113 | uint32_t burst_size; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1114 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1115 | }; |
| 1116 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1117 | struct of_meter_band_dscp_remark : of_meter_band { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1118 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1119 | uint16_t len; |
| 1120 | uint32_t rate; |
| 1121 | uint32_t burst_size; |
| 1122 | uint8_t prec_level; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1123 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1124 | }; |
| 1125 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1126 | struct of_meter_band_experimenter : of_meter_band { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1127 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1128 | uint16_t len; |
| 1129 | uint32_t rate; |
| 1130 | uint32_t burst_size; |
| 1131 | uint32_t experimenter; |
| 1132 | }; |
| 1133 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1134 | struct of_meter_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1135 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1136 | uint8_t type == 29; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1137 | uint16_t length; |
| 1138 | uint32_t xid; |
| 1139 | uint16_t command; |
| 1140 | uint16_t flags; |
| 1141 | uint32_t meter_id; |
| 1142 | list(of_meter_band_t) meters; |
| 1143 | }; |
| 1144 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1145 | struct of_error_msg : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1146 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1147 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1148 | uint16_t length; |
| 1149 | uint32_t xid; |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 1150 | uint16_t err_type == ?; |
| 1151 | }; |
| 1152 | |
| 1153 | struct of_hello_failed_error_msg : of_error_msg { |
| 1154 | uint8_t version; |
| 1155 | uint8_t type == 1; |
| 1156 | uint16_t length; |
| 1157 | uint32_t xid; |
| 1158 | uint16_t err_type == 0; |
| 1159 | enum ofp_hello_failed_code code; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1160 | of_octets_t data; |
| 1161 | }; |
| 1162 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 1163 | struct of_bad_request_error_msg : of_error_msg { |
| 1164 | uint8_t version; |
| 1165 | uint8_t type == 1; |
| 1166 | uint16_t length; |
| 1167 | uint32_t xid; |
| 1168 | uint16_t err_type == 1; |
| 1169 | enum ofp_bad_request_code code; |
| 1170 | of_octets_t data; |
| 1171 | }; |
| 1172 | |
| 1173 | struct of_bad_action_error_msg : of_error_msg { |
| 1174 | uint8_t version; |
| 1175 | uint8_t type == 1; |
| 1176 | uint16_t length; |
| 1177 | uint32_t xid; |
| 1178 | uint16_t err_type == 2; |
| 1179 | enum ofp_bad_action_code code; |
| 1180 | of_octets_t data; |
| 1181 | }; |
| 1182 | |
| 1183 | struct of_bad_instruction_error_msg : of_error_msg { |
| 1184 | uint8_t version; |
| 1185 | uint8_t type == 1; |
| 1186 | uint16_t length; |
| 1187 | uint32_t xid; |
| 1188 | uint16_t err_type == 3; |
| 1189 | enum ofp_bad_instruction_code code; |
| 1190 | of_octets_t data; |
| 1191 | }; |
| 1192 | |
| 1193 | struct of_bad_match_error_msg : of_error_msg { |
| 1194 | uint8_t version; |
| 1195 | uint8_t type == 1; |
| 1196 | uint16_t length; |
| 1197 | uint32_t xid; |
| 1198 | uint16_t err_type == 4; |
| 1199 | enum ofp_bad_match_code code; |
| 1200 | of_octets_t data; |
| 1201 | }; |
| 1202 | |
| 1203 | struct of_flow_mod_failed_error_msg : of_error_msg { |
| 1204 | uint8_t version; |
| 1205 | uint8_t type == 1; |
| 1206 | uint16_t length; |
| 1207 | uint32_t xid; |
| 1208 | uint16_t err_type == 5; |
| 1209 | enum ofp_flow_mod_failed_code code; |
| 1210 | of_octets_t data; |
| 1211 | }; |
| 1212 | |
| 1213 | struct of_group_mod_failed_error_msg : of_error_msg { |
| 1214 | uint8_t version; |
| 1215 | uint8_t type == 1; |
| 1216 | uint16_t length; |
| 1217 | uint32_t xid; |
| 1218 | uint16_t err_type == 6; |
| 1219 | enum ofp_group_mod_failed_code code; |
| 1220 | of_octets_t data; |
| 1221 | }; |
| 1222 | |
| 1223 | struct of_port_mod_failed_error_msg : of_error_msg { |
| 1224 | uint8_t version; |
| 1225 | uint8_t type == 1; |
| 1226 | uint16_t length; |
| 1227 | uint32_t xid; |
| 1228 | uint16_t err_type == 7; |
| 1229 | enum ofp_port_mod_failed_code code; |
| 1230 | of_octets_t data; |
| 1231 | }; |
| 1232 | |
| 1233 | struct of_table_mod_failed_error_msg : of_error_msg { |
| 1234 | uint8_t version; |
| 1235 | uint8_t type == 1; |
| 1236 | uint16_t length; |
| 1237 | uint32_t xid; |
| 1238 | uint16_t err_type == 8; |
| 1239 | enum ofp_table_mod_failed_code code; |
| 1240 | of_octets_t data; |
| 1241 | }; |
| 1242 | |
| 1243 | struct of_queue_op_failed_error_msg : of_error_msg { |
| 1244 | uint8_t version; |
| 1245 | uint8_t type == 1; |
| 1246 | uint16_t length; |
| 1247 | uint32_t xid; |
| 1248 | uint16_t err_type == 9; |
| 1249 | enum ofp_queue_op_failed_code code; |
| 1250 | of_octets_t data; |
| 1251 | }; |
| 1252 | |
| 1253 | struct of_switch_config_failed_error_msg : of_error_msg { |
| 1254 | uint8_t version; |
| 1255 | uint8_t type == 1; |
| 1256 | uint16_t length; |
| 1257 | uint32_t xid; |
| 1258 | uint16_t err_type == 10; |
| 1259 | enum ofp_switch_config_failed_code code; |
| 1260 | of_octets_t data; |
| 1261 | }; |
| 1262 | |
| 1263 | struct of_role_request_failed_error_msg : of_error_msg { |
| 1264 | uint8_t version; |
| 1265 | uint8_t type == 1; |
| 1266 | uint16_t length; |
| 1267 | uint32_t xid; |
| 1268 | uint16_t err_type == 11; |
| 1269 | enum ofp_role_request_failed_code code; |
| 1270 | of_octets_t data; |
| 1271 | }; |
| 1272 | |
| 1273 | struct of_meter_mod_failed_error_msg : of_error_msg { |
| 1274 | uint8_t version; |
| 1275 | uint8_t type == 1; |
| 1276 | uint16_t length; |
| 1277 | uint32_t xid; |
| 1278 | uint16_t err_type == 12; |
| 1279 | enum ofp_meter_mod_failed_code code; |
| 1280 | of_octets_t data; |
| 1281 | }; |
| 1282 | |
| 1283 | struct of_table_features_failed_error_msg : of_error_msg { |
| 1284 | uint8_t version; |
| 1285 | uint8_t type == 1; |
| 1286 | uint16_t length; |
| 1287 | uint32_t xid; |
| 1288 | uint16_t err_type == 13; |
| 1289 | enum ofp_table_features_failed_code code; |
| 1290 | of_octets_t data; |
| 1291 | }; |
| 1292 | |
| 1293 | struct of_experimenter_error_msg { |
| 1294 | uint8_t version; |
| 1295 | uint8_t type == 1; |
| 1296 | uint16_t length; |
| 1297 | uint32_t xid; |
| 1298 | uint16_t err_type == 0xffff; |
| 1299 | uint16_t subtype; |
| 1300 | uint32_t experimenter; |
| 1301 | of_octets_t data; |
| 1302 | }; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1303 | |
| 1304 | // STATS ENTRIES: flow, table, port, queue, group stats, group desc stats |
| 1305 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1306 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1307 | uint16_t length; |
| 1308 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1309 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1310 | uint32_t duration_sec; |
| 1311 | uint32_t duration_nsec; |
| 1312 | uint16_t priority; |
| 1313 | uint16_t idle_timeout; |
| 1314 | uint16_t hard_timeout; |
Rich Lane | 1a47c1c | 2013-08-28 15:27:00 -0700 | [diff] [blame] | 1315 | uint16_t flags; |
| 1316 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1317 | uint64_t cookie; |
| 1318 | uint64_t packet_count; |
| 1319 | uint64_t byte_count; |
| 1320 | of_match_t match; |
| 1321 | list(of_instruction_t) instructions; |
| 1322 | }; |
| 1323 | |
| 1324 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1325 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1326 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1327 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1328 | uint32_t active_count; |
| 1329 | uint64_t lookup_count; |
| 1330 | uint64_t matched_count; |
| 1331 | }; |
| 1332 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1333 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1334 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1335 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1336 | uint64_t rx_packets; |
| 1337 | uint64_t tx_packets; |
| 1338 | uint64_t rx_bytes; |
| 1339 | uint64_t tx_bytes; |
| 1340 | uint64_t rx_dropped; |
| 1341 | uint64_t tx_dropped; |
| 1342 | uint64_t rx_errors; |
| 1343 | uint64_t tx_errors; |
| 1344 | uint64_t rx_frame_err; |
| 1345 | uint64_t rx_over_err; |
| 1346 | uint64_t rx_crc_err; |
| 1347 | uint64_t collisions; |
| 1348 | uint32_t duration_sec; |
| 1349 | uint32_t duration_nsec; |
| 1350 | }; |
| 1351 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1352 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1353 | of_port_no_t port_no; |
| 1354 | uint32_t queue_id; |
| 1355 | uint64_t tx_bytes; |
| 1356 | uint64_t tx_packets; |
| 1357 | uint64_t tx_errors; |
| 1358 | uint32_t duration_sec; |
| 1359 | uint32_t duration_nsec; |
| 1360 | }; |
| 1361 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1362 | struct of_bucket_counter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1363 | uint64_t packet_count; |
| 1364 | uint64_t byte_count; |
| 1365 | }; |
| 1366 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1367 | struct of_group_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1368 | uint16_t length; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1369 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1370 | uint32_t group_id; |
| 1371 | uint32_t ref_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1372 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1373 | uint64_t packet_count; |
| 1374 | uint64_t byte_count; |
| 1375 | uint32_t duration_sec; |
| 1376 | uint32_t duration_nsec; |
| 1377 | list(of_bucket_counter_t) bucket_stats; |
| 1378 | }; |
| 1379 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1380 | struct of_group_desc_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1381 | uint16_t length; |
Rich Lane | 35e7ac7 | 2013-10-15 10:36:10 -0700 | [diff] [blame] | 1382 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1383 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1384 | uint32_t group_id; |
| 1385 | list(of_bucket_t) buckets; |
| 1386 | }; |
| 1387 | |
| 1388 | // STATS: |
| 1389 | // Desc, flow, agg, table, port, queue, group, group_desc, group_feat, experi |
| 1390 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1391 | struct of_stats_request : of_header { |
| 1392 | uint8_t version; |
| 1393 | uint8_t type == 18; |
| 1394 | uint16_t length; |
| 1395 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1396 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1397 | uint16_t flags; |
| 1398 | pad(4); |
| 1399 | }; |
| 1400 | |
| 1401 | struct of_stats_reply : of_header { |
| 1402 | uint8_t version; |
| 1403 | uint8_t type == 19; |
| 1404 | uint16_t length; |
| 1405 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1406 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1407 | uint16_t flags; |
| 1408 | pad(4); |
| 1409 | }; |
| 1410 | |
| 1411 | struct of_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1412 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1413 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1414 | uint16_t length; |
| 1415 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1416 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1417 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1418 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1419 | }; |
| 1420 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1421 | struct of_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1422 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1423 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1424 | uint16_t length; |
| 1425 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1426 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1427 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1428 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1429 | of_desc_str_t mfr_desc; |
| 1430 | of_desc_str_t hw_desc; |
| 1431 | of_desc_str_t sw_desc; |
| 1432 | of_serial_num_t serial_num; |
| 1433 | of_desc_str_t dp_desc; |
| 1434 | }; |
| 1435 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1436 | struct of_flow_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1437 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1438 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1439 | uint16_t length; |
| 1440 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1441 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1442 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1443 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1444 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1445 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1446 | of_port_no_t out_port; |
| 1447 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1448 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1449 | uint64_t cookie; |
| 1450 | uint64_t cookie_mask; |
| 1451 | of_match_t match; |
| 1452 | }; |
| 1453 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1454 | struct of_flow_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1455 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1456 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1457 | uint16_t length; |
| 1458 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1459 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1460 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1461 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1462 | list(of_flow_stats_entry_t) entries; |
| 1463 | }; |
| 1464 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1465 | struct of_aggregate_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1466 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1467 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1468 | uint16_t length; |
| 1469 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1470 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1471 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1472 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1473 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1474 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1475 | of_port_no_t out_port; |
| 1476 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1477 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1478 | uint64_t cookie; |
| 1479 | uint64_t cookie_mask; |
| 1480 | of_match_t match; |
| 1481 | }; |
| 1482 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1483 | struct of_aggregate_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1484 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1485 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1486 | uint16_t length; |
| 1487 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1488 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1489 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1490 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1491 | uint64_t packet_count; |
| 1492 | uint64_t byte_count; |
| 1493 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1494 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1495 | }; |
| 1496 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1497 | struct of_table_stats_request : of_stats_request { |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1498 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1499 | uint8_t type == 18; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1500 | uint16_t length; |
| 1501 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1502 | uint16_t stats_type == 3; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1503 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1504 | pad(4); |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1505 | }; |
| 1506 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1507 | struct of_table_stats_reply : of_stats_reply { |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1508 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1509 | uint8_t type == 19; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1510 | uint16_t length; |
| 1511 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1512 | uint16_t stats_type == 3; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1513 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1514 | pad(4); |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1515 | list(of_table_stats_entry_t) entries; |
| 1516 | }; |
| 1517 | |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1518 | // FIXME: These are padded to 8 byte align beyond the length indicated |
| 1519 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1520 | struct of_table_feature_prop { |
Rich Lane | a1b8f44 | 2013-10-01 22:05:22 -0700 | [diff] [blame] | 1521 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1522 | uint16_t length; |
| 1523 | }; |
| 1524 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1525 | struct of_table_feature_prop_instructions : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1526 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1527 | uint16_t length; |
| 1528 | // FIXME Check if instruction_t is right for ids here |
| 1529 | list(of_instruction_t) instruction_ids; |
| 1530 | }; |
| 1531 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1532 | struct of_table_feature_prop_instructions_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1533 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1534 | uint16_t length; |
| 1535 | list(of_instruction_t) instruction_ids; |
| 1536 | }; |
| 1537 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1538 | struct of_table_feature_prop_next_tables : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1539 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1540 | uint16_t length; |
| 1541 | list(of_uint8_t) next_table_ids; |
| 1542 | }; |
| 1543 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1544 | struct of_table_feature_prop_next_tables_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1545 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1546 | uint16_t length; |
| 1547 | list(of_uint8_t) next_table_ids; |
| 1548 | }; |
| 1549 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1550 | struct of_table_feature_prop_write_actions : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1551 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1552 | uint16_t length; |
| 1553 | list(of_action_id_t) action_ids; |
| 1554 | }; |
| 1555 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1556 | struct of_table_feature_prop_write_actions_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1557 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1558 | uint16_t length; |
| 1559 | list(of_action_id_t) action_ids; |
| 1560 | }; |
| 1561 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1562 | struct of_table_feature_prop_apply_actions : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1563 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1564 | uint16_t length; |
| 1565 | list(of_action_id_t) action_ids; |
| 1566 | }; |
| 1567 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1568 | struct of_table_feature_prop_apply_actions_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1569 | uint16_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1570 | uint16_t length; |
| 1571 | list(of_action_id_t) action_ids; |
| 1572 | }; |
| 1573 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1574 | struct of_table_feature_prop_match : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1575 | uint16_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1576 | uint16_t length; |
| 1577 | list(of_uint32_t) oxm_ids; |
| 1578 | }; |
| 1579 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1580 | struct of_table_feature_prop_wildcards : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1581 | uint16_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1582 | uint16_t length; |
| 1583 | list(of_uint32_t) oxm_ids; |
| 1584 | }; |
| 1585 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1586 | struct of_table_feature_prop_write_setfield : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1587 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1588 | uint16_t length; |
| 1589 | list(of_uint32_t) oxm_ids; |
| 1590 | }; |
| 1591 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1592 | struct of_table_feature_prop_write_setfield_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1593 | uint16_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1594 | uint16_t length; |
| 1595 | list(of_uint32_t) oxm_ids; |
| 1596 | }; |
| 1597 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1598 | struct of_table_feature_prop_apply_setfield : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1599 | uint16_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1600 | uint16_t length; |
| 1601 | list(of_uint32_t) oxm_ids; |
| 1602 | }; |
| 1603 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1604 | struct of_table_feature_prop_apply_setfield_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1605 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1606 | uint16_t length; |
| 1607 | list(of_uint32_t) oxm_ids; |
| 1608 | }; |
| 1609 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1610 | struct of_table_feature_prop_experimenter : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1611 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1612 | uint16_t length; |
| 1613 | uint32_t experimenter; |
| 1614 | uint32_t subtype; |
| 1615 | of_octets_t experimenter_data; |
| 1616 | }; |
| 1617 | |
| 1618 | // Not yet supported |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1619 | // struct of_table_feature_prop_experimenter_miss : of_table_feature_prop { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1620 | // uint16_t type; |
| 1621 | // uint16_t length; |
| 1622 | // uint32_t experimenter; |
| 1623 | // uint32_t subtype; |
| 1624 | // of_octets_t experimenter_data; |
| 1625 | // }; |
| 1626 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1627 | struct of_table_features { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1628 | uint16_t length; |
| 1629 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1630 | pad(5); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1631 | of_table_name_t name; |
| 1632 | uint64_t metadata_match; |
| 1633 | uint64_t metadata_write; |
| 1634 | uint32_t config; |
| 1635 | uint32_t max_entries; |
| 1636 | list(of_table_feature_prop_t) properties; |
| 1637 | }; |
| 1638 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1639 | struct of_meter_features { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1640 | uint32_t max_meter; |
| 1641 | uint32_t band_types; |
| 1642 | uint32_t capabilities; |
| 1643 | uint8_t max_bands; |
| 1644 | uint8_t max_color; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1645 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1646 | }; |
| 1647 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1648 | struct of_port_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1649 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1650 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1651 | uint16_t length; |
| 1652 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1653 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1654 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1655 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1656 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1657 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1658 | }; |
| 1659 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1660 | struct of_port_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1661 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1662 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1663 | uint16_t length; |
| 1664 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1665 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1666 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1667 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1668 | list(of_port_stats_entry_t) entries; |
| 1669 | }; |
| 1670 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1671 | struct of_queue_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1672 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1673 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1674 | uint16_t length; |
| 1675 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1676 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1677 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1678 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1679 | of_port_no_t port_no; |
| 1680 | uint32_t queue_id; |
| 1681 | }; |
| 1682 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1683 | struct of_queue_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1684 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1685 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1686 | uint16_t length; |
| 1687 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1688 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1689 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1690 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1691 | list(of_queue_stats_entry_t) entries; |
| 1692 | }; |
| 1693 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1694 | struct of_group_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1695 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1696 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1697 | uint16_t length; |
| 1698 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1699 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1700 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1701 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1702 | uint32_t group_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1703 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1704 | }; |
| 1705 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1706 | struct of_group_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1707 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1708 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1709 | uint16_t length; |
| 1710 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1711 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1712 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1713 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1714 | list(of_group_stats_entry_t) entries; |
| 1715 | }; |
| 1716 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1717 | struct of_group_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1718 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1719 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1720 | uint16_t length; |
| 1721 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1722 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1723 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1724 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1725 | }; |
| 1726 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1727 | struct of_group_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1728 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1729 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1730 | uint16_t length; |
| 1731 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1732 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1733 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1734 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1735 | list(of_group_desc_stats_entry_t) entries; |
| 1736 | }; |
| 1737 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1738 | struct of_group_features_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1739 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1740 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1741 | uint16_t length; |
| 1742 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1743 | uint16_t stats_type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1744 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1745 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1746 | }; |
| 1747 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1748 | struct of_group_features_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1749 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1750 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1751 | uint16_t length; |
| 1752 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1753 | uint16_t stats_type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1754 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1755 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1756 | uint32_t types; |
| 1757 | uint32_t capabilities; |
| 1758 | uint32_t max_groups_all; |
| 1759 | uint32_t max_groups_select; |
| 1760 | uint32_t max_groups_indirect; |
| 1761 | uint32_t max_groups_ff; |
| 1762 | uint32_t actions_all; |
| 1763 | uint32_t actions_select; |
| 1764 | uint32_t actions_indirect; |
| 1765 | uint32_t actions_ff; |
| 1766 | }; |
| 1767 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1768 | struct of_meter_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1769 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1770 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1771 | uint16_t length; |
| 1772 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1773 | uint16_t stats_type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1774 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1775 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1776 | uint32_t meter_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1777 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1778 | }; |
| 1779 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1780 | struct of_meter_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1781 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1782 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1783 | uint16_t length; |
| 1784 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1785 | uint16_t stats_type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1786 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1787 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1788 | list(of_meter_stats_t) entries; |
| 1789 | }; |
| 1790 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1791 | struct of_meter_config_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1792 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1793 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1794 | uint16_t length; |
| 1795 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1796 | uint16_t stats_type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1797 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1798 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1799 | uint32_t meter_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1800 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1801 | }; |
| 1802 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1803 | struct of_meter_config_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1804 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1805 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1806 | uint16_t length; |
| 1807 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1808 | uint16_t stats_type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1809 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1810 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1811 | list(of_meter_band_t) entries; |
| 1812 | }; |
| 1813 | |
| 1814 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1815 | struct of_meter_features_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1816 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1817 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1818 | uint16_t length; |
| 1819 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1820 | uint16_t stats_type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1821 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1822 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1823 | }; |
| 1824 | |
| 1825 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1826 | struct of_meter_features_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1827 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1828 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1829 | uint16_t length; |
| 1830 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1831 | uint16_t stats_type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1832 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1833 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1834 | of_meter_features_t features; |
| 1835 | }; |
| 1836 | |
| 1837 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1838 | struct of_table_features_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1839 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1840 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1841 | uint16_t length; |
| 1842 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1843 | uint16_t stats_type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1844 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1845 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1846 | list(of_table_features_t) entries; |
| 1847 | }; |
| 1848 | |
| 1849 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1850 | struct of_table_features_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1851 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1852 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1853 | uint16_t length; |
| 1854 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1855 | uint16_t stats_type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1856 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1857 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1858 | list(of_table_features_t) entries; |
| 1859 | }; |
| 1860 | |
| 1861 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1862 | struct of_port_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1863 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1864 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1865 | uint16_t length; |
| 1866 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1867 | uint16_t stats_type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1868 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1869 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1870 | }; |
| 1871 | |
| 1872 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1873 | struct of_port_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1874 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1875 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1876 | uint16_t length; |
| 1877 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1878 | uint16_t stats_type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1879 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1880 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1881 | list(of_port_desc_t) entries; |
| 1882 | }; |
| 1883 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1884 | struct of_meter_band_stats { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1885 | uint64_t packet_band_count; |
| 1886 | uint64_t byte_band_count; |
| 1887 | }; |
| 1888 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1889 | struct of_meter_stats { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1890 | uint32_t meter_id; |
| 1891 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1892 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1893 | uint32_t flow_count; |
| 1894 | uint64_t packet_in_count; |
| 1895 | uint64_t byte_in_count; |
| 1896 | uint32_t duration_sec; |
| 1897 | uint32_t duration_nsec; |
| 1898 | list(of_meter_band_stats_t) band_stats; |
| 1899 | }; |
| 1900 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1901 | struct of_meter_config { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1902 | uint16_t length; |
| 1903 | uint16_t flags; |
| 1904 | uint32_t meter_id; |
| 1905 | list(of_meter_band_t) entries; |
| 1906 | }; |
| 1907 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 1908 | struct of_experimenter_stats_header { |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1909 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1910 | uint32_t subtype; |
| 1911 | }; |
| 1912 | |
| 1913 | // END OF STATS OBJECTS |
| 1914 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1915 | struct of_queue_prop { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1916 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1917 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1918 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1919 | }; |
| 1920 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1921 | struct of_queue_prop_min_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1922 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1923 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1924 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1925 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1926 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1927 | }; |
| 1928 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1929 | struct of_queue_prop_max_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1930 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1931 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1932 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1933 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1934 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1935 | }; |
| 1936 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1937 | struct of_queue_prop_experimenter : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1938 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1939 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1940 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1941 | uint32_t experimenter == ?; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1942 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1943 | of_octets_t data; |
| 1944 | }; |
| 1945 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1946 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1947 | uint32_t queue_id; |
| 1948 | of_port_no_t port; |
| 1949 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1950 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1951 | list(of_queue_prop_t) properties; |
| 1952 | }; |
| 1953 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1954 | struct of_queue_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1955 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1956 | uint8_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1957 | uint16_t length; |
| 1958 | uint32_t xid; |
| 1959 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1960 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1961 | }; |
| 1962 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1963 | struct of_queue_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1964 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1965 | uint8_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1966 | uint16_t length; |
| 1967 | uint32_t xid; |
| 1968 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1969 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1970 | list(of_packet_queue_t) queues; |
| 1971 | }; |
| 1972 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1973 | struct of_role_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1974 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1975 | uint8_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1976 | uint16_t length; |
| 1977 | uint32_t xid; |
| 1978 | uint32_t role; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1979 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1980 | uint64_t generation_id; |
| 1981 | }; |
| 1982 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1983 | struct of_role_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1984 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1985 | uint8_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1986 | uint16_t length; |
| 1987 | uint32_t xid; |
| 1988 | of_octets_t data; |
| 1989 | }; |
| 1990 | |
| 1991 | //////////////////////////////////////////////////////////////// |
| 1992 | // FIXME understand async; where do bitmasks live? |
| 1993 | // Determine bitmap type for masks below. |
| 1994 | // DOCUMENT masks where uint32_t[0] is interest for equal/master |
| 1995 | // while uint32_t[1] is interest for slave |
| 1996 | //////////////////////////////////////////////////////////////// |
| 1997 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1998 | struct of_async_get_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1999 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 2000 | uint8_t type == 26; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 2001 | uint16_t length; |
| 2002 | uint32_t xid; |
| 2003 | uint32_t packet_in_mask_equal_master; |
| 2004 | uint32_t packet_in_mask_slave; |
| 2005 | uint32_t port_status_mask_equal_master; |
| 2006 | uint32_t port_status_mask_slave; |
| 2007 | uint32_t flow_removed_mask_equal_master; |
| 2008 | uint32_t flow_removed_mask_slave; |
| 2009 | }; |
| 2010 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 2011 | struct of_async_get_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 2012 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 2013 | uint8_t type == 27; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 2014 | uint16_t length; |
| 2015 | uint32_t xid; |
| 2016 | uint32_t packet_in_mask_equal_master; |
| 2017 | uint32_t packet_in_mask_slave; |
| 2018 | uint32_t port_status_mask_equal_master; |
| 2019 | uint32_t port_status_mask_slave; |
| 2020 | uint32_t flow_removed_mask_equal_master; |
| 2021 | uint32_t flow_removed_mask_slave; |
| 2022 | }; |
| 2023 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 2024 | struct of_async_set : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 2025 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 2026 | uint8_t type == 28; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 2027 | uint16_t length; |
| 2028 | uint32_t xid; |
| 2029 | uint32_t packet_in_mask_equal_master; |
| 2030 | uint32_t packet_in_mask_slave; |
| 2031 | uint32_t port_status_mask_equal_master; |
| 2032 | uint32_t port_status_mask_slave; |
| 2033 | uint32_t flow_removed_mask_equal_master; |
| 2034 | uint32_t flow_removed_mask_slave; |
| 2035 | }; |