| Rich Lane | b1f347d | 2013-05-16 16:39:12 -0700 | [diff] [blame] | 1 | -- binary |
| 2 | 01 0f # version/type |
| 3 | 00 20 # length |
| 4 | 00 00 00 02 # xid |
| 5 | ff fd # port_no |
| 6 | 01 02 03 04 05 06 # hw_addr |
| 7 | 90 ab cd ef # config |
| 8 | ff 11 ff 11 # mask |
| 9 | ca fe 67 89 # advertise |
| 10 | 00 00 00 00 # pad |
| 11 | -- python |
| 12 | ofp.message.port_mod( |
| 13 | xid=2, |
| 14 | port_no=ofp.OFPP_CONTROLLER, |
| 15 | hw_addr=[1,2,3,4,5,6], |
| 16 | config=0x90ABCDEF, |
| 17 | mask=0xFF11FF11, |
| 18 | advertise=0xCAFE6789) |
| Rich Lane | ccae031 | 2013-07-21 23:34:13 -0700 | [diff] [blame] | 19 | -- c |
| 20 | obj = of_port_mod_new(OF_VERSION_1_0); |
| Rich Lane | 03be4f8 | 2013-12-16 17:08:26 -0800 | [diff] [blame] | 21 | of_port_mod_advertise_set(obj, 0xCAFE6789); |
| 22 | of_port_mod_config_set(obj, 0x90ABCDEF); |
| Rich Lane | ccae031 | 2013-07-21 23:34:13 -0700 | [diff] [blame] | 23 | { |
| 24 | of_mac_addr_t hw_addr = { { 1, 2, 3, 4, 5, 6 } }; |
| 25 | of_port_mod_hw_addr_set(obj, hw_addr); |
| 26 | } |
| Rich Lane | 03be4f8 | 2013-12-16 17:08:26 -0800 | [diff] [blame] | 27 | of_port_mod_mask_set(obj, 0xFF11FF11); |
| Rich Lane | ccae031 | 2013-07-21 23:34:13 -0700 | [diff] [blame] | 28 | of_port_mod_port_no_set(obj, 65533); |
| 29 | of_port_mod_xid_set(obj, 2); |