Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 4 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
Wilson Ng | d72013d | 2013-09-29 10:21:48 -0700 | [diff] [blame] | 38 | OFP_TCP_PORT = 6653, |
| 39 | OFP_SSL_PORT = 6653, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFP_VLAN_NONE = 0, |
| 46 | |
| 47 | OFP_FLOW_PERMANENT = 0, |
| 48 | |
| 49 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 50 | |
| 51 | OFP_NO_BUFFER = 0xffffffff, |
| 52 | |
| 53 | DESC_STR_LEN = 256, |
| 54 | SERIAL_NUM_LEN = 32, |
| 55 | |
| 56 | OFPQ_ALL = 0xffffffff, |
| 57 | OFPQ_MAX_RATE_UNCFG = 0xffff, |
| 58 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 59 | }; |
| 60 | |
Andreas Wundsam | 7933beb | 2013-08-02 22:36:42 -0700 | [diff] [blame] | 61 | enum ofp_port_no(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 62 | OFPP_ANY = 0xffffffff, |
| 63 | }; |
| 64 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 65 | enum ofp_port(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 66 | OFPP_MAX = 0xffffff00, |
| 67 | OFPP_IN_PORT = 0xfffffff8, |
| 68 | OFPP_TABLE = 0xfffffff9, |
| 69 | OFPP_NORMAL = 0xfffffffa, |
| 70 | OFPP_FLOOD = 0xfffffffb, |
| 71 | OFPP_ALL = 0xfffffffc, |
| 72 | OFPP_CONTROLLER = 0xfffffffd, |
| 73 | OFPP_LOCAL = 0xfffffffe, |
| 74 | }; |
| 75 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 76 | enum ofp_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 77 | OFPT_HELLO = 0, |
| 78 | OFPT_ERROR = 1, |
| 79 | OFPT_ECHO_REQUEST = 2, |
| 80 | OFPT_ECHO_REPLY = 3, |
| 81 | OFPT_EXPERIMENTER = 4, |
| 82 | OFPT_FEATURES_REQUEST = 5, |
| 83 | OFPT_FEATURES_REPLY = 6, |
| 84 | OFPT_GET_CONFIG_REQUEST = 7, |
| 85 | OFPT_GET_CONFIG_REPLY = 8, |
| 86 | OFPT_SET_CONFIG = 9, |
| 87 | OFPT_PACKET_IN = 10, |
| 88 | OFPT_FLOW_REMOVED = 11, |
| 89 | OFPT_PORT_STATUS = 12, |
| 90 | OFPT_PACKET_OUT = 13, |
| 91 | OFPT_FLOW_MOD = 14, |
| 92 | OFPT_GROUP_MOD = 15, |
| 93 | OFPT_PORT_MOD = 16, |
| 94 | OFPT_TABLE_MOD = 17, |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 95 | OFPT_STATS_REQUEST = 18, |
| 96 | OFPT_STATS_REPLY = 19, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 97 | OFPT_BARRIER_REQUEST = 20, |
| 98 | OFPT_BARRIER_REPLY = 21, |
| 99 | OFPT_QUEUE_GET_CONFIG_REQUEST = 22, |
| 100 | OFPT_QUEUE_GET_CONFIG_REPLY = 23, |
| 101 | OFPT_ROLE_REQUEST = 24, |
| 102 | OFPT_ROLE_REPLY = 25, |
| 103 | OFPT_GET_ASYNC_REQUEST = 26, |
| 104 | OFPT_GET_ASYNC_REPLY = 27, |
| 105 | OFPT_SET_ASYNC = 28, |
| 106 | OFPT_METER_MOD = 29, |
| 107 | }; |
| 108 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 109 | enum ofp_config_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 110 | OFPC_FRAG_NORMAL = 0, |
| 111 | OFPC_FRAG_DROP = 1, |
| 112 | OFPC_FRAG_REASM = 2, |
| 113 | OFPC_FRAG_MASK = 3, |
| 114 | }; |
| 115 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 116 | enum ofp_table_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 117 | OFPTC_DEPRECATED_MASK = 0x3, |
| 118 | }; |
| 119 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 120 | enum ofp_table(wire_type=uint8_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 121 | OFPTT_MAX = 0xfe, |
| 122 | OFPTT_ALL = 0xff, |
| 123 | }; |
| 124 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 125 | enum ofp_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 126 | OFPC_FLOW_STATS = 0x1, |
| 127 | OFPC_TABLE_STATS = 0x2, |
| 128 | OFPC_PORT_STATS = 0x4, |
| 129 | OFPC_GROUP_STATS = 0x8, |
| 130 | OFPC_IP_REASM = 0x20, |
| 131 | OFPC_QUEUE_STATS = 0x40, |
| 132 | OFPC_PORT_BLOCKED = 0x100, |
| 133 | }; |
| 134 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 135 | enum ofp_port_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 136 | OFPPC_PORT_DOWN = 0x1, |
| 137 | OFPPC_NO_RECV = 0x4, |
| 138 | OFPPC_NO_FWD = 0x20, |
| 139 | OFPPC_NO_PACKET_IN = 0x40, |
| 140 | }; |
| 141 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 142 | enum ofp_port_state(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 143 | OFPPS_LINK_DOWN = 0x1, |
| 144 | OFPPS_BLOCKED = 0x2, |
| 145 | OFPPS_LIVE = 0x4, |
| 146 | }; |
| 147 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 148 | enum ofp_port_features(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 149 | OFPPF_10MB_HD = 0x1, |
| 150 | OFPPF_10MB_FD = 0x2, |
| 151 | OFPPF_100MB_HD = 0x4, |
| 152 | OFPPF_100MB_FD = 0x8, |
| 153 | OFPPF_1GB_HD = 0x10, |
| 154 | OFPPF_1GB_FD = 0x20, |
| 155 | OFPPF_10GB_FD = 0x40, |
| 156 | OFPPF_40GB_FD = 0x80, |
| 157 | OFPPF_100GB_FD = 0x100, |
| 158 | OFPPF_1TB_FD = 0x200, |
| 159 | OFPPF_OTHER = 0x400, |
| 160 | OFPPF_COPPER = 0x800, |
| 161 | OFPPF_FIBER = 0x1000, |
| 162 | OFPPF_AUTONEG = 0x2000, |
| 163 | OFPPF_PAUSE = 0x4000, |
| 164 | OFPPF_PAUSE_ASYM = 0x8000, |
| 165 | }; |
| 166 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 167 | enum ofp_port_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 168 | OFPPR_ADD = 0, |
| 169 | OFPPR_DELETE = 1, |
| 170 | OFPPR_MODIFY = 2, |
| 171 | }; |
| 172 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 173 | enum ofp_match_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 174 | OFPMT_STANDARD = 0, |
| 175 | OFPMT_OXM = 1, |
| 176 | }; |
| 177 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 178 | enum ofp_oxm_class(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 179 | OFPXMC_NXM_0 = 0, |
| 180 | OFPXMC_NXM_1 = 1, |
| 181 | OFPXMC_OPENFLOW_BASIC = 0x8000, |
| 182 | OFPXMC_EXPERIMENTER = 0xffff, |
| 183 | }; |
| 184 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 185 | enum ofp_vlan_id(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 186 | OFPVID_NONE = 0, |
| 187 | OFPVID_PRESENT = 0x1000, |
| 188 | }; |
| 189 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 190 | // FIXME: OF spec specified this as '9' bits, implicitly adding |
| 191 | // to full byte |
| 192 | enum ofp_ipv6exthdr_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 193 | OFPIEH_NONEXT = 0x1, |
| 194 | OFPIEH_ESP = 0x2, |
| 195 | OFPIEH_AUTH = 0x4, |
| 196 | OFPIEH_DEST = 0x8, |
| 197 | OFPIEH_FRAG = 0x10, |
| 198 | OFPIEH_ROUTER = 0x20, |
| 199 | OFPIEH_HOP = 0x40, |
| 200 | OFPIEH_UNREP = 0x80, |
| 201 | OFPIEH_UNSEQ = 0x100, |
| 202 | }; |
| 203 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 204 | enum ofp_action_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 205 | OFPAT_OUTPUT = 0, |
| 206 | OFPAT_COPY_TTL_OUT = 0xb, |
| 207 | OFPAT_COPY_TTL_IN = 0xc, |
| 208 | OFPAT_SET_MPLS_TTL = 0xf, |
| 209 | OFPAT_DEC_MPLS_TTL = 0x10, |
| 210 | OFPAT_PUSH_VLAN = 0x11, |
| 211 | OFPAT_POP_VLAN = 0x12, |
| 212 | OFPAT_PUSH_MPLS = 0x13, |
| 213 | OFPAT_POP_MPLS = 0x14, |
| 214 | OFPAT_SET_QUEUE = 0x15, |
| 215 | OFPAT_GROUP = 0x16, |
| 216 | OFPAT_SET_NW_TTL = 0x17, |
| 217 | OFPAT_DEC_NW_TTL = 0x18, |
| 218 | OFPAT_SET_FIELD = 0x19, |
| 219 | OFPAT_PUSH_PBB = 0x1a, |
| 220 | OFPAT_POP_PBB = 0x1b, |
| 221 | OFPAT_EXPERIMENTER = 0xffff, |
| 222 | }; |
| 223 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 224 | enum ofp_controller_max_len(wire_type=uint16_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 225 | OFPCML_MAX = 0xffe5, |
| 226 | OFPCML_NO_BUFFER = 0xffff, |
| 227 | }; |
| 228 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 229 | enum ofp_instruction_type(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 230 | OFPIT_GOTO_TABLE = 0x1, |
| 231 | OFPIT_WRITE_METADATA = 0x2, |
| 232 | OFPIT_WRITE_ACTIONS = 0x3, |
| 233 | OFPIT_APPLY_ACTIONS = 0x4, |
| 234 | OFPIT_CLEAR_ACTIONS = 0x5, |
| 235 | OFPIT_METER = 0x6, |
| 236 | OFPIT_EXPERIMENTER = 0xffff, |
| 237 | }; |
| 238 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 239 | enum ofp_flow_mod_command(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 240 | OFPFC_ADD = 0, |
| 241 | OFPFC_MODIFY = 1, |
| 242 | OFPFC_MODIFY_STRICT = 2, |
| 243 | OFPFC_DELETE = 3, |
| 244 | OFPFC_DELETE_STRICT = 4, |
| 245 | }; |
| 246 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 247 | enum ofp_flow_mod_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 248 | OFPFF_SEND_FLOW_REM = 0x1, |
| 249 | OFPFF_CHECK_OVERLAP = 0x2, |
| 250 | OFPFF_RESET_COUNTS = 0x4, |
| 251 | OFPFF_NO_PKT_COUNTS = 0x8, |
| 252 | OFPFF_NO_BYT_COUNTS = 0x10, |
Rich Lane | f86f39a | 2013-10-07 18:04:11 -0700 | [diff] [blame] | 253 | |
| 254 | /* Non-standard, enabled by an experimenter message */ |
| 255 | /* See the bsn_flow_idle input file */ |
| 256 | OFPFF_BSN_SEND_IDLE = 0x80, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 257 | }; |
| 258 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 259 | enum ofp_group(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 260 | OFPG_MAX = 0xffffff00, |
| 261 | OFPG_ALL = 0xfffffffc, |
| 262 | OFPG_ANY = 0xffffffff, |
| 263 | }; |
| 264 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 265 | enum ofp_group_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 266 | OFPGC_ADD = 0, |
| 267 | OFPGC_MODIFY = 1, |
| 268 | OFPGC_DELETE = 2, |
| 269 | }; |
| 270 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 271 | enum ofp_group_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 272 | OFPGT_ALL = 0, |
| 273 | OFPGT_SELECT = 1, |
| 274 | OFPGT_INDIRECT = 2, |
| 275 | OFPGT_FF = 3, |
| 276 | }; |
| 277 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 278 | enum ofp_packet_in_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 279 | OFPR_NO_MATCH = 0, |
| 280 | OFPR_ACTION = 1, |
| 281 | OFPR_INVALID_TTL = 2, |
| 282 | }; |
| 283 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 284 | enum ofp_flow_removed_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 285 | OFPRR_IDLE_TIMEOUT = 0, |
| 286 | OFPRR_HARD_TIMEOUT = 1, |
| 287 | OFPRR_DELETE = 2, |
| 288 | OFPRR_GROUP_DELETE = 3, |
| 289 | }; |
| 290 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 291 | enum ofp_meter(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 292 | OFPM_MAX = 0xffff0000, |
| 293 | OFPM_SLOWPATH = 0xfffffffd, |
| 294 | OFPM_CONTROLLER = 0xfffffffe, |
| 295 | OFPM_ALL = 0xffffffff, |
| 296 | }; |
| 297 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 298 | enum ofp_meter_band_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 299 | OFPMBT_DROP = 0x1, |
| 300 | OFPMBT_DSCP_REMARK = 0x2, |
| 301 | OFPMBT_EXPERIMENTER = 0xffff, |
| 302 | }; |
| 303 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 304 | enum ofp_meter_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 305 | OFPMC_ADD = 0, |
| 306 | OFPMC_MODIFY = 1, |
| 307 | OFPMC_DELETE = 2, |
| 308 | }; |
| 309 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 310 | enum ofp_meter_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 311 | OFPMF_KBPS = 0x1, |
| 312 | OFPMF_PKTPS = 0x2, |
| 313 | OFPMF_BURST = 0x4, |
| 314 | OFPMF_STATS = 0x8, |
| 315 | }; |
| 316 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 317 | enum ofp_error_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 318 | OFPET_HELLO_FAILED = 0, |
| 319 | OFPET_BAD_REQUEST = 1, |
| 320 | OFPET_BAD_ACTION = 2, |
| 321 | OFPET_BAD_INSTRUCTION = 3, |
| 322 | OFPET_BAD_MATCH = 4, |
| 323 | OFPET_FLOW_MOD_FAILED = 5, |
| 324 | OFPET_GROUP_MOD_FAILED = 6, |
| 325 | OFPET_PORT_MOD_FAILED = 7, |
| 326 | OFPET_TABLE_MOD_FAILED = 8, |
| 327 | OFPET_QUEUE_OP_FAILED = 9, |
| 328 | OFPET_SWITCH_CONFIG_FAILED = 10, |
| 329 | OFPET_ROLE_REQUEST_FAILED = 11, |
| 330 | OFPET_METER_MOD_FAILED = 12, |
| 331 | OFPET_TABLE_FEATURES_FAILED = 13, |
| 332 | OFPET_EXPERIMENTER = 0xffff, |
| 333 | }; |
| 334 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 335 | enum ofp_hello_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 336 | OFPHFC_INCOMPATIBLE = 0, |
| 337 | OFPHFC_EPERM = 1, |
| 338 | }; |
| 339 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 340 | enum ofp_bad_request_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 341 | OFPBRC_BAD_VERSION = 0, |
| 342 | OFPBRC_BAD_TYPE = 1, |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 343 | OFPBRC_BAD_STAT = 2, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 344 | OFPBRC_BAD_EXPERIMENTER = 3, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 345 | OFPBRC_BAD_EXPERIMENTER_TYPE = 4, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 346 | OFPBRC_EPERM = 5, |
| 347 | OFPBRC_BAD_LEN = 6, |
| 348 | OFPBRC_BUFFER_EMPTY = 7, |
| 349 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 350 | OFPBRC_BAD_TABLE_ID = 9, |
| 351 | OFPBRC_IS_SLAVE = 10, |
| 352 | OFPBRC_BAD_PORT = 11, |
| 353 | OFPBRC_BAD_PACKET = 12, |
| 354 | OFPBRC_MULTIPART_BUFFER_OVERFLOW = 13, |
| 355 | }; |
| 356 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 357 | enum ofp_bad_action_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 358 | OFPBAC_BAD_TYPE = 0, |
| 359 | OFPBAC_BAD_LEN = 1, |
| 360 | OFPBAC_BAD_EXPERIMENTER = 2, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 361 | OFPBAC_BAD_EXPERIMENTER_TYPE = 3, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 362 | OFPBAC_BAD_OUT_PORT = 4, |
| 363 | OFPBAC_BAD_ARGUMENT = 5, |
| 364 | OFPBAC_EPERM = 6, |
| 365 | OFPBAC_TOO_MANY = 7, |
| 366 | OFPBAC_BAD_QUEUE = 8, |
| 367 | OFPBAC_BAD_OUT_GROUP = 9, |
| 368 | OFPBAC_MATCH_INCONSISTENT = 10, |
| 369 | OFPBAC_UNSUPPORTED_ORDER = 11, |
| 370 | OFPBAC_BAD_TAG = 12, |
| 371 | OFPBAC_BAD_SET_TYPE = 13, |
| 372 | OFPBAC_BAD_SET_LEN = 14, |
| 373 | OFPBAC_BAD_SET_ARGUMENT = 15, |
| 374 | }; |
| 375 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 376 | enum ofp_bad_instruction_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 377 | OFPBIC_UNKNOWN_INST = 0, |
| 378 | OFPBIC_UNSUP_INST = 1, |
| 379 | OFPBIC_BAD_TABLE_ID = 2, |
| 380 | OFPBIC_UNSUP_METADATA = 3, |
| 381 | OFPBIC_UNSUP_METADATA_MASK = 4, |
| 382 | OFPBIC_BAD_EXPERIMENTER = 5, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 383 | OFPBIC_BAD_EXPERIMENTER_TYPE = 6, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 384 | OFPBIC_BAD_LEN = 7, |
| 385 | OFPBIC_EPERM = 8, |
| 386 | }; |
| 387 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 388 | enum ofp_bad_match_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 389 | OFPBMC_BAD_TYPE = 0, |
| 390 | OFPBMC_BAD_LEN = 1, |
| 391 | OFPBMC_BAD_TAG = 2, |
| 392 | OFPBMC_BAD_DL_ADDR_MASK = 3, |
| 393 | OFPBMC_BAD_NW_ADDR_MASK = 4, |
| 394 | OFPBMC_BAD_WILDCARDS = 5, |
| 395 | OFPBMC_BAD_FIELD = 6, |
| 396 | OFPBMC_BAD_VALUE = 7, |
| 397 | OFPBMC_BAD_MASK = 8, |
| 398 | OFPBMC_BAD_PREREQ = 9, |
| 399 | OFPBMC_DUP_FIELD = 10, |
| 400 | OFPBMC_EPERM = 11, |
| 401 | }; |
| 402 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 403 | enum ofp_flow_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 404 | OFPFMFC_UNKNOWN = 0, |
| 405 | OFPFMFC_TABLE_FULL = 1, |
| 406 | OFPFMFC_BAD_TABLE_ID = 2, |
| 407 | OFPFMFC_OVERLAP = 3, |
| 408 | OFPFMFC_EPERM = 4, |
| 409 | OFPFMFC_BAD_TIMEOUT = 5, |
| 410 | OFPFMFC_BAD_COMMAND = 6, |
| 411 | OFPFMFC_BAD_FLAGS = 7, |
| 412 | }; |
| 413 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 414 | enum ofp_group_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 415 | OFPGMFC_GROUP_EXISTS = 0, |
| 416 | OFPGMFC_INVALID_GROUP = 1, |
| 417 | OFPGMFC_WEIGHT_UNSUPPORTED = 2, |
| 418 | OFPGMFC_OUT_OF_GROUPS = 3, |
| 419 | OFPGMFC_OUT_OF_BUCKETS = 4, |
| 420 | OFPGMFC_CHAINING_UNSUPPORTED = 5, |
| 421 | OFPGMFC_WATCH_UNSUPPORTED = 6, |
| 422 | OFPGMFC_LOOP = 7, |
| 423 | OFPGMFC_UNKNOWN_GROUP = 8, |
| 424 | OFPGMFC_CHAINED_GROUP = 9, |
| 425 | OFPGMFC_BAD_TYPE = 10, |
| 426 | OFPGMFC_BAD_COMMAND = 11, |
| 427 | OFPGMFC_BAD_BUCKET = 12, |
| 428 | OFPGMFC_BAD_WATCH = 13, |
| 429 | OFPGMFC_EPERM = 14, |
| 430 | }; |
| 431 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 432 | enum ofp_port_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 433 | OFPPMFC_BAD_PORT = 0, |
| 434 | OFPPMFC_BAD_HW_ADDR = 1, |
| 435 | OFPPMFC_BAD_CONFIG = 2, |
| 436 | OFPPMFC_BAD_ADVERTISE = 3, |
| 437 | OFPPMFC_EPERM = 4, |
| 438 | }; |
| 439 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 440 | enum ofp_table_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 441 | OFPTMFC_BAD_TABLE = 0, |
| 442 | OFPTMFC_BAD_CONFIG = 1, |
| 443 | OFPTMFC_EPERM = 2, |
| 444 | }; |
| 445 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 446 | enum ofp_queue_op_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 447 | OFPQOFC_BAD_PORT = 0, |
| 448 | OFPQOFC_BAD_QUEUE = 1, |
| 449 | OFPQOFC_EPERM = 2, |
| 450 | }; |
| 451 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 452 | enum ofp_switch_config_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 453 | OFPSCFC_BAD_FLAGS = 0, |
| 454 | OFPSCFC_BAD_LEN = 1, |
| 455 | OFPSCFC_EPERM = 2, |
| 456 | }; |
| 457 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 458 | enum ofp_role_request_failed_code(wire_type=uint16_t){ |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 459 | OFPRRFC_STALE = 0, |
| 460 | OFPRRFC_UNSUP = 1, |
| 461 | OFPRRFC_BAD_ROLE = 2, |
| 462 | }; |
| 463 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 464 | enum ofp_meter_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 465 | OFPMMFC_UNKNOWN = 0, |
| 466 | OFPMMFC_METER_EXISTS = 1, |
| 467 | OFPMMFC_INVALID_METER = 2, |
| 468 | OFPMMFC_UNKNOWN_METER = 3, |
| 469 | OFPMMFC_BAD_COMMAND = 4, |
| 470 | OFPMMFC_BAD_FLAGS = 5, |
| 471 | OFPMMFC_BAD_RATE = 6, |
| 472 | OFPMMFC_BAD_BURST = 7, |
| 473 | OFPMMFC_BAD_BAND = 8, |
| 474 | OFPMMFC_BAD_BAND_VALUE = 9, |
| 475 | OFPMMFC_OUT_OF_METERS = 10, |
| 476 | OFPMMFC_OUT_OF_BANDS = 11, |
| 477 | }; |
| 478 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 479 | enum ofp_table_features_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 480 | OFPTFFC_BAD_TABLE = 0, |
| 481 | OFPTFFC_BAD_METADATA = 1, |
| 482 | OFPTFFC_BAD_TYPE = 2, |
| 483 | OFPTFFC_BAD_LEN = 3, |
| 484 | OFPTFFC_BAD_ARGUMENT = 4, |
| 485 | OFPTFFC_EPERM = 5, |
| 486 | }; |
| 487 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 488 | enum ofp_stats_type(wire_type=uint16_t) { |
| 489 | OFPST_DESC = 0, |
| 490 | OFPST_FLOW = 1, |
| 491 | OFPST_AGGREGATE = 2, |
| 492 | OFPST_TABLE = 3, |
| 493 | OFPST_PORT = 4, |
| 494 | OFPST_QUEUE = 5, |
| 495 | OFPST_GROUP = 6, |
| 496 | OFPST_GROUP_DESC = 7, |
| 497 | OFPST_GROUP_FEATURES = 8, |
| 498 | OFPST_METER = 9, |
| 499 | OFPST_METER_CONFIG = 10, |
| 500 | OFPST_METER_FEATURES = 11, |
| 501 | OFPST_TABLE_FEATURES = 12, |
| 502 | OFPST_PORT_DESC = 13, |
| 503 | OFPST_EXPERIMENTER = 0xffff, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 504 | }; |
| 505 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 506 | enum ofp_stats_request_flags(wire_type=uint16_t, bitmask=True) { |
| 507 | OFPSF_REQ_MORE = 0x1, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 508 | }; |
| 509 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 510 | enum ofp_stats_reply_flags(wire_type=uint16_t, bitmask=True) { |
| 511 | OFPSF_REPLY_MORE = 0x1, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 512 | }; |
| 513 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 514 | enum ofp_table_feature_prop_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 515 | OFPTFPT_INSTRUCTIONS = 0, |
| 516 | OFPTFPT_INSTRUCTIONS_MISS = 1, |
| 517 | OFPTFPT_NEXT_TABLES = 2, |
| 518 | OFPTFPT_NEXT_TABLES_MISS = 3, |
| 519 | OFPTFPT_WRITE_ACTIONS = 4, |
| 520 | OFPTFPT_WRITE_ACTIONS_MISS = 5, |
| 521 | OFPTFPT_APPLY_ACTIONS = 6, |
| 522 | OFPTFPT_APPLY_ACTIONS_MISS = 7, |
| 523 | OFPTFPT_MATCH = 8, |
| 524 | OFPTFPT_WILDCARDS = 0xa, |
| 525 | OFPTFPT_WRITE_SETFIELD = 0xc, |
| 526 | OFPTFPT_WRITE_SETFIELD_MISS = 0xd, |
| 527 | OFPTFPT_APPLY_SETFIELD = 0xe, |
| 528 | OFPTFPT_APPLY_SETFIELD_MISS = 0xf, |
| 529 | OFPTFPT_EXPERIMENTER = 0xfffe, |
| 530 | OFPTFPT_EXPERIMENTER_MISS = 0xffff, |
| 531 | }; |
| 532 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 533 | enum ofp_group_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 534 | OFPGFC_SELECT_WEIGHT = 0x1, |
| 535 | OFPGFC_SELECT_LIVENESS = 0x2, |
| 536 | OFPGFC_CHAINING = 0x4, |
| 537 | OFPGFC_CHAINING_CHECKS = 0x8, |
| 538 | }; |
| 539 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 540 | enum ofp_queue_properties(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 541 | OFPQT_MIN_RATE = 0x1, |
| 542 | OFPQT_MAX_RATE = 0x2, |
| 543 | OFPQT_EXPERIMENTER = 0xffff, |
| 544 | }; |
| 545 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 546 | enum ofp_controller_role(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 547 | OFPCR_ROLE_NOCHANGE = 0, |
| 548 | OFPCR_ROLE_EQUAL = 1, |
| 549 | OFPCR_ROLE_MASTER = 2, |
| 550 | OFPCR_ROLE_SLAVE = 3, |
| 551 | }; |
| 552 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 553 | enum ofp_hello_elem_type(wire_type=uint16_t) { |
Rich Lane | 0733cd6 | 2013-04-18 21:14:42 -0700 | [diff] [blame] | 554 | OFPHET_VERSIONBITMAP = 1, |
| 555 | }; |
| 556 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 557 | /* XXX rename to of_message */ |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 558 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 559 | uint8_t version; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 560 | uint8_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 561 | uint16_t length; |
| 562 | uint32_t xid; |
| 563 | }; |
| 564 | |
| 565 | // Special structures used for managing scalar list elements |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 566 | struct of_uint32 { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 567 | uint32_t value; |
| 568 | }; |
| 569 | |
| 570 | // Special structures used for managing scalar list elements |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 571 | struct of_uint8 { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 572 | uint8_t value; |
| 573 | }; |
| 574 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 575 | struct of_hello_elem { |
Andreas Wundsam | 70411bf | 2013-08-02 22:26:38 -0700 | [diff] [blame] | 576 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 577 | uint16_t length; |
| 578 | }; |
| 579 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 580 | struct of_hello_elem_versionbitmap : of_hello_elem { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 581 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 582 | uint16_t length; |
| 583 | list(of_uint32_t) bitmaps; |
| 584 | }; |
| 585 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 586 | struct of_hello : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 587 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 588 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 589 | uint16_t length; |
| 590 | uint32_t xid; |
| 591 | list(of_hello_elem_t) elements; |
| 592 | }; |
| 593 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 594 | struct of_echo_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 595 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 596 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 597 | uint16_t length; |
| 598 | uint32_t xid; |
| 599 | of_octets_t data; |
| 600 | }; |
| 601 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 602 | struct of_echo_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 603 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 604 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 605 | uint16_t length; |
| 606 | uint32_t xid; |
| 607 | of_octets_t data; |
| 608 | }; |
| 609 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 610 | struct of_experimenter : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 611 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 612 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 613 | uint16_t length; |
| 614 | uint32_t xid; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 615 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 616 | uint32_t subtype; |
| 617 | of_octets_t data; |
| 618 | }; |
| 619 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 620 | struct of_barrier_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 621 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 622 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 623 | uint16_t length; |
| 624 | uint32_t xid; |
| 625 | }; |
| 626 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 627 | struct of_barrier_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 628 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 629 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 630 | uint16_t length; |
| 631 | uint32_t xid; |
| 632 | }; |
| 633 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 634 | struct of_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 635 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 636 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 637 | uint16_t length; |
| 638 | uint32_t xid; |
| 639 | }; |
| 640 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 641 | struct of_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 642 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 643 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 644 | uint16_t length; |
| 645 | uint32_t xid; |
| 646 | uint16_t flags; |
| 647 | uint16_t miss_send_len; |
| 648 | }; |
| 649 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 650 | struct of_set_config : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 651 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 652 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 653 | uint16_t length; |
| 654 | uint32_t xid; |
| 655 | uint16_t flags; |
| 656 | uint16_t miss_send_len; |
| 657 | }; |
| 658 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 659 | struct of_table_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 660 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 661 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 662 | uint16_t length; |
| 663 | uint32_t xid; |
| 664 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 665 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 666 | uint32_t config; |
| 667 | }; |
| 668 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 669 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 670 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 671 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 672 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 673 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 674 | of_port_name_t name; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 675 | enum ofp_port_config config; |
| 676 | enum ofp_port_state state; |
| 677 | enum ofp_port_features curr; |
| 678 | enum ofp_port_features advertised; |
| 679 | enum ofp_port_features supported; |
| 680 | enum ofp_port_features peer; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 681 | uint32_t curr_speed; |
| 682 | uint32_t max_speed; |
| 683 | }; |
| 684 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 685 | struct of_features_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 686 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 687 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 688 | uint16_t length; |
| 689 | uint32_t xid; |
| 690 | }; |
| 691 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 692 | struct of_features_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 693 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 694 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 695 | uint16_t length; |
| 696 | uint32_t xid; |
| 697 | uint64_t datapath_id; |
| 698 | uint32_t n_buffers; |
| 699 | uint8_t n_tables; |
| 700 | uint8_t auxiliary_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 701 | pad(2); |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 702 | enum ofp_capabilities capabilities; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 703 | uint32_t reserved; |
| 704 | }; |
| 705 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 706 | struct of_port_status : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 707 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 708 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 709 | uint16_t length; |
| 710 | uint32_t xid; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 711 | enum ofp_port_reason reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 712 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 713 | of_port_desc_t desc; |
| 714 | }; |
| 715 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 716 | struct of_port_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 717 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 718 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 719 | uint16_t length; |
| 720 | uint32_t xid; |
| 721 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 722 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 723 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 724 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 725 | uint32_t config; |
| 726 | uint32_t mask; |
| 727 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 728 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 729 | }; |
| 730 | |
| 731 | // FIXME Does this need to be v4? |
Andreas Wundsam | fef7d5f | 2013-08-01 22:15:44 -0700 | [diff] [blame] | 732 | struct of_match_v3(align=8) { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 733 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 734 | uint16_t length; |
| 735 | list(of_oxm_t) oxm_list; |
| 736 | }; |
| 737 | |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 738 | // This looks like an action header, but is standalone. See |
| 739 | // ofp_table_features_prop_actions |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 740 | struct of_action_id { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 741 | uint16_t type; |
| 742 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 743 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 744 | }; |
| 745 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 746 | struct of_action_output : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 747 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 748 | uint16_t len; |
| 749 | of_port_no_t port; |
| 750 | uint16_t max_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 751 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 752 | }; |
| 753 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 754 | struct of_action_copy_ttl_out : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 755 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 756 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 757 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 758 | }; |
| 759 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 760 | struct of_action_copy_ttl_in : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 761 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 762 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 763 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 764 | }; |
| 765 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 766 | struct of_action_set_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 767 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 768 | uint16_t len; |
| 769 | uint8_t mpls_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 770 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 771 | }; |
| 772 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 773 | struct of_action_dec_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 774 | uint16_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 775 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 776 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 777 | }; |
| 778 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 779 | struct of_action_push_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 780 | uint16_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 781 | uint16_t len; |
| 782 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 783 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 784 | }; |
| 785 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 786 | struct of_action_pop_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 787 | uint16_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 788 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 789 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 790 | }; |
| 791 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 792 | struct of_action_push_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 793 | uint16_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 794 | uint16_t len; |
| 795 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 796 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 797 | }; |
| 798 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 799 | struct of_action_pop_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 800 | uint16_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 801 | uint16_t len; |
| 802 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 803 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 804 | }; |
| 805 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 806 | struct of_action_set_queue : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 807 | uint16_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 808 | uint16_t len; |
| 809 | uint32_t queue_id; |
| 810 | }; |
| 811 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 812 | struct of_action_group : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 813 | uint16_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 814 | uint16_t len; |
| 815 | uint32_t group_id; |
| 816 | }; |
| 817 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 818 | struct of_action_set_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 819 | uint16_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 820 | uint16_t len; |
| 821 | uint8_t nw_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 822 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 823 | }; |
| 824 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 825 | struct of_action_dec_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 826 | uint16_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 827 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 828 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 829 | }; |
| 830 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 831 | struct of_action_set_field : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 832 | uint16_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 833 | uint16_t len; |
Rich Lane | be90eae | 2013-07-22 16:44:26 -0700 | [diff] [blame] | 834 | of_oxm_t field; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 835 | }; |
| 836 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 837 | struct of_action_experimenter : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 838 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 839 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 840 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 841 | of_octets_t data; |
| 842 | }; |
| 843 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 844 | struct of_action_pop_pbb : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 845 | uint16_t type == 27; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 846 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 847 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 848 | }; |
| 849 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 850 | struct of_action_push_pbb : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 851 | uint16_t type == 26; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 852 | uint16_t len; |
| 853 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 854 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 855 | }; |
| 856 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 857 | struct of_action { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 858 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 859 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 860 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 861 | }; |
| 862 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 863 | struct of_instruction { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 864 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 865 | uint16_t len; |
| 866 | }; |
| 867 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 868 | struct of_instruction_goto_table : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 869 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 870 | uint16_t len; |
| 871 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 872 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 873 | }; |
| 874 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 875 | struct of_instruction_write_metadata : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 876 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 877 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 878 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 879 | uint64_t metadata; |
| 880 | uint64_t metadata_mask; |
| 881 | }; |
| 882 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 883 | struct of_instruction_write_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 884 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 885 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 886 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 887 | list(of_action_t) actions; |
| 888 | }; |
| 889 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 890 | struct of_instruction_apply_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 891 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 892 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 893 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 894 | list(of_action_t) actions; |
| 895 | }; |
| 896 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 897 | struct of_instruction_clear_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 898 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 899 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 900 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 901 | }; |
| 902 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 903 | struct of_instruction_meter : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 904 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 905 | uint16_t len; |
| 906 | uint32_t meter_id; |
| 907 | }; |
| 908 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 909 | struct of_instruction_experimenter : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 910 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 911 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 912 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 913 | of_octets_t data; |
| 914 | }; |
| 915 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 916 | struct of_flow_mod : of_header { |
| 917 | uint8_t version; |
| 918 | uint8_t type == 14; |
| 919 | uint16_t length; |
| 920 | uint32_t xid; |
| 921 | uint64_t cookie; |
| 922 | uint64_t cookie_mask; |
| 923 | uint8_t table_id; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 924 | of_fm_cmd_t _command == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 925 | uint16_t idle_timeout; |
| 926 | uint16_t hard_timeout; |
| 927 | uint16_t priority; |
| 928 | uint32_t buffer_id; |
| 929 | of_port_no_t out_port; |
| 930 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 931 | enum ofp_flow_mod_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 932 | pad(2); |
| 933 | of_match_t match; |
| 934 | list(of_instruction_t) instructions; |
| 935 | }; |
| 936 | |
| 937 | struct of_flow_add : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 938 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 939 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 940 | uint16_t length; |
| 941 | uint32_t xid; |
| 942 | uint64_t cookie; |
| 943 | uint64_t cookie_mask; |
| 944 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 945 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 946 | uint16_t idle_timeout; |
| 947 | uint16_t hard_timeout; |
| 948 | uint16_t priority; |
| 949 | uint32_t buffer_id; |
| 950 | of_port_no_t out_port; |
| 951 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 952 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 953 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 954 | of_match_t match; |
| 955 | list(of_instruction_t) instructions; |
| 956 | }; |
| 957 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 958 | struct of_flow_modify : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 959 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 960 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 961 | uint16_t length; |
| 962 | uint32_t xid; |
| 963 | uint64_t cookie; |
| 964 | uint64_t cookie_mask; |
| 965 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 966 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 967 | uint16_t idle_timeout; |
| 968 | uint16_t hard_timeout; |
| 969 | uint16_t priority; |
| 970 | uint32_t buffer_id; |
| 971 | of_port_no_t out_port; |
| 972 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 973 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 974 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 975 | of_match_t match; |
| 976 | list(of_instruction_t) instructions; |
| 977 | }; |
| 978 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 979 | struct of_flow_modify_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 980 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 981 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 982 | uint16_t length; |
| 983 | uint32_t xid; |
| 984 | uint64_t cookie; |
| 985 | uint64_t cookie_mask; |
| 986 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 987 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 988 | uint16_t idle_timeout; |
| 989 | uint16_t hard_timeout; |
| 990 | uint16_t priority; |
| 991 | uint32_t buffer_id; |
| 992 | of_port_no_t out_port; |
| 993 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 994 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 995 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 996 | of_match_t match; |
| 997 | list(of_instruction_t) instructions; |
| 998 | }; |
| 999 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1000 | struct of_flow_delete : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1001 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1002 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1003 | uint16_t length; |
| 1004 | uint32_t xid; |
| 1005 | uint64_t cookie; |
| 1006 | uint64_t cookie_mask; |
| 1007 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1008 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1009 | uint16_t idle_timeout; |
| 1010 | uint16_t hard_timeout; |
| 1011 | uint16_t priority; |
| 1012 | uint32_t buffer_id; |
| 1013 | of_port_no_t out_port; |
| 1014 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 1015 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1016 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1017 | of_match_t match; |
| 1018 | list(of_instruction_t) instructions; |
| 1019 | }; |
| 1020 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1021 | struct of_flow_delete_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1022 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1023 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1024 | uint16_t length; |
| 1025 | uint32_t xid; |
| 1026 | uint64_t cookie; |
| 1027 | uint64_t cookie_mask; |
| 1028 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1029 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1030 | uint16_t idle_timeout; |
| 1031 | uint16_t hard_timeout; |
| 1032 | uint16_t priority; |
| 1033 | uint32_t buffer_id; |
| 1034 | of_port_no_t out_port; |
| 1035 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 1036 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1037 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1038 | of_match_t match; |
| 1039 | list(of_instruction_t) instructions; |
| 1040 | }; |
| 1041 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1042 | struct of_bucket { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1043 | uint16_t len; |
| 1044 | uint16_t weight; |
| 1045 | of_port_no_t watch_port; |
| 1046 | uint32_t watch_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1047 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1048 | list(of_action_t) actions; |
| 1049 | }; |
| 1050 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1051 | struct of_group_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1052 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1053 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1054 | uint16_t length; |
| 1055 | uint32_t xid; |
| 1056 | uint16_t command; |
| 1057 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1058 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1059 | uint32_t group_id; |
| 1060 | list(of_bucket_t) buckets; |
| 1061 | }; |
| 1062 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1063 | struct of_packet_out : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1064 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1065 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1066 | uint16_t length; |
| 1067 | uint32_t xid; |
| 1068 | uint32_t buffer_id; |
| 1069 | of_port_no_t in_port; |
| 1070 | uint16_t actions_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1071 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1072 | list(of_action_t) actions; |
| 1073 | of_octets_t data; |
| 1074 | }; |
| 1075 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1076 | struct of_packet_in : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1077 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1078 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1079 | uint16_t length; |
| 1080 | uint32_t xid; |
| 1081 | uint32_t buffer_id; |
| 1082 | uint16_t total_len; |
| 1083 | uint8_t reason; |
| 1084 | uint8_t table_id; |
| 1085 | uint64_t cookie; |
| 1086 | of_match_t match; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1087 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1088 | of_octets_t data; /* FIXME: Ensure total_len gets updated */ |
| 1089 | }; |
| 1090 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1091 | struct of_flow_removed : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1092 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1093 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1094 | uint16_t length; |
| 1095 | uint32_t xid; |
| 1096 | uint64_t cookie; |
| 1097 | uint16_t priority; |
| 1098 | uint8_t reason; |
| 1099 | uint8_t table_id; |
| 1100 | uint32_t duration_sec; |
| 1101 | uint32_t duration_nsec; |
| 1102 | uint16_t idle_timeout; |
| 1103 | uint16_t hard_timeout; |
| 1104 | uint64_t packet_count; |
| 1105 | uint64_t byte_count; |
| 1106 | of_match_t match; |
| 1107 | }; |
| 1108 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1109 | struct of_meter_band { |
Andreas Wundsam | 9ba6536 | 2013-08-02 19:14:42 -0700 | [diff] [blame] | 1110 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1111 | uint16_t len; |
| 1112 | // uint32_t rate; // These are excluded b/c this is the header |
| 1113 | // uint32_t burst_size; // These are excluded b/c this is the header |
| 1114 | }; |
| 1115 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1116 | struct of_meter_band_drop : of_meter_band { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1117 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1118 | uint16_t len; |
| 1119 | uint32_t rate; |
| 1120 | uint32_t burst_size; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1121 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1122 | }; |
| 1123 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1124 | struct of_meter_band_dscp_remark : of_meter_band { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1125 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1126 | uint16_t len; |
| 1127 | uint32_t rate; |
| 1128 | uint32_t burst_size; |
| 1129 | uint8_t prec_level; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1130 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1131 | }; |
| 1132 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1133 | struct of_meter_band_experimenter : of_meter_band { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1134 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1135 | uint16_t len; |
| 1136 | uint32_t rate; |
| 1137 | uint32_t burst_size; |
| 1138 | uint32_t experimenter; |
| 1139 | }; |
| 1140 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1141 | struct of_meter_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1142 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1143 | uint8_t type == 29; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1144 | uint16_t length; |
| 1145 | uint32_t xid; |
| 1146 | uint16_t command; |
| 1147 | uint16_t flags; |
| 1148 | uint32_t meter_id; |
| 1149 | list(of_meter_band_t) meters; |
| 1150 | }; |
| 1151 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1152 | struct of_error_msg : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1153 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1154 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1155 | uint16_t length; |
| 1156 | uint32_t xid; |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 1157 | uint16_t err_type == ?; |
| 1158 | }; |
| 1159 | |
| 1160 | struct of_hello_failed_error_msg : of_error_msg { |
| 1161 | uint8_t version; |
| 1162 | uint8_t type == 1; |
| 1163 | uint16_t length; |
| 1164 | uint32_t xid; |
| 1165 | uint16_t err_type == 0; |
| 1166 | enum ofp_hello_failed_code code; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1167 | of_octets_t data; |
| 1168 | }; |
| 1169 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 1170 | struct of_bad_request_error_msg : of_error_msg { |
| 1171 | uint8_t version; |
| 1172 | uint8_t type == 1; |
| 1173 | uint16_t length; |
| 1174 | uint32_t xid; |
| 1175 | uint16_t err_type == 1; |
| 1176 | enum ofp_bad_request_code code; |
| 1177 | of_octets_t data; |
| 1178 | }; |
| 1179 | |
| 1180 | struct of_bad_action_error_msg : of_error_msg { |
| 1181 | uint8_t version; |
| 1182 | uint8_t type == 1; |
| 1183 | uint16_t length; |
| 1184 | uint32_t xid; |
| 1185 | uint16_t err_type == 2; |
| 1186 | enum ofp_bad_action_code code; |
| 1187 | of_octets_t data; |
| 1188 | }; |
| 1189 | |
| 1190 | struct of_bad_instruction_error_msg : of_error_msg { |
| 1191 | uint8_t version; |
| 1192 | uint8_t type == 1; |
| 1193 | uint16_t length; |
| 1194 | uint32_t xid; |
| 1195 | uint16_t err_type == 3; |
| 1196 | enum ofp_bad_instruction_code code; |
| 1197 | of_octets_t data; |
| 1198 | }; |
| 1199 | |
| 1200 | struct of_bad_match_error_msg : of_error_msg { |
| 1201 | uint8_t version; |
| 1202 | uint8_t type == 1; |
| 1203 | uint16_t length; |
| 1204 | uint32_t xid; |
| 1205 | uint16_t err_type == 4; |
| 1206 | enum ofp_bad_match_code code; |
| 1207 | of_octets_t data; |
| 1208 | }; |
| 1209 | |
| 1210 | struct of_flow_mod_failed_error_msg : of_error_msg { |
| 1211 | uint8_t version; |
| 1212 | uint8_t type == 1; |
| 1213 | uint16_t length; |
| 1214 | uint32_t xid; |
| 1215 | uint16_t err_type == 5; |
| 1216 | enum ofp_flow_mod_failed_code code; |
| 1217 | of_octets_t data; |
| 1218 | }; |
| 1219 | |
| 1220 | struct of_group_mod_failed_error_msg : of_error_msg { |
| 1221 | uint8_t version; |
| 1222 | uint8_t type == 1; |
| 1223 | uint16_t length; |
| 1224 | uint32_t xid; |
| 1225 | uint16_t err_type == 6; |
| 1226 | enum ofp_group_mod_failed_code code; |
| 1227 | of_octets_t data; |
| 1228 | }; |
| 1229 | |
| 1230 | struct of_port_mod_failed_error_msg : of_error_msg { |
| 1231 | uint8_t version; |
| 1232 | uint8_t type == 1; |
| 1233 | uint16_t length; |
| 1234 | uint32_t xid; |
| 1235 | uint16_t err_type == 7; |
| 1236 | enum ofp_port_mod_failed_code code; |
| 1237 | of_octets_t data; |
| 1238 | }; |
| 1239 | |
| 1240 | struct of_table_mod_failed_error_msg : of_error_msg { |
| 1241 | uint8_t version; |
| 1242 | uint8_t type == 1; |
| 1243 | uint16_t length; |
| 1244 | uint32_t xid; |
| 1245 | uint16_t err_type == 8; |
| 1246 | enum ofp_table_mod_failed_code code; |
| 1247 | of_octets_t data; |
| 1248 | }; |
| 1249 | |
| 1250 | struct of_queue_op_failed_error_msg : of_error_msg { |
| 1251 | uint8_t version; |
| 1252 | uint8_t type == 1; |
| 1253 | uint16_t length; |
| 1254 | uint32_t xid; |
| 1255 | uint16_t err_type == 9; |
| 1256 | enum ofp_queue_op_failed_code code; |
| 1257 | of_octets_t data; |
| 1258 | }; |
| 1259 | |
| 1260 | struct of_switch_config_failed_error_msg : of_error_msg { |
| 1261 | uint8_t version; |
| 1262 | uint8_t type == 1; |
| 1263 | uint16_t length; |
| 1264 | uint32_t xid; |
| 1265 | uint16_t err_type == 10; |
| 1266 | enum ofp_switch_config_failed_code code; |
| 1267 | of_octets_t data; |
| 1268 | }; |
| 1269 | |
| 1270 | struct of_role_request_failed_error_msg : of_error_msg { |
| 1271 | uint8_t version; |
| 1272 | uint8_t type == 1; |
| 1273 | uint16_t length; |
| 1274 | uint32_t xid; |
| 1275 | uint16_t err_type == 11; |
| 1276 | enum ofp_role_request_failed_code code; |
| 1277 | of_octets_t data; |
| 1278 | }; |
| 1279 | |
| 1280 | struct of_meter_mod_failed_error_msg : of_error_msg { |
| 1281 | uint8_t version; |
| 1282 | uint8_t type == 1; |
| 1283 | uint16_t length; |
| 1284 | uint32_t xid; |
| 1285 | uint16_t err_type == 12; |
| 1286 | enum ofp_meter_mod_failed_code code; |
| 1287 | of_octets_t data; |
| 1288 | }; |
| 1289 | |
| 1290 | struct of_table_features_failed_error_msg : of_error_msg { |
| 1291 | uint8_t version; |
| 1292 | uint8_t type == 1; |
| 1293 | uint16_t length; |
| 1294 | uint32_t xid; |
| 1295 | uint16_t err_type == 13; |
| 1296 | enum ofp_table_features_failed_code code; |
| 1297 | of_octets_t data; |
| 1298 | }; |
| 1299 | |
| 1300 | struct of_experimenter_error_msg { |
| 1301 | uint8_t version; |
| 1302 | uint8_t type == 1; |
| 1303 | uint16_t length; |
| 1304 | uint32_t xid; |
| 1305 | uint16_t err_type == 0xffff; |
| 1306 | uint16_t subtype; |
| 1307 | uint32_t experimenter; |
| 1308 | of_octets_t data; |
| 1309 | }; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1310 | |
| 1311 | // STATS ENTRIES: flow, table, port, queue, group stats, group desc stats |
| 1312 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1313 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1314 | uint16_t length; |
| 1315 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1316 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1317 | uint32_t duration_sec; |
| 1318 | uint32_t duration_nsec; |
| 1319 | uint16_t priority; |
| 1320 | uint16_t idle_timeout; |
| 1321 | uint16_t hard_timeout; |
Rich Lane | 1a47c1c | 2013-08-28 15:27:00 -0700 | [diff] [blame] | 1322 | uint16_t flags; |
| 1323 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1324 | uint64_t cookie; |
| 1325 | uint64_t packet_count; |
| 1326 | uint64_t byte_count; |
| 1327 | of_match_t match; |
| 1328 | list(of_instruction_t) instructions; |
| 1329 | }; |
| 1330 | |
| 1331 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1332 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1333 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1334 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1335 | uint32_t active_count; |
| 1336 | uint64_t lookup_count; |
| 1337 | uint64_t matched_count; |
| 1338 | }; |
| 1339 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1340 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1341 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1342 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1343 | uint64_t rx_packets; |
| 1344 | uint64_t tx_packets; |
| 1345 | uint64_t rx_bytes; |
| 1346 | uint64_t tx_bytes; |
| 1347 | uint64_t rx_dropped; |
| 1348 | uint64_t tx_dropped; |
| 1349 | uint64_t rx_errors; |
| 1350 | uint64_t tx_errors; |
| 1351 | uint64_t rx_frame_err; |
| 1352 | uint64_t rx_over_err; |
| 1353 | uint64_t rx_crc_err; |
| 1354 | uint64_t collisions; |
| 1355 | uint32_t duration_sec; |
| 1356 | uint32_t duration_nsec; |
| 1357 | }; |
| 1358 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1359 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1360 | of_port_no_t port_no; |
| 1361 | uint32_t queue_id; |
| 1362 | uint64_t tx_bytes; |
| 1363 | uint64_t tx_packets; |
| 1364 | uint64_t tx_errors; |
| 1365 | uint32_t duration_sec; |
| 1366 | uint32_t duration_nsec; |
| 1367 | }; |
| 1368 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1369 | struct of_bucket_counter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1370 | uint64_t packet_count; |
| 1371 | uint64_t byte_count; |
| 1372 | }; |
| 1373 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1374 | struct of_group_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1375 | uint16_t length; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1376 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1377 | uint32_t group_id; |
| 1378 | uint32_t ref_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1379 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1380 | uint64_t packet_count; |
| 1381 | uint64_t byte_count; |
| 1382 | uint32_t duration_sec; |
| 1383 | uint32_t duration_nsec; |
| 1384 | list(of_bucket_counter_t) bucket_stats; |
| 1385 | }; |
| 1386 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1387 | struct of_group_desc_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1388 | uint16_t length; |
Rich Lane | 35e7ac7 | 2013-10-15 10:36:10 -0700 | [diff] [blame] | 1389 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1390 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1391 | uint32_t group_id; |
| 1392 | list(of_bucket_t) buckets; |
| 1393 | }; |
| 1394 | |
| 1395 | // STATS: |
| 1396 | // Desc, flow, agg, table, port, queue, group, group_desc, group_feat, experi |
| 1397 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1398 | struct of_stats_request : of_header { |
| 1399 | uint8_t version; |
| 1400 | uint8_t type == 18; |
| 1401 | uint16_t length; |
| 1402 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1403 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1404 | uint16_t flags; |
| 1405 | pad(4); |
| 1406 | }; |
| 1407 | |
| 1408 | struct of_stats_reply : of_header { |
| 1409 | uint8_t version; |
| 1410 | uint8_t type == 19; |
| 1411 | uint16_t length; |
| 1412 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1413 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1414 | uint16_t flags; |
| 1415 | pad(4); |
| 1416 | }; |
| 1417 | |
| 1418 | struct of_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1419 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1420 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1421 | uint16_t length; |
| 1422 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1423 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1424 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1425 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1426 | }; |
| 1427 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1428 | struct of_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1429 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1430 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1431 | uint16_t length; |
| 1432 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1433 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1434 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1435 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1436 | of_desc_str_t mfr_desc; |
| 1437 | of_desc_str_t hw_desc; |
| 1438 | of_desc_str_t sw_desc; |
| 1439 | of_serial_num_t serial_num; |
| 1440 | of_desc_str_t dp_desc; |
| 1441 | }; |
| 1442 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1443 | struct of_flow_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1444 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1445 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1446 | uint16_t length; |
| 1447 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1448 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1449 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1450 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1451 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1452 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1453 | of_port_no_t out_port; |
| 1454 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1455 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1456 | uint64_t cookie; |
| 1457 | uint64_t cookie_mask; |
| 1458 | of_match_t match; |
| 1459 | }; |
| 1460 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1461 | struct of_flow_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1462 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1463 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1464 | uint16_t length; |
| 1465 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1466 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1467 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1468 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1469 | list(of_flow_stats_entry_t) entries; |
| 1470 | }; |
| 1471 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1472 | struct of_aggregate_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1473 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1474 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1475 | uint16_t length; |
| 1476 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1477 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1478 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1479 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1480 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1481 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1482 | of_port_no_t out_port; |
| 1483 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1484 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1485 | uint64_t cookie; |
| 1486 | uint64_t cookie_mask; |
| 1487 | of_match_t match; |
| 1488 | }; |
| 1489 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1490 | struct of_aggregate_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1491 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1492 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1493 | uint16_t length; |
| 1494 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1495 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1496 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1497 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1498 | uint64_t packet_count; |
| 1499 | uint64_t byte_count; |
| 1500 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1501 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1502 | }; |
| 1503 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1504 | struct of_table_stats_request : of_stats_request { |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1505 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1506 | uint8_t type == 18; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1507 | uint16_t length; |
| 1508 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1509 | uint16_t stats_type == 3; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1510 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1511 | pad(4); |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1512 | }; |
| 1513 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1514 | struct of_table_stats_reply : of_stats_reply { |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1515 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1516 | uint8_t type == 19; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1517 | uint16_t length; |
| 1518 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1519 | uint16_t stats_type == 3; |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1520 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1521 | pad(4); |
Rich Lane | 8bfdafc | 2013-05-02 14:54:42 -0700 | [diff] [blame] | 1522 | list(of_table_stats_entry_t) entries; |
| 1523 | }; |
| 1524 | |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1525 | // FIXME: These are padded to 8 byte align beyond the length indicated |
| 1526 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1527 | struct of_table_feature_prop { |
Rich Lane | a1b8f44 | 2013-10-01 22:05:22 -0700 | [diff] [blame] | 1528 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1529 | uint16_t length; |
| 1530 | }; |
| 1531 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1532 | struct of_table_feature_prop_instructions : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1533 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1534 | uint16_t length; |
| 1535 | // FIXME Check if instruction_t is right for ids here |
| 1536 | list(of_instruction_t) instruction_ids; |
| 1537 | }; |
| 1538 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1539 | struct of_table_feature_prop_instructions_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1540 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1541 | uint16_t length; |
| 1542 | list(of_instruction_t) instruction_ids; |
| 1543 | }; |
| 1544 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1545 | struct of_table_feature_prop_next_tables : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1546 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1547 | uint16_t length; |
| 1548 | list(of_uint8_t) next_table_ids; |
| 1549 | }; |
| 1550 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1551 | struct of_table_feature_prop_next_tables_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1552 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1553 | uint16_t length; |
| 1554 | list(of_uint8_t) next_table_ids; |
| 1555 | }; |
| 1556 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1557 | struct of_table_feature_prop_write_actions : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1558 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1559 | uint16_t length; |
| 1560 | list(of_action_id_t) action_ids; |
| 1561 | }; |
| 1562 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1563 | struct of_table_feature_prop_write_actions_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1564 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1565 | uint16_t length; |
| 1566 | list(of_action_id_t) action_ids; |
| 1567 | }; |
| 1568 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1569 | struct of_table_feature_prop_apply_actions : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1570 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1571 | uint16_t length; |
| 1572 | list(of_action_id_t) action_ids; |
| 1573 | }; |
| 1574 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1575 | struct of_table_feature_prop_apply_actions_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1576 | uint16_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1577 | uint16_t length; |
| 1578 | list(of_action_id_t) action_ids; |
| 1579 | }; |
| 1580 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1581 | struct of_table_feature_prop_match : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1582 | uint16_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1583 | uint16_t length; |
| 1584 | list(of_uint32_t) oxm_ids; |
| 1585 | }; |
| 1586 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1587 | struct of_table_feature_prop_wildcards : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1588 | uint16_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1589 | uint16_t length; |
| 1590 | list(of_uint32_t) oxm_ids; |
| 1591 | }; |
| 1592 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1593 | struct of_table_feature_prop_write_setfield : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1594 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1595 | uint16_t length; |
| 1596 | list(of_uint32_t) oxm_ids; |
| 1597 | }; |
| 1598 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1599 | struct of_table_feature_prop_write_setfield_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1600 | uint16_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1601 | uint16_t length; |
| 1602 | list(of_uint32_t) oxm_ids; |
| 1603 | }; |
| 1604 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1605 | struct of_table_feature_prop_apply_setfield : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1606 | uint16_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1607 | uint16_t length; |
| 1608 | list(of_uint32_t) oxm_ids; |
| 1609 | }; |
| 1610 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1611 | struct of_table_feature_prop_apply_setfield_miss : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1612 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1613 | uint16_t length; |
| 1614 | list(of_uint32_t) oxm_ids; |
| 1615 | }; |
| 1616 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1617 | struct of_table_feature_prop_experimenter : of_table_feature_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1618 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1619 | uint16_t length; |
| 1620 | uint32_t experimenter; |
| 1621 | uint32_t subtype; |
| 1622 | of_octets_t experimenter_data; |
| 1623 | }; |
| 1624 | |
| 1625 | // Not yet supported |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1626 | // struct of_table_feature_prop_experimenter_miss : of_table_feature_prop { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1627 | // uint16_t type; |
| 1628 | // uint16_t length; |
| 1629 | // uint32_t experimenter; |
| 1630 | // uint32_t subtype; |
| 1631 | // of_octets_t experimenter_data; |
| 1632 | // }; |
| 1633 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1634 | struct of_table_features { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1635 | uint16_t length; |
| 1636 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1637 | pad(5); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1638 | of_table_name_t name; |
| 1639 | uint64_t metadata_match; |
| 1640 | uint64_t metadata_write; |
| 1641 | uint32_t config; |
| 1642 | uint32_t max_entries; |
| 1643 | list(of_table_feature_prop_t) properties; |
| 1644 | }; |
| 1645 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1646 | struct of_meter_features { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1647 | uint32_t max_meter; |
| 1648 | uint32_t band_types; |
| 1649 | uint32_t capabilities; |
| 1650 | uint8_t max_bands; |
| 1651 | uint8_t max_color; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1652 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1653 | }; |
| 1654 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1655 | struct of_port_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1656 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1657 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1658 | uint16_t length; |
| 1659 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1660 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1661 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1662 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1663 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1664 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1665 | }; |
| 1666 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1667 | struct of_port_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1668 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1669 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1670 | uint16_t length; |
| 1671 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1672 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1673 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1674 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1675 | list(of_port_stats_entry_t) entries; |
| 1676 | }; |
| 1677 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1678 | struct of_queue_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1679 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1680 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1681 | uint16_t length; |
| 1682 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1683 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1684 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1685 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1686 | of_port_no_t port_no; |
| 1687 | uint32_t queue_id; |
| 1688 | }; |
| 1689 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1690 | struct of_queue_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1691 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1692 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1693 | uint16_t length; |
| 1694 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1695 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1696 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1697 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1698 | list(of_queue_stats_entry_t) entries; |
| 1699 | }; |
| 1700 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1701 | struct of_group_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1702 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1703 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1704 | uint16_t length; |
| 1705 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1706 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1707 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1708 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1709 | uint32_t group_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1710 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1711 | }; |
| 1712 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1713 | struct of_group_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1714 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1715 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1716 | uint16_t length; |
| 1717 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1718 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1719 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1720 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1721 | list(of_group_stats_entry_t) entries; |
| 1722 | }; |
| 1723 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1724 | struct of_group_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1725 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1726 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1727 | uint16_t length; |
| 1728 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1729 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1730 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1731 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1732 | }; |
| 1733 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1734 | struct of_group_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1735 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1736 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1737 | uint16_t length; |
| 1738 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1739 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1740 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1741 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1742 | list(of_group_desc_stats_entry_t) entries; |
| 1743 | }; |
| 1744 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1745 | struct of_group_features_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1746 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1747 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1748 | uint16_t length; |
| 1749 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1750 | uint16_t stats_type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1751 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1752 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1753 | }; |
| 1754 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1755 | struct of_group_features_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1756 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1757 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1758 | uint16_t length; |
| 1759 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1760 | uint16_t stats_type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1761 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1762 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1763 | uint32_t types; |
| 1764 | uint32_t capabilities; |
| 1765 | uint32_t max_groups_all; |
| 1766 | uint32_t max_groups_select; |
| 1767 | uint32_t max_groups_indirect; |
| 1768 | uint32_t max_groups_ff; |
| 1769 | uint32_t actions_all; |
| 1770 | uint32_t actions_select; |
| 1771 | uint32_t actions_indirect; |
| 1772 | uint32_t actions_ff; |
| 1773 | }; |
| 1774 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1775 | struct of_meter_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1776 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1777 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1778 | uint16_t length; |
| 1779 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1780 | uint16_t stats_type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1781 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1782 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1783 | uint32_t meter_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1784 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1785 | }; |
| 1786 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1787 | struct of_meter_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1788 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1789 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1790 | uint16_t length; |
| 1791 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1792 | uint16_t stats_type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1793 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1794 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1795 | list(of_meter_stats_t) entries; |
| 1796 | }; |
| 1797 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1798 | struct of_meter_config_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1799 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1800 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1801 | uint16_t length; |
| 1802 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1803 | uint16_t stats_type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1804 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1805 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1806 | uint32_t meter_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1807 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1808 | }; |
| 1809 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1810 | struct of_meter_config_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1811 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1812 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1813 | uint16_t length; |
| 1814 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1815 | uint16_t stats_type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1816 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1817 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1818 | list(of_meter_band_t) entries; |
| 1819 | }; |
| 1820 | |
| 1821 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1822 | struct of_meter_features_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1823 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1824 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1825 | uint16_t length; |
| 1826 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1827 | uint16_t stats_type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1828 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1829 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1830 | }; |
| 1831 | |
| 1832 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1833 | struct of_meter_features_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1834 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1835 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1836 | uint16_t length; |
| 1837 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1838 | uint16_t stats_type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1839 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1840 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1841 | of_meter_features_t features; |
| 1842 | }; |
| 1843 | |
| 1844 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1845 | struct of_table_features_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1846 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1847 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1848 | uint16_t length; |
| 1849 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1850 | uint16_t stats_type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1851 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1852 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1853 | list(of_table_features_t) entries; |
| 1854 | }; |
| 1855 | |
| 1856 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1857 | struct of_table_features_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1858 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1859 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1860 | uint16_t length; |
| 1861 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1862 | uint16_t stats_type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1863 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1864 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1865 | list(of_table_features_t) entries; |
| 1866 | }; |
| 1867 | |
| 1868 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1869 | struct of_port_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1870 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1871 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1872 | uint16_t length; |
| 1873 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1874 | uint16_t stats_type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1875 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1876 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1877 | }; |
| 1878 | |
| 1879 | // FIXME stats added to get things working |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1880 | struct of_port_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1881 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1882 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1883 | uint16_t length; |
| 1884 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1885 | uint16_t stats_type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1886 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1887 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1888 | list(of_port_desc_t) entries; |
| 1889 | }; |
| 1890 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1891 | struct of_meter_band_stats { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1892 | uint64_t packet_band_count; |
| 1893 | uint64_t byte_band_count; |
| 1894 | }; |
| 1895 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1896 | struct of_meter_stats { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1897 | uint32_t meter_id; |
| 1898 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1899 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1900 | uint32_t flow_count; |
| 1901 | uint64_t packet_in_count; |
| 1902 | uint64_t byte_in_count; |
| 1903 | uint32_t duration_sec; |
| 1904 | uint32_t duration_nsec; |
| 1905 | list(of_meter_band_stats_t) band_stats; |
| 1906 | }; |
| 1907 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1908 | struct of_meter_config { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1909 | uint16_t length; |
| 1910 | uint16_t flags; |
| 1911 | uint32_t meter_id; |
| 1912 | list(of_meter_band_t) entries; |
| 1913 | }; |
| 1914 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 1915 | struct of_experimenter_stats_header { |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1916 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1917 | uint32_t subtype; |
| 1918 | }; |
| 1919 | |
| 1920 | // END OF STATS OBJECTS |
| 1921 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1922 | struct of_queue_prop { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1923 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1924 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1925 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1926 | }; |
| 1927 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1928 | struct of_queue_prop_min_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1929 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1930 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1931 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1932 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1933 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1934 | }; |
| 1935 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1936 | struct of_queue_prop_max_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1937 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1938 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1939 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1940 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1941 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1942 | }; |
| 1943 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1944 | struct of_queue_prop_experimenter : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1945 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1946 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1947 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1948 | uint32_t experimenter == ?; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1949 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1950 | of_octets_t data; |
| 1951 | }; |
| 1952 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1953 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1954 | uint32_t queue_id; |
| 1955 | of_port_no_t port; |
| 1956 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1957 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1958 | list(of_queue_prop_t) properties; |
| 1959 | }; |
| 1960 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1961 | struct of_queue_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1962 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1963 | uint8_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1964 | uint16_t length; |
| 1965 | uint32_t xid; |
| 1966 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1967 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1968 | }; |
| 1969 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1970 | struct of_queue_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1971 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1972 | uint8_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1973 | uint16_t length; |
| 1974 | uint32_t xid; |
| 1975 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1976 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1977 | list(of_packet_queue_t) queues; |
| 1978 | }; |
| 1979 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1980 | struct of_role_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1981 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1982 | uint8_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1983 | uint16_t length; |
| 1984 | uint32_t xid; |
| 1985 | uint32_t role; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1986 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1987 | uint64_t generation_id; |
| 1988 | }; |
| 1989 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1990 | struct of_role_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1991 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1992 | uint8_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1993 | uint16_t length; |
| 1994 | uint32_t xid; |
| 1995 | of_octets_t data; |
| 1996 | }; |
| 1997 | |
| 1998 | //////////////////////////////////////////////////////////////// |
| 1999 | // FIXME understand async; where do bitmasks live? |
| 2000 | // Determine bitmap type for masks below. |
| 2001 | // DOCUMENT masks where uint32_t[0] is interest for equal/master |
| 2002 | // while uint32_t[1] is interest for slave |
| 2003 | //////////////////////////////////////////////////////////////// |
| 2004 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 2005 | struct of_async_get_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 2006 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 2007 | uint8_t type == 26; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 2008 | uint16_t length; |
| 2009 | uint32_t xid; |
| 2010 | uint32_t packet_in_mask_equal_master; |
| 2011 | uint32_t packet_in_mask_slave; |
| 2012 | uint32_t port_status_mask_equal_master; |
| 2013 | uint32_t port_status_mask_slave; |
| 2014 | uint32_t flow_removed_mask_equal_master; |
| 2015 | uint32_t flow_removed_mask_slave; |
| 2016 | }; |
| 2017 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 2018 | struct of_async_get_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 2019 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 2020 | uint8_t type == 27; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 2021 | uint16_t length; |
| 2022 | uint32_t xid; |
| 2023 | uint32_t packet_in_mask_equal_master; |
| 2024 | uint32_t packet_in_mask_slave; |
| 2025 | uint32_t port_status_mask_equal_master; |
| 2026 | uint32_t port_status_mask_slave; |
| 2027 | uint32_t flow_removed_mask_equal_master; |
| 2028 | uint32_t flow_removed_mask_slave; |
| 2029 | }; |
| 2030 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 2031 | struct of_async_set : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 2032 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 2033 | uint8_t type == 28; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 2034 | uint16_t length; |
| 2035 | uint32_t xid; |
| 2036 | uint32_t packet_in_mask_equal_master; |
| 2037 | uint32_t packet_in_mask_slave; |
| 2038 | uint32_t port_status_mask_equal_master; |
| 2039 | uint32_t port_status_mask_slave; |
| 2040 | uint32_t flow_removed_mask_equal_master; |
| 2041 | uint32_t flow_removed_mask_slave; |
| 2042 | }; |