Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 3 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
Wilson Ng | d72013d | 2013-09-29 10:21:48 -0700 | [diff] [blame] | 38 | OFP_TCP_PORT = 6653, |
| 39 | OFP_SSL_PORT = 6653, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFP_VLAN_NONE = 0, |
| 46 | |
| 47 | OFP_FLOW_PERMANENT = 0, |
| 48 | |
| 49 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 50 | |
| 51 | OFP_NO_BUFFER = 0xffffffff, |
| 52 | |
| 53 | DESC_STR_LEN = 256, |
| 54 | SERIAL_NUM_LEN = 32, |
| 55 | |
| 56 | OFPQ_ALL = 0xffffffff, |
| 57 | |
| 58 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 59 | OFPQ_MAX_RATE_UNCFG = 0xffff, |
| 60 | }; |
| 61 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 62 | enum ofp_port(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 63 | OFPP_MAX = 0xffffff00, |
| 64 | OFPP_IN_PORT = 0xfffffff8, |
| 65 | OFPP_TABLE = 0xfffffff9, |
| 66 | OFPP_NORMAL = 0xfffffffa, |
| 67 | OFPP_FLOOD = 0xfffffffb, |
| 68 | OFPP_ALL = 0xfffffffc, |
| 69 | OFPP_CONTROLLER = 0xfffffffd, |
| 70 | OFPP_LOCAL = 0xfffffffe, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 71 | OFPP_ANY = 0xffffffff, |
| 72 | }; |
| 73 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 74 | enum ofp_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 75 | OFPT_HELLO = 0, |
| 76 | OFPT_ERROR = 1, |
| 77 | OFPT_ECHO_REQUEST = 2, |
| 78 | OFPT_ECHO_REPLY = 3, |
| 79 | OFPT_EXPERIMENTER = 4, |
| 80 | OFPT_FEATURES_REQUEST = 5, |
| 81 | OFPT_FEATURES_REPLY = 6, |
| 82 | OFPT_GET_CONFIG_REQUEST = 7, |
| 83 | OFPT_GET_CONFIG_REPLY = 8, |
| 84 | OFPT_SET_CONFIG = 9, |
| 85 | OFPT_PACKET_IN = 10, |
| 86 | OFPT_FLOW_REMOVED = 11, |
| 87 | OFPT_PORT_STATUS = 12, |
| 88 | OFPT_PACKET_OUT = 13, |
| 89 | OFPT_FLOW_MOD = 14, |
| 90 | OFPT_GROUP_MOD = 15, |
| 91 | OFPT_PORT_MOD = 16, |
| 92 | OFPT_TABLE_MOD = 17, |
| 93 | OFPT_STATS_REQUEST = 18, |
| 94 | OFPT_STATS_REPLY = 19, |
| 95 | OFPT_BARRIER_REQUEST = 20, |
| 96 | OFPT_BARRIER_REPLY = 21, |
| 97 | OFPT_QUEUE_GET_CONFIG_REQUEST = 22, |
| 98 | OFPT_QUEUE_GET_CONFIG_REPLY = 23, |
| 99 | OFPT_ROLE_REQUEST = 24, |
| 100 | OFPT_ROLE_REPLY = 25, |
| 101 | }; |
| 102 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 103 | enum ofp_config_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 104 | OFPC_FRAG_NORMAL = 0, |
| 105 | OFPC_FRAG_DROP = 1, |
| 106 | OFPC_FRAG_REASM = 2, |
| 107 | OFPC_FRAG_MASK = 3, |
| 108 | OFPC_INVALID_TTL_TO_CONTROLLER = 4, |
| 109 | }; |
| 110 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 111 | enum ofp_table_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 112 | OFPTC_TABLE_MISS_CONTROLLER = 0, |
| 113 | OFPTC_TABLE_MISS_CONTINUE = 1, |
| 114 | OFPTC_TABLE_MISS_DROP = 2, |
| 115 | OFPTC_TABLE_MISS_MASK = 3, |
| 116 | }; |
| 117 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 118 | enum ofp_table(wire_type=uint8_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 119 | OFPTT_MAX = 0xfe, |
| 120 | OFPTT_ALL = 0xff, |
| 121 | }; |
| 122 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 123 | enum ofp_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 124 | OFPC_FLOW_STATS = 0x1, |
| 125 | OFPC_TABLE_STATS = 0x2, |
| 126 | OFPC_PORT_STATS = 0x4, |
| 127 | OFPC_GROUP_STATS = 0x8, |
| 128 | OFPC_IP_REASM = 0x20, |
| 129 | OFPC_QUEUE_STATS = 0x40, |
| 130 | OFPC_PORT_BLOCKED = 0x100, |
| 131 | }; |
| 132 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 133 | enum ofp_port_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 134 | OFPPC_PORT_DOWN = 0x1, |
| 135 | OFPPC_NO_RECV = 0x4, |
| 136 | OFPPC_NO_FWD = 0x20, |
| 137 | OFPPC_NO_PACKET_IN = 0x40, |
| 138 | }; |
| 139 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 140 | enum ofp_port_state(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 141 | OFPPS_LINK_DOWN = 0x1, |
| 142 | OFPPS_BLOCKED = 0x2, |
| 143 | OFPPS_LIVE = 0x4, |
| 144 | }; |
| 145 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 146 | enum ofp_port_features(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 147 | OFPPF_10MB_HD = 0x1, |
| 148 | OFPPF_10MB_FD = 0x2, |
| 149 | OFPPF_100MB_HD = 0x4, |
| 150 | OFPPF_100MB_FD = 0x8, |
| 151 | OFPPF_1GB_HD = 0x10, |
| 152 | OFPPF_1GB_FD = 0x20, |
| 153 | OFPPF_10GB_FD = 0x40, |
| 154 | OFPPF_40GB_FD = 0x80, |
| 155 | OFPPF_100GB_FD = 0x100, |
| 156 | OFPPF_1TB_FD = 0x200, |
| 157 | OFPPF_OTHER = 0x400, |
| 158 | OFPPF_COPPER = 0x800, |
| 159 | OFPPF_FIBER = 0x1000, |
| 160 | OFPPF_AUTONEG = 0x2000, |
| 161 | OFPPF_PAUSE = 0x4000, |
| 162 | OFPPF_PAUSE_ASYM = 0x8000, |
| 163 | }; |
| 164 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 165 | enum ofp_port_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 166 | OFPPR_ADD = 0, |
| 167 | OFPPR_DELETE = 1, |
| 168 | OFPPR_MODIFY = 2, |
| 169 | }; |
| 170 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 171 | enum ofp_match_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 172 | OFPMT_STANDARD = 0, |
| 173 | OFPMT_OXM = 1, |
| 174 | }; |
| 175 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 176 | enum ofp_oxm_class(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 177 | OFPXMC_NXM_0 = 0, |
| 178 | OFPXMC_NXM_1 = 1, |
| 179 | OFPXMC_OPENFLOW_BASIC = 0x8000, |
| 180 | OFPXMC_EXPERIMENTER = 0xffff, |
| 181 | }; |
| 182 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 183 | enum ofp_vlan_id(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 184 | OFPVID_NONE = 0, |
| 185 | OFPVID_PRESENT = 0x1000, |
| 186 | }; |
| 187 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 188 | enum ofp_action_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 189 | OFPAT_OUTPUT = 0, |
| 190 | OFPAT_COPY_TTL_OUT = 0xb, |
| 191 | OFPAT_COPY_TTL_IN = 0xc, |
| 192 | OFPAT_SET_MPLS_TTL = 0xf, |
| 193 | OFPAT_DEC_MPLS_TTL = 0x10, |
| 194 | OFPAT_PUSH_VLAN = 0x11, |
| 195 | OFPAT_POP_VLAN = 0x12, |
| 196 | OFPAT_PUSH_MPLS = 0x13, |
| 197 | OFPAT_POP_MPLS = 0x14, |
| 198 | OFPAT_SET_QUEUE = 0x15, |
| 199 | OFPAT_GROUP = 0x16, |
| 200 | OFPAT_SET_NW_TTL = 0x17, |
| 201 | OFPAT_DEC_NW_TTL = 0x18, |
| 202 | OFPAT_SET_FIELD = 0x19, |
| 203 | OFPAT_EXPERIMENTER = 0xffff, |
| 204 | }; |
| 205 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 206 | enum ofp_controller_max_len(wire_type=uint16_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 207 | OFPCML_MAX = 0xffe5, |
| 208 | OFPCML_NO_BUFFER = 0xffff, |
| 209 | }; |
| 210 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 211 | enum ofp_instruction_type(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 212 | OFPIT_GOTO_TABLE = 0x1, |
| 213 | OFPIT_WRITE_METADATA = 0x2, |
| 214 | OFPIT_WRITE_ACTIONS = 0x3, |
| 215 | OFPIT_APPLY_ACTIONS = 0x4, |
| 216 | OFPIT_CLEAR_ACTIONS = 0x5, |
| 217 | OFPIT_EXPERIMENTER = 0xffff, |
| 218 | }; |
| 219 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 220 | enum ofp_flow_mod_command(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 221 | OFPFC_ADD = 0, |
| 222 | OFPFC_MODIFY = 1, |
| 223 | OFPFC_MODIFY_STRICT = 2, |
| 224 | OFPFC_DELETE = 3, |
| 225 | OFPFC_DELETE_STRICT = 4, |
| 226 | }; |
| 227 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 228 | enum ofp_flow_mod_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 229 | OFPFF_SEND_FLOW_REM = 0x1, |
| 230 | OFPFF_CHECK_OVERLAP = 0x2, |
| 231 | OFPFF_RESET_COUNTS = 0x4, |
| 232 | }; |
| 233 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 234 | enum ofp_group(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 235 | OFPG_MAX = 0xffffff00, |
| 236 | OFPG_ALL = 0xfffffffc, |
| 237 | OFPG_ANY = 0xffffffff, |
| 238 | }; |
| 239 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 240 | enum ofp_group_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 241 | OFPGC_ADD = 0, |
| 242 | OFPGC_MODIFY = 1, |
| 243 | OFPGC_DELETE = 2, |
| 244 | }; |
| 245 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 246 | enum ofp_group_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 247 | OFPGT_ALL = 0, |
| 248 | OFPGT_SELECT = 1, |
| 249 | OFPGT_INDIRECT = 2, |
| 250 | OFPGT_FF = 3, |
| 251 | }; |
| 252 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 253 | enum ofp_packet_in_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 254 | OFPR_NO_MATCH = 0, |
| 255 | OFPR_ACTION = 1, |
| 256 | OFPR_INVALID_TTL = 2, |
| 257 | }; |
| 258 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 259 | enum ofp_flow_removed_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 260 | OFPRR_IDLE_TIMEOUT = 0, |
| 261 | OFPRR_HARD_TIMEOUT = 1, |
| 262 | OFPRR_DELETE = 2, |
| 263 | OFPRR_GROUP_DELETE = 3, |
| 264 | }; |
| 265 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 266 | enum ofp_error_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 267 | OFPET_HELLO_FAILED = 0, |
| 268 | OFPET_BAD_REQUEST = 1, |
| 269 | OFPET_BAD_ACTION = 2, |
| 270 | OFPET_BAD_INSTRUCTION = 3, |
| 271 | OFPET_BAD_MATCH = 4, |
| 272 | OFPET_FLOW_MOD_FAILED = 5, |
| 273 | OFPET_GROUP_MOD_FAILED = 6, |
| 274 | OFPET_PORT_MOD_FAILED = 7, |
| 275 | OFPET_TABLE_MOD_FAILED = 8, |
| 276 | OFPET_QUEUE_OP_FAILED = 9, |
| 277 | OFPET_SWITCH_CONFIG_FAILED = 10, |
| 278 | OFPET_ROLE_REQUEST_FAILED = 11, |
| 279 | OFPET_EXPERIMENTER = 0xffff, |
| 280 | }; |
| 281 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 282 | enum ofp_hello_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 283 | OFPHFC_INCOMPATIBLE = 0, |
| 284 | OFPHFC_EPERM = 1, |
| 285 | }; |
| 286 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 287 | enum ofp_bad_request_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 288 | OFPBRC_BAD_VERSION = 0, |
| 289 | OFPBRC_BAD_TYPE = 1, |
| 290 | OFPBRC_BAD_STAT = 2, |
| 291 | OFPBRC_BAD_EXPERIMENTER = 3, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 292 | OFPBRC_BAD_EXPERIMENTER_TYPE = 4, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 293 | OFPBRC_EPERM = 5, |
| 294 | OFPBRC_BAD_LEN = 6, |
| 295 | OFPBRC_BUFFER_EMPTY = 7, |
| 296 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 297 | OFPBRC_BAD_TABLE_ID = 9, |
| 298 | OFPBRC_IS_SLAVE = 10, |
| 299 | OFPBRC_BAD_PORT = 11, |
| 300 | OFPBRC_BAD_PACKET = 12, |
| 301 | }; |
| 302 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 303 | enum ofp_bad_action_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 304 | OFPBAC_BAD_TYPE = 0, |
| 305 | OFPBAC_BAD_LEN = 1, |
| 306 | OFPBAC_BAD_EXPERIMENTER = 2, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 307 | OFPBAC_BAD_EXPERIMENTER_TYPE = 3, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 308 | OFPBAC_BAD_OUT_PORT = 4, |
| 309 | OFPBAC_BAD_ARGUMENT = 5, |
| 310 | OFPBAC_EPERM = 6, |
| 311 | OFPBAC_TOO_MANY = 7, |
| 312 | OFPBAC_BAD_QUEUE = 8, |
| 313 | OFPBAC_BAD_OUT_GROUP = 9, |
| 314 | OFPBAC_MATCH_INCONSISTENT = 10, |
| 315 | OFPBAC_UNSUPPORTED_ORDER = 11, |
| 316 | OFPBAC_BAD_TAG = 12, |
| 317 | OFPBAC_BAD_SET_TYPE = 13, |
| 318 | OFPBAC_BAD_SET_LEN = 14, |
| 319 | OFPBAC_BAD_SET_ARGUMENT = 15, |
| 320 | }; |
| 321 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 322 | enum ofp_bad_instruction_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 323 | OFPBIC_UNKNOWN_INST = 0, |
| 324 | OFPBIC_UNSUP_INST = 1, |
| 325 | OFPBIC_BAD_TABLE_ID = 2, |
| 326 | OFPBIC_UNSUP_METADATA = 3, |
| 327 | OFPBIC_UNSUP_METADATA_MASK = 4, |
| 328 | OFPBIC_BAD_EXPERIMENTER = 5, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 329 | OFPBIC_BAD_EXPERIMENTER_TYPE = 6, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 330 | OFPBIC_BAD_LEN = 7, |
| 331 | OFPBIC_EPERM = 8, |
| 332 | }; |
| 333 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 334 | enum ofp_bad_match_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 335 | OFPBMC_BAD_TYPE = 0, |
| 336 | OFPBMC_BAD_LEN = 1, |
| 337 | OFPBMC_BAD_TAG = 2, |
| 338 | OFPBMC_BAD_DL_ADDR_MASK = 3, |
| 339 | OFPBMC_BAD_NW_ADDR_MASK = 4, |
| 340 | OFPBMC_BAD_WILDCARDS = 5, |
| 341 | OFPBMC_BAD_FIELD = 6, |
| 342 | OFPBMC_BAD_VALUE = 7, |
| 343 | OFPBMC_BAD_MASK = 8, |
| 344 | OFPBMC_BAD_PREREQ = 9, |
| 345 | OFPBMC_DUP_FIELD = 10, |
| 346 | OFPBMC_EPERM = 11, |
| 347 | }; |
| 348 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 349 | enum ofp_flow_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 350 | OFPFMFC_UNKNOWN = 0, |
| 351 | OFPFMFC_TABLE_FULL = 1, |
| 352 | OFPFMFC_BAD_TABLE_ID = 2, |
| 353 | OFPFMFC_OVERLAP = 3, |
| 354 | OFPFMFC_EPERM = 4, |
| 355 | OFPFMFC_BAD_TIMEOUT = 5, |
| 356 | OFPFMFC_BAD_COMMAND = 6, |
| 357 | OFPFMFC_BAD_FLAGS = 7, |
| 358 | }; |
| 359 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 360 | enum ofp_group_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 361 | OFPGMFC_GROUP_EXISTS = 0, |
| 362 | OFPGMFC_INVALID_GROUP = 1, |
| 363 | OFPGMFC_WEIGHT_UNSUPPORTED = 2, |
| 364 | OFPGMFC_OUT_OF_GROUPS = 3, |
| 365 | OFPGMFC_OUT_OF_BUCKETS = 4, |
| 366 | OFPGMFC_CHAINING_UNSUPPORTED = 5, |
| 367 | OFPGMFC_WATCH_UNSUPPORTED = 6, |
| 368 | OFPGMFC_LOOP = 7, |
| 369 | OFPGMFC_UNKNOWN_GROUP = 8, |
| 370 | OFPGMFC_CHAINED_GROUP = 9, |
| 371 | OFPGMFC_BAD_TYPE = 10, |
| 372 | OFPGMFC_BAD_COMMAND = 11, |
| 373 | OFPGMFC_BAD_BUCKET = 12, |
| 374 | OFPGMFC_BAD_WATCH = 13, |
| 375 | OFPGMFC_EPERM = 14, |
| 376 | }; |
| 377 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 378 | enum ofp_port_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 379 | OFPPMFC_BAD_PORT = 0, |
| 380 | OFPPMFC_BAD_HW_ADDR = 1, |
| 381 | OFPPMFC_BAD_CONFIG = 2, |
| 382 | OFPPMFC_BAD_ADVERTISE = 3, |
| 383 | OFPPMFC_EPERM = 4, |
| 384 | }; |
| 385 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 386 | enum ofp_table_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 387 | OFPTMFC_BAD_TABLE = 0, |
| 388 | OFPTMFC_BAD_CONFIG = 1, |
| 389 | OFPTMFC_EPERM = 2, |
| 390 | }; |
| 391 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 392 | enum ofp_queue_op_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 393 | OFPQOFC_BAD_PORT = 0, |
| 394 | OFPQOFC_BAD_QUEUE = 1, |
| 395 | OFPQOFC_EPERM = 2, |
| 396 | }; |
| 397 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 398 | enum ofp_switch_config_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 399 | OFPSCFC_BAD_FLAGS = 0, |
| 400 | OFPSCFC_BAD_LEN = 1, |
| 401 | OFPSCFC_EPERM = 2, |
| 402 | }; |
| 403 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 404 | enum ofp_role_request_failed_code (wire_type=uint16_t){ |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 405 | OFPRRFC_STALE = 0, |
| 406 | OFPRRFC_UNSUP = 1, |
| 407 | OFPRRFC_BAD_ROLE = 2, |
| 408 | }; |
| 409 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 410 | enum ofp_stats_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 411 | OFPST_DESC = 0, |
| 412 | OFPST_FLOW = 1, |
| 413 | OFPST_AGGREGATE = 2, |
| 414 | OFPST_TABLE = 3, |
| 415 | OFPST_PORT = 4, |
| 416 | OFPST_QUEUE = 5, |
| 417 | OFPST_GROUP = 6, |
| 418 | OFPST_GROUP_DESC = 7, |
| 419 | OFPST_GROUP_FEATURES = 8, |
| 420 | OFPST_EXPERIMENTER = 0xffff, |
| 421 | }; |
| 422 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 423 | enum ofp_stats_reply_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 424 | OFPSF_REPLY_MORE = 0x1, |
| 425 | }; |
| 426 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 427 | enum ofp_group_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 428 | OFPGFC_SELECT_WEIGHT = 0x1, |
| 429 | OFPGFC_SELECT_LIVENESS = 0x2, |
| 430 | OFPGFC_CHAINING = 0x4, |
| 431 | OFPGFC_CHAINING_CHECKS = 0x8, |
| 432 | }; |
| 433 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 434 | enum ofp_queue_properties(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 435 | OFPQT_MIN_RATE = 0x1, |
| 436 | OFPQT_MAX_RATE = 0x2, |
| 437 | OFPQT_EXPERIMENTER = 0xffff, |
| 438 | }; |
| 439 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 440 | enum ofp_controller_role(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 441 | OFPCR_ROLE_NOCHANGE = 0, |
| 442 | OFPCR_ROLE_EQUAL = 1, |
| 443 | OFPCR_ROLE_MASTER = 2, |
| 444 | OFPCR_ROLE_SLAVE = 3, |
| 445 | }; |
| 446 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 447 | /* XXX rename to of_message */ |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 448 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 449 | uint8_t version; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 450 | uint8_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 451 | uint16_t length; |
| 452 | uint32_t xid; |
| 453 | }; |
| 454 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 455 | struct of_hello : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 456 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 457 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 458 | uint16_t length; |
| 459 | uint32_t xid; |
| 460 | }; |
| 461 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 462 | struct of_echo_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 463 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 464 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 465 | uint16_t length; |
| 466 | uint32_t xid; |
| 467 | of_octets_t data; |
| 468 | }; |
| 469 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 470 | struct of_echo_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 471 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 472 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 473 | uint16_t length; |
| 474 | uint32_t xid; |
| 475 | of_octets_t data; |
| 476 | }; |
| 477 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 478 | struct of_experimenter : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 479 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 480 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 481 | uint16_t length; |
| 482 | uint32_t xid; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 483 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 484 | uint32_t subtype; |
| 485 | of_octets_t data; |
| 486 | }; |
| 487 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 488 | struct of_barrier_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 489 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 490 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 491 | uint16_t length; |
| 492 | uint32_t xid; |
| 493 | }; |
| 494 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 495 | struct of_barrier_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 496 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 497 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 498 | uint16_t length; |
| 499 | uint32_t xid; |
| 500 | }; |
| 501 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 502 | struct of_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 503 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 504 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 505 | uint16_t length; |
| 506 | uint32_t xid; |
| 507 | }; |
| 508 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 509 | struct of_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 510 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 511 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 512 | uint16_t length; |
| 513 | uint32_t xid; |
| 514 | uint16_t flags; |
| 515 | uint16_t miss_send_len; |
| 516 | }; |
| 517 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 518 | struct of_set_config : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 519 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 520 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 521 | uint16_t length; |
| 522 | uint32_t xid; |
| 523 | uint16_t flags; |
| 524 | uint16_t miss_send_len; |
| 525 | }; |
| 526 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 527 | struct of_table_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 528 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 529 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 530 | uint16_t length; |
| 531 | uint32_t xid; |
| 532 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 533 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 534 | uint32_t config; |
| 535 | }; |
| 536 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 537 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 538 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 539 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 540 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 541 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 542 | of_port_name_t name; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 543 | enum ofp_port_config config; |
| 544 | enum ofp_port_state state; |
| 545 | enum ofp_port_features curr; |
| 546 | enum ofp_port_features advertised; |
| 547 | enum ofp_port_features supported; |
| 548 | enum ofp_port_features peer; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 549 | uint32_t curr_speed; |
| 550 | uint32_t max_speed; |
| 551 | }; |
| 552 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 553 | struct of_features_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 554 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 555 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 556 | uint16_t length; |
| 557 | uint32_t xid; |
| 558 | }; |
| 559 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 560 | struct of_features_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 561 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 562 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 563 | uint16_t length; |
| 564 | uint32_t xid; |
| 565 | uint64_t datapath_id; |
| 566 | uint32_t n_buffers; |
| 567 | uint8_t n_tables; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 568 | pad(3); |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 569 | enum ofp_capabilities capabilities; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 570 | uint32_t reserved; |
| 571 | list(of_port_desc_t) ports; |
| 572 | }; |
| 573 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 574 | struct of_port_status : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 575 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 576 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 577 | uint16_t length; |
| 578 | uint32_t xid; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 579 | enum ofp_port_reason reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 580 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 581 | of_port_desc_t desc; |
| 582 | }; |
| 583 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 584 | struct of_port_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 585 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 586 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 587 | uint16_t length; |
| 588 | uint32_t xid; |
| 589 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 590 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 591 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 592 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 593 | uint32_t config; |
| 594 | uint32_t mask; |
| 595 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 596 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 597 | }; |
| 598 | |
Andreas Wundsam | fef7d5f | 2013-08-01 22:15:44 -0700 | [diff] [blame] | 599 | struct of_match_v3(align=8) { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 600 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 601 | uint16_t length; |
| 602 | list(of_oxm_t) oxm_list; |
| 603 | }; |
| 604 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 605 | struct of_action_output : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 606 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 607 | uint16_t len; |
| 608 | of_port_no_t port; |
| 609 | uint16_t max_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 610 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 611 | }; |
| 612 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 613 | struct of_action_copy_ttl_out : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 614 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 615 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 616 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 617 | }; |
| 618 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 619 | struct of_action_copy_ttl_in : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 620 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 621 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 622 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 623 | }; |
| 624 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 625 | struct of_action_set_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 626 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 627 | uint16_t len; |
| 628 | uint8_t mpls_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 629 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 630 | }; |
| 631 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 632 | struct of_action_dec_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 633 | uint16_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 634 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 635 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 636 | }; |
| 637 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 638 | struct of_action_push_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 639 | uint16_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 640 | uint16_t len; |
| 641 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 642 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 643 | }; |
| 644 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 645 | struct of_action_pop_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 646 | uint16_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 647 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 648 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 649 | }; |
| 650 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 651 | struct of_action_push_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 652 | uint16_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 653 | uint16_t len; |
| 654 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 655 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 656 | }; |
| 657 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 658 | struct of_action_pop_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 659 | uint16_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 660 | uint16_t len; |
| 661 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 662 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 663 | }; |
| 664 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 665 | struct of_action_set_queue : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 666 | uint16_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 667 | uint16_t len; |
| 668 | uint32_t queue_id; |
| 669 | }; |
| 670 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 671 | struct of_action_group : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 672 | uint16_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 673 | uint16_t len; |
| 674 | uint32_t group_id; |
| 675 | }; |
| 676 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 677 | struct of_action_set_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 678 | uint16_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 679 | uint16_t len; |
| 680 | uint8_t nw_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 681 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 682 | }; |
| 683 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 684 | struct of_action_dec_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 685 | uint16_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 686 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 687 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 688 | }; |
| 689 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 690 | struct of_action_set_field : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 691 | uint16_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 692 | uint16_t len; |
Rich Lane | be90eae | 2013-07-22 16:44:26 -0700 | [diff] [blame] | 693 | of_oxm_t field; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 694 | }; |
| 695 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 696 | struct of_action_experimenter : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 697 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 698 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 699 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 700 | of_octets_t data; |
| 701 | }; |
| 702 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 703 | struct of_action { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 704 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 705 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 706 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 707 | }; |
| 708 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 709 | struct of_instruction { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 710 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 711 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 712 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 713 | }; |
| 714 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 715 | struct of_instruction_goto_table : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 716 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 717 | uint16_t len; |
| 718 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 719 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 720 | }; |
| 721 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 722 | struct of_instruction_write_metadata : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 723 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 724 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 725 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 726 | uint64_t metadata; |
| 727 | uint64_t metadata_mask; |
| 728 | }; |
| 729 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 730 | struct of_instruction_write_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 731 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 732 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 733 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 734 | list(of_action_t) actions; |
| 735 | }; |
| 736 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 737 | struct of_instruction_apply_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 738 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 739 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 740 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 741 | list(of_action_t) actions; |
| 742 | }; |
| 743 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 744 | struct of_instruction_clear_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 745 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 746 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 747 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 748 | }; |
| 749 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 750 | struct of_instruction_experimenter : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 751 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 752 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 753 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 754 | of_octets_t data; |
| 755 | }; |
| 756 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 757 | struct of_flow_mod : of_header { |
| 758 | uint8_t version; |
| 759 | uint8_t type == 14; |
| 760 | uint16_t length; |
| 761 | uint32_t xid; |
| 762 | uint64_t cookie; |
| 763 | uint64_t cookie_mask; |
| 764 | uint8_t table_id; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 765 | of_fm_cmd_t _command == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 766 | uint16_t idle_timeout; |
| 767 | uint16_t hard_timeout; |
| 768 | uint16_t priority; |
| 769 | uint32_t buffer_id; |
| 770 | of_port_no_t out_port; |
| 771 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 772 | enum ofp_flow_mod_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 773 | pad(2); |
| 774 | of_match_t match; |
| 775 | list(of_instruction_t) instructions; |
| 776 | }; |
| 777 | |
| 778 | struct of_flow_add : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 779 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 780 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 781 | uint16_t length; |
| 782 | uint32_t xid; |
| 783 | uint64_t cookie; |
| 784 | uint64_t cookie_mask; |
| 785 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 786 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 787 | uint16_t idle_timeout; |
| 788 | uint16_t hard_timeout; |
| 789 | uint16_t priority; |
| 790 | uint32_t buffer_id; |
| 791 | of_port_no_t out_port; |
| 792 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 793 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 794 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 795 | of_match_t match; |
| 796 | list(of_instruction_t) instructions; |
| 797 | }; |
| 798 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 799 | struct of_flow_modify : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 800 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 801 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 802 | uint16_t length; |
| 803 | uint32_t xid; |
| 804 | uint64_t cookie; |
| 805 | uint64_t cookie_mask; |
| 806 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 807 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 808 | uint16_t idle_timeout; |
| 809 | uint16_t hard_timeout; |
| 810 | uint16_t priority; |
| 811 | uint32_t buffer_id; |
| 812 | of_port_no_t out_port; |
| 813 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 814 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 815 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 816 | of_match_t match; |
| 817 | list(of_instruction_t) instructions; |
| 818 | }; |
| 819 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 820 | struct of_flow_modify_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 821 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 822 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 823 | uint16_t length; |
| 824 | uint32_t xid; |
| 825 | uint64_t cookie; |
| 826 | uint64_t cookie_mask; |
| 827 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 828 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 829 | uint16_t idle_timeout; |
| 830 | uint16_t hard_timeout; |
| 831 | uint16_t priority; |
| 832 | uint32_t buffer_id; |
| 833 | of_port_no_t out_port; |
| 834 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 835 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 836 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 837 | of_match_t match; |
| 838 | list(of_instruction_t) instructions; |
| 839 | }; |
| 840 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 841 | struct of_flow_delete : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 842 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 843 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 844 | uint16_t length; |
| 845 | uint32_t xid; |
| 846 | uint64_t cookie; |
| 847 | uint64_t cookie_mask; |
| 848 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 849 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 850 | uint16_t idle_timeout; |
| 851 | uint16_t hard_timeout; |
| 852 | uint16_t priority; |
| 853 | uint32_t buffer_id; |
| 854 | of_port_no_t out_port; |
| 855 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 856 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 857 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 858 | of_match_t match; |
| 859 | list(of_instruction_t) instructions; |
| 860 | }; |
| 861 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 862 | struct of_flow_delete_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 863 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 864 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 865 | uint16_t length; |
| 866 | uint32_t xid; |
| 867 | uint64_t cookie; |
| 868 | uint64_t cookie_mask; |
| 869 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 870 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 871 | uint16_t idle_timeout; |
| 872 | uint16_t hard_timeout; |
| 873 | uint16_t priority; |
| 874 | uint32_t buffer_id; |
| 875 | of_port_no_t out_port; |
| 876 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 877 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 878 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 879 | of_match_t match; |
| 880 | list(of_instruction_t) instructions; |
| 881 | }; |
| 882 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 883 | struct of_bucket { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 884 | uint16_t len; |
| 885 | uint16_t weight; |
| 886 | of_port_no_t watch_port; |
| 887 | uint32_t watch_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 888 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 889 | list(of_action_t) actions; |
| 890 | }; |
| 891 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 892 | struct of_group_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 893 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 894 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 895 | uint16_t length; |
| 896 | uint32_t xid; |
| 897 | uint16_t command; |
| 898 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 899 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 900 | uint32_t group_id; |
| 901 | list(of_bucket_t) buckets; |
| 902 | }; |
| 903 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 904 | struct of_packet_out : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 905 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 906 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 907 | uint16_t length; |
| 908 | uint32_t xid; |
| 909 | uint32_t buffer_id; |
| 910 | of_port_no_t in_port; |
| 911 | uint16_t actions_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 912 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 913 | list(of_action_t) actions; |
| 914 | of_octets_t data; |
| 915 | }; |
| 916 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 917 | struct of_packet_in : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 918 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 919 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 920 | uint16_t length; |
| 921 | uint32_t xid; |
| 922 | uint32_t buffer_id; |
| 923 | uint16_t total_len; |
| 924 | uint8_t reason; |
| 925 | uint8_t table_id; |
| 926 | of_match_t match; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 927 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 928 | of_octets_t data; /* FIXME: Ensure total_len gets updated */ |
| 929 | }; |
| 930 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 931 | struct of_flow_removed : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 932 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 933 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 934 | uint16_t length; |
| 935 | uint32_t xid; |
| 936 | uint64_t cookie; |
| 937 | uint16_t priority; |
| 938 | uint8_t reason; |
| 939 | uint8_t table_id; |
| 940 | uint32_t duration_sec; |
| 941 | uint32_t duration_nsec; |
| 942 | uint16_t idle_timeout; |
| 943 | uint16_t hard_timeout; |
| 944 | uint64_t packet_count; |
| 945 | uint64_t byte_count; |
| 946 | of_match_t match; |
| 947 | }; |
| 948 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 949 | struct of_error_msg : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 950 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 951 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 952 | uint16_t length; |
| 953 | uint32_t xid; |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 954 | uint16_t err_type == ?; |
| 955 | }; |
| 956 | |
| 957 | struct of_hello_failed_error_msg : of_error_msg { |
| 958 | uint8_t version; |
| 959 | uint8_t type == 1; |
| 960 | uint16_t length; |
| 961 | uint32_t xid; |
| 962 | uint16_t err_type == 0; |
| 963 | enum ofp_hello_failed_code code; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 964 | of_octets_t data; |
| 965 | }; |
| 966 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 967 | struct of_bad_request_error_msg : of_error_msg { |
| 968 | uint8_t version; |
| 969 | uint8_t type == 1; |
| 970 | uint16_t length; |
| 971 | uint32_t xid; |
| 972 | uint16_t err_type == 1; |
| 973 | enum ofp_bad_request_code code; |
| 974 | of_octets_t data; |
| 975 | }; |
| 976 | |
| 977 | struct of_bad_action_error_msg : of_error_msg { |
| 978 | uint8_t version; |
| 979 | uint8_t type == 1; |
| 980 | uint16_t length; |
| 981 | uint32_t xid; |
| 982 | uint16_t err_type == 2; |
| 983 | enum ofp_bad_action_code code; |
| 984 | of_octets_t data; |
| 985 | }; |
| 986 | |
| 987 | struct of_bad_instruction_error_msg : of_error_msg { |
| 988 | uint8_t version; |
| 989 | uint8_t type == 1; |
| 990 | uint16_t length; |
| 991 | uint32_t xid; |
| 992 | uint16_t err_type == 3; |
| 993 | enum ofp_bad_instruction_code code; |
| 994 | of_octets_t data; |
| 995 | }; |
| 996 | |
| 997 | struct of_bad_match_error_msg : of_error_msg { |
| 998 | uint8_t version; |
| 999 | uint8_t type == 1; |
| 1000 | uint16_t length; |
| 1001 | uint32_t xid; |
| 1002 | uint16_t err_type == 4; |
| 1003 | enum ofp_bad_match_code code; |
| 1004 | of_octets_t data; |
| 1005 | }; |
| 1006 | |
| 1007 | struct of_flow_mod_failed_error_msg : of_error_msg { |
| 1008 | uint8_t version; |
| 1009 | uint8_t type == 1; |
| 1010 | uint16_t length; |
| 1011 | uint32_t xid; |
| 1012 | uint16_t err_type == 5; |
| 1013 | enum ofp_flow_mod_failed_code code; |
| 1014 | of_octets_t data; |
| 1015 | }; |
| 1016 | |
| 1017 | struct of_group_mod_failed_error_msg : of_error_msg { |
| 1018 | uint8_t version; |
| 1019 | uint8_t type == 1; |
| 1020 | uint16_t length; |
| 1021 | uint32_t xid; |
| 1022 | uint16_t err_type == 6; |
| 1023 | enum ofp_group_mod_failed_code code; |
| 1024 | of_octets_t data; |
| 1025 | }; |
| 1026 | |
| 1027 | struct of_port_mod_failed_error_msg : of_error_msg { |
| 1028 | uint8_t version; |
| 1029 | uint8_t type == 1; |
| 1030 | uint16_t length; |
| 1031 | uint32_t xid; |
| 1032 | uint16_t err_type == 7; |
| 1033 | enum ofp_port_mod_failed_code code; |
| 1034 | of_octets_t data; |
| 1035 | }; |
| 1036 | |
| 1037 | struct of_table_mod_failed_error_msg : of_error_msg { |
| 1038 | uint8_t version; |
| 1039 | uint8_t type == 1; |
| 1040 | uint16_t length; |
| 1041 | uint32_t xid; |
| 1042 | uint16_t err_type == 8; |
| 1043 | enum ofp_table_mod_failed_code code; |
| 1044 | of_octets_t data; |
| 1045 | }; |
| 1046 | |
| 1047 | struct of_queue_op_failed_error_msg : of_error_msg { |
| 1048 | uint8_t version; |
| 1049 | uint8_t type == 1; |
| 1050 | uint16_t length; |
| 1051 | uint32_t xid; |
| 1052 | uint16_t err_type == 9; |
| 1053 | enum ofp_queue_op_failed_code code; |
| 1054 | of_octets_t data; |
| 1055 | }; |
| 1056 | |
| 1057 | struct of_switch_config_failed_error_msg : of_error_msg { |
| 1058 | uint8_t version; |
| 1059 | uint8_t type == 1; |
| 1060 | uint16_t length; |
| 1061 | uint32_t xid; |
| 1062 | uint16_t err_type == 10; |
| 1063 | enum ofp_switch_config_failed_code code; |
| 1064 | of_octets_t data; |
| 1065 | }; |
| 1066 | |
| 1067 | struct of_role_request_failed_error_msg : of_error_msg { |
| 1068 | uint8_t version; |
| 1069 | uint8_t type == 1; |
| 1070 | uint16_t length; |
| 1071 | uint32_t xid; |
| 1072 | uint16_t err_type == 11; |
| 1073 | enum ofp_role_request_failed_code code; |
| 1074 | of_octets_t data; |
| 1075 | }; |
| 1076 | |
| 1077 | struct of_experimenter_error_msg { |
| 1078 | uint8_t version; |
| 1079 | uint8_t type == 1; |
| 1080 | uint16_t length; |
| 1081 | uint32_t xid; |
| 1082 | uint16_t err_type == 0xffff; |
| 1083 | uint16_t subtype; |
| 1084 | uint32_t experimenter; |
| 1085 | of_octets_t data; |
| 1086 | }; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1087 | |
| 1088 | // STATS ENTRIES: flow, table, port, queue, group stats, group desc stats |
| 1089 | // FIXME: Verify disambiguation w/ length in object and entry |
| 1090 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1091 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1092 | uint16_t length; |
| 1093 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1094 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1095 | uint32_t duration_sec; |
| 1096 | uint32_t duration_nsec; |
| 1097 | uint16_t priority; |
| 1098 | uint16_t idle_timeout; |
| 1099 | uint16_t hard_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1100 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1101 | uint64_t cookie; |
| 1102 | uint64_t packet_count; |
| 1103 | uint64_t byte_count; |
| 1104 | of_match_t match; |
| 1105 | list(of_instruction_t) instructions; |
| 1106 | }; |
| 1107 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1108 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1109 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1110 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1111 | of_table_name_t name; |
| 1112 | of_match_bmap_t match; |
| 1113 | of_wc_bmap_t wildcards; |
| 1114 | uint32_t write_actions; |
| 1115 | uint32_t apply_actions; |
| 1116 | uint64_t write_setfields; |
| 1117 | uint64_t apply_setfields; |
| 1118 | uint64_t metadata_match; |
| 1119 | uint64_t metadata_write; |
| 1120 | uint32_t instructions; |
| 1121 | uint32_t config; |
| 1122 | uint32_t max_entries; |
| 1123 | uint32_t active_count; |
| 1124 | uint64_t lookup_count; |
| 1125 | uint64_t matched_count; |
| 1126 | }; |
| 1127 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1128 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1129 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1130 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1131 | uint64_t rx_packets; |
| 1132 | uint64_t tx_packets; |
| 1133 | uint64_t rx_bytes; |
| 1134 | uint64_t tx_bytes; |
| 1135 | uint64_t rx_dropped; |
| 1136 | uint64_t tx_dropped; |
| 1137 | uint64_t rx_errors; |
| 1138 | uint64_t tx_errors; |
| 1139 | uint64_t rx_frame_err; |
| 1140 | uint64_t rx_over_err; |
| 1141 | uint64_t rx_crc_err; |
| 1142 | uint64_t collisions; |
| 1143 | }; |
| 1144 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1145 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1146 | of_port_no_t port_no; |
| 1147 | uint32_t queue_id; |
| 1148 | uint64_t tx_bytes; |
| 1149 | uint64_t tx_packets; |
| 1150 | uint64_t tx_errors; |
| 1151 | }; |
| 1152 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1153 | struct of_bucket_counter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1154 | uint64_t packet_count; |
| 1155 | uint64_t byte_count; |
| 1156 | }; |
| 1157 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1158 | struct of_group_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1159 | uint16_t length; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1160 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1161 | uint32_t group_id; |
| 1162 | uint32_t ref_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1163 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1164 | uint64_t packet_count; |
| 1165 | uint64_t byte_count; |
| 1166 | list(of_bucket_counter_t) bucket_stats; |
| 1167 | }; |
| 1168 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1169 | struct of_group_desc_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1170 | uint16_t length; |
Rich Lane | 35e7ac7 | 2013-10-15 10:36:10 -0700 | [diff] [blame] | 1171 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1172 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1173 | uint32_t group_id; |
| 1174 | list(of_bucket_t) buckets; |
| 1175 | }; |
| 1176 | |
| 1177 | // STATS: |
| 1178 | // Desc, flow, agg, table, port, queue, group, group_desc, group_feat, experi |
| 1179 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1180 | struct of_stats_request : of_header { |
| 1181 | uint8_t version; |
| 1182 | uint8_t type == 18; |
| 1183 | uint16_t length; |
| 1184 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1185 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1186 | uint16_t flags; |
| 1187 | pad(4); |
| 1188 | }; |
| 1189 | |
| 1190 | struct of_stats_reply : of_header { |
| 1191 | uint8_t version; |
| 1192 | uint8_t type == 19; |
| 1193 | uint16_t length; |
| 1194 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1195 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1196 | uint16_t flags; |
| 1197 | pad(4); |
| 1198 | }; |
| 1199 | |
| 1200 | struct of_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1201 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1202 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1203 | uint16_t length; |
| 1204 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1205 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1206 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1207 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1208 | }; |
| 1209 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1210 | struct of_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1211 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1212 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1213 | uint16_t length; |
| 1214 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1215 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1216 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1217 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1218 | of_desc_str_t mfr_desc; |
| 1219 | of_desc_str_t hw_desc; |
| 1220 | of_desc_str_t sw_desc; |
| 1221 | of_serial_num_t serial_num; |
| 1222 | of_desc_str_t dp_desc; |
| 1223 | }; |
| 1224 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1225 | struct of_flow_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1226 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1227 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1228 | uint16_t length; |
| 1229 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1230 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1231 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1232 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1233 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1234 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1235 | of_port_no_t out_port; |
| 1236 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1237 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1238 | uint64_t cookie; |
| 1239 | uint64_t cookie_mask; |
| 1240 | of_match_t match; |
| 1241 | }; |
| 1242 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1243 | struct of_flow_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1244 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1245 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1246 | uint16_t length; |
| 1247 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1248 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1249 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1250 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1251 | list(of_flow_stats_entry_t) entries; |
| 1252 | }; |
| 1253 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1254 | struct of_aggregate_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1255 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1256 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1257 | uint16_t length; |
| 1258 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1259 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1260 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1261 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1262 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1263 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1264 | of_port_no_t out_port; |
| 1265 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1266 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1267 | uint64_t cookie; |
| 1268 | uint64_t cookie_mask; |
| 1269 | of_match_t match; |
| 1270 | }; |
| 1271 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1272 | struct of_aggregate_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1273 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1274 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1275 | uint16_t length; |
| 1276 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1277 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1278 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1279 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1280 | uint64_t packet_count; |
| 1281 | uint64_t byte_count; |
| 1282 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1283 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1284 | }; |
| 1285 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1286 | struct of_table_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1287 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1288 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1289 | uint16_t length; |
| 1290 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1291 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1292 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1293 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1294 | }; |
| 1295 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1296 | struct of_table_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1297 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1298 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1299 | uint16_t length; |
| 1300 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1301 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1302 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1303 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1304 | list(of_table_stats_entry_t) entries; |
| 1305 | }; |
| 1306 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1307 | struct of_port_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1308 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1309 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1310 | uint16_t length; |
| 1311 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1312 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1313 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1314 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1315 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1316 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1317 | }; |
| 1318 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1319 | struct of_port_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1320 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1321 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1322 | uint16_t length; |
| 1323 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1324 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1325 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1326 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1327 | list(of_port_stats_entry_t) entries; |
| 1328 | }; |
| 1329 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1330 | struct of_queue_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1331 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1332 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1333 | uint16_t length; |
| 1334 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1335 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1336 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1337 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1338 | of_port_no_t port_no; |
| 1339 | uint32_t queue_id; |
| 1340 | }; |
| 1341 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1342 | struct of_queue_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1343 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1344 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1345 | uint16_t length; |
| 1346 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1347 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1348 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1349 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1350 | list(of_queue_stats_entry_t) entries; |
| 1351 | }; |
| 1352 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1353 | struct of_group_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1354 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1355 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1356 | uint16_t length; |
| 1357 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1358 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1359 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1360 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1361 | uint32_t group_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1362 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1363 | }; |
| 1364 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1365 | struct of_group_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1366 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1367 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1368 | uint16_t length; |
| 1369 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1370 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1371 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1372 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1373 | list(of_group_stats_entry_t) entries; |
| 1374 | }; |
| 1375 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1376 | struct of_group_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1377 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1378 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1379 | uint16_t length; |
| 1380 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1381 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1382 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1383 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1384 | }; |
| 1385 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1386 | struct of_group_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1387 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1388 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1389 | uint16_t length; |
| 1390 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1391 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1392 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1393 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1394 | list(of_group_desc_stats_entry_t) entries; |
| 1395 | }; |
| 1396 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1397 | struct of_group_features_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1398 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1399 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1400 | uint16_t length; |
| 1401 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1402 | uint16_t stats_type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1403 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1404 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1405 | }; |
| 1406 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1407 | struct of_group_features_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1408 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1409 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1410 | uint16_t length; |
| 1411 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1412 | uint16_t stats_type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1413 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1414 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1415 | uint32_t types; |
| 1416 | uint32_t capabilities; |
| 1417 | uint32_t max_groups_all; |
| 1418 | uint32_t max_groups_select; |
| 1419 | uint32_t max_groups_indirect; |
| 1420 | uint32_t max_groups_ff; |
| 1421 | uint32_t actions_all; |
| 1422 | uint32_t actions_select; |
| 1423 | uint32_t actions_indirect; |
| 1424 | uint32_t actions_ff; |
| 1425 | }; |
| 1426 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1427 | struct of_experimenter_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1428 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1429 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1430 | uint16_t length; |
| 1431 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1432 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1433 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1434 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1435 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1436 | uint32_t subtype; |
| 1437 | of_octets_t data; |
| 1438 | }; |
| 1439 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1440 | struct of_experimenter_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1441 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1442 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1443 | uint16_t length; |
| 1444 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1445 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1446 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1447 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1448 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1449 | uint32_t subtype; |
| 1450 | of_octets_t data; |
| 1451 | }; |
| 1452 | |
| 1453 | // END OF STATS OBJECTS |
| 1454 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1455 | struct of_queue_prop { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1456 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1457 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1458 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1459 | }; |
| 1460 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1461 | struct of_queue_prop_min_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1462 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1463 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1464 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1465 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1466 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1467 | }; |
| 1468 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1469 | struct of_queue_prop_max_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1470 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1471 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1472 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1473 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1474 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1475 | }; |
| 1476 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1477 | struct of_queue_prop_experimenter : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1478 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1479 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1480 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1481 | uint32_t experimenter == ?; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1482 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1483 | of_octets_t data; |
| 1484 | }; |
| 1485 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1486 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1487 | uint32_t queue_id; |
| 1488 | of_port_no_t port; |
| 1489 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1490 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1491 | list(of_queue_prop_t) properties; |
| 1492 | }; |
| 1493 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1494 | struct of_queue_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1495 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1496 | uint8_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1497 | uint16_t length; |
| 1498 | uint32_t xid; |
| 1499 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1500 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1501 | }; |
| 1502 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1503 | struct of_queue_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1504 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1505 | uint8_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1506 | uint16_t length; |
| 1507 | uint32_t xid; |
| 1508 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1509 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1510 | list(of_packet_queue_t) queues; |
| 1511 | }; |
| 1512 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1513 | struct of_role_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1514 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1515 | uint8_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1516 | uint16_t length; |
| 1517 | uint32_t xid; |
| 1518 | uint32_t role; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1519 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1520 | uint64_t generation_id; |
| 1521 | }; |
| 1522 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1523 | struct of_role_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1524 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1525 | uint8_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1526 | uint16_t length; |
| 1527 | uint32_t xid; |
| 1528 | of_octets_t data; |
| 1529 | }; |