Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
| 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
| 31 | |
| 32 | #version 3 |
| 33 | #version 4 |
alshabib | 9f50e48 | 2014-08-23 17:10:57 -0500 | [diff] [blame] | 34 | #version 5 |
Murat Parlakisik | f95672c | 2016-12-05 00:53:17 -0800 | [diff] [blame] | 35 | #version 6 |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 36 | |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 37 | struct of_oxm { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 38 | uint32_t type_len == ?; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 39 | }; |
| 40 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 41 | struct of_oxm_arp_op : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 42 | uint32_t type_len == 0x80002a02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 43 | uint16_t value; |
| 44 | }; |
| 45 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 46 | struct of_oxm_arp_op_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 47 | uint32_t type_len == 0x80002b04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 48 | uint16_t value; |
| 49 | uint16_t value_mask; |
| 50 | }; |
| 51 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 52 | struct of_oxm_arp_sha : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 53 | uint32_t type_len == 0x80003006; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 54 | of_mac_addr_t value; |
| 55 | }; |
| 56 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 57 | struct of_oxm_arp_sha_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 58 | uint32_t type_len == 0x8000310c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 59 | of_mac_addr_t value; |
| 60 | of_mac_addr_t value_mask; |
| 61 | }; |
| 62 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 63 | struct of_oxm_arp_spa : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 64 | uint32_t type_len == 0x80002c04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 65 | uint32_t value; |
| 66 | }; |
| 67 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 68 | struct of_oxm_arp_spa_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 69 | uint32_t type_len == 0x80002d08; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 70 | uint32_t value; |
| 71 | uint32_t value_mask; |
| 72 | }; |
| 73 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 74 | struct of_oxm_arp_tha : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 75 | uint32_t type_len == 0x80003206; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 76 | of_mac_addr_t value; |
| 77 | }; |
| 78 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 79 | struct of_oxm_arp_tha_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 80 | uint32_t type_len == 0x8000330c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 81 | of_mac_addr_t value; |
| 82 | of_mac_addr_t value_mask; |
| 83 | }; |
| 84 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 85 | struct of_oxm_arp_tpa : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 86 | uint32_t type_len == 0x80002e04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 87 | uint32_t value; |
| 88 | }; |
| 89 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 90 | struct of_oxm_arp_tpa_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 91 | uint32_t type_len == 0x80002f08; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 92 | uint32_t value; |
| 93 | uint32_t value_mask; |
| 94 | }; |
| 95 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 96 | struct of_oxm_eth_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 97 | uint32_t type_len == 0x80000606; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 98 | of_mac_addr_t value; |
| 99 | }; |
| 100 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 101 | struct of_oxm_eth_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 102 | uint32_t type_len == 0x8000070c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 103 | of_mac_addr_t value; |
| 104 | of_mac_addr_t value_mask; |
| 105 | }; |
| 106 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 107 | struct of_oxm_eth_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 108 | uint32_t type_len == 0x80000806; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 109 | of_mac_addr_t value; |
| 110 | }; |
| 111 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 112 | struct of_oxm_eth_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 113 | uint32_t type_len == 0x8000090c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 114 | of_mac_addr_t value; |
| 115 | of_mac_addr_t value_mask; |
| 116 | }; |
| 117 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 118 | struct of_oxm_eth_type : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 119 | uint32_t type_len == 0x80000a02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 120 | uint16_t value; |
| 121 | }; |
| 122 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 123 | struct of_oxm_eth_type_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 124 | uint32_t type_len == 0x80000b04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 125 | uint16_t value; |
| 126 | uint16_t value_mask; |
| 127 | }; |
| 128 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 129 | struct of_oxm_icmpv4_code : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 130 | uint32_t type_len == 0x80002801; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 131 | uint8_t value; |
| 132 | }; |
| 133 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 134 | struct of_oxm_icmpv4_code_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 135 | uint32_t type_len == 0x80002902; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 136 | uint8_t value; |
| 137 | uint8_t value_mask; |
| 138 | }; |
| 139 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 140 | struct of_oxm_icmpv4_type : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 141 | uint32_t type_len == 0x80002601; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 142 | uint8_t value; |
| 143 | }; |
| 144 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 145 | struct of_oxm_icmpv4_type_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 146 | uint32_t type_len == 0x80002702; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 147 | uint8_t value; |
| 148 | uint8_t value_mask; |
| 149 | }; |
| 150 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 151 | struct of_oxm_icmpv6_code : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 152 | uint32_t type_len == 0x80003c01; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 153 | uint8_t value; |
| 154 | }; |
| 155 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 156 | struct of_oxm_icmpv6_code_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 157 | uint32_t type_len == 0x80003d02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 158 | uint8_t value; |
| 159 | uint8_t value_mask; |
| 160 | }; |
| 161 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 162 | struct of_oxm_icmpv6_type : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 163 | uint32_t type_len == 0x80003a01; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 164 | uint8_t value; |
| 165 | }; |
| 166 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 167 | struct of_oxm_icmpv6_type_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 168 | uint32_t type_len == 0x80003b02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 169 | uint8_t value; |
| 170 | uint8_t value_mask; |
| 171 | }; |
| 172 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 173 | struct of_oxm_in_phy_port : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 174 | uint32_t type_len == 0x80000204; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 175 | of_port_no_t value; |
| 176 | }; |
| 177 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 178 | struct of_oxm_in_phy_port_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 179 | uint32_t type_len == 0x80000308; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 180 | of_port_no_t value; |
| 181 | of_port_no_t value_mask; |
| 182 | }; |
| 183 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 184 | struct of_oxm_in_port : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 185 | uint32_t type_len == 0x80000004; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 186 | of_port_no_t value; |
| 187 | }; |
| 188 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 189 | struct of_oxm_in_port_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 190 | uint32_t type_len == 0x80000108; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 191 | of_port_no_t value; |
| 192 | of_port_no_t value_mask; |
| 193 | }; |
| 194 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 195 | struct of_oxm_ip_dscp : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 196 | uint32_t type_len == 0x80001001; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 197 | uint8_t value; |
| 198 | }; |
| 199 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 200 | struct of_oxm_ip_dscp_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 201 | uint32_t type_len == 0x80001102; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 202 | uint8_t value; |
| 203 | uint8_t value_mask; |
| 204 | }; |
| 205 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 206 | struct of_oxm_ip_ecn : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 207 | uint32_t type_len == 0x80001201; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 208 | uint8_t value; |
| 209 | }; |
| 210 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 211 | struct of_oxm_ip_ecn_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 212 | uint32_t type_len == 0x80001302; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 213 | uint8_t value; |
| 214 | uint8_t value_mask; |
| 215 | }; |
| 216 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 217 | struct of_oxm_ip_proto : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 218 | uint32_t type_len == 0x80001401; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 219 | uint8_t value; |
| 220 | }; |
| 221 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 222 | struct of_oxm_ip_proto_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 223 | uint32_t type_len == 0x80001502; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 224 | uint8_t value; |
| 225 | uint8_t value_mask; |
| 226 | }; |
| 227 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 228 | struct of_oxm_ipv4_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 229 | uint32_t type_len == 0x80001804; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 230 | of_ipv4_t value; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 231 | }; |
| 232 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 233 | struct of_oxm_ipv4_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 234 | uint32_t type_len == 0x80001908; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 235 | of_ipv4_t value; |
| 236 | of_ipv4_t value_mask; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 237 | }; |
| 238 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 239 | struct of_oxm_ipv4_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 240 | uint32_t type_len == 0x80001604; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 241 | of_ipv4_t value; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 242 | }; |
| 243 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 244 | struct of_oxm_ipv4_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 245 | uint32_t type_len == 0x80001708; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 246 | of_ipv4_t value; |
| 247 | of_ipv4_t value_mask; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 248 | }; |
| 249 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 250 | struct of_oxm_ipv6_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 251 | uint32_t type_len == 0x80003610; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 252 | of_ipv6_t value; |
| 253 | }; |
| 254 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 255 | struct of_oxm_ipv6_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 256 | uint32_t type_len == 0x80003720; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 257 | of_ipv6_t value; |
| 258 | of_ipv6_t value_mask; |
| 259 | }; |
| 260 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 261 | struct of_oxm_ipv6_flabel : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 262 | uint32_t type_len == 0x80003804; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 263 | uint32_t value; |
| 264 | }; |
| 265 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 266 | struct of_oxm_ipv6_flabel_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 267 | uint32_t type_len == 0x80003908; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 268 | uint32_t value; |
| 269 | uint32_t value_mask; |
| 270 | }; |
| 271 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 272 | struct of_oxm_ipv6_nd_sll : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 273 | uint32_t type_len == 0x80004006; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 274 | of_mac_addr_t value; |
| 275 | }; |
| 276 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 277 | struct of_oxm_ipv6_nd_sll_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 278 | uint32_t type_len == 0x8000410c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 279 | of_mac_addr_t value; |
| 280 | of_mac_addr_t value_mask; |
| 281 | }; |
| 282 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 283 | struct of_oxm_ipv6_nd_target : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 284 | uint32_t type_len == 0x80003e10; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 285 | of_ipv6_t value; |
| 286 | }; |
| 287 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 288 | struct of_oxm_ipv6_nd_target_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 289 | uint32_t type_len == 0x80003f20; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 290 | of_ipv6_t value; |
| 291 | of_ipv6_t value_mask; |
| 292 | }; |
| 293 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 294 | struct of_oxm_ipv6_nd_tll : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 295 | uint32_t type_len == 0x80004206; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 296 | of_mac_addr_t value; |
| 297 | }; |
| 298 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 299 | struct of_oxm_ipv6_nd_tll_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 300 | uint32_t type_len == 0x8000430c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 301 | of_mac_addr_t value; |
| 302 | of_mac_addr_t value_mask; |
| 303 | }; |
| 304 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 305 | struct of_oxm_ipv6_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 306 | uint32_t type_len == 0x80003410; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 307 | of_ipv6_t value; |
| 308 | }; |
| 309 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 310 | struct of_oxm_ipv6_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 311 | uint32_t type_len == 0x80003520; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 312 | of_ipv6_t value; |
| 313 | of_ipv6_t value_mask; |
| 314 | }; |
| 315 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 316 | struct of_oxm_metadata : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 317 | uint32_t type_len == 0x80000408; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 318 | uint64_t value; |
| 319 | }; |
| 320 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 321 | struct of_oxm_metadata_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 322 | uint32_t type_len == 0x80000510; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 323 | uint64_t value; |
| 324 | uint64_t value_mask; |
| 325 | }; |
| 326 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 327 | struct of_oxm_mpls_label : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 328 | uint32_t type_len == 0x80004404; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 329 | uint32_t value; |
| 330 | }; |
| 331 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 332 | struct of_oxm_mpls_label_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 333 | uint32_t type_len == 0x80004508; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 334 | uint32_t value; |
| 335 | uint32_t value_mask; |
| 336 | }; |
| 337 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 338 | struct of_oxm_mpls_tc : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 339 | uint32_t type_len == 0x80004601; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 340 | uint8_t value; |
| 341 | }; |
| 342 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 343 | struct of_oxm_mpls_tc_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 344 | uint32_t type_len == 0x80004702; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 345 | uint8_t value; |
| 346 | uint8_t value_mask; |
| 347 | }; |
| 348 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 349 | struct of_oxm_sctp_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 350 | uint32_t type_len == 0x80002402; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 351 | uint16_t value; |
| 352 | }; |
| 353 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 354 | struct of_oxm_sctp_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 355 | uint32_t type_len == 0x80002504; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 356 | uint16_t value; |
| 357 | uint16_t value_mask; |
| 358 | }; |
| 359 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 360 | struct of_oxm_sctp_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 361 | uint32_t type_len == 0x80002202; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 362 | uint16_t value; |
| 363 | }; |
| 364 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 365 | struct of_oxm_sctp_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 366 | uint32_t type_len == 0x80002304; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 367 | uint16_t value; |
| 368 | uint16_t value_mask; |
| 369 | }; |
| 370 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 371 | struct of_oxm_tcp_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 372 | uint32_t type_len == 0x80001c02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 373 | uint16_t value; |
| 374 | }; |
| 375 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 376 | struct of_oxm_tcp_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 377 | uint32_t type_len == 0x80001d04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 378 | uint16_t value; |
| 379 | uint16_t value_mask; |
| 380 | }; |
| 381 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 382 | struct of_oxm_tcp_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 383 | uint32_t type_len == 0x80001a02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 384 | uint16_t value; |
| 385 | }; |
| 386 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 387 | struct of_oxm_tcp_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 388 | uint32_t type_len == 0x80001b04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 389 | uint16_t value; |
| 390 | uint16_t value_mask; |
| 391 | }; |
| 392 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 393 | struct of_oxm_udp_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 394 | uint32_t type_len == 0x80002002; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 395 | uint16_t value; |
| 396 | }; |
| 397 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 398 | struct of_oxm_udp_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 399 | uint32_t type_len == 0x80002104; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 400 | uint16_t value; |
| 401 | uint16_t value_mask; |
| 402 | }; |
| 403 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 404 | struct of_oxm_udp_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 405 | uint32_t type_len == 0x80001e02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 406 | uint16_t value; |
| 407 | }; |
| 408 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 409 | struct of_oxm_udp_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 410 | uint32_t type_len == 0x80001f04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 411 | uint16_t value; |
| 412 | uint16_t value_mask; |
| 413 | }; |
| 414 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 415 | struct of_oxm_vlan_pcp : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 416 | uint32_t type_len == 0x80000e01; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 417 | uint8_t value; |
| 418 | }; |
| 419 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 420 | struct of_oxm_vlan_pcp_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 421 | uint32_t type_len == 0x80000f02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 422 | uint8_t value; |
| 423 | uint8_t value_mask; |
| 424 | }; |
| 425 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 426 | struct of_oxm_vlan_vid : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 427 | uint32_t type_len == 0x80000c02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 428 | uint16_t value; |
| 429 | }; |
| 430 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 431 | struct of_oxm_vlan_vid_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 432 | uint32_t type_len == 0x80000d04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 433 | uint16_t value; |
| 434 | uint16_t value_mask; |
| 435 | }; |