Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 1 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
| 38 | OFP_TCP_PORT = 6633, |
| 39 | OFP_SSL_PORT = 6633, |
| 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFP_VLAN_NONE = 0xffff, |
| 46 | |
| 47 | OFPFW_ICMP_TYPE = 0x40, |
| 48 | OFPFW_ICMP_CODE = 0x80, |
| 49 | |
| 50 | OFP_DL_TYPE_ETH2_CUTOFF = 0x600, |
| 51 | OFP_DL_TYPE_NOT_ETH_TYPE = 0x5ff, |
| 52 | |
| 53 | OFP_FLOW_PERMANENT = 0, |
| 54 | |
| 55 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 56 | |
| 57 | DESC_STR_LEN = 256, |
| 58 | SERIAL_NUM_LEN = 32, |
| 59 | |
| 60 | OFPQ_ALL = 0xffffffff, |
| 61 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 62 | }; |
| 63 | |
| 64 | enum ofp_type { |
| 65 | OFPT_HELLO = 0, |
| 66 | OFPT_ERROR = 1, |
| 67 | OFPT_ECHO_REQUEST = 2, |
| 68 | OFPT_ECHO_REPLY = 3, |
| 69 | OFPT_VENDOR = 4, |
| 70 | OFPT_FEATURES_REQUEST = 5, |
| 71 | OFPT_FEATURES_REPLY = 6, |
| 72 | OFPT_GET_CONFIG_REQUEST = 7, |
| 73 | OFPT_GET_CONFIG_REPLY = 8, |
| 74 | OFPT_SET_CONFIG = 9, |
| 75 | OFPT_PACKET_IN = 10, |
| 76 | OFPT_FLOW_REMOVED = 11, |
| 77 | OFPT_PORT_STATUS = 12, |
| 78 | OFPT_PACKET_OUT = 13, |
| 79 | OFPT_FLOW_MOD = 14, |
| 80 | OFPT_PORT_MOD = 15, |
| 81 | OFPT_STATS_REQUEST = 16, |
| 82 | OFPT_STATS_REPLY = 17, |
| 83 | OFPT_BARRIER_REQUEST = 18, |
| 84 | OFPT_BARRIER_REPLY = 19, |
| 85 | OFPT_QUEUE_GET_CONFIG_REQUEST = 20, |
| 86 | OFPT_QUEUE_GET_CONFIG_REPLY = 21, |
| 87 | }; |
| 88 | |
| 89 | enum ofp_port_config { |
| 90 | OFPPC_PORT_DOWN = 0x1, |
| 91 | OFPPC_NO_STP = 0x2, |
| 92 | OFPPC_NO_RECV = 0x4, |
| 93 | OFPPC_NO_RECV_STP = 0x8, |
| 94 | OFPPC_NO_FLOOD = 0x10, |
| 95 | OFPPC_NO_FWD = 0x20, |
| 96 | OFPPC_NO_PACKET_IN = 0x40, |
| 97 | }; |
| 98 | |
| 99 | enum ofp_port_state { |
| 100 | OFPPS_STP_LISTEN = 0, |
| 101 | OFPPS_LINK_DOWN = 1, |
| 102 | OFPPS_STP_LEARN = 0x100, |
| 103 | OFPPS_STP_FORWARD = 0x200, |
| 104 | OFPPS_STP_BLOCK = 0x300, |
| 105 | OFPPS_STP_MASK = 0x300, |
| 106 | }; |
| 107 | |
| 108 | enum ofp_port { |
| 109 | OFPP_MAX = 0xffffff00, |
| 110 | OFPP_IN_PORT = 0xfffffff8, |
| 111 | OFPP_TABLE = 0xfffffff9, |
| 112 | OFPP_NORMAL = 0xfffffffa, |
| 113 | OFPP_FLOOD = 0xfffffffb, |
| 114 | OFPP_ALL = 0xfffffffc, |
| 115 | OFPP_CONTROLLER = 0xfffffffd, |
| 116 | OFPP_LOCAL = 0xfffffffe, |
| 117 | OFPP_NONE = 0xffffffff, |
| 118 | }; |
| 119 | |
| 120 | enum ofp_port_features { |
| 121 | OFPPF_10MB_HD = 0x1, |
| 122 | OFPPF_10MB_FD = 0x2, |
| 123 | OFPPF_100MB_HD = 0x4, |
| 124 | OFPPF_100MB_FD = 0x8, |
| 125 | OFPPF_1GB_HD = 0x10, |
| 126 | OFPPF_1GB_FD = 0x20, |
| 127 | OFPPF_10GB_FD = 0x40, |
| 128 | OFPPF_COPPER = 0x80, |
| 129 | OFPPF_FIBER = 0x100, |
| 130 | OFPPF_AUTONEG = 0x200, |
| 131 | OFPPF_PAUSE = 0x400, |
| 132 | OFPPF_PAUSE_ASYM = 0x800, |
| 133 | }; |
| 134 | |
| 135 | enum ofp_queue_properties { |
| 136 | OFPQT_NONE = 0, |
| 137 | OFPQT_MIN_RATE = 1, |
| 138 | }; |
| 139 | |
| 140 | enum ofp_flow_wildcards { |
| 141 | OFPFW_IN_PORT = 0x1, |
| 142 | OFPFW_DL_VLAN = 0x2, |
| 143 | OFPFW_DL_SRC = 0x4, |
| 144 | OFPFW_NW_DST_BITS = 0x6, |
| 145 | OFPFW_NW_SRC_BITS = 0x6, |
| 146 | OFPFW_NW_SRC_SHIFT = 0x8, |
| 147 | OFPFW_DL_DST = 0x8, |
| 148 | OFPFW_NW_DST_SHIFT = 0xe, |
| 149 | OFPFW_DL_TYPE = 0x10, |
| 150 | OFPFW_NW_PROTO = 0x20, |
| 151 | OFPFW_TP_SRC = 0x40, |
| 152 | OFPFW_TP_DST = 0x80, |
| 153 | OFPFW_NW_SRC_ALL = 0x2000, |
| 154 | OFPFW_NW_SRC_MASK = 0x3f00, |
| 155 | OFPFW_NW_DST_ALL = 0x80000, |
| 156 | OFPFW_NW_DST_MASK = 0xfc000, |
| 157 | OFPFW_DL_VLAN_PCP = 0x100000, |
| 158 | OFPFW_NW_TOS = 0x200000, |
Rob Sherwood | 6798fff | 2013-06-11 14:46:20 -0700 | [diff] [blame^] | 159 | OFPFW_SRC_META_ID = 0x400000, |
| 160 | OFPFW_DST_META_ID = 0x800000, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 161 | OFPFW_ALL = 0x3fffff, |
| 162 | }; |
| 163 | |
| 164 | enum ofp_action_type { |
| 165 | OFPAT_OUTPUT = 0, |
| 166 | OFPAT_SET_VLAN_VID = 1, |
| 167 | OFPAT_SET_VLAN_PCP = 2, |
| 168 | OFPAT_STRIP_VLAN = 3, |
| 169 | OFPAT_SET_DL_SRC = 4, |
| 170 | OFPAT_SET_DL_DST = 5, |
| 171 | OFPAT_SET_NW_SRC = 6, |
| 172 | OFPAT_SET_NW_DST = 7, |
| 173 | OFPAT_SET_NW_TOS = 8, |
| 174 | OFPAT_SET_TP_SRC = 9, |
| 175 | OFPAT_SET_TP_DST = 10, |
| 176 | OFPAT_ENQUEUE = 11, |
| 177 | OFPAT_VENDOR = 0xffff, |
| 178 | }; |
| 179 | |
| 180 | enum ofp_capabilities { |
| 181 | OFPC_FLOW_STATS = 0x1, |
| 182 | OFPC_TABLE_STATS = 0x2, |
| 183 | OFPC_PORT_STATS = 0x4, |
| 184 | OFPC_STP = 0x8, |
| 185 | OFPC_RESERVED = 0x10, |
| 186 | OFPC_IP_REASM = 0x20, |
| 187 | OFPC_QUEUE_STATS = 0x40, |
| 188 | OFPC_ARP_MATCH_IP = 0x80, |
| 189 | }; |
| 190 | |
| 191 | enum ofp_config_flags { |
| 192 | OFPC_FRAG_NORMAL = 0x0, |
| 193 | OFPC_FRAG_DROP = 0x1, |
| 194 | OFPC_FRAG_REASM = 0x2, |
| 195 | OFPC_FRAG_MASK = 0x3, |
| 196 | }; |
| 197 | |
| 198 | enum ofp_flow_mod_command { |
| 199 | OFPFC_ADD = 0, |
| 200 | OFPFC_MODIFY = 1, |
| 201 | OFPFC_MODIFY_STRICT = 2, |
| 202 | OFPFC_DELETE = 3, |
| 203 | OFPFC_DELETE_STRICT = 4, |
| 204 | }; |
| 205 | |
| 206 | enum ofp_flow_mod_flags { |
| 207 | OFPFF_SEND_FLOW_REM = 0x1, |
| 208 | OFPFF_CHECK_OVERLAP = 0x2, |
| 209 | OFPFF_EMERG = 0x4, |
| 210 | }; |
| 211 | |
| 212 | enum ofp_stats_reply_flags { |
| 213 | OFPSF_REPLY_MORE = 0x1, |
| 214 | }; |
| 215 | |
| 216 | enum ofp_stats_types { |
| 217 | OFPST_DESC = 0, |
| 218 | OFPST_FLOW = 1, |
| 219 | OFPST_AGGREGATE = 2, |
| 220 | OFPST_TABLE = 3, |
| 221 | OFPST_PORT = 4, |
| 222 | OFPST_QUEUE = 5, |
| 223 | OFPST_VENDOR = 0xffff, |
| 224 | }; |
| 225 | |
| 226 | enum ofp_packet_in_reason { |
| 227 | OFPR_NO_MATCH = 0, |
| 228 | OFPR_ACTION = 1, |
| 229 | }; |
| 230 | |
| 231 | enum ofp_flow_removed_reason { |
| 232 | OFPRR_IDLE_TIMEOUT = 0, |
| 233 | OFPRR_HARD_TIMEOUT = 1, |
| 234 | OFPRR_DELETE = 2, |
| 235 | }; |
| 236 | |
| 237 | enum ofp_port_reason { |
| 238 | OFPPR_ADD = 0, |
| 239 | OFPPR_DELETE = 1, |
| 240 | OFPPR_MODIFY = 2, |
| 241 | }; |
| 242 | |
| 243 | enum ofp_error_type { |
| 244 | OFPET_HELLO_FAILED = 0, |
| 245 | OFPET_BAD_REQUEST = 1, |
| 246 | OFPET_BAD_ACTION = 2, |
| 247 | OFPET_FLOW_MOD_FAILED = 3, |
| 248 | OFPET_PORT_MOD_FAILED = 4, |
| 249 | OFPET_QUEUE_OP_FAILED = 5, |
| 250 | }; |
| 251 | |
| 252 | enum ofp_hello_failed_code { |
| 253 | OFPHFC_INCOMPATIBLE = 0, |
| 254 | OFPHFC_EPERM = 1, |
| 255 | }; |
| 256 | |
| 257 | enum ofp_bad_request_code { |
| 258 | OFPBRC_BAD_VERSION = 0, |
| 259 | OFPBRC_BAD_TYPE = 1, |
| 260 | OFPBRC_BAD_STAT = 2, |
| 261 | OFPBRC_BAD_VENDOR = 3, |
| 262 | OFPBRC_BAD_SUBTYPE = 4, |
| 263 | OFPBRC_EPERM = 5, |
| 264 | OFPBRC_BAD_LEN = 6, |
| 265 | OFPBRC_BUFFER_EMPTY = 7, |
| 266 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 267 | }; |
| 268 | |
| 269 | enum ofp_bad_action_code { |
| 270 | OFPBAC_BAD_TYPE = 0, |
| 271 | OFPBAC_BAD_LEN = 1, |
| 272 | OFPBAC_BAD_VENDOR = 2, |
| 273 | OFPBAC_BAD_VENDOR_TYPE = 3, |
| 274 | OFPBAC_BAD_OUT_PORT = 4, |
| 275 | OFPBAC_BAD_ARGUMENT = 5, |
| 276 | OFPBAC_EPERM = 6, |
| 277 | OFPBAC_TOO_MANY = 7, |
| 278 | OFPBAC_BAD_QUEUE = 8, |
| 279 | }; |
| 280 | |
| 281 | enum ofp_flow_mod_failed_code { |
| 282 | OFPFMFC_ALL_TABLES_FULL = 0, |
| 283 | OFPFMFC_OVERLAP = 1, |
| 284 | OFPFMFC_EPERM = 2, |
| 285 | OFPFMFC_BAD_EMERG_TIMEOUT = 3, |
| 286 | OFPFMFC_BAD_COMMAND = 4, |
| 287 | OFPFMFC_UNSUPPORTED = 5, |
| 288 | }; |
| 289 | |
| 290 | enum ofp_port_mod_failed_code { |
| 291 | OFPPMFC_BAD_PORT = 0, |
| 292 | OFPPMFC_BAD_HW_ADDR = 1, |
| 293 | }; |
| 294 | |
| 295 | enum ofp_queue_op_failed_code { |
| 296 | OFPQOFC_BAD_PORT = 0, |
| 297 | OFPQOFC_BAD_QUEUE = 1, |
| 298 | OFPQOFC_EPERM = 2, |
| 299 | }; |
| 300 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 301 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 302 | uint8_t version; |
| 303 | uint8_t type; |
| 304 | uint16_t length; |
| 305 | uint32_t xid; |
| 306 | }; |
| 307 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 308 | struct of_hello { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 309 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 310 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 311 | uint16_t length; |
| 312 | uint32_t xid; |
| 313 | }; |
| 314 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 315 | struct of_echo_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 316 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 317 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 318 | uint16_t length; |
| 319 | uint32_t xid; |
| 320 | of_octets_t data; |
| 321 | }; |
| 322 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 323 | struct of_echo_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 324 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 325 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 326 | uint16_t length; |
| 327 | uint32_t xid; |
| 328 | of_octets_t data; |
| 329 | }; |
| 330 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 331 | struct of_experimenter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 332 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 333 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 334 | uint16_t length; |
| 335 | uint32_t xid; |
| 336 | uint32_t experimenter; |
| 337 | uint32_t subtype; |
| 338 | of_octets_t data; |
| 339 | }; |
| 340 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 341 | struct of_barrier_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 342 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 343 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 344 | uint16_t length; |
| 345 | uint32_t xid; |
| 346 | }; |
| 347 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 348 | struct of_barrier_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 349 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 350 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 351 | uint16_t length; |
| 352 | uint32_t xid; |
| 353 | }; |
| 354 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 355 | struct of_get_config_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 356 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 357 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 358 | uint16_t length; |
| 359 | uint32_t xid; |
| 360 | }; |
| 361 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 362 | struct of_get_config_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 363 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 364 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 365 | uint16_t length; |
| 366 | uint32_t xid; |
| 367 | uint16_t flags; |
| 368 | uint16_t miss_send_len; |
| 369 | }; |
| 370 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 371 | struct of_set_config { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 372 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 373 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 374 | uint16_t length; |
| 375 | uint32_t xid; |
| 376 | uint16_t flags; |
| 377 | uint16_t miss_send_len; |
| 378 | }; |
| 379 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 380 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 381 | of_port_no_t port_no; |
| 382 | of_mac_addr_t hw_addr; |
| 383 | of_port_name_t name; |
| 384 | uint32_t config; |
| 385 | uint32_t state; |
| 386 | uint32_t curr; |
| 387 | uint32_t advertised; |
| 388 | uint32_t supported; |
| 389 | uint32_t peer; |
| 390 | }; |
| 391 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 392 | struct of_features_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 393 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 394 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 395 | uint16_t length; |
| 396 | uint32_t xid; |
| 397 | }; |
| 398 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 399 | struct of_features_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 400 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 401 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 402 | uint16_t length; |
| 403 | uint32_t xid; |
| 404 | uint64_t datapath_id; |
| 405 | uint32_t n_buffers; |
| 406 | uint8_t n_tables; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 407 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 408 | uint32_t capabilities; |
| 409 | uint32_t actions; |
| 410 | list(of_port_desc_t) ports; |
| 411 | }; |
| 412 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 413 | struct of_port_status { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 414 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 415 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 416 | uint16_t length; |
| 417 | uint32_t xid; |
| 418 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 419 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 420 | of_port_desc_t desc; |
| 421 | }; |
| 422 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 423 | struct of_port_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 424 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 425 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 426 | uint16_t length; |
| 427 | uint32_t xid; |
| 428 | of_port_no_t port_no; |
| 429 | of_mac_addr_t hw_addr; |
| 430 | uint32_t config; |
| 431 | uint32_t mask; |
| 432 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 433 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 434 | }; |
| 435 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 436 | struct of_packet_in { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 437 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 438 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 439 | uint16_t length; |
| 440 | uint32_t xid; |
| 441 | uint32_t buffer_id; |
| 442 | uint16_t total_len; |
| 443 | of_port_no_t in_port; |
| 444 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 445 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 446 | of_octets_t data; |
| 447 | }; |
| 448 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 449 | struct of_action_output { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 450 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 451 | uint16_t len; |
| 452 | of_port_no_t port; |
| 453 | uint16_t max_len; |
| 454 | }; |
| 455 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 456 | struct of_action_set_vlan_vid { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 457 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 458 | uint16_t len; |
| 459 | uint16_t vlan_vid; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 460 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 461 | }; |
| 462 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 463 | struct of_action_strip_vlan { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 464 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 465 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 466 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 467 | }; |
| 468 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 469 | struct of_action_set_vlan_pcp { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 470 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 471 | uint16_t len; |
| 472 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 473 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 474 | }; |
| 475 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 476 | struct of_action_set_dl_src { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 477 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 478 | uint16_t len; |
| 479 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 480 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 481 | }; |
| 482 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 483 | struct of_action_set_dl_dst { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 484 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 485 | uint16_t len; |
| 486 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 487 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 488 | }; |
| 489 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 490 | struct of_action_set_nw_src { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 491 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 492 | uint16_t len; |
| 493 | uint32_t nw_addr; |
| 494 | }; |
| 495 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 496 | struct of_action_set_nw_dst { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 497 | uint16_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 498 | uint16_t len; |
| 499 | uint32_t nw_addr; |
| 500 | }; |
| 501 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 502 | struct of_action_set_tp_src { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 503 | uint16_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 504 | uint16_t len; |
| 505 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 506 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 507 | }; |
| 508 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 509 | struct of_action_set_tp_dst { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 510 | uint16_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 511 | uint16_t len; |
| 512 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 513 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 514 | }; |
| 515 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 516 | struct of_action_set_nw_tos { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 517 | uint16_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 518 | uint16_t len; |
| 519 | uint8_t nw_tos; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 520 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 521 | }; |
| 522 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 523 | struct of_action_experimenter { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 524 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 525 | uint16_t len; |
| 526 | uint32_t experimenter; |
| 527 | of_octets_t data; |
| 528 | }; |
| 529 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 530 | struct of_action_enqueue { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 531 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 532 | uint16_t len; |
| 533 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 534 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 535 | uint32_t queue_id; |
| 536 | }; |
| 537 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 538 | struct of_action { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 539 | uint16_t type; |
| 540 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 541 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 542 | }; |
| 543 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 544 | struct of_packet_out { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 545 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 546 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 547 | uint16_t length; |
| 548 | uint32_t xid; |
| 549 | uint32_t buffer_id; |
| 550 | of_port_no_t in_port; |
| 551 | uint16_t actions_len; |
| 552 | list(of_action_t) actions; |
| 553 | of_octets_t data; |
| 554 | }; |
| 555 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 556 | struct of_match_v1 { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 557 | of_wc_bmap_t wildcards; |
| 558 | of_port_no_t in_port; |
| 559 | of_mac_addr_t eth_src; |
| 560 | of_mac_addr_t eth_dst; |
| 561 | uint16_t vlan_vid; |
| 562 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 563 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 564 | uint16_t eth_type; |
| 565 | uint8_t ip_dscp; |
| 566 | uint8_t ip_proto; |
Rob Sherwood | 6798fff | 2013-06-11 14:46:20 -0700 | [diff] [blame^] | 567 | uint8_t src_meta_id; |
| 568 | uint8_t dst_meta_id; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 569 | uint32_t ipv4_src; |
| 570 | uint32_t ipv4_dst; |
| 571 | uint16_t tcp_src; |
| 572 | uint16_t tcp_dst; |
| 573 | }; |
| 574 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 575 | struct of_flow_add { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 576 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 577 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 578 | uint16_t length; |
| 579 | uint32_t xid; |
| 580 | of_match_t match; |
| 581 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 582 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 583 | uint16_t idle_timeout; |
| 584 | uint16_t hard_timeout; |
| 585 | uint16_t priority; |
| 586 | uint32_t buffer_id; |
| 587 | of_port_no_t out_port; |
| 588 | uint16_t flags; |
| 589 | list(of_action_t) actions; |
| 590 | }; |
| 591 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 592 | struct of_flow_modify { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 593 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 594 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 595 | uint16_t length; |
| 596 | uint32_t xid; |
| 597 | of_match_t match; |
| 598 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 599 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 600 | uint16_t idle_timeout; |
| 601 | uint16_t hard_timeout; |
| 602 | uint16_t priority; |
| 603 | uint32_t buffer_id; |
| 604 | of_port_no_t out_port; |
| 605 | uint16_t flags; |
| 606 | list(of_action_t) actions; |
| 607 | }; |
| 608 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 609 | struct of_flow_modify_strict { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 610 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 611 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 612 | uint16_t length; |
| 613 | uint32_t xid; |
| 614 | of_match_t match; |
| 615 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 616 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 617 | uint16_t idle_timeout; |
| 618 | uint16_t hard_timeout; |
| 619 | uint16_t priority; |
| 620 | uint32_t buffer_id; |
| 621 | of_port_no_t out_port; |
| 622 | uint16_t flags; |
| 623 | list(of_action_t) actions; |
| 624 | }; |
| 625 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 626 | struct of_flow_delete { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 627 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 628 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 629 | uint16_t length; |
| 630 | uint32_t xid; |
| 631 | of_match_t match; |
| 632 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 633 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 634 | uint16_t idle_timeout; |
| 635 | uint16_t hard_timeout; |
| 636 | uint16_t priority; |
| 637 | uint32_t buffer_id; |
| 638 | of_port_no_t out_port; |
| 639 | uint16_t flags; |
| 640 | list(of_action_t) actions; |
| 641 | }; |
| 642 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 643 | struct of_flow_delete_strict { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 644 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 645 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 646 | uint16_t length; |
| 647 | uint32_t xid; |
| 648 | of_match_t match; |
| 649 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 650 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 651 | uint16_t idle_timeout; |
| 652 | uint16_t hard_timeout; |
| 653 | uint16_t priority; |
| 654 | uint32_t buffer_id; |
| 655 | of_port_no_t out_port; |
| 656 | uint16_t flags; |
| 657 | list(of_action_t) actions; |
| 658 | }; |
| 659 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 660 | struct of_flow_removed { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 661 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 662 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 663 | uint16_t length; |
| 664 | uint32_t xid; |
| 665 | of_match_t match; |
| 666 | uint64_t cookie; |
| 667 | uint16_t priority; |
| 668 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 669 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 670 | uint32_t duration_sec; |
| 671 | uint32_t duration_nsec; |
| 672 | uint16_t idle_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 673 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 674 | uint64_t packet_count; |
| 675 | uint64_t byte_count; |
| 676 | }; |
| 677 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 678 | struct of_error_msg { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 679 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 680 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 681 | uint16_t length; |
| 682 | uint32_t xid; |
| 683 | uint16_t err_type; |
| 684 | uint16_t code; |
| 685 | of_octets_t data; |
| 686 | }; |
| 687 | |
| 688 | // STATS ENTRIES: flow, table, port, queue, |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 689 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 690 | uint16_t length; |
| 691 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 692 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 693 | of_match_t match; |
| 694 | uint32_t duration_sec; |
| 695 | uint32_t duration_nsec; |
| 696 | uint16_t priority; |
| 697 | uint16_t idle_timeout; |
| 698 | uint16_t hard_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 699 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 700 | uint64_t cookie; |
| 701 | uint64_t packet_count; |
| 702 | uint64_t byte_count; |
| 703 | list(of_action_t) actions; |
| 704 | }; |
| 705 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 706 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 707 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 708 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 709 | of_table_name_t name; |
| 710 | of_wc_bmap_t wildcards; |
| 711 | uint32_t max_entries; |
| 712 | uint32_t active_count; |
| 713 | uint64_t lookup_count; |
| 714 | uint64_t matched_count; |
| 715 | }; |
| 716 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 717 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 718 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 719 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 720 | uint64_t rx_packets; |
| 721 | uint64_t tx_packets; |
| 722 | uint64_t rx_bytes; |
| 723 | uint64_t tx_bytes; |
| 724 | uint64_t rx_dropped; |
| 725 | uint64_t tx_dropped; |
| 726 | uint64_t rx_errors; |
| 727 | uint64_t tx_errors; |
| 728 | uint64_t rx_frame_err; |
| 729 | uint64_t rx_over_err; |
| 730 | uint64_t rx_crc_err; |
| 731 | uint64_t collisions; |
| 732 | }; |
| 733 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 734 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 735 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 736 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 737 | uint32_t queue_id; |
| 738 | uint64_t tx_bytes; |
| 739 | uint64_t tx_packets; |
| 740 | uint64_t tx_errors; |
| 741 | }; |
| 742 | |
| 743 | // STATS request/reply: Desc, flow, agg, table, port, queue |
| 744 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 745 | struct of_desc_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 746 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 747 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 748 | uint16_t length; |
| 749 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 750 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 751 | uint16_t flags; |
| 752 | }; |
| 753 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 754 | struct of_desc_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 755 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 756 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 757 | uint16_t length; |
| 758 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 759 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 760 | uint16_t flags; |
| 761 | of_desc_str_t mfr_desc; |
| 762 | of_desc_str_t hw_desc; |
| 763 | of_desc_str_t sw_desc; |
| 764 | of_serial_num_t serial_num; |
| 765 | of_desc_str_t dp_desc; |
| 766 | }; |
| 767 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 768 | struct of_flow_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 769 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 770 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 771 | uint16_t length; |
| 772 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 773 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 774 | uint16_t flags; |
| 775 | of_match_t match; |
| 776 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 777 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 778 | of_port_no_t out_port; |
| 779 | }; |
| 780 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 781 | struct of_flow_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 782 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 783 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 784 | uint16_t length; |
| 785 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 786 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 787 | uint16_t flags; |
| 788 | list(of_flow_stats_entry_t) entries; |
| 789 | }; |
| 790 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 791 | struct of_aggregate_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 792 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 793 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 794 | uint16_t length; |
| 795 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 796 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 797 | uint16_t flags; |
| 798 | of_match_t match; |
| 799 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 800 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 801 | of_port_no_t out_port; |
| 802 | }; |
| 803 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 804 | struct of_aggregate_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 805 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 806 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 807 | uint16_t length; |
| 808 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 809 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 810 | uint16_t flags; |
| 811 | uint64_t packet_count; |
| 812 | uint64_t byte_count; |
| 813 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 814 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 815 | }; |
| 816 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 817 | struct of_table_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 818 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 819 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 820 | uint16_t length; |
| 821 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 822 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 823 | uint16_t flags; |
| 824 | }; |
| 825 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 826 | struct of_table_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 827 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 828 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 829 | uint16_t length; |
| 830 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 831 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 832 | uint16_t flags; |
| 833 | list(of_table_stats_entry_t) entries; |
| 834 | }; |
| 835 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 836 | struct of_port_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 837 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 838 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 839 | uint16_t length; |
| 840 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 841 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 842 | uint16_t flags; |
| 843 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 844 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 845 | }; |
| 846 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 847 | struct of_port_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 848 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 849 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 850 | uint16_t length; |
| 851 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 852 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 853 | uint16_t flags; |
| 854 | list(of_port_stats_entry_t) entries; |
| 855 | }; |
| 856 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 857 | struct of_queue_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 858 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 859 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 860 | uint16_t length; |
| 861 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 862 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 863 | uint16_t flags; |
| 864 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 865 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 866 | uint32_t queue_id; |
| 867 | }; |
| 868 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 869 | struct of_queue_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 870 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 871 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 872 | uint16_t length; |
| 873 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 874 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 875 | uint16_t flags; |
| 876 | list(of_queue_stats_entry_t) entries; |
| 877 | }; |
| 878 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 879 | struct of_experimenter_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 880 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 881 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 882 | uint16_t length; |
| 883 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 884 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 885 | uint16_t flags; |
| 886 | uint32_t experimenter; |
| 887 | of_octets_t data; |
| 888 | }; |
| 889 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 890 | struct of_experimenter_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 891 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 892 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 893 | uint16_t length; |
| 894 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 895 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 896 | uint16_t flags; |
| 897 | uint32_t experimenter; |
| 898 | of_octets_t data; |
| 899 | }; |
| 900 | |
| 901 | // END OF STATS OBJECTS |
| 902 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 903 | struct of_queue_prop { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 904 | uint16_t type; |
| 905 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 906 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 907 | }; |
| 908 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 909 | struct of_queue_prop_min_rate { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 910 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 911 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 912 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 913 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 914 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 915 | }; |
| 916 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 917 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 918 | uint32_t queue_id; |
| 919 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 920 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 921 | list(of_queue_prop_t) properties; |
| 922 | }; |
| 923 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 924 | struct of_queue_get_config_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 925 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 926 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 927 | uint16_t length; |
| 928 | uint32_t xid; |
| 929 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 930 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 931 | }; |
| 932 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 933 | struct of_queue_get_config_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 934 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 935 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 936 | uint16_t length; |
| 937 | uint32_t xid; |
| 938 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 939 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 940 | list(of_packet_queue_t) queues; |
| 941 | }; |