Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 1 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
| 38 | OFP_TCP_PORT = 6633, |
| 39 | OFP_SSL_PORT = 6633, |
| 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFP_VLAN_NONE = 0xffff, |
| 46 | |
| 47 | OFPFW_ICMP_TYPE = 0x40, |
| 48 | OFPFW_ICMP_CODE = 0x80, |
| 49 | |
| 50 | OFP_DL_TYPE_ETH2_CUTOFF = 0x600, |
| 51 | OFP_DL_TYPE_NOT_ETH_TYPE = 0x5ff, |
| 52 | |
| 53 | OFP_FLOW_PERMANENT = 0, |
| 54 | |
| 55 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 56 | |
| 57 | DESC_STR_LEN = 256, |
| 58 | SERIAL_NUM_LEN = 32, |
| 59 | |
| 60 | OFPQ_ALL = 0xffffffff, |
| 61 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 62 | }; |
| 63 | |
| 64 | enum ofp_type { |
| 65 | OFPT_HELLO = 0, |
| 66 | OFPT_ERROR = 1, |
| 67 | OFPT_ECHO_REQUEST = 2, |
| 68 | OFPT_ECHO_REPLY = 3, |
| 69 | OFPT_VENDOR = 4, |
| 70 | OFPT_FEATURES_REQUEST = 5, |
| 71 | OFPT_FEATURES_REPLY = 6, |
| 72 | OFPT_GET_CONFIG_REQUEST = 7, |
| 73 | OFPT_GET_CONFIG_REPLY = 8, |
| 74 | OFPT_SET_CONFIG = 9, |
| 75 | OFPT_PACKET_IN = 10, |
| 76 | OFPT_FLOW_REMOVED = 11, |
| 77 | OFPT_PORT_STATUS = 12, |
| 78 | OFPT_PACKET_OUT = 13, |
| 79 | OFPT_FLOW_MOD = 14, |
| 80 | OFPT_PORT_MOD = 15, |
| 81 | OFPT_STATS_REQUEST = 16, |
| 82 | OFPT_STATS_REPLY = 17, |
| 83 | OFPT_BARRIER_REQUEST = 18, |
| 84 | OFPT_BARRIER_REPLY = 19, |
| 85 | OFPT_QUEUE_GET_CONFIG_REQUEST = 20, |
| 86 | OFPT_QUEUE_GET_CONFIG_REPLY = 21, |
| 87 | }; |
| 88 | |
| 89 | enum ofp_port_config { |
| 90 | OFPPC_PORT_DOWN = 0x1, |
| 91 | OFPPC_NO_STP = 0x2, |
| 92 | OFPPC_NO_RECV = 0x4, |
| 93 | OFPPC_NO_RECV_STP = 0x8, |
| 94 | OFPPC_NO_FLOOD = 0x10, |
| 95 | OFPPC_NO_FWD = 0x20, |
| 96 | OFPPC_NO_PACKET_IN = 0x40, |
| 97 | }; |
| 98 | |
| 99 | enum ofp_port_state { |
| 100 | OFPPS_STP_LISTEN = 0, |
| 101 | OFPPS_LINK_DOWN = 1, |
| 102 | OFPPS_STP_LEARN = 0x100, |
| 103 | OFPPS_STP_FORWARD = 0x200, |
| 104 | OFPPS_STP_BLOCK = 0x300, |
| 105 | OFPPS_STP_MASK = 0x300, |
| 106 | }; |
| 107 | |
| 108 | enum ofp_port { |
| 109 | OFPP_MAX = 0xffffff00, |
| 110 | OFPP_IN_PORT = 0xfffffff8, |
| 111 | OFPP_TABLE = 0xfffffff9, |
| 112 | OFPP_NORMAL = 0xfffffffa, |
| 113 | OFPP_FLOOD = 0xfffffffb, |
| 114 | OFPP_ALL = 0xfffffffc, |
| 115 | OFPP_CONTROLLER = 0xfffffffd, |
| 116 | OFPP_LOCAL = 0xfffffffe, |
| 117 | OFPP_NONE = 0xffffffff, |
| 118 | }; |
| 119 | |
| 120 | enum ofp_port_features { |
| 121 | OFPPF_10MB_HD = 0x1, |
| 122 | OFPPF_10MB_FD = 0x2, |
| 123 | OFPPF_100MB_HD = 0x4, |
| 124 | OFPPF_100MB_FD = 0x8, |
| 125 | OFPPF_1GB_HD = 0x10, |
| 126 | OFPPF_1GB_FD = 0x20, |
| 127 | OFPPF_10GB_FD = 0x40, |
| 128 | OFPPF_COPPER = 0x80, |
| 129 | OFPPF_FIBER = 0x100, |
| 130 | OFPPF_AUTONEG = 0x200, |
| 131 | OFPPF_PAUSE = 0x400, |
| 132 | OFPPF_PAUSE_ASYM = 0x800, |
| 133 | }; |
| 134 | |
| 135 | enum ofp_queue_properties { |
| 136 | OFPQT_NONE = 0, |
| 137 | OFPQT_MIN_RATE = 1, |
| 138 | }; |
| 139 | |
| 140 | enum ofp_flow_wildcards { |
| 141 | OFPFW_IN_PORT = 0x1, |
| 142 | OFPFW_DL_VLAN = 0x2, |
| 143 | OFPFW_DL_SRC = 0x4, |
| 144 | OFPFW_NW_DST_BITS = 0x6, |
| 145 | OFPFW_NW_SRC_BITS = 0x6, |
| 146 | OFPFW_NW_SRC_SHIFT = 0x8, |
| 147 | OFPFW_DL_DST = 0x8, |
| 148 | OFPFW_NW_DST_SHIFT = 0xe, |
| 149 | OFPFW_DL_TYPE = 0x10, |
| 150 | OFPFW_NW_PROTO = 0x20, |
| 151 | OFPFW_TP_SRC = 0x40, |
| 152 | OFPFW_TP_DST = 0x80, |
| 153 | OFPFW_NW_SRC_ALL = 0x2000, |
| 154 | OFPFW_NW_SRC_MASK = 0x3f00, |
| 155 | OFPFW_NW_DST_ALL = 0x80000, |
| 156 | OFPFW_NW_DST_MASK = 0xfc000, |
| 157 | OFPFW_DL_VLAN_PCP = 0x100000, |
| 158 | OFPFW_NW_TOS = 0x200000, |
| 159 | OFPFW_ALL = 0x3fffff, |
| 160 | }; |
| 161 | |
| 162 | enum ofp_action_type { |
| 163 | OFPAT_OUTPUT = 0, |
| 164 | OFPAT_SET_VLAN_VID = 1, |
| 165 | OFPAT_SET_VLAN_PCP = 2, |
| 166 | OFPAT_STRIP_VLAN = 3, |
| 167 | OFPAT_SET_DL_SRC = 4, |
| 168 | OFPAT_SET_DL_DST = 5, |
| 169 | OFPAT_SET_NW_SRC = 6, |
| 170 | OFPAT_SET_NW_DST = 7, |
| 171 | OFPAT_SET_NW_TOS = 8, |
| 172 | OFPAT_SET_TP_SRC = 9, |
| 173 | OFPAT_SET_TP_DST = 10, |
| 174 | OFPAT_ENQUEUE = 11, |
| 175 | OFPAT_VENDOR = 0xffff, |
| 176 | }; |
| 177 | |
| 178 | enum ofp_capabilities { |
| 179 | OFPC_FLOW_STATS = 0x1, |
| 180 | OFPC_TABLE_STATS = 0x2, |
| 181 | OFPC_PORT_STATS = 0x4, |
| 182 | OFPC_STP = 0x8, |
| 183 | OFPC_RESERVED = 0x10, |
| 184 | OFPC_IP_REASM = 0x20, |
| 185 | OFPC_QUEUE_STATS = 0x40, |
| 186 | OFPC_ARP_MATCH_IP = 0x80, |
| 187 | }; |
| 188 | |
| 189 | enum ofp_config_flags { |
| 190 | OFPC_FRAG_NORMAL = 0x0, |
| 191 | OFPC_FRAG_DROP = 0x1, |
| 192 | OFPC_FRAG_REASM = 0x2, |
| 193 | OFPC_FRAG_MASK = 0x3, |
| 194 | }; |
| 195 | |
| 196 | enum ofp_flow_mod_command { |
| 197 | OFPFC_ADD = 0, |
| 198 | OFPFC_MODIFY = 1, |
| 199 | OFPFC_MODIFY_STRICT = 2, |
| 200 | OFPFC_DELETE = 3, |
| 201 | OFPFC_DELETE_STRICT = 4, |
| 202 | }; |
| 203 | |
| 204 | enum ofp_flow_mod_flags { |
| 205 | OFPFF_SEND_FLOW_REM = 0x1, |
| 206 | OFPFF_CHECK_OVERLAP = 0x2, |
| 207 | OFPFF_EMERG = 0x4, |
| 208 | }; |
| 209 | |
| 210 | enum ofp_stats_reply_flags { |
| 211 | OFPSF_REPLY_MORE = 0x1, |
| 212 | }; |
| 213 | |
| 214 | enum ofp_stats_types { |
| 215 | OFPST_DESC = 0, |
| 216 | OFPST_FLOW = 1, |
| 217 | OFPST_AGGREGATE = 2, |
| 218 | OFPST_TABLE = 3, |
| 219 | OFPST_PORT = 4, |
| 220 | OFPST_QUEUE = 5, |
| 221 | OFPST_VENDOR = 0xffff, |
| 222 | }; |
| 223 | |
| 224 | enum ofp_packet_in_reason { |
| 225 | OFPR_NO_MATCH = 0, |
| 226 | OFPR_ACTION = 1, |
| 227 | }; |
| 228 | |
| 229 | enum ofp_flow_removed_reason { |
| 230 | OFPRR_IDLE_TIMEOUT = 0, |
| 231 | OFPRR_HARD_TIMEOUT = 1, |
| 232 | OFPRR_DELETE = 2, |
| 233 | }; |
| 234 | |
| 235 | enum ofp_port_reason { |
| 236 | OFPPR_ADD = 0, |
| 237 | OFPPR_DELETE = 1, |
| 238 | OFPPR_MODIFY = 2, |
| 239 | }; |
| 240 | |
| 241 | enum ofp_error_type { |
| 242 | OFPET_HELLO_FAILED = 0, |
| 243 | OFPET_BAD_REQUEST = 1, |
| 244 | OFPET_BAD_ACTION = 2, |
| 245 | OFPET_FLOW_MOD_FAILED = 3, |
| 246 | OFPET_PORT_MOD_FAILED = 4, |
| 247 | OFPET_QUEUE_OP_FAILED = 5, |
| 248 | }; |
| 249 | |
| 250 | enum ofp_hello_failed_code { |
| 251 | OFPHFC_INCOMPATIBLE = 0, |
| 252 | OFPHFC_EPERM = 1, |
| 253 | }; |
| 254 | |
| 255 | enum ofp_bad_request_code { |
| 256 | OFPBRC_BAD_VERSION = 0, |
| 257 | OFPBRC_BAD_TYPE = 1, |
| 258 | OFPBRC_BAD_STAT = 2, |
| 259 | OFPBRC_BAD_VENDOR = 3, |
| 260 | OFPBRC_BAD_SUBTYPE = 4, |
| 261 | OFPBRC_EPERM = 5, |
| 262 | OFPBRC_BAD_LEN = 6, |
| 263 | OFPBRC_BUFFER_EMPTY = 7, |
| 264 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 265 | }; |
| 266 | |
| 267 | enum ofp_bad_action_code { |
| 268 | OFPBAC_BAD_TYPE = 0, |
| 269 | OFPBAC_BAD_LEN = 1, |
| 270 | OFPBAC_BAD_VENDOR = 2, |
| 271 | OFPBAC_BAD_VENDOR_TYPE = 3, |
| 272 | OFPBAC_BAD_OUT_PORT = 4, |
| 273 | OFPBAC_BAD_ARGUMENT = 5, |
| 274 | OFPBAC_EPERM = 6, |
| 275 | OFPBAC_TOO_MANY = 7, |
| 276 | OFPBAC_BAD_QUEUE = 8, |
| 277 | }; |
| 278 | |
| 279 | enum ofp_flow_mod_failed_code { |
| 280 | OFPFMFC_ALL_TABLES_FULL = 0, |
| 281 | OFPFMFC_OVERLAP = 1, |
| 282 | OFPFMFC_EPERM = 2, |
| 283 | OFPFMFC_BAD_EMERG_TIMEOUT = 3, |
| 284 | OFPFMFC_BAD_COMMAND = 4, |
| 285 | OFPFMFC_UNSUPPORTED = 5, |
| 286 | }; |
| 287 | |
| 288 | enum ofp_port_mod_failed_code { |
| 289 | OFPPMFC_BAD_PORT = 0, |
| 290 | OFPPMFC_BAD_HW_ADDR = 1, |
| 291 | }; |
| 292 | |
| 293 | enum ofp_queue_op_failed_code { |
| 294 | OFPQOFC_BAD_PORT = 0, |
| 295 | OFPQOFC_BAD_QUEUE = 1, |
| 296 | OFPQOFC_EPERM = 2, |
| 297 | }; |
| 298 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 299 | /* XXX rename to of_message */ |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 300 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 301 | uint8_t version; |
| 302 | uint8_t type; |
| 303 | uint16_t length; |
| 304 | uint32_t xid; |
| 305 | }; |
| 306 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 307 | struct of_hello : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 308 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 309 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 310 | uint16_t length; |
| 311 | uint32_t xid; |
| 312 | }; |
| 313 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 314 | struct of_echo_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 315 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 316 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 317 | uint16_t length; |
| 318 | uint32_t xid; |
| 319 | of_octets_t data; |
| 320 | }; |
| 321 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 322 | struct of_echo_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 323 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 324 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 325 | uint16_t length; |
| 326 | uint32_t xid; |
| 327 | of_octets_t data; |
| 328 | }; |
| 329 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 330 | struct of_experimenter : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 331 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 332 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 333 | uint16_t length; |
| 334 | uint32_t xid; |
| 335 | uint32_t experimenter; |
| 336 | uint32_t subtype; |
| 337 | of_octets_t data; |
| 338 | }; |
| 339 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 340 | struct of_barrier_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 341 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 342 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 343 | uint16_t length; |
| 344 | uint32_t xid; |
| 345 | }; |
| 346 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 347 | struct of_barrier_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 348 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 349 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 350 | uint16_t length; |
| 351 | uint32_t xid; |
| 352 | }; |
| 353 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 354 | struct of_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 355 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 356 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 357 | uint16_t length; |
| 358 | uint32_t xid; |
| 359 | }; |
| 360 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 361 | struct of_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 362 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 363 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 364 | uint16_t length; |
| 365 | uint32_t xid; |
| 366 | uint16_t flags; |
| 367 | uint16_t miss_send_len; |
| 368 | }; |
| 369 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 370 | struct of_set_config : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 371 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 372 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 373 | uint16_t length; |
| 374 | uint32_t xid; |
| 375 | uint16_t flags; |
| 376 | uint16_t miss_send_len; |
| 377 | }; |
| 378 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 379 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 380 | of_port_no_t port_no; |
| 381 | of_mac_addr_t hw_addr; |
| 382 | of_port_name_t name; |
| 383 | uint32_t config; |
| 384 | uint32_t state; |
| 385 | uint32_t curr; |
| 386 | uint32_t advertised; |
| 387 | uint32_t supported; |
| 388 | uint32_t peer; |
| 389 | }; |
| 390 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 391 | struct of_features_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 392 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 393 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 394 | uint16_t length; |
| 395 | uint32_t xid; |
| 396 | }; |
| 397 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 398 | struct of_features_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 399 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 400 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 401 | uint16_t length; |
| 402 | uint32_t xid; |
| 403 | uint64_t datapath_id; |
| 404 | uint32_t n_buffers; |
| 405 | uint8_t n_tables; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 406 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 407 | uint32_t capabilities; |
| 408 | uint32_t actions; |
| 409 | list(of_port_desc_t) ports; |
| 410 | }; |
| 411 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 412 | struct of_port_status : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 413 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 414 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 415 | uint16_t length; |
| 416 | uint32_t xid; |
| 417 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 418 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 419 | of_port_desc_t desc; |
| 420 | }; |
| 421 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 422 | struct of_port_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 423 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 424 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 425 | uint16_t length; |
| 426 | uint32_t xid; |
| 427 | of_port_no_t port_no; |
| 428 | of_mac_addr_t hw_addr; |
| 429 | uint32_t config; |
| 430 | uint32_t mask; |
| 431 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 432 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 433 | }; |
| 434 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 435 | struct of_packet_in : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 436 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 437 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 438 | uint16_t length; |
| 439 | uint32_t xid; |
| 440 | uint32_t buffer_id; |
| 441 | uint16_t total_len; |
| 442 | of_port_no_t in_port; |
| 443 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 444 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 445 | of_octets_t data; |
| 446 | }; |
| 447 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 448 | struct of_action_output : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 449 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 450 | uint16_t len; |
| 451 | of_port_no_t port; |
| 452 | uint16_t max_len; |
| 453 | }; |
| 454 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 455 | struct of_action_set_vlan_vid : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 456 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 457 | uint16_t len; |
| 458 | uint16_t vlan_vid; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 459 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 460 | }; |
| 461 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 462 | struct of_action_strip_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 463 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 464 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 465 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 466 | }; |
| 467 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 468 | struct of_action_set_vlan_pcp : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 469 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 470 | uint16_t len; |
| 471 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 472 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 473 | }; |
| 474 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 475 | struct of_action_set_dl_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 476 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 477 | uint16_t len; |
| 478 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 479 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 480 | }; |
| 481 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 482 | struct of_action_set_dl_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 483 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 484 | uint16_t len; |
| 485 | of_mac_addr_t dl_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 486 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 487 | }; |
| 488 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 489 | struct of_action_set_nw_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 490 | uint16_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 491 | uint16_t len; |
| 492 | uint32_t nw_addr; |
| 493 | }; |
| 494 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 495 | struct of_action_set_nw_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 496 | uint16_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 497 | uint16_t len; |
| 498 | uint32_t nw_addr; |
| 499 | }; |
| 500 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 501 | struct of_action_set_tp_src : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 502 | uint16_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 503 | uint16_t len; |
| 504 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 505 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 506 | }; |
| 507 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 508 | struct of_action_set_tp_dst : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 509 | uint16_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 510 | uint16_t len; |
| 511 | uint16_t tp_port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 512 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 513 | }; |
| 514 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 515 | struct of_action_set_nw_tos : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 516 | uint16_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 517 | uint16_t len; |
| 518 | uint8_t nw_tos; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 519 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 520 | }; |
| 521 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 522 | struct of_action_experimenter : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 523 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 524 | uint16_t len; |
| 525 | uint32_t experimenter; |
| 526 | of_octets_t data; |
| 527 | }; |
| 528 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 529 | struct of_action_enqueue : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 530 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 531 | uint16_t len; |
| 532 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 533 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 534 | uint32_t queue_id; |
| 535 | }; |
| 536 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 537 | struct of_action { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 538 | uint16_t type; |
| 539 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 540 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 541 | }; |
| 542 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 543 | struct of_packet_out : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 544 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 545 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 546 | uint16_t length; |
| 547 | uint32_t xid; |
| 548 | uint32_t buffer_id; |
| 549 | of_port_no_t in_port; |
| 550 | uint16_t actions_len; |
| 551 | list(of_action_t) actions; |
| 552 | of_octets_t data; |
| 553 | }; |
| 554 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 555 | struct of_match_v1 { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 556 | of_wc_bmap_t wildcards; |
| 557 | of_port_no_t in_port; |
| 558 | of_mac_addr_t eth_src; |
| 559 | of_mac_addr_t eth_dst; |
| 560 | uint16_t vlan_vid; |
| 561 | uint8_t vlan_pcp; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 562 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 563 | uint16_t eth_type; |
| 564 | uint8_t ip_dscp; |
| 565 | uint8_t ip_proto; |
Rob Sherwood | 53989c8 | 2013-07-03 16:49:50 -0700 | [diff] [blame] | 566 | pad(2); |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 567 | of_ipv4_t ipv4_src; |
| 568 | of_ipv4_t ipv4_dst; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 569 | uint16_t tcp_src; |
| 570 | uint16_t tcp_dst; |
| 571 | }; |
| 572 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 573 | struct of_flow_mod : of_header { |
| 574 | uint8_t version; |
| 575 | uint8_t type == 14; |
| 576 | uint16_t length; |
| 577 | uint32_t xid; |
| 578 | of_match_t match; |
| 579 | uint64_t cookie; |
| 580 | of_fm_cmd_t _command; |
| 581 | uint16_t idle_timeout; |
| 582 | uint16_t hard_timeout; |
| 583 | uint16_t priority; |
| 584 | uint32_t buffer_id; |
| 585 | of_port_no_t out_port; |
| 586 | uint16_t flags; |
| 587 | list(of_action_t) actions; |
| 588 | }; |
| 589 | |
| 590 | struct of_flow_add : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 591 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 592 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 593 | uint16_t length; |
| 594 | uint32_t xid; |
| 595 | of_match_t match; |
| 596 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 597 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 598 | uint16_t idle_timeout; |
| 599 | uint16_t hard_timeout; |
| 600 | uint16_t priority; |
| 601 | uint32_t buffer_id; |
| 602 | of_port_no_t out_port; |
| 603 | uint16_t flags; |
| 604 | list(of_action_t) actions; |
| 605 | }; |
| 606 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 607 | struct of_flow_modify : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 608 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 609 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 610 | uint16_t length; |
| 611 | uint32_t xid; |
| 612 | of_match_t match; |
| 613 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 614 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 615 | uint16_t idle_timeout; |
| 616 | uint16_t hard_timeout; |
| 617 | uint16_t priority; |
| 618 | uint32_t buffer_id; |
| 619 | of_port_no_t out_port; |
| 620 | uint16_t flags; |
| 621 | list(of_action_t) actions; |
| 622 | }; |
| 623 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 624 | struct of_flow_modify_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 625 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 626 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 627 | uint16_t length; |
| 628 | uint32_t xid; |
| 629 | of_match_t match; |
| 630 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 631 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 632 | uint16_t idle_timeout; |
| 633 | uint16_t hard_timeout; |
| 634 | uint16_t priority; |
| 635 | uint32_t buffer_id; |
| 636 | of_port_no_t out_port; |
| 637 | uint16_t flags; |
| 638 | list(of_action_t) actions; |
| 639 | }; |
| 640 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 641 | struct of_flow_delete : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 642 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 643 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 644 | uint16_t length; |
| 645 | uint32_t xid; |
| 646 | of_match_t match; |
| 647 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 648 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 649 | uint16_t idle_timeout; |
| 650 | uint16_t hard_timeout; |
| 651 | uint16_t priority; |
| 652 | uint32_t buffer_id; |
| 653 | of_port_no_t out_port; |
| 654 | uint16_t flags; |
| 655 | list(of_action_t) actions; |
| 656 | }; |
| 657 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 658 | struct of_flow_delete_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 659 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 660 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 661 | uint16_t length; |
| 662 | uint32_t xid; |
| 663 | of_match_t match; |
| 664 | uint64_t cookie; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 665 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 666 | uint16_t idle_timeout; |
| 667 | uint16_t hard_timeout; |
| 668 | uint16_t priority; |
| 669 | uint32_t buffer_id; |
| 670 | of_port_no_t out_port; |
| 671 | uint16_t flags; |
| 672 | list(of_action_t) actions; |
| 673 | }; |
| 674 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 675 | struct of_flow_removed : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 676 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 677 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 678 | uint16_t length; |
| 679 | uint32_t xid; |
| 680 | of_match_t match; |
| 681 | uint64_t cookie; |
| 682 | uint16_t priority; |
| 683 | uint8_t reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 684 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 685 | uint32_t duration_sec; |
| 686 | uint32_t duration_nsec; |
| 687 | uint16_t idle_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 688 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 689 | uint64_t packet_count; |
| 690 | uint64_t byte_count; |
| 691 | }; |
| 692 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 693 | struct of_error_msg : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 694 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 695 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 696 | uint16_t length; |
| 697 | uint32_t xid; |
| 698 | uint16_t err_type; |
| 699 | uint16_t code; |
| 700 | of_octets_t data; |
| 701 | }; |
| 702 | |
| 703 | // STATS ENTRIES: flow, table, port, queue, |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 704 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 705 | uint16_t length; |
| 706 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 707 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 708 | of_match_t match; |
| 709 | uint32_t duration_sec; |
| 710 | uint32_t duration_nsec; |
| 711 | uint16_t priority; |
| 712 | uint16_t idle_timeout; |
| 713 | uint16_t hard_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 714 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 715 | uint64_t cookie; |
| 716 | uint64_t packet_count; |
| 717 | uint64_t byte_count; |
| 718 | list(of_action_t) actions; |
| 719 | }; |
| 720 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 721 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 722 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 723 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 724 | of_table_name_t name; |
| 725 | of_wc_bmap_t wildcards; |
| 726 | uint32_t max_entries; |
| 727 | uint32_t active_count; |
| 728 | uint64_t lookup_count; |
| 729 | uint64_t matched_count; |
| 730 | }; |
| 731 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 732 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 733 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 734 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 735 | uint64_t rx_packets; |
| 736 | uint64_t tx_packets; |
| 737 | uint64_t rx_bytes; |
| 738 | uint64_t tx_bytes; |
| 739 | uint64_t rx_dropped; |
| 740 | uint64_t tx_dropped; |
| 741 | uint64_t rx_errors; |
| 742 | uint64_t tx_errors; |
| 743 | uint64_t rx_frame_err; |
| 744 | uint64_t rx_over_err; |
| 745 | uint64_t rx_crc_err; |
| 746 | uint64_t collisions; |
| 747 | }; |
| 748 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 749 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 750 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 751 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 752 | uint32_t queue_id; |
| 753 | uint64_t tx_bytes; |
| 754 | uint64_t tx_packets; |
| 755 | uint64_t tx_errors; |
| 756 | }; |
| 757 | |
| 758 | // STATS request/reply: Desc, flow, agg, table, port, queue |
| 759 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 760 | struct of_stats_request : of_header { |
| 761 | uint8_t version; |
| 762 | uint8_t type == 16; |
| 763 | uint16_t length; |
| 764 | uint32_t xid; |
| 765 | uint16_t stats_type; |
| 766 | uint16_t flags; |
| 767 | }; |
| 768 | |
| 769 | struct of_stats_reply : of_header { |
| 770 | uint8_t version; |
| 771 | uint8_t type == 17; |
| 772 | uint16_t length; |
| 773 | uint32_t xid; |
| 774 | uint16_t stats_type; |
| 775 | uint16_t flags; |
| 776 | }; |
| 777 | |
| 778 | struct of_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 779 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 780 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 781 | uint16_t length; |
| 782 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 783 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 784 | uint16_t flags; |
| 785 | }; |
| 786 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 787 | struct of_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 788 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 789 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 790 | uint16_t length; |
| 791 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 792 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 793 | uint16_t flags; |
| 794 | of_desc_str_t mfr_desc; |
| 795 | of_desc_str_t hw_desc; |
| 796 | of_desc_str_t sw_desc; |
| 797 | of_serial_num_t serial_num; |
| 798 | of_desc_str_t dp_desc; |
| 799 | }; |
| 800 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 801 | struct of_flow_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 802 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 803 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 804 | uint16_t length; |
| 805 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 806 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 807 | uint16_t flags; |
| 808 | of_match_t match; |
| 809 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 810 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 811 | of_port_no_t out_port; |
| 812 | }; |
| 813 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 814 | struct of_flow_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 815 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 816 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 817 | uint16_t length; |
| 818 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 819 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 820 | uint16_t flags; |
| 821 | list(of_flow_stats_entry_t) entries; |
| 822 | }; |
| 823 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 824 | struct of_aggregate_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 825 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 826 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 827 | uint16_t length; |
| 828 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 829 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 830 | uint16_t flags; |
| 831 | of_match_t match; |
| 832 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 833 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 834 | of_port_no_t out_port; |
| 835 | }; |
| 836 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 837 | struct of_aggregate_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 838 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 839 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 840 | uint16_t length; |
| 841 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 842 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 843 | uint16_t flags; |
| 844 | uint64_t packet_count; |
| 845 | uint64_t byte_count; |
| 846 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 847 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 848 | }; |
| 849 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 850 | struct of_table_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 851 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 852 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 853 | uint16_t length; |
| 854 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 855 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 856 | uint16_t flags; |
| 857 | }; |
| 858 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 859 | struct of_table_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 860 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 861 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 862 | uint16_t length; |
| 863 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 864 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 865 | uint16_t flags; |
| 866 | list(of_table_stats_entry_t) entries; |
| 867 | }; |
| 868 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 869 | struct of_port_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 870 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 871 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 872 | uint16_t length; |
| 873 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 874 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 875 | uint16_t flags; |
| 876 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 877 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 878 | }; |
| 879 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 880 | struct of_port_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 881 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 882 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 883 | uint16_t length; |
| 884 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 885 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 886 | uint16_t flags; |
| 887 | list(of_port_stats_entry_t) entries; |
| 888 | }; |
| 889 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 890 | struct of_queue_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 891 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 892 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 893 | uint16_t length; |
| 894 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 895 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 896 | uint16_t flags; |
| 897 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 898 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 899 | uint32_t queue_id; |
| 900 | }; |
| 901 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 902 | struct of_queue_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 903 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 904 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 905 | uint16_t length; |
| 906 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 907 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 908 | uint16_t flags; |
| 909 | list(of_queue_stats_entry_t) entries; |
| 910 | }; |
| 911 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 912 | struct of_experimenter_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 913 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 914 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 915 | uint16_t length; |
| 916 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 917 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 918 | uint16_t flags; |
| 919 | uint32_t experimenter; |
| 920 | of_octets_t data; |
| 921 | }; |
| 922 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 923 | struct of_experimenter_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 924 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 925 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 926 | uint16_t length; |
| 927 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 928 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 929 | uint16_t flags; |
| 930 | uint32_t experimenter; |
| 931 | of_octets_t data; |
| 932 | }; |
| 933 | |
| 934 | // END OF STATS OBJECTS |
| 935 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 936 | struct of_queue_prop { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 937 | uint16_t type; |
| 938 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 939 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 940 | }; |
| 941 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 942 | struct of_queue_prop_min_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 943 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 944 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 945 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 946 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 947 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 948 | }; |
| 949 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 950 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 951 | uint32_t queue_id; |
| 952 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 953 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 954 | list(of_queue_prop_t) properties; |
| 955 | }; |
| 956 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 957 | struct of_queue_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 958 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 959 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 960 | uint16_t length; |
| 961 | uint32_t xid; |
| 962 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 963 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 964 | }; |
| 965 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 966 | struct of_queue_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 967 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 968 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 969 | uint16_t length; |
| 970 | uint32_t xid; |
| 971 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 972 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 973 | list(of_packet_queue_t) queues; |
| 974 | }; |