Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 3 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
Wilson Ng | d72013d | 2013-09-29 10:21:48 -0700 | [diff] [blame] | 38 | OFP_TCP_PORT = 6653, |
| 39 | OFP_SSL_PORT = 6653, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFP_VLAN_NONE = 0, |
| 46 | |
| 47 | OFP_FLOW_PERMANENT = 0, |
| 48 | |
| 49 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 50 | |
| 51 | OFP_NO_BUFFER = 0xffffffff, |
| 52 | |
| 53 | DESC_STR_LEN = 256, |
| 54 | SERIAL_NUM_LEN = 32, |
| 55 | |
| 56 | OFPQ_ALL = 0xffffffff, |
| 57 | |
| 58 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 59 | OFPQ_MAX_RATE_UNCFG = 0xffff, |
| 60 | }; |
| 61 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 62 | enum ofp_port(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 63 | OFPP_MAX = 0xffffff00, |
| 64 | OFPP_IN_PORT = 0xfffffff8, |
| 65 | OFPP_TABLE = 0xfffffff9, |
| 66 | OFPP_NORMAL = 0xfffffffa, |
| 67 | OFPP_FLOOD = 0xfffffffb, |
| 68 | OFPP_ALL = 0xfffffffc, |
| 69 | OFPP_CONTROLLER = 0xfffffffd, |
| 70 | OFPP_LOCAL = 0xfffffffe, |
| 71 | }; |
| 72 | |
Andreas Wundsam | 7933beb | 2013-08-02 22:36:42 -0700 | [diff] [blame] | 73 | enum ofp_port_no(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 74 | OFPP_ANY = 0xffffffff, |
| 75 | }; |
| 76 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 77 | enum ofp_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 78 | OFPT_HELLO = 0, |
| 79 | OFPT_ERROR = 1, |
| 80 | OFPT_ECHO_REQUEST = 2, |
| 81 | OFPT_ECHO_REPLY = 3, |
| 82 | OFPT_EXPERIMENTER = 4, |
| 83 | OFPT_FEATURES_REQUEST = 5, |
| 84 | OFPT_FEATURES_REPLY = 6, |
| 85 | OFPT_GET_CONFIG_REQUEST = 7, |
| 86 | OFPT_GET_CONFIG_REPLY = 8, |
| 87 | OFPT_SET_CONFIG = 9, |
| 88 | OFPT_PACKET_IN = 10, |
| 89 | OFPT_FLOW_REMOVED = 11, |
| 90 | OFPT_PORT_STATUS = 12, |
| 91 | OFPT_PACKET_OUT = 13, |
| 92 | OFPT_FLOW_MOD = 14, |
| 93 | OFPT_GROUP_MOD = 15, |
| 94 | OFPT_PORT_MOD = 16, |
| 95 | OFPT_TABLE_MOD = 17, |
| 96 | OFPT_STATS_REQUEST = 18, |
| 97 | OFPT_STATS_REPLY = 19, |
| 98 | OFPT_BARRIER_REQUEST = 20, |
| 99 | OFPT_BARRIER_REPLY = 21, |
| 100 | OFPT_QUEUE_GET_CONFIG_REQUEST = 22, |
| 101 | OFPT_QUEUE_GET_CONFIG_REPLY = 23, |
| 102 | OFPT_ROLE_REQUEST = 24, |
| 103 | OFPT_ROLE_REPLY = 25, |
| 104 | }; |
| 105 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 106 | enum ofp_config_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 107 | OFPC_FRAG_NORMAL = 0, |
| 108 | OFPC_FRAG_DROP = 1, |
| 109 | OFPC_FRAG_REASM = 2, |
| 110 | OFPC_FRAG_MASK = 3, |
| 111 | OFPC_INVALID_TTL_TO_CONTROLLER = 4, |
| 112 | }; |
| 113 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 114 | enum ofp_table_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 115 | OFPTC_TABLE_MISS_CONTROLLER = 0, |
| 116 | OFPTC_TABLE_MISS_CONTINUE = 1, |
| 117 | OFPTC_TABLE_MISS_DROP = 2, |
| 118 | OFPTC_TABLE_MISS_MASK = 3, |
| 119 | }; |
| 120 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 121 | enum ofp_table(wire_type=uint8_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 122 | OFPTT_MAX = 0xfe, |
| 123 | OFPTT_ALL = 0xff, |
| 124 | }; |
| 125 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 126 | enum ofp_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 127 | OFPC_FLOW_STATS = 0x1, |
| 128 | OFPC_TABLE_STATS = 0x2, |
| 129 | OFPC_PORT_STATS = 0x4, |
| 130 | OFPC_GROUP_STATS = 0x8, |
| 131 | OFPC_IP_REASM = 0x20, |
| 132 | OFPC_QUEUE_STATS = 0x40, |
| 133 | OFPC_PORT_BLOCKED = 0x100, |
| 134 | }; |
| 135 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 136 | enum ofp_port_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 137 | OFPPC_PORT_DOWN = 0x1, |
| 138 | OFPPC_NO_RECV = 0x4, |
| 139 | OFPPC_NO_FWD = 0x20, |
| 140 | OFPPC_NO_PACKET_IN = 0x40, |
Rob Vaterlaus | 0a8ec14 | 2013-10-10 13:27:14 -0700 | [diff] [blame] | 141 | OFPPC_BSN_MIRROR_DEST = 0x80000000, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 142 | }; |
| 143 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 144 | enum ofp_port_state(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 145 | OFPPS_LINK_DOWN = 0x1, |
| 146 | OFPPS_BLOCKED = 0x2, |
| 147 | OFPPS_LIVE = 0x4, |
| 148 | }; |
| 149 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 150 | enum ofp_port_features(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 151 | OFPPF_10MB_HD = 0x1, |
| 152 | OFPPF_10MB_FD = 0x2, |
| 153 | OFPPF_100MB_HD = 0x4, |
| 154 | OFPPF_100MB_FD = 0x8, |
| 155 | OFPPF_1GB_HD = 0x10, |
| 156 | OFPPF_1GB_FD = 0x20, |
| 157 | OFPPF_10GB_FD = 0x40, |
| 158 | OFPPF_40GB_FD = 0x80, |
| 159 | OFPPF_100GB_FD = 0x100, |
| 160 | OFPPF_1TB_FD = 0x200, |
| 161 | OFPPF_OTHER = 0x400, |
| 162 | OFPPF_COPPER = 0x800, |
| 163 | OFPPF_FIBER = 0x1000, |
| 164 | OFPPF_AUTONEG = 0x2000, |
| 165 | OFPPF_PAUSE = 0x4000, |
| 166 | OFPPF_PAUSE_ASYM = 0x8000, |
| 167 | }; |
| 168 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 169 | enum ofp_port_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 170 | OFPPR_ADD = 0, |
| 171 | OFPPR_DELETE = 1, |
| 172 | OFPPR_MODIFY = 2, |
| 173 | }; |
| 174 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 175 | enum ofp_match_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 176 | OFPMT_STANDARD = 0, |
| 177 | OFPMT_OXM = 1, |
| 178 | }; |
| 179 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 180 | enum ofp_oxm_class(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 181 | OFPXMC_NXM_0 = 0, |
| 182 | OFPXMC_NXM_1 = 1, |
| 183 | OFPXMC_OPENFLOW_BASIC = 0x8000, |
| 184 | OFPXMC_EXPERIMENTER = 0xffff, |
| 185 | }; |
| 186 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 187 | enum ofp_vlan_id(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 188 | OFPVID_NONE = 0, |
| 189 | OFPVID_PRESENT = 0x1000, |
| 190 | }; |
| 191 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 192 | enum ofp_action_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 193 | OFPAT_OUTPUT = 0, |
| 194 | OFPAT_COPY_TTL_OUT = 0xb, |
| 195 | OFPAT_COPY_TTL_IN = 0xc, |
| 196 | OFPAT_SET_MPLS_TTL = 0xf, |
| 197 | OFPAT_DEC_MPLS_TTL = 0x10, |
| 198 | OFPAT_PUSH_VLAN = 0x11, |
| 199 | OFPAT_POP_VLAN = 0x12, |
| 200 | OFPAT_PUSH_MPLS = 0x13, |
| 201 | OFPAT_POP_MPLS = 0x14, |
| 202 | OFPAT_SET_QUEUE = 0x15, |
| 203 | OFPAT_GROUP = 0x16, |
| 204 | OFPAT_SET_NW_TTL = 0x17, |
| 205 | OFPAT_DEC_NW_TTL = 0x18, |
| 206 | OFPAT_SET_FIELD = 0x19, |
| 207 | OFPAT_EXPERIMENTER = 0xffff, |
| 208 | }; |
| 209 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 210 | enum ofp_controller_max_len(wire_type=uint16_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 211 | OFPCML_MAX = 0xffe5, |
| 212 | OFPCML_NO_BUFFER = 0xffff, |
| 213 | }; |
| 214 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 215 | enum ofp_instruction_type(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 216 | OFPIT_GOTO_TABLE = 0x1, |
| 217 | OFPIT_WRITE_METADATA = 0x2, |
| 218 | OFPIT_WRITE_ACTIONS = 0x3, |
| 219 | OFPIT_APPLY_ACTIONS = 0x4, |
| 220 | OFPIT_CLEAR_ACTIONS = 0x5, |
| 221 | OFPIT_EXPERIMENTER = 0xffff, |
| 222 | }; |
| 223 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 224 | enum ofp_flow_mod_command(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 225 | OFPFC_ADD = 0, |
| 226 | OFPFC_MODIFY = 1, |
| 227 | OFPFC_MODIFY_STRICT = 2, |
| 228 | OFPFC_DELETE = 3, |
| 229 | OFPFC_DELETE_STRICT = 4, |
| 230 | }; |
| 231 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 232 | enum ofp_flow_mod_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 233 | OFPFF_SEND_FLOW_REM = 0x1, |
| 234 | OFPFF_CHECK_OVERLAP = 0x2, |
| 235 | OFPFF_RESET_COUNTS = 0x4, |
| 236 | }; |
| 237 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 238 | enum ofp_group(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 239 | OFPG_MAX = 0xffffff00, |
| 240 | OFPG_ALL = 0xfffffffc, |
| 241 | OFPG_ANY = 0xffffffff, |
| 242 | }; |
| 243 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 244 | enum ofp_group_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 245 | OFPGC_ADD = 0, |
| 246 | OFPGC_MODIFY = 1, |
| 247 | OFPGC_DELETE = 2, |
| 248 | }; |
| 249 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 250 | enum ofp_group_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 251 | OFPGT_ALL = 0, |
| 252 | OFPGT_SELECT = 1, |
| 253 | OFPGT_INDIRECT = 2, |
| 254 | OFPGT_FF = 3, |
| 255 | }; |
| 256 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 257 | enum ofp_packet_in_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 258 | OFPR_NO_MATCH = 0, |
| 259 | OFPR_ACTION = 1, |
| 260 | OFPR_INVALID_TTL = 2, |
| 261 | }; |
| 262 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 263 | enum ofp_flow_removed_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 264 | OFPRR_IDLE_TIMEOUT = 0, |
| 265 | OFPRR_HARD_TIMEOUT = 1, |
| 266 | OFPRR_DELETE = 2, |
| 267 | OFPRR_GROUP_DELETE = 3, |
| 268 | }; |
| 269 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 270 | enum ofp_error_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 271 | OFPET_HELLO_FAILED = 0, |
| 272 | OFPET_BAD_REQUEST = 1, |
| 273 | OFPET_BAD_ACTION = 2, |
| 274 | OFPET_BAD_INSTRUCTION = 3, |
| 275 | OFPET_BAD_MATCH = 4, |
| 276 | OFPET_FLOW_MOD_FAILED = 5, |
| 277 | OFPET_GROUP_MOD_FAILED = 6, |
| 278 | OFPET_PORT_MOD_FAILED = 7, |
| 279 | OFPET_TABLE_MOD_FAILED = 8, |
| 280 | OFPET_QUEUE_OP_FAILED = 9, |
| 281 | OFPET_SWITCH_CONFIG_FAILED = 10, |
| 282 | OFPET_ROLE_REQUEST_FAILED = 11, |
| 283 | OFPET_EXPERIMENTER = 0xffff, |
| 284 | }; |
| 285 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 286 | enum ofp_hello_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 287 | OFPHFC_INCOMPATIBLE = 0, |
| 288 | OFPHFC_EPERM = 1, |
| 289 | }; |
| 290 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 291 | enum ofp_bad_request_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 292 | OFPBRC_BAD_VERSION = 0, |
| 293 | OFPBRC_BAD_TYPE = 1, |
| 294 | OFPBRC_BAD_STAT = 2, |
| 295 | OFPBRC_BAD_EXPERIMENTER = 3, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 296 | OFPBRC_BAD_EXPERIMENTER_TYPE = 4, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 297 | OFPBRC_EPERM = 5, |
| 298 | OFPBRC_BAD_LEN = 6, |
| 299 | OFPBRC_BUFFER_EMPTY = 7, |
| 300 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 301 | OFPBRC_BAD_TABLE_ID = 9, |
| 302 | OFPBRC_IS_SLAVE = 10, |
| 303 | OFPBRC_BAD_PORT = 11, |
| 304 | OFPBRC_BAD_PACKET = 12, |
| 305 | }; |
| 306 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 307 | enum ofp_bad_action_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 308 | OFPBAC_BAD_TYPE = 0, |
| 309 | OFPBAC_BAD_LEN = 1, |
| 310 | OFPBAC_BAD_EXPERIMENTER = 2, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 311 | OFPBAC_BAD_EXPERIMENTER_TYPE = 3, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 312 | OFPBAC_BAD_OUT_PORT = 4, |
| 313 | OFPBAC_BAD_ARGUMENT = 5, |
| 314 | OFPBAC_EPERM = 6, |
| 315 | OFPBAC_TOO_MANY = 7, |
| 316 | OFPBAC_BAD_QUEUE = 8, |
| 317 | OFPBAC_BAD_OUT_GROUP = 9, |
| 318 | OFPBAC_MATCH_INCONSISTENT = 10, |
| 319 | OFPBAC_UNSUPPORTED_ORDER = 11, |
| 320 | OFPBAC_BAD_TAG = 12, |
| 321 | OFPBAC_BAD_SET_TYPE = 13, |
| 322 | OFPBAC_BAD_SET_LEN = 14, |
| 323 | OFPBAC_BAD_SET_ARGUMENT = 15, |
| 324 | }; |
| 325 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 326 | enum ofp_bad_instruction_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 327 | OFPBIC_UNKNOWN_INST = 0, |
| 328 | OFPBIC_UNSUP_INST = 1, |
| 329 | OFPBIC_BAD_TABLE_ID = 2, |
| 330 | OFPBIC_UNSUP_METADATA = 3, |
| 331 | OFPBIC_UNSUP_METADATA_MASK = 4, |
| 332 | OFPBIC_BAD_EXPERIMENTER = 5, |
Rob Vaterlaus | b3f49d9 | 2013-10-01 17:57:31 -0700 | [diff] [blame] | 333 | OFPBIC_BAD_EXPERIMENTER_TYPE = 6, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 334 | OFPBIC_BAD_LEN = 7, |
| 335 | OFPBIC_EPERM = 8, |
| 336 | }; |
| 337 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 338 | enum ofp_bad_match_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 339 | OFPBMC_BAD_TYPE = 0, |
| 340 | OFPBMC_BAD_LEN = 1, |
| 341 | OFPBMC_BAD_TAG = 2, |
| 342 | OFPBMC_BAD_DL_ADDR_MASK = 3, |
| 343 | OFPBMC_BAD_NW_ADDR_MASK = 4, |
| 344 | OFPBMC_BAD_WILDCARDS = 5, |
| 345 | OFPBMC_BAD_FIELD = 6, |
| 346 | OFPBMC_BAD_VALUE = 7, |
| 347 | OFPBMC_BAD_MASK = 8, |
| 348 | OFPBMC_BAD_PREREQ = 9, |
| 349 | OFPBMC_DUP_FIELD = 10, |
| 350 | OFPBMC_EPERM = 11, |
| 351 | }; |
| 352 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 353 | enum ofp_flow_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 354 | OFPFMFC_UNKNOWN = 0, |
| 355 | OFPFMFC_TABLE_FULL = 1, |
| 356 | OFPFMFC_BAD_TABLE_ID = 2, |
| 357 | OFPFMFC_OVERLAP = 3, |
| 358 | OFPFMFC_EPERM = 4, |
| 359 | OFPFMFC_BAD_TIMEOUT = 5, |
| 360 | OFPFMFC_BAD_COMMAND = 6, |
| 361 | OFPFMFC_BAD_FLAGS = 7, |
| 362 | }; |
| 363 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 364 | enum ofp_group_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 365 | OFPGMFC_GROUP_EXISTS = 0, |
| 366 | OFPGMFC_INVALID_GROUP = 1, |
| 367 | OFPGMFC_WEIGHT_UNSUPPORTED = 2, |
| 368 | OFPGMFC_OUT_OF_GROUPS = 3, |
| 369 | OFPGMFC_OUT_OF_BUCKETS = 4, |
| 370 | OFPGMFC_CHAINING_UNSUPPORTED = 5, |
| 371 | OFPGMFC_WATCH_UNSUPPORTED = 6, |
| 372 | OFPGMFC_LOOP = 7, |
| 373 | OFPGMFC_UNKNOWN_GROUP = 8, |
| 374 | OFPGMFC_CHAINED_GROUP = 9, |
| 375 | OFPGMFC_BAD_TYPE = 10, |
| 376 | OFPGMFC_BAD_COMMAND = 11, |
| 377 | OFPGMFC_BAD_BUCKET = 12, |
| 378 | OFPGMFC_BAD_WATCH = 13, |
| 379 | OFPGMFC_EPERM = 14, |
| 380 | }; |
| 381 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 382 | enum ofp_port_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 383 | OFPPMFC_BAD_PORT = 0, |
| 384 | OFPPMFC_BAD_HW_ADDR = 1, |
| 385 | OFPPMFC_BAD_CONFIG = 2, |
| 386 | OFPPMFC_BAD_ADVERTISE = 3, |
| 387 | OFPPMFC_EPERM = 4, |
| 388 | }; |
| 389 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 390 | enum ofp_table_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 391 | OFPTMFC_BAD_TABLE = 0, |
| 392 | OFPTMFC_BAD_CONFIG = 1, |
| 393 | OFPTMFC_EPERM = 2, |
| 394 | }; |
| 395 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 396 | enum ofp_queue_op_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 397 | OFPQOFC_BAD_PORT = 0, |
| 398 | OFPQOFC_BAD_QUEUE = 1, |
| 399 | OFPQOFC_EPERM = 2, |
| 400 | }; |
| 401 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 402 | enum ofp_switch_config_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 403 | OFPSCFC_BAD_FLAGS = 0, |
| 404 | OFPSCFC_BAD_LEN = 1, |
| 405 | OFPSCFC_EPERM = 2, |
| 406 | }; |
| 407 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 408 | enum ofp_role_request_failed_code (wire_type=uint16_t){ |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 409 | OFPRRFC_STALE = 0, |
| 410 | OFPRRFC_UNSUP = 1, |
| 411 | OFPRRFC_BAD_ROLE = 2, |
| 412 | }; |
| 413 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 414 | enum ofp_stats_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 415 | OFPST_DESC = 0, |
| 416 | OFPST_FLOW = 1, |
| 417 | OFPST_AGGREGATE = 2, |
| 418 | OFPST_TABLE = 3, |
| 419 | OFPST_PORT = 4, |
| 420 | OFPST_QUEUE = 5, |
| 421 | OFPST_GROUP = 6, |
| 422 | OFPST_GROUP_DESC = 7, |
| 423 | OFPST_GROUP_FEATURES = 8, |
| 424 | OFPST_EXPERIMENTER = 0xffff, |
| 425 | }; |
| 426 | |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 427 | enum ofp_stats_request_flags(wire_type=uint16_t, bitmask=True) { |
| 428 | }; |
| 429 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 430 | enum ofp_stats_reply_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 431 | OFPSF_REPLY_MORE = 0x1, |
| 432 | }; |
| 433 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 434 | enum ofp_group_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 435 | OFPGFC_SELECT_WEIGHT = 0x1, |
| 436 | OFPGFC_SELECT_LIVENESS = 0x2, |
| 437 | OFPGFC_CHAINING = 0x4, |
| 438 | OFPGFC_CHAINING_CHECKS = 0x8, |
| 439 | }; |
| 440 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 441 | enum ofp_queue_properties(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 442 | OFPQT_MIN_RATE = 0x1, |
| 443 | OFPQT_MAX_RATE = 0x2, |
| 444 | OFPQT_EXPERIMENTER = 0xffff, |
| 445 | }; |
| 446 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 447 | enum ofp_controller_role(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 448 | OFPCR_ROLE_NOCHANGE = 0, |
| 449 | OFPCR_ROLE_EQUAL = 1, |
| 450 | OFPCR_ROLE_MASTER = 2, |
| 451 | OFPCR_ROLE_SLAVE = 3, |
| 452 | }; |
| 453 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 454 | /* XXX rename to of_message */ |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 455 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 456 | uint8_t version; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 457 | uint8_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 458 | uint16_t length; |
| 459 | uint32_t xid; |
| 460 | }; |
| 461 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 462 | struct of_hello : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 463 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 464 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 465 | uint16_t length; |
| 466 | uint32_t xid; |
| 467 | }; |
| 468 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 469 | struct of_echo_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 470 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 471 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 472 | uint16_t length; |
| 473 | uint32_t xid; |
| 474 | of_octets_t data; |
| 475 | }; |
| 476 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 477 | struct of_echo_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 478 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 479 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 480 | uint16_t length; |
| 481 | uint32_t xid; |
| 482 | of_octets_t data; |
| 483 | }; |
| 484 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 485 | struct of_experimenter : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 486 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 487 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 488 | uint16_t length; |
| 489 | uint32_t xid; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 490 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 491 | uint32_t subtype; |
| 492 | of_octets_t data; |
| 493 | }; |
| 494 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 495 | struct of_barrier_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 496 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 497 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 498 | uint16_t length; |
| 499 | uint32_t xid; |
| 500 | }; |
| 501 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 502 | struct of_barrier_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 503 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 504 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 505 | uint16_t length; |
| 506 | uint32_t xid; |
| 507 | }; |
| 508 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 509 | struct of_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 510 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 511 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 512 | uint16_t length; |
| 513 | uint32_t xid; |
| 514 | }; |
| 515 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 516 | struct of_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 517 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 518 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 519 | uint16_t length; |
| 520 | uint32_t xid; |
| 521 | uint16_t flags; |
| 522 | uint16_t miss_send_len; |
| 523 | }; |
| 524 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 525 | struct of_set_config : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 526 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 527 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 528 | uint16_t length; |
| 529 | uint32_t xid; |
| 530 | uint16_t flags; |
| 531 | uint16_t miss_send_len; |
| 532 | }; |
| 533 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 534 | struct of_table_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 535 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 536 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 537 | uint16_t length; |
| 538 | uint32_t xid; |
| 539 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 540 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 541 | uint32_t config; |
| 542 | }; |
| 543 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 544 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 545 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 546 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 547 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 548 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 549 | of_port_name_t name; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 550 | enum ofp_port_config config; |
| 551 | enum ofp_port_state state; |
| 552 | enum ofp_port_features curr; |
| 553 | enum ofp_port_features advertised; |
| 554 | enum ofp_port_features supported; |
| 555 | enum ofp_port_features peer; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 556 | uint32_t curr_speed; |
| 557 | uint32_t max_speed; |
| 558 | }; |
| 559 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 560 | struct of_features_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 561 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 562 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 563 | uint16_t length; |
| 564 | uint32_t xid; |
| 565 | }; |
| 566 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 567 | struct of_features_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 568 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 569 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 570 | uint16_t length; |
| 571 | uint32_t xid; |
| 572 | uint64_t datapath_id; |
| 573 | uint32_t n_buffers; |
| 574 | uint8_t n_tables; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 575 | pad(3); |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 576 | enum ofp_capabilities capabilities; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 577 | uint32_t reserved; |
| 578 | list(of_port_desc_t) ports; |
| 579 | }; |
| 580 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 581 | struct of_port_status : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 582 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 583 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 584 | uint16_t length; |
| 585 | uint32_t xid; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 586 | enum ofp_port_reason reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 587 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 588 | of_port_desc_t desc; |
| 589 | }; |
| 590 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 591 | struct of_port_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 592 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 593 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 594 | uint16_t length; |
| 595 | uint32_t xid; |
| 596 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 597 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 598 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 599 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 600 | uint32_t config; |
| 601 | uint32_t mask; |
| 602 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 603 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 604 | }; |
| 605 | |
Andreas Wundsam | 5da6851 | 2013-10-22 22:18:00 -0700 | [diff] [blame] | 606 | struct of_match_v3(align=8, length_includes_align=False) { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 607 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 608 | uint16_t length; |
| 609 | list(of_oxm_t) oxm_list; |
| 610 | }; |
| 611 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 612 | struct of_action_output : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 613 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 614 | uint16_t len; |
| 615 | of_port_no_t port; |
| 616 | uint16_t max_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 617 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 618 | }; |
| 619 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 620 | struct of_action_copy_ttl_out : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 621 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 622 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 623 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 624 | }; |
| 625 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 626 | struct of_action_copy_ttl_in : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 627 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 628 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 629 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 630 | }; |
| 631 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 632 | struct of_action_set_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 633 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 634 | uint16_t len; |
| 635 | uint8_t mpls_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 636 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 637 | }; |
| 638 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 639 | struct of_action_dec_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 640 | uint16_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 641 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 642 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 643 | }; |
| 644 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 645 | struct of_action_push_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 646 | uint16_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 647 | uint16_t len; |
| 648 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 649 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 650 | }; |
| 651 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 652 | struct of_action_pop_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 653 | uint16_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 654 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 655 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 656 | }; |
| 657 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 658 | struct of_action_push_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 659 | uint16_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 660 | uint16_t len; |
| 661 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 662 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 663 | }; |
| 664 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 665 | struct of_action_pop_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 666 | uint16_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 667 | uint16_t len; |
| 668 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 669 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 670 | }; |
| 671 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 672 | struct of_action_set_queue : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 673 | uint16_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 674 | uint16_t len; |
| 675 | uint32_t queue_id; |
| 676 | }; |
| 677 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 678 | struct of_action_group : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 679 | uint16_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 680 | uint16_t len; |
| 681 | uint32_t group_id; |
| 682 | }; |
| 683 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 684 | struct of_action_set_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 685 | uint16_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 686 | uint16_t len; |
| 687 | uint8_t nw_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 688 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 689 | }; |
| 690 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 691 | struct of_action_dec_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 692 | uint16_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 693 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 694 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 695 | }; |
| 696 | |
Andreas Wundsam | 5da6851 | 2013-10-22 22:18:00 -0700 | [diff] [blame] | 697 | struct of_action_set_field(align=8, length_includes_align=True) : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 698 | uint16_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 699 | uint16_t len; |
Rich Lane | be90eae | 2013-07-22 16:44:26 -0700 | [diff] [blame] | 700 | of_oxm_t field; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 701 | }; |
| 702 | |
Andreas Wundsam | 5da6851 | 2013-10-22 22:18:00 -0700 | [diff] [blame] | 703 | struct of_action_experimenter(align=8, length_includes_align=True) : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 704 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 705 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 706 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 707 | of_octets_t data; |
| 708 | }; |
| 709 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 710 | struct of_action { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 711 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 712 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 713 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 714 | }; |
| 715 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 716 | struct of_instruction { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 717 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 718 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 719 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 720 | }; |
| 721 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 722 | struct of_instruction_goto_table : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 723 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 724 | uint16_t len; |
| 725 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 726 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 727 | }; |
| 728 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 729 | struct of_instruction_write_metadata : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 730 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 731 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 732 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 733 | uint64_t metadata; |
| 734 | uint64_t metadata_mask; |
| 735 | }; |
| 736 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 737 | struct of_instruction_write_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 738 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 739 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 740 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 741 | list(of_action_t) actions; |
| 742 | }; |
| 743 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 744 | struct of_instruction_apply_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 745 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 746 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 747 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 748 | list(of_action_t) actions; |
| 749 | }; |
| 750 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 751 | struct of_instruction_clear_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 752 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 753 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 754 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 755 | }; |
| 756 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 757 | struct of_instruction_experimenter : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 758 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 759 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 760 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 761 | of_octets_t data; |
| 762 | }; |
| 763 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 764 | struct of_flow_mod : of_header { |
| 765 | uint8_t version; |
| 766 | uint8_t type == 14; |
| 767 | uint16_t length; |
| 768 | uint32_t xid; |
| 769 | uint64_t cookie; |
| 770 | uint64_t cookie_mask; |
| 771 | uint8_t table_id; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 772 | of_fm_cmd_t _command == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 773 | uint16_t idle_timeout; |
| 774 | uint16_t hard_timeout; |
| 775 | uint16_t priority; |
| 776 | uint32_t buffer_id; |
| 777 | of_port_no_t out_port; |
| 778 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 779 | enum ofp_flow_mod_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 780 | pad(2); |
| 781 | of_match_t match; |
| 782 | list(of_instruction_t) instructions; |
| 783 | }; |
| 784 | |
| 785 | struct of_flow_add : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 786 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 787 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 788 | uint16_t length; |
| 789 | uint32_t xid; |
| 790 | uint64_t cookie; |
| 791 | uint64_t cookie_mask; |
| 792 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 793 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 794 | uint16_t idle_timeout; |
| 795 | uint16_t hard_timeout; |
| 796 | uint16_t priority; |
| 797 | uint32_t buffer_id; |
| 798 | of_port_no_t out_port; |
| 799 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 800 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 801 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 802 | of_match_t match; |
| 803 | list(of_instruction_t) instructions; |
| 804 | }; |
| 805 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 806 | struct of_flow_modify : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 807 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 808 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 809 | uint16_t length; |
| 810 | uint32_t xid; |
| 811 | uint64_t cookie; |
| 812 | uint64_t cookie_mask; |
| 813 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 814 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 815 | uint16_t idle_timeout; |
| 816 | uint16_t hard_timeout; |
| 817 | uint16_t priority; |
| 818 | uint32_t buffer_id; |
| 819 | of_port_no_t out_port; |
| 820 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 821 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 822 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 823 | of_match_t match; |
| 824 | list(of_instruction_t) instructions; |
| 825 | }; |
| 826 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 827 | struct of_flow_modify_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 828 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 829 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 830 | uint16_t length; |
| 831 | uint32_t xid; |
| 832 | uint64_t cookie; |
| 833 | uint64_t cookie_mask; |
| 834 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 835 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 836 | uint16_t idle_timeout; |
| 837 | uint16_t hard_timeout; |
| 838 | uint16_t priority; |
| 839 | uint32_t buffer_id; |
| 840 | of_port_no_t out_port; |
| 841 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 842 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 843 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 844 | of_match_t match; |
| 845 | list(of_instruction_t) instructions; |
| 846 | }; |
| 847 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 848 | struct of_flow_delete : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 849 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 850 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 851 | uint16_t length; |
| 852 | uint32_t xid; |
| 853 | uint64_t cookie; |
| 854 | uint64_t cookie_mask; |
| 855 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 856 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 857 | uint16_t idle_timeout; |
| 858 | uint16_t hard_timeout; |
| 859 | uint16_t priority; |
| 860 | uint32_t buffer_id; |
| 861 | of_port_no_t out_port; |
| 862 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 863 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 864 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 865 | of_match_t match; |
| 866 | list(of_instruction_t) instructions; |
| 867 | }; |
| 868 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 869 | struct of_flow_delete_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 870 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 871 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 872 | uint16_t length; |
| 873 | uint32_t xid; |
| 874 | uint64_t cookie; |
| 875 | uint64_t cookie_mask; |
| 876 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 877 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 878 | uint16_t idle_timeout; |
| 879 | uint16_t hard_timeout; |
| 880 | uint16_t priority; |
| 881 | uint32_t buffer_id; |
| 882 | of_port_no_t out_port; |
| 883 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 884 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 885 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 886 | of_match_t match; |
| 887 | list(of_instruction_t) instructions; |
| 888 | }; |
| 889 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 890 | struct of_bucket { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 891 | uint16_t len; |
| 892 | uint16_t weight; |
| 893 | of_port_no_t watch_port; |
| 894 | uint32_t watch_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 895 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 896 | list(of_action_t) actions; |
| 897 | }; |
| 898 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 899 | struct of_group_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 900 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 901 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 902 | uint16_t length; |
| 903 | uint32_t xid; |
| 904 | uint16_t command; |
| 905 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 906 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 907 | uint32_t group_id; |
| 908 | list(of_bucket_t) buckets; |
| 909 | }; |
| 910 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 911 | struct of_packet_out : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 912 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 913 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 914 | uint16_t length; |
| 915 | uint32_t xid; |
| 916 | uint32_t buffer_id; |
| 917 | of_port_no_t in_port; |
| 918 | uint16_t actions_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 919 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 920 | list(of_action_t) actions; |
| 921 | of_octets_t data; |
| 922 | }; |
| 923 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 924 | struct of_packet_in : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 925 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 926 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 927 | uint16_t length; |
| 928 | uint32_t xid; |
| 929 | uint32_t buffer_id; |
| 930 | uint16_t total_len; |
| 931 | uint8_t reason; |
| 932 | uint8_t table_id; |
| 933 | of_match_t match; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 934 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 935 | of_octets_t data; /* FIXME: Ensure total_len gets updated */ |
| 936 | }; |
| 937 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 938 | struct of_flow_removed : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 939 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 940 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 941 | uint16_t length; |
| 942 | uint32_t xid; |
| 943 | uint64_t cookie; |
| 944 | uint16_t priority; |
| 945 | uint8_t reason; |
| 946 | uint8_t table_id; |
| 947 | uint32_t duration_sec; |
| 948 | uint32_t duration_nsec; |
| 949 | uint16_t idle_timeout; |
| 950 | uint16_t hard_timeout; |
| 951 | uint64_t packet_count; |
| 952 | uint64_t byte_count; |
| 953 | of_match_t match; |
| 954 | }; |
| 955 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 956 | struct of_error_msg : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 957 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 958 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 959 | uint16_t length; |
| 960 | uint32_t xid; |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 961 | uint16_t err_type == ?; |
| 962 | }; |
| 963 | |
| 964 | struct of_hello_failed_error_msg : of_error_msg { |
| 965 | uint8_t version; |
| 966 | uint8_t type == 1; |
| 967 | uint16_t length; |
| 968 | uint32_t xid; |
| 969 | uint16_t err_type == 0; |
| 970 | enum ofp_hello_failed_code code; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 971 | of_octets_t data; |
| 972 | }; |
| 973 | |
Rob Vaterlaus | feee371 | 2013-09-30 11:24:19 -0700 | [diff] [blame] | 974 | struct of_bad_request_error_msg : of_error_msg { |
| 975 | uint8_t version; |
| 976 | uint8_t type == 1; |
| 977 | uint16_t length; |
| 978 | uint32_t xid; |
| 979 | uint16_t err_type == 1; |
| 980 | enum ofp_bad_request_code code; |
| 981 | of_octets_t data; |
| 982 | }; |
| 983 | |
| 984 | struct of_bad_action_error_msg : of_error_msg { |
| 985 | uint8_t version; |
| 986 | uint8_t type == 1; |
| 987 | uint16_t length; |
| 988 | uint32_t xid; |
| 989 | uint16_t err_type == 2; |
| 990 | enum ofp_bad_action_code code; |
| 991 | of_octets_t data; |
| 992 | }; |
| 993 | |
| 994 | struct of_bad_instruction_error_msg : of_error_msg { |
| 995 | uint8_t version; |
| 996 | uint8_t type == 1; |
| 997 | uint16_t length; |
| 998 | uint32_t xid; |
| 999 | uint16_t err_type == 3; |
| 1000 | enum ofp_bad_instruction_code code; |
| 1001 | of_octets_t data; |
| 1002 | }; |
| 1003 | |
| 1004 | struct of_bad_match_error_msg : of_error_msg { |
| 1005 | uint8_t version; |
| 1006 | uint8_t type == 1; |
| 1007 | uint16_t length; |
| 1008 | uint32_t xid; |
| 1009 | uint16_t err_type == 4; |
| 1010 | enum ofp_bad_match_code code; |
| 1011 | of_octets_t data; |
| 1012 | }; |
| 1013 | |
| 1014 | struct of_flow_mod_failed_error_msg : of_error_msg { |
| 1015 | uint8_t version; |
| 1016 | uint8_t type == 1; |
| 1017 | uint16_t length; |
| 1018 | uint32_t xid; |
| 1019 | uint16_t err_type == 5; |
| 1020 | enum ofp_flow_mod_failed_code code; |
| 1021 | of_octets_t data; |
| 1022 | }; |
| 1023 | |
| 1024 | struct of_group_mod_failed_error_msg : of_error_msg { |
| 1025 | uint8_t version; |
| 1026 | uint8_t type == 1; |
| 1027 | uint16_t length; |
| 1028 | uint32_t xid; |
| 1029 | uint16_t err_type == 6; |
| 1030 | enum ofp_group_mod_failed_code code; |
| 1031 | of_octets_t data; |
| 1032 | }; |
| 1033 | |
| 1034 | struct of_port_mod_failed_error_msg : of_error_msg { |
| 1035 | uint8_t version; |
| 1036 | uint8_t type == 1; |
| 1037 | uint16_t length; |
| 1038 | uint32_t xid; |
| 1039 | uint16_t err_type == 7; |
| 1040 | enum ofp_port_mod_failed_code code; |
| 1041 | of_octets_t data; |
| 1042 | }; |
| 1043 | |
| 1044 | struct of_table_mod_failed_error_msg : of_error_msg { |
| 1045 | uint8_t version; |
| 1046 | uint8_t type == 1; |
| 1047 | uint16_t length; |
| 1048 | uint32_t xid; |
| 1049 | uint16_t err_type == 8; |
| 1050 | enum ofp_table_mod_failed_code code; |
| 1051 | of_octets_t data; |
| 1052 | }; |
| 1053 | |
| 1054 | struct of_queue_op_failed_error_msg : of_error_msg { |
| 1055 | uint8_t version; |
| 1056 | uint8_t type == 1; |
| 1057 | uint16_t length; |
| 1058 | uint32_t xid; |
| 1059 | uint16_t err_type == 9; |
| 1060 | enum ofp_queue_op_failed_code code; |
| 1061 | of_octets_t data; |
| 1062 | }; |
| 1063 | |
| 1064 | struct of_switch_config_failed_error_msg : of_error_msg { |
| 1065 | uint8_t version; |
| 1066 | uint8_t type == 1; |
| 1067 | uint16_t length; |
| 1068 | uint32_t xid; |
| 1069 | uint16_t err_type == 10; |
| 1070 | enum ofp_switch_config_failed_code code; |
| 1071 | of_octets_t data; |
| 1072 | }; |
| 1073 | |
| 1074 | struct of_role_request_failed_error_msg : of_error_msg { |
| 1075 | uint8_t version; |
| 1076 | uint8_t type == 1; |
| 1077 | uint16_t length; |
| 1078 | uint32_t xid; |
| 1079 | uint16_t err_type == 11; |
| 1080 | enum ofp_role_request_failed_code code; |
| 1081 | of_octets_t data; |
| 1082 | }; |
| 1083 | |
| 1084 | struct of_experimenter_error_msg { |
| 1085 | uint8_t version; |
| 1086 | uint8_t type == 1; |
| 1087 | uint16_t length; |
| 1088 | uint32_t xid; |
| 1089 | uint16_t err_type == 0xffff; |
| 1090 | uint16_t subtype; |
| 1091 | uint32_t experimenter; |
| 1092 | of_octets_t data; |
| 1093 | }; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1094 | |
| 1095 | // STATS ENTRIES: flow, table, port, queue, group stats, group desc stats |
| 1096 | // FIXME: Verify disambiguation w/ length in object and entry |
| 1097 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1098 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1099 | uint16_t length; |
| 1100 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1101 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1102 | uint32_t duration_sec; |
| 1103 | uint32_t duration_nsec; |
| 1104 | uint16_t priority; |
| 1105 | uint16_t idle_timeout; |
| 1106 | uint16_t hard_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1107 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1108 | uint64_t cookie; |
| 1109 | uint64_t packet_count; |
| 1110 | uint64_t byte_count; |
| 1111 | of_match_t match; |
| 1112 | list(of_instruction_t) instructions; |
| 1113 | }; |
| 1114 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1115 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1116 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1117 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1118 | of_table_name_t name; |
| 1119 | of_match_bmap_t match; |
| 1120 | of_wc_bmap_t wildcards; |
| 1121 | uint32_t write_actions; |
| 1122 | uint32_t apply_actions; |
| 1123 | uint64_t write_setfields; |
| 1124 | uint64_t apply_setfields; |
| 1125 | uint64_t metadata_match; |
| 1126 | uint64_t metadata_write; |
| 1127 | uint32_t instructions; |
| 1128 | uint32_t config; |
| 1129 | uint32_t max_entries; |
| 1130 | uint32_t active_count; |
| 1131 | uint64_t lookup_count; |
| 1132 | uint64_t matched_count; |
| 1133 | }; |
| 1134 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1135 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1136 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1137 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1138 | uint64_t rx_packets; |
| 1139 | uint64_t tx_packets; |
| 1140 | uint64_t rx_bytes; |
| 1141 | uint64_t tx_bytes; |
| 1142 | uint64_t rx_dropped; |
| 1143 | uint64_t tx_dropped; |
| 1144 | uint64_t rx_errors; |
| 1145 | uint64_t tx_errors; |
| 1146 | uint64_t rx_frame_err; |
| 1147 | uint64_t rx_over_err; |
| 1148 | uint64_t rx_crc_err; |
| 1149 | uint64_t collisions; |
| 1150 | }; |
| 1151 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1152 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1153 | of_port_no_t port_no; |
| 1154 | uint32_t queue_id; |
| 1155 | uint64_t tx_bytes; |
| 1156 | uint64_t tx_packets; |
| 1157 | uint64_t tx_errors; |
| 1158 | }; |
| 1159 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1160 | struct of_bucket_counter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1161 | uint64_t packet_count; |
| 1162 | uint64_t byte_count; |
| 1163 | }; |
| 1164 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1165 | struct of_group_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1166 | uint16_t length; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1167 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1168 | uint32_t group_id; |
| 1169 | uint32_t ref_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1170 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1171 | uint64_t packet_count; |
| 1172 | uint64_t byte_count; |
| 1173 | list(of_bucket_counter_t) bucket_stats; |
| 1174 | }; |
| 1175 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1176 | struct of_group_desc_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1177 | uint16_t length; |
Rich Lane | 35e7ac7 | 2013-10-15 10:36:10 -0700 | [diff] [blame] | 1178 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1179 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1180 | uint32_t group_id; |
| 1181 | list(of_bucket_t) buckets; |
| 1182 | }; |
| 1183 | |
| 1184 | // STATS: |
| 1185 | // Desc, flow, agg, table, port, queue, group, group_desc, group_feat, experi |
| 1186 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1187 | struct of_stats_request : of_header { |
| 1188 | uint8_t version; |
| 1189 | uint8_t type == 18; |
| 1190 | uint16_t length; |
| 1191 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1192 | uint16_t stats_type == ?; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1193 | enum ofp_stats_request_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1194 | pad(4); |
| 1195 | }; |
| 1196 | |
| 1197 | struct of_stats_reply : of_header { |
| 1198 | uint8_t version; |
| 1199 | uint8_t type == 19; |
| 1200 | uint16_t length; |
| 1201 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1202 | uint16_t stats_type == ?; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1203 | enum ofp_stats_reply_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1204 | pad(4); |
| 1205 | }; |
| 1206 | |
| 1207 | struct of_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1208 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1209 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1210 | uint16_t length; |
| 1211 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1212 | uint16_t stats_type == 0; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1213 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1214 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1215 | }; |
| 1216 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1217 | struct of_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1218 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1219 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1220 | uint16_t length; |
| 1221 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1222 | uint16_t stats_type == 0; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1223 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1224 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1225 | of_desc_str_t mfr_desc; |
| 1226 | of_desc_str_t hw_desc; |
| 1227 | of_desc_str_t sw_desc; |
| 1228 | of_serial_num_t serial_num; |
| 1229 | of_desc_str_t dp_desc; |
| 1230 | }; |
| 1231 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1232 | struct of_flow_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1233 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1234 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1235 | uint16_t length; |
| 1236 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1237 | uint16_t stats_type == 1; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1238 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1239 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1240 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1241 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1242 | of_port_no_t out_port; |
| 1243 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1244 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1245 | uint64_t cookie; |
| 1246 | uint64_t cookie_mask; |
| 1247 | of_match_t match; |
| 1248 | }; |
| 1249 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1250 | struct of_flow_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1251 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1252 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1253 | uint16_t length; |
| 1254 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1255 | uint16_t stats_type == 1; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1256 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1257 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1258 | list(of_flow_stats_entry_t) entries; |
| 1259 | }; |
| 1260 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1261 | struct of_aggregate_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1262 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1263 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1264 | uint16_t length; |
| 1265 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1266 | uint16_t stats_type == 2; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1267 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1268 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1269 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1270 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1271 | of_port_no_t out_port; |
| 1272 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1273 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1274 | uint64_t cookie; |
| 1275 | uint64_t cookie_mask; |
| 1276 | of_match_t match; |
| 1277 | }; |
| 1278 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1279 | struct of_aggregate_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1280 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1281 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1282 | uint16_t length; |
| 1283 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1284 | uint16_t stats_type == 2; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1285 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1286 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1287 | uint64_t packet_count; |
| 1288 | uint64_t byte_count; |
| 1289 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1290 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1291 | }; |
| 1292 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1293 | struct of_table_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1294 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1295 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1296 | uint16_t length; |
| 1297 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1298 | uint16_t stats_type == 3; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1299 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1300 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1301 | }; |
| 1302 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1303 | struct of_table_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1304 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1305 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1306 | uint16_t length; |
| 1307 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1308 | uint16_t stats_type == 3; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1309 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1310 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1311 | list(of_table_stats_entry_t) entries; |
| 1312 | }; |
| 1313 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1314 | struct of_port_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1315 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1316 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1317 | uint16_t length; |
| 1318 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1319 | uint16_t stats_type == 4; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1320 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1321 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1322 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1323 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1324 | }; |
| 1325 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1326 | struct of_port_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1327 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1328 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1329 | uint16_t length; |
| 1330 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1331 | uint16_t stats_type == 4; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1332 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1333 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1334 | list(of_port_stats_entry_t) entries; |
| 1335 | }; |
| 1336 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1337 | struct of_queue_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1338 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1339 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1340 | uint16_t length; |
| 1341 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1342 | uint16_t stats_type == 5; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1343 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1344 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1345 | of_port_no_t port_no; |
| 1346 | uint32_t queue_id; |
| 1347 | }; |
| 1348 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1349 | struct of_queue_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1350 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1351 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1352 | uint16_t length; |
| 1353 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1354 | uint16_t stats_type == 5; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1355 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1356 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1357 | list(of_queue_stats_entry_t) entries; |
| 1358 | }; |
| 1359 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1360 | struct of_group_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1361 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1362 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1363 | uint16_t length; |
| 1364 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1365 | uint16_t stats_type == 6; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1366 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1367 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1368 | uint32_t group_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1369 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1370 | }; |
| 1371 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1372 | struct of_group_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1373 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1374 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1375 | uint16_t length; |
| 1376 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1377 | uint16_t stats_type == 6; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1378 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1379 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1380 | list(of_group_stats_entry_t) entries; |
| 1381 | }; |
| 1382 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1383 | struct of_group_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1384 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1385 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1386 | uint16_t length; |
| 1387 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1388 | uint16_t stats_type == 7; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1389 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1390 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1391 | }; |
| 1392 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1393 | struct of_group_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1394 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1395 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1396 | uint16_t length; |
| 1397 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1398 | uint16_t stats_type == 7; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1399 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1400 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1401 | list(of_group_desc_stats_entry_t) entries; |
| 1402 | }; |
| 1403 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1404 | struct of_group_features_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1405 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1406 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1407 | uint16_t length; |
| 1408 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1409 | uint16_t stats_type == 8; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1410 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1411 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1412 | }; |
| 1413 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1414 | struct of_group_features_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1415 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1416 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1417 | uint16_t length; |
| 1418 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1419 | uint16_t stats_type == 8; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1420 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1421 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1422 | uint32_t types; |
| 1423 | uint32_t capabilities; |
| 1424 | uint32_t max_groups_all; |
| 1425 | uint32_t max_groups_select; |
| 1426 | uint32_t max_groups_indirect; |
| 1427 | uint32_t max_groups_ff; |
| 1428 | uint32_t actions_all; |
| 1429 | uint32_t actions_select; |
| 1430 | uint32_t actions_indirect; |
| 1431 | uint32_t actions_ff; |
| 1432 | }; |
| 1433 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1434 | struct of_experimenter_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1435 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1436 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1437 | uint16_t length; |
| 1438 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1439 | uint16_t stats_type == 0xffff; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1440 | enum ofp_stats_request_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1441 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1442 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1443 | uint32_t subtype; |
| 1444 | of_octets_t data; |
| 1445 | }; |
| 1446 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1447 | struct of_experimenter_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1448 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1449 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1450 | uint16_t length; |
| 1451 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1452 | uint16_t stats_type == 0xffff; |
Andreas Wundsam | b47d7e8 | 2013-10-18 17:43:00 -0700 | [diff] [blame] | 1453 | enum ofp_stats_reply_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1454 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1455 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1456 | uint32_t subtype; |
| 1457 | of_octets_t data; |
| 1458 | }; |
| 1459 | |
| 1460 | // END OF STATS OBJECTS |
| 1461 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1462 | struct of_queue_prop { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1463 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1464 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1465 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1466 | }; |
| 1467 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1468 | struct of_queue_prop_min_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1469 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1470 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1471 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1472 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1473 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1474 | }; |
| 1475 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1476 | struct of_queue_prop_max_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1477 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1478 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1479 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1480 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1481 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1482 | }; |
| 1483 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1484 | struct of_queue_prop_experimenter : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1485 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1486 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1487 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1488 | uint32_t experimenter == ?; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1489 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1490 | of_octets_t data; |
| 1491 | }; |
| 1492 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1493 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1494 | uint32_t queue_id; |
| 1495 | of_port_no_t port; |
| 1496 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1497 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1498 | list(of_queue_prop_t) properties; |
| 1499 | }; |
| 1500 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1501 | struct of_queue_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1502 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1503 | uint8_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1504 | uint16_t length; |
| 1505 | uint32_t xid; |
| 1506 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1507 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1508 | }; |
| 1509 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1510 | struct of_queue_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1511 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1512 | uint8_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1513 | uint16_t length; |
| 1514 | uint32_t xid; |
| 1515 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1516 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1517 | list(of_packet_queue_t) queues; |
| 1518 | }; |
| 1519 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1520 | struct of_role_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1521 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1522 | uint8_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1523 | uint16_t length; |
| 1524 | uint32_t xid; |
Andreas Wundsam | 4f796b7 | 2013-10-18 17:33:23 -0700 | [diff] [blame] | 1525 | enum ofp_controller_role role; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1526 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1527 | uint64_t generation_id; |
| 1528 | }; |
| 1529 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1530 | struct of_role_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1531 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1532 | uint8_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1533 | uint16_t length; |
| 1534 | uint32_t xid; |
Andreas Wundsam | 4f796b7 | 2013-10-18 17:33:23 -0700 | [diff] [blame] | 1535 | enum ofp_controller_role role; |
| 1536 | pad(4); |
| 1537 | uint64_t generation_id; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1538 | }; |