Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
| 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
| 31 | |
| 32 | #version 3 |
| 33 | #version 4 |
alshabib | 9f50e48 | 2014-08-23 17:10:57 -0500 | [diff] [blame] | 34 | #version 5 |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 35 | |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 36 | struct of_oxm { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 37 | uint32_t type_len == ?; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 38 | }; |
| 39 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 40 | struct of_oxm_arp_op : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 41 | uint32_t type_len == 0x80002a02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 42 | uint16_t value; |
| 43 | }; |
| 44 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 45 | struct of_oxm_arp_op_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 46 | uint32_t type_len == 0x80002b04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 47 | uint16_t value; |
| 48 | uint16_t value_mask; |
| 49 | }; |
| 50 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 51 | struct of_oxm_arp_sha : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 52 | uint32_t type_len == 0x80003006; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 53 | of_mac_addr_t value; |
| 54 | }; |
| 55 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 56 | struct of_oxm_arp_sha_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 57 | uint32_t type_len == 0x8000310c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 58 | of_mac_addr_t value; |
| 59 | of_mac_addr_t value_mask; |
| 60 | }; |
| 61 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 62 | struct of_oxm_arp_spa : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 63 | uint32_t type_len == 0x80002c04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 64 | uint32_t value; |
| 65 | }; |
| 66 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 67 | struct of_oxm_arp_spa_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 68 | uint32_t type_len == 0x80002d08; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 69 | uint32_t value; |
| 70 | uint32_t value_mask; |
| 71 | }; |
| 72 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 73 | struct of_oxm_arp_tha : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 74 | uint32_t type_len == 0x80003206; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 75 | of_mac_addr_t value; |
| 76 | }; |
| 77 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 78 | struct of_oxm_arp_tha_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 79 | uint32_t type_len == 0x8000330c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 80 | of_mac_addr_t value; |
| 81 | of_mac_addr_t value_mask; |
| 82 | }; |
| 83 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 84 | struct of_oxm_arp_tpa : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 85 | uint32_t type_len == 0x80002e04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 86 | uint32_t value; |
| 87 | }; |
| 88 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 89 | struct of_oxm_arp_tpa_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 90 | uint32_t type_len == 0x80002f08; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 91 | uint32_t value; |
| 92 | uint32_t value_mask; |
| 93 | }; |
| 94 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 95 | struct of_oxm_eth_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 96 | uint32_t type_len == 0x80000606; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 97 | of_mac_addr_t value; |
| 98 | }; |
| 99 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 100 | struct of_oxm_eth_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 101 | uint32_t type_len == 0x8000070c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 102 | of_mac_addr_t value; |
| 103 | of_mac_addr_t value_mask; |
| 104 | }; |
| 105 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 106 | struct of_oxm_eth_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 107 | uint32_t type_len == 0x80000806; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 108 | of_mac_addr_t value; |
| 109 | }; |
| 110 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 111 | struct of_oxm_eth_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 112 | uint32_t type_len == 0x8000090c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 113 | of_mac_addr_t value; |
| 114 | of_mac_addr_t value_mask; |
| 115 | }; |
| 116 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 117 | struct of_oxm_eth_type : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 118 | uint32_t type_len == 0x80000a02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 119 | uint16_t value; |
| 120 | }; |
| 121 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 122 | struct of_oxm_eth_type_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 123 | uint32_t type_len == 0x80000b04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 124 | uint16_t value; |
| 125 | uint16_t value_mask; |
| 126 | }; |
| 127 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 128 | struct of_oxm_icmpv4_code : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 129 | uint32_t type_len == 0x80002801; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 130 | uint8_t value; |
| 131 | }; |
| 132 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 133 | struct of_oxm_icmpv4_code_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 134 | uint32_t type_len == 0x80002902; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 135 | uint8_t value; |
| 136 | uint8_t value_mask; |
| 137 | }; |
| 138 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 139 | struct of_oxm_icmpv4_type : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 140 | uint32_t type_len == 0x80002601; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 141 | uint8_t value; |
| 142 | }; |
| 143 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 144 | struct of_oxm_icmpv4_type_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 145 | uint32_t type_len == 0x80002702; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 146 | uint8_t value; |
| 147 | uint8_t value_mask; |
| 148 | }; |
| 149 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 150 | struct of_oxm_icmpv6_code : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 151 | uint32_t type_len == 0x80003c01; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 152 | uint8_t value; |
| 153 | }; |
| 154 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 155 | struct of_oxm_icmpv6_code_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 156 | uint32_t type_len == 0x80003d02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 157 | uint8_t value; |
| 158 | uint8_t value_mask; |
| 159 | }; |
| 160 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 161 | struct of_oxm_icmpv6_type : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 162 | uint32_t type_len == 0x80003a01; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 163 | uint8_t value; |
| 164 | }; |
| 165 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 166 | struct of_oxm_icmpv6_type_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 167 | uint32_t type_len == 0x80003b02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 168 | uint8_t value; |
| 169 | uint8_t value_mask; |
| 170 | }; |
| 171 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 172 | struct of_oxm_in_phy_port : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 173 | uint32_t type_len == 0x80000204; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 174 | of_port_no_t value; |
| 175 | }; |
| 176 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 177 | struct of_oxm_in_phy_port_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 178 | uint32_t type_len == 0x80000308; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 179 | of_port_no_t value; |
| 180 | of_port_no_t value_mask; |
| 181 | }; |
| 182 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 183 | struct of_oxm_in_port : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 184 | uint32_t type_len == 0x80000004; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 185 | of_port_no_t value; |
| 186 | }; |
| 187 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 188 | struct of_oxm_in_port_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 189 | uint32_t type_len == 0x80000108; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 190 | of_port_no_t value; |
| 191 | of_port_no_t value_mask; |
| 192 | }; |
| 193 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 194 | struct of_oxm_ip_dscp : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 195 | uint32_t type_len == 0x80001001; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 196 | uint8_t value; |
| 197 | }; |
| 198 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 199 | struct of_oxm_ip_dscp_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 200 | uint32_t type_len == 0x80001102; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 201 | uint8_t value; |
| 202 | uint8_t value_mask; |
| 203 | }; |
| 204 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 205 | struct of_oxm_ip_ecn : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 206 | uint32_t type_len == 0x80001201; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 207 | uint8_t value; |
| 208 | }; |
| 209 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 210 | struct of_oxm_ip_ecn_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 211 | uint32_t type_len == 0x80001302; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 212 | uint8_t value; |
| 213 | uint8_t value_mask; |
| 214 | }; |
| 215 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 216 | struct of_oxm_ip_proto : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 217 | uint32_t type_len == 0x80001401; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 218 | uint8_t value; |
| 219 | }; |
| 220 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 221 | struct of_oxm_ip_proto_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 222 | uint32_t type_len == 0x80001502; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 223 | uint8_t value; |
| 224 | uint8_t value_mask; |
| 225 | }; |
| 226 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 227 | struct of_oxm_ipv4_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 228 | uint32_t type_len == 0x80001804; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 229 | of_ipv4_t value; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 230 | }; |
| 231 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 232 | struct of_oxm_ipv4_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 233 | uint32_t type_len == 0x80001908; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 234 | of_ipv4_t value; |
| 235 | of_ipv4_t value_mask; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 236 | }; |
| 237 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 238 | struct of_oxm_ipv4_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 239 | uint32_t type_len == 0x80001604; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 240 | of_ipv4_t value; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 241 | }; |
| 242 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 243 | struct of_oxm_ipv4_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 244 | uint32_t type_len == 0x80001708; |
Andreas Wundsam | b566a16 | 2013-07-18 19:30:23 -0700 | [diff] [blame] | 245 | of_ipv4_t value; |
| 246 | of_ipv4_t value_mask; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 247 | }; |
| 248 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 249 | struct of_oxm_ipv6_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 250 | uint32_t type_len == 0x80003610; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 251 | of_ipv6_t value; |
| 252 | }; |
| 253 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 254 | struct of_oxm_ipv6_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 255 | uint32_t type_len == 0x80003720; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 256 | of_ipv6_t value; |
| 257 | of_ipv6_t value_mask; |
| 258 | }; |
| 259 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 260 | struct of_oxm_ipv6_flabel : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 261 | uint32_t type_len == 0x80003804; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 262 | uint32_t value; |
| 263 | }; |
| 264 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 265 | struct of_oxm_ipv6_flabel_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 266 | uint32_t type_len == 0x80003908; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 267 | uint32_t value; |
| 268 | uint32_t value_mask; |
| 269 | }; |
| 270 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 271 | struct of_oxm_ipv6_nd_sll : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 272 | uint32_t type_len == 0x80004006; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 273 | of_mac_addr_t value; |
| 274 | }; |
| 275 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 276 | struct of_oxm_ipv6_nd_sll_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 277 | uint32_t type_len == 0x8000410c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 278 | of_mac_addr_t value; |
| 279 | of_mac_addr_t value_mask; |
| 280 | }; |
| 281 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 282 | struct of_oxm_ipv6_nd_target : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 283 | uint32_t type_len == 0x80003e10; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 284 | of_ipv6_t value; |
| 285 | }; |
| 286 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 287 | struct of_oxm_ipv6_nd_target_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 288 | uint32_t type_len == 0x80003f20; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 289 | of_ipv6_t value; |
| 290 | of_ipv6_t value_mask; |
| 291 | }; |
| 292 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 293 | struct of_oxm_ipv6_nd_tll : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 294 | uint32_t type_len == 0x80004206; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 295 | of_mac_addr_t value; |
| 296 | }; |
| 297 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 298 | struct of_oxm_ipv6_nd_tll_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 299 | uint32_t type_len == 0x8000430c; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 300 | of_mac_addr_t value; |
| 301 | of_mac_addr_t value_mask; |
| 302 | }; |
| 303 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 304 | struct of_oxm_ipv6_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 305 | uint32_t type_len == 0x80003410; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 306 | of_ipv6_t value; |
| 307 | }; |
| 308 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 309 | struct of_oxm_ipv6_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 310 | uint32_t type_len == 0x80003520; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 311 | of_ipv6_t value; |
| 312 | of_ipv6_t value_mask; |
| 313 | }; |
| 314 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 315 | struct of_oxm_metadata : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 316 | uint32_t type_len == 0x80000408; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 317 | uint64_t value; |
| 318 | }; |
| 319 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 320 | struct of_oxm_metadata_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 321 | uint32_t type_len == 0x80000510; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 322 | uint64_t value; |
| 323 | uint64_t value_mask; |
| 324 | }; |
| 325 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 326 | struct of_oxm_mpls_label : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 327 | uint32_t type_len == 0x80004404; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 328 | uint32_t value; |
| 329 | }; |
| 330 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 331 | struct of_oxm_mpls_label_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 332 | uint32_t type_len == 0x80004508; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 333 | uint32_t value; |
| 334 | uint32_t value_mask; |
| 335 | }; |
| 336 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 337 | struct of_oxm_mpls_tc : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 338 | uint32_t type_len == 0x80004601; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 339 | uint8_t value; |
| 340 | }; |
| 341 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 342 | struct of_oxm_mpls_tc_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 343 | uint32_t type_len == 0x80004702; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 344 | uint8_t value; |
| 345 | uint8_t value_mask; |
| 346 | }; |
| 347 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 348 | struct of_oxm_sctp_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 349 | uint32_t type_len == 0x80002402; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 350 | uint16_t value; |
| 351 | }; |
| 352 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 353 | struct of_oxm_sctp_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 354 | uint32_t type_len == 0x80002504; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 355 | uint16_t value; |
| 356 | uint16_t value_mask; |
| 357 | }; |
| 358 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 359 | struct of_oxm_sctp_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 360 | uint32_t type_len == 0x80002202; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 361 | uint16_t value; |
| 362 | }; |
| 363 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 364 | struct of_oxm_sctp_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 365 | uint32_t type_len == 0x80002304; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 366 | uint16_t value; |
| 367 | uint16_t value_mask; |
| 368 | }; |
| 369 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 370 | struct of_oxm_tcp_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 371 | uint32_t type_len == 0x80001c02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 372 | uint16_t value; |
| 373 | }; |
| 374 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 375 | struct of_oxm_tcp_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 376 | uint32_t type_len == 0x80001d04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 377 | uint16_t value; |
| 378 | uint16_t value_mask; |
| 379 | }; |
| 380 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 381 | struct of_oxm_tcp_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 382 | uint32_t type_len == 0x80001a02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 383 | uint16_t value; |
| 384 | }; |
| 385 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 386 | struct of_oxm_tcp_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 387 | uint32_t type_len == 0x80001b04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 388 | uint16_t value; |
| 389 | uint16_t value_mask; |
| 390 | }; |
| 391 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 392 | struct of_oxm_udp_dst : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 393 | uint32_t type_len == 0x80002002; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 394 | uint16_t value; |
| 395 | }; |
| 396 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 397 | struct of_oxm_udp_dst_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 398 | uint32_t type_len == 0x80002104; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 399 | uint16_t value; |
| 400 | uint16_t value_mask; |
| 401 | }; |
| 402 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 403 | struct of_oxm_udp_src : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 404 | uint32_t type_len == 0x80001e02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 405 | uint16_t value; |
| 406 | }; |
| 407 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 408 | struct of_oxm_udp_src_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 409 | uint32_t type_len == 0x80001f04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 410 | uint16_t value; |
| 411 | uint16_t value_mask; |
| 412 | }; |
| 413 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 414 | struct of_oxm_vlan_pcp : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 415 | uint32_t type_len == 0x80000e01; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 416 | uint8_t value; |
| 417 | }; |
| 418 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 419 | struct of_oxm_vlan_pcp_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 420 | uint32_t type_len == 0x80000f02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 421 | uint8_t value; |
| 422 | uint8_t value_mask; |
| 423 | }; |
| 424 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 425 | struct of_oxm_vlan_vid : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 426 | uint32_t type_len == 0x80000c02; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 427 | uint16_t value; |
| 428 | }; |
| 429 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 430 | struct of_oxm_vlan_vid_masked : of_oxm { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 431 | uint32_t type_len == 0x80000d04; |
Rich Lane | 883919c | 2013-05-09 17:53:18 -0700 | [diff] [blame] | 432 | uint16_t value; |
| 433 | uint16_t value_mask; |
| 434 | }; |