Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1 | // Copyright 2013, Big Switch Networks, Inc. |
| 2 | // |
| 3 | // LoxiGen is licensed under the Eclipse Public License, version 1.0 (EPL), with |
| 4 | // the following special exception: |
| 5 | // |
| 6 | // LOXI Exception |
| 7 | // |
| 8 | // As a special exception to the terms of the EPL, you may distribute libraries |
| 9 | // generated by LoxiGen (LoxiGen Libraries) under the terms of your choice, provided |
| 10 | // that copyright and licensing notices generated by LoxiGen are not altered or removed |
| 11 | // from the LoxiGen Libraries and the notice provided below is (i) included in |
| 12 | // the LoxiGen Libraries, if distributed in source code form and (ii) included in any |
| 13 | // documentation for the LoxiGen Libraries, if distributed in binary form. |
| 14 | // |
| 15 | // Notice: "Copyright 2013, Big Switch Networks, Inc. This library was generated by the LoxiGen Compiler." |
| 16 | // |
| 17 | // You may not use this file except in compliance with the EPL or LOXI Exception. You may obtain |
| 18 | // a copy of the EPL at: |
| 19 | // |
| 20 | // http://www.eclipse.org/legal/epl-v10.html |
| 21 | // |
| 22 | // Unless required by applicable law or agreed to in writing, software |
| 23 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 24 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 25 | // EPL for the specific language governing permissions and limitations |
| 26 | // under the EPL. |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 27 | // |
| 28 | // Also derived from the OpenFlow header files which have these copyrights: |
| 29 | // Copyright (c) 2008 The Board of Trustees of The Leland Stanford Junior University |
| 30 | // Copyright (c) 2011, 2012 Open Networking Foundation |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 31 | |
| 32 | #version 3 |
| 33 | |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 34 | enum macro_definitions { |
| 35 | OFP_MAX_TABLE_NAME_LEN = 32, |
| 36 | OFP_MAX_PORT_NAME_LEN = 16, |
| 37 | |
Wilson Ng | d72013d | 2013-09-29 10:21:48 -0700 | [diff] [blame] | 38 | OFP_TCP_PORT = 6653, |
| 39 | OFP_SSL_PORT = 6653, |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 40 | |
| 41 | OFP_ETH_ALEN = 6, |
| 42 | |
| 43 | OFP_DEFAULT_MISS_SEND_LEN = 128, |
| 44 | |
| 45 | OFP_VLAN_NONE = 0, |
| 46 | |
| 47 | OFP_FLOW_PERMANENT = 0, |
| 48 | |
| 49 | OFP_DEFAULT_PRIORITY = 0x8000, |
| 50 | |
| 51 | OFP_NO_BUFFER = 0xffffffff, |
| 52 | |
| 53 | DESC_STR_LEN = 256, |
| 54 | SERIAL_NUM_LEN = 32, |
| 55 | |
| 56 | OFPQ_ALL = 0xffffffff, |
| 57 | |
| 58 | OFPQ_MIN_RATE_UNCFG = 0xffff, |
| 59 | OFPQ_MAX_RATE_UNCFG = 0xffff, |
| 60 | }; |
| 61 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 62 | enum ofp_port(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 63 | OFPP_MAX = 0xffffff00, |
| 64 | OFPP_IN_PORT = 0xfffffff8, |
| 65 | OFPP_TABLE = 0xfffffff9, |
| 66 | OFPP_NORMAL = 0xfffffffa, |
| 67 | OFPP_FLOOD = 0xfffffffb, |
| 68 | OFPP_ALL = 0xfffffffc, |
| 69 | OFPP_CONTROLLER = 0xfffffffd, |
| 70 | OFPP_LOCAL = 0xfffffffe, |
| 71 | }; |
| 72 | |
Andreas Wundsam | 7933beb | 2013-08-02 22:36:42 -0700 | [diff] [blame] | 73 | enum ofp_port_no(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 74 | OFPP_ANY = 0xffffffff, |
| 75 | }; |
| 76 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 77 | enum ofp_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 78 | OFPT_HELLO = 0, |
| 79 | OFPT_ERROR = 1, |
| 80 | OFPT_ECHO_REQUEST = 2, |
| 81 | OFPT_ECHO_REPLY = 3, |
| 82 | OFPT_EXPERIMENTER = 4, |
| 83 | OFPT_FEATURES_REQUEST = 5, |
| 84 | OFPT_FEATURES_REPLY = 6, |
| 85 | OFPT_GET_CONFIG_REQUEST = 7, |
| 86 | OFPT_GET_CONFIG_REPLY = 8, |
| 87 | OFPT_SET_CONFIG = 9, |
| 88 | OFPT_PACKET_IN = 10, |
| 89 | OFPT_FLOW_REMOVED = 11, |
| 90 | OFPT_PORT_STATUS = 12, |
| 91 | OFPT_PACKET_OUT = 13, |
| 92 | OFPT_FLOW_MOD = 14, |
| 93 | OFPT_GROUP_MOD = 15, |
| 94 | OFPT_PORT_MOD = 16, |
| 95 | OFPT_TABLE_MOD = 17, |
| 96 | OFPT_STATS_REQUEST = 18, |
| 97 | OFPT_STATS_REPLY = 19, |
| 98 | OFPT_BARRIER_REQUEST = 20, |
| 99 | OFPT_BARRIER_REPLY = 21, |
| 100 | OFPT_QUEUE_GET_CONFIG_REQUEST = 22, |
| 101 | OFPT_QUEUE_GET_CONFIG_REPLY = 23, |
| 102 | OFPT_ROLE_REQUEST = 24, |
| 103 | OFPT_ROLE_REPLY = 25, |
| 104 | }; |
| 105 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 106 | enum ofp_config_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 107 | OFPC_FRAG_NORMAL = 0, |
| 108 | OFPC_FRAG_DROP = 1, |
| 109 | OFPC_FRAG_REASM = 2, |
| 110 | OFPC_FRAG_MASK = 3, |
| 111 | OFPC_INVALID_TTL_TO_CONTROLLER = 4, |
| 112 | }; |
| 113 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 114 | enum ofp_table_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 115 | OFPTC_TABLE_MISS_CONTROLLER = 0, |
| 116 | OFPTC_TABLE_MISS_CONTINUE = 1, |
| 117 | OFPTC_TABLE_MISS_DROP = 2, |
| 118 | OFPTC_TABLE_MISS_MASK = 3, |
| 119 | }; |
| 120 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 121 | enum ofp_table(wire_type=uint8_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 122 | OFPTT_MAX = 0xfe, |
| 123 | OFPTT_ALL = 0xff, |
| 124 | }; |
| 125 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 126 | enum ofp_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 127 | OFPC_FLOW_STATS = 0x1, |
| 128 | OFPC_TABLE_STATS = 0x2, |
| 129 | OFPC_PORT_STATS = 0x4, |
| 130 | OFPC_GROUP_STATS = 0x8, |
| 131 | OFPC_IP_REASM = 0x20, |
| 132 | OFPC_QUEUE_STATS = 0x40, |
| 133 | OFPC_PORT_BLOCKED = 0x100, |
| 134 | }; |
| 135 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 136 | enum ofp_port_config(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 137 | OFPPC_PORT_DOWN = 0x1, |
| 138 | OFPPC_NO_RECV = 0x4, |
| 139 | OFPPC_NO_FWD = 0x20, |
| 140 | OFPPC_NO_PACKET_IN = 0x40, |
| 141 | }; |
| 142 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 143 | enum ofp_port_state(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 144 | OFPPS_LINK_DOWN = 0x1, |
| 145 | OFPPS_BLOCKED = 0x2, |
| 146 | OFPPS_LIVE = 0x4, |
| 147 | }; |
| 148 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 149 | enum ofp_port_features(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 150 | OFPPF_10MB_HD = 0x1, |
| 151 | OFPPF_10MB_FD = 0x2, |
| 152 | OFPPF_100MB_HD = 0x4, |
| 153 | OFPPF_100MB_FD = 0x8, |
| 154 | OFPPF_1GB_HD = 0x10, |
| 155 | OFPPF_1GB_FD = 0x20, |
| 156 | OFPPF_10GB_FD = 0x40, |
| 157 | OFPPF_40GB_FD = 0x80, |
| 158 | OFPPF_100GB_FD = 0x100, |
| 159 | OFPPF_1TB_FD = 0x200, |
| 160 | OFPPF_OTHER = 0x400, |
| 161 | OFPPF_COPPER = 0x800, |
| 162 | OFPPF_FIBER = 0x1000, |
| 163 | OFPPF_AUTONEG = 0x2000, |
| 164 | OFPPF_PAUSE = 0x4000, |
| 165 | OFPPF_PAUSE_ASYM = 0x8000, |
| 166 | }; |
| 167 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 168 | enum ofp_port_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 169 | OFPPR_ADD = 0, |
| 170 | OFPPR_DELETE = 1, |
| 171 | OFPPR_MODIFY = 2, |
| 172 | }; |
| 173 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 174 | enum ofp_match_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 175 | OFPMT_STANDARD = 0, |
| 176 | OFPMT_OXM = 1, |
| 177 | }; |
| 178 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 179 | enum ofp_oxm_class(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 180 | OFPXMC_NXM_0 = 0, |
| 181 | OFPXMC_NXM_1 = 1, |
| 182 | OFPXMC_OPENFLOW_BASIC = 0x8000, |
| 183 | OFPXMC_EXPERIMENTER = 0xffff, |
| 184 | }; |
| 185 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 186 | enum ofp_vlan_id(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 187 | OFPVID_NONE = 0, |
| 188 | OFPVID_PRESENT = 0x1000, |
| 189 | }; |
| 190 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 191 | enum ofp_action_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 192 | OFPAT_OUTPUT = 0, |
| 193 | OFPAT_COPY_TTL_OUT = 0xb, |
| 194 | OFPAT_COPY_TTL_IN = 0xc, |
| 195 | OFPAT_SET_MPLS_TTL = 0xf, |
| 196 | OFPAT_DEC_MPLS_TTL = 0x10, |
| 197 | OFPAT_PUSH_VLAN = 0x11, |
| 198 | OFPAT_POP_VLAN = 0x12, |
| 199 | OFPAT_PUSH_MPLS = 0x13, |
| 200 | OFPAT_POP_MPLS = 0x14, |
| 201 | OFPAT_SET_QUEUE = 0x15, |
| 202 | OFPAT_GROUP = 0x16, |
| 203 | OFPAT_SET_NW_TTL = 0x17, |
| 204 | OFPAT_DEC_NW_TTL = 0x18, |
| 205 | OFPAT_SET_FIELD = 0x19, |
| 206 | OFPAT_EXPERIMENTER = 0xffff, |
| 207 | }; |
| 208 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 209 | enum ofp_controller_max_len(wire_type=uint16_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 210 | OFPCML_MAX = 0xffe5, |
| 211 | OFPCML_NO_BUFFER = 0xffff, |
| 212 | }; |
| 213 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 214 | enum ofp_instruction_type(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 215 | OFPIT_GOTO_TABLE = 0x1, |
| 216 | OFPIT_WRITE_METADATA = 0x2, |
| 217 | OFPIT_WRITE_ACTIONS = 0x3, |
| 218 | OFPIT_APPLY_ACTIONS = 0x4, |
| 219 | OFPIT_CLEAR_ACTIONS = 0x5, |
| 220 | OFPIT_EXPERIMENTER = 0xffff, |
| 221 | }; |
| 222 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 223 | enum ofp_flow_mod_command(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 224 | OFPFC_ADD = 0, |
| 225 | OFPFC_MODIFY = 1, |
| 226 | OFPFC_MODIFY_STRICT = 2, |
| 227 | OFPFC_DELETE = 3, |
| 228 | OFPFC_DELETE_STRICT = 4, |
| 229 | }; |
| 230 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 231 | enum ofp_flow_mod_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 232 | OFPFF_SEND_FLOW_REM = 0x1, |
| 233 | OFPFF_CHECK_OVERLAP = 0x2, |
| 234 | OFPFF_RESET_COUNTS = 0x4, |
| 235 | }; |
| 236 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 237 | enum ofp_group(wire_type=uint32_t, complete=False) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 238 | OFPG_MAX = 0xffffff00, |
| 239 | OFPG_ALL = 0xfffffffc, |
| 240 | OFPG_ANY = 0xffffffff, |
| 241 | }; |
| 242 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 243 | enum ofp_group_mod_command(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 244 | OFPGC_ADD = 0, |
| 245 | OFPGC_MODIFY = 1, |
| 246 | OFPGC_DELETE = 2, |
| 247 | }; |
| 248 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 249 | enum ofp_group_type(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 250 | OFPGT_ALL = 0, |
| 251 | OFPGT_SELECT = 1, |
| 252 | OFPGT_INDIRECT = 2, |
| 253 | OFPGT_FF = 3, |
| 254 | }; |
| 255 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 256 | enum ofp_packet_in_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 257 | OFPR_NO_MATCH = 0, |
| 258 | OFPR_ACTION = 1, |
| 259 | OFPR_INVALID_TTL = 2, |
| 260 | }; |
| 261 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 262 | enum ofp_flow_removed_reason(wire_type=uint8_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 263 | OFPRR_IDLE_TIMEOUT = 0, |
| 264 | OFPRR_HARD_TIMEOUT = 1, |
| 265 | OFPRR_DELETE = 2, |
| 266 | OFPRR_GROUP_DELETE = 3, |
| 267 | }; |
| 268 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 269 | enum ofp_error_type(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 270 | OFPET_HELLO_FAILED = 0, |
| 271 | OFPET_BAD_REQUEST = 1, |
| 272 | OFPET_BAD_ACTION = 2, |
| 273 | OFPET_BAD_INSTRUCTION = 3, |
| 274 | OFPET_BAD_MATCH = 4, |
| 275 | OFPET_FLOW_MOD_FAILED = 5, |
| 276 | OFPET_GROUP_MOD_FAILED = 6, |
| 277 | OFPET_PORT_MOD_FAILED = 7, |
| 278 | OFPET_TABLE_MOD_FAILED = 8, |
| 279 | OFPET_QUEUE_OP_FAILED = 9, |
| 280 | OFPET_SWITCH_CONFIG_FAILED = 10, |
| 281 | OFPET_ROLE_REQUEST_FAILED = 11, |
| 282 | OFPET_EXPERIMENTER = 0xffff, |
| 283 | }; |
| 284 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 285 | enum ofp_hello_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 286 | OFPHFC_INCOMPATIBLE = 0, |
| 287 | OFPHFC_EPERM = 1, |
| 288 | }; |
| 289 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 290 | enum ofp_bad_request_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 291 | OFPBRC_BAD_VERSION = 0, |
| 292 | OFPBRC_BAD_TYPE = 1, |
| 293 | OFPBRC_BAD_STAT = 2, |
| 294 | OFPBRC_BAD_EXPERIMENTER = 3, |
| 295 | OFPBRC_BAD_EXP_TYPE = 4, |
| 296 | OFPBRC_EPERM = 5, |
| 297 | OFPBRC_BAD_LEN = 6, |
| 298 | OFPBRC_BUFFER_EMPTY = 7, |
| 299 | OFPBRC_BUFFER_UNKNOWN = 8, |
| 300 | OFPBRC_BAD_TABLE_ID = 9, |
| 301 | OFPBRC_IS_SLAVE = 10, |
| 302 | OFPBRC_BAD_PORT = 11, |
| 303 | OFPBRC_BAD_PACKET = 12, |
| 304 | }; |
| 305 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 306 | enum ofp_bad_action_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 307 | OFPBAC_BAD_TYPE = 0, |
| 308 | OFPBAC_BAD_LEN = 1, |
| 309 | OFPBAC_BAD_EXPERIMENTER = 2, |
| 310 | OFPBAC_BAD_EXP_TYPE = 3, |
| 311 | OFPBAC_BAD_OUT_PORT = 4, |
| 312 | OFPBAC_BAD_ARGUMENT = 5, |
| 313 | OFPBAC_EPERM = 6, |
| 314 | OFPBAC_TOO_MANY = 7, |
| 315 | OFPBAC_BAD_QUEUE = 8, |
| 316 | OFPBAC_BAD_OUT_GROUP = 9, |
| 317 | OFPBAC_MATCH_INCONSISTENT = 10, |
| 318 | OFPBAC_UNSUPPORTED_ORDER = 11, |
| 319 | OFPBAC_BAD_TAG = 12, |
| 320 | OFPBAC_BAD_SET_TYPE = 13, |
| 321 | OFPBAC_BAD_SET_LEN = 14, |
| 322 | OFPBAC_BAD_SET_ARGUMENT = 15, |
| 323 | }; |
| 324 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 325 | enum ofp_bad_instruction_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 326 | OFPBIC_UNKNOWN_INST = 0, |
| 327 | OFPBIC_UNSUP_INST = 1, |
| 328 | OFPBIC_BAD_TABLE_ID = 2, |
| 329 | OFPBIC_UNSUP_METADATA = 3, |
| 330 | OFPBIC_UNSUP_METADATA_MASK = 4, |
| 331 | OFPBIC_BAD_EXPERIMENTER = 5, |
| 332 | OFPBIC_BAD_EXP_TYPE = 6, |
| 333 | OFPBIC_BAD_LEN = 7, |
| 334 | OFPBIC_EPERM = 8, |
| 335 | }; |
| 336 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 337 | enum ofp_bad_match_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 338 | OFPBMC_BAD_TYPE = 0, |
| 339 | OFPBMC_BAD_LEN = 1, |
| 340 | OFPBMC_BAD_TAG = 2, |
| 341 | OFPBMC_BAD_DL_ADDR_MASK = 3, |
| 342 | OFPBMC_BAD_NW_ADDR_MASK = 4, |
| 343 | OFPBMC_BAD_WILDCARDS = 5, |
| 344 | OFPBMC_BAD_FIELD = 6, |
| 345 | OFPBMC_BAD_VALUE = 7, |
| 346 | OFPBMC_BAD_MASK = 8, |
| 347 | OFPBMC_BAD_PREREQ = 9, |
| 348 | OFPBMC_DUP_FIELD = 10, |
| 349 | OFPBMC_EPERM = 11, |
| 350 | }; |
| 351 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 352 | enum ofp_flow_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 353 | OFPFMFC_UNKNOWN = 0, |
| 354 | OFPFMFC_TABLE_FULL = 1, |
| 355 | OFPFMFC_BAD_TABLE_ID = 2, |
| 356 | OFPFMFC_OVERLAP = 3, |
| 357 | OFPFMFC_EPERM = 4, |
| 358 | OFPFMFC_BAD_TIMEOUT = 5, |
| 359 | OFPFMFC_BAD_COMMAND = 6, |
| 360 | OFPFMFC_BAD_FLAGS = 7, |
| 361 | }; |
| 362 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 363 | enum ofp_group_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 364 | OFPGMFC_GROUP_EXISTS = 0, |
| 365 | OFPGMFC_INVALID_GROUP = 1, |
| 366 | OFPGMFC_WEIGHT_UNSUPPORTED = 2, |
| 367 | OFPGMFC_OUT_OF_GROUPS = 3, |
| 368 | OFPGMFC_OUT_OF_BUCKETS = 4, |
| 369 | OFPGMFC_CHAINING_UNSUPPORTED = 5, |
| 370 | OFPGMFC_WATCH_UNSUPPORTED = 6, |
| 371 | OFPGMFC_LOOP = 7, |
| 372 | OFPGMFC_UNKNOWN_GROUP = 8, |
| 373 | OFPGMFC_CHAINED_GROUP = 9, |
| 374 | OFPGMFC_BAD_TYPE = 10, |
| 375 | OFPGMFC_BAD_COMMAND = 11, |
| 376 | OFPGMFC_BAD_BUCKET = 12, |
| 377 | OFPGMFC_BAD_WATCH = 13, |
| 378 | OFPGMFC_EPERM = 14, |
| 379 | }; |
| 380 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 381 | enum ofp_port_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 382 | OFPPMFC_BAD_PORT = 0, |
| 383 | OFPPMFC_BAD_HW_ADDR = 1, |
| 384 | OFPPMFC_BAD_CONFIG = 2, |
| 385 | OFPPMFC_BAD_ADVERTISE = 3, |
| 386 | OFPPMFC_EPERM = 4, |
| 387 | }; |
| 388 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 389 | enum ofp_table_mod_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 390 | OFPTMFC_BAD_TABLE = 0, |
| 391 | OFPTMFC_BAD_CONFIG = 1, |
| 392 | OFPTMFC_EPERM = 2, |
| 393 | }; |
| 394 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 395 | enum ofp_queue_op_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 396 | OFPQOFC_BAD_PORT = 0, |
| 397 | OFPQOFC_BAD_QUEUE = 1, |
| 398 | OFPQOFC_EPERM = 2, |
| 399 | }; |
| 400 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 401 | enum ofp_switch_config_failed_code(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 402 | OFPSCFC_BAD_FLAGS = 0, |
| 403 | OFPSCFC_BAD_LEN = 1, |
| 404 | OFPSCFC_EPERM = 2, |
| 405 | }; |
| 406 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 407 | enum ofp_role_request_failed_code (wire_type=uint16_t){ |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 408 | OFPRRFC_STALE = 0, |
| 409 | OFPRRFC_UNSUP = 1, |
| 410 | OFPRRFC_BAD_ROLE = 2, |
| 411 | }; |
| 412 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 413 | enum ofp_stats_types(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 414 | OFPST_DESC = 0, |
| 415 | OFPST_FLOW = 1, |
| 416 | OFPST_AGGREGATE = 2, |
| 417 | OFPST_TABLE = 3, |
| 418 | OFPST_PORT = 4, |
| 419 | OFPST_QUEUE = 5, |
| 420 | OFPST_GROUP = 6, |
| 421 | OFPST_GROUP_DESC = 7, |
| 422 | OFPST_GROUP_FEATURES = 8, |
| 423 | OFPST_EXPERIMENTER = 0xffff, |
| 424 | }; |
| 425 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 426 | enum ofp_stats_reply_flags(wire_type=uint16_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 427 | OFPSF_REPLY_MORE = 0x1, |
| 428 | }; |
| 429 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 430 | enum ofp_group_capabilities(wire_type=uint32_t, bitmask=True) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 431 | OFPGFC_SELECT_WEIGHT = 0x1, |
| 432 | OFPGFC_SELECT_LIVENESS = 0x2, |
| 433 | OFPGFC_CHAINING = 0x4, |
| 434 | OFPGFC_CHAINING_CHECKS = 0x8, |
| 435 | }; |
| 436 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 437 | enum ofp_queue_properties(wire_type=uint16_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 438 | OFPQT_MIN_RATE = 0x1, |
| 439 | OFPQT_MAX_RATE = 0x2, |
| 440 | OFPQT_EXPERIMENTER = 0xffff, |
| 441 | }; |
| 442 | |
Andreas Wundsam | 4ee5146 | 2013-07-30 11:00:37 -0700 | [diff] [blame] | 443 | enum ofp_controller_role(wire_type=uint32_t) { |
Rich Lane | 5d33a62 | 2013-04-08 17:33:11 -0700 | [diff] [blame] | 444 | OFPCR_ROLE_NOCHANGE = 0, |
| 445 | OFPCR_ROLE_EQUAL = 1, |
| 446 | OFPCR_ROLE_MASTER = 2, |
| 447 | OFPCR_ROLE_SLAVE = 3, |
| 448 | }; |
| 449 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 450 | /* XXX rename to of_message */ |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 451 | struct of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 452 | uint8_t version; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 453 | uint8_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 454 | uint16_t length; |
| 455 | uint32_t xid; |
| 456 | }; |
| 457 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 458 | struct of_hello : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 459 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 460 | uint8_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 461 | uint16_t length; |
| 462 | uint32_t xid; |
| 463 | }; |
| 464 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 465 | struct of_echo_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 466 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 467 | uint8_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 468 | uint16_t length; |
| 469 | uint32_t xid; |
| 470 | of_octets_t data; |
| 471 | }; |
| 472 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 473 | struct of_echo_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 474 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 475 | uint8_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 476 | uint16_t length; |
| 477 | uint32_t xid; |
| 478 | of_octets_t data; |
| 479 | }; |
| 480 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 481 | struct of_experimenter : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 482 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 483 | uint8_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 484 | uint16_t length; |
| 485 | uint32_t xid; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 486 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 487 | uint32_t subtype; |
| 488 | of_octets_t data; |
| 489 | }; |
| 490 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 491 | struct of_barrier_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 492 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 493 | uint8_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 494 | uint16_t length; |
| 495 | uint32_t xid; |
| 496 | }; |
| 497 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 498 | struct of_barrier_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 499 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 500 | uint8_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 501 | uint16_t length; |
| 502 | uint32_t xid; |
| 503 | }; |
| 504 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 505 | struct of_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 506 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 507 | uint8_t type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 508 | uint16_t length; |
| 509 | uint32_t xid; |
| 510 | }; |
| 511 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 512 | struct of_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 513 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 514 | uint8_t type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 515 | uint16_t length; |
| 516 | uint32_t xid; |
| 517 | uint16_t flags; |
| 518 | uint16_t miss_send_len; |
| 519 | }; |
| 520 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 521 | struct of_set_config : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 522 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 523 | uint8_t type == 9; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 524 | uint16_t length; |
| 525 | uint32_t xid; |
| 526 | uint16_t flags; |
| 527 | uint16_t miss_send_len; |
| 528 | }; |
| 529 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 530 | struct of_table_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 531 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 532 | uint8_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 533 | uint16_t length; |
| 534 | uint32_t xid; |
| 535 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 536 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 537 | uint32_t config; |
| 538 | }; |
| 539 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 540 | struct of_port_desc { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 541 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 542 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 543 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 544 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 545 | of_port_name_t name; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 546 | enum ofp_port_config config; |
| 547 | enum ofp_port_state state; |
| 548 | enum ofp_port_features curr; |
| 549 | enum ofp_port_features advertised; |
| 550 | enum ofp_port_features supported; |
| 551 | enum ofp_port_features peer; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 552 | uint32_t curr_speed; |
| 553 | uint32_t max_speed; |
| 554 | }; |
| 555 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 556 | struct of_features_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 557 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 558 | uint8_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 559 | uint16_t length; |
| 560 | uint32_t xid; |
| 561 | }; |
| 562 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 563 | struct of_features_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 564 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 565 | uint8_t type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 566 | uint16_t length; |
| 567 | uint32_t xid; |
| 568 | uint64_t datapath_id; |
| 569 | uint32_t n_buffers; |
| 570 | uint8_t n_tables; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 571 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 572 | uint32_t capabilities; |
| 573 | uint32_t reserved; |
| 574 | list(of_port_desc_t) ports; |
| 575 | }; |
| 576 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 577 | struct of_port_status : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 578 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 579 | uint8_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 580 | uint16_t length; |
| 581 | uint32_t xid; |
Rob Vaterlaus | d9d72d2 | 2013-09-23 14:50:52 -0700 | [diff] [blame] | 582 | enum ofp_port_reason reason; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 583 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 584 | of_port_desc_t desc; |
| 585 | }; |
| 586 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 587 | struct of_port_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 588 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 589 | uint8_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 590 | uint16_t length; |
| 591 | uint32_t xid; |
| 592 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 593 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 594 | of_mac_addr_t hw_addr; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 595 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 596 | uint32_t config; |
| 597 | uint32_t mask; |
| 598 | uint32_t advertise; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 599 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 600 | }; |
| 601 | |
Andreas Wundsam | fef7d5f | 2013-08-01 22:15:44 -0700 | [diff] [blame] | 602 | struct of_match_v3(align=8) { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 603 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 604 | uint16_t length; |
| 605 | list(of_oxm_t) oxm_list; |
| 606 | }; |
| 607 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 608 | struct of_action_output : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 609 | uint16_t type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 610 | uint16_t len; |
| 611 | of_port_no_t port; |
| 612 | uint16_t max_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 613 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 614 | }; |
| 615 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 616 | struct of_action_copy_ttl_out : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 617 | uint16_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 618 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 619 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 620 | }; |
| 621 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 622 | struct of_action_copy_ttl_in : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 623 | uint16_t type == 12; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 624 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 625 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 626 | }; |
| 627 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 628 | struct of_action_set_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 629 | uint16_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 630 | uint16_t len; |
| 631 | uint8_t mpls_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 632 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 633 | }; |
| 634 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 635 | struct of_action_dec_mpls_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 636 | uint16_t type == 16; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 637 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 638 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 639 | }; |
| 640 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 641 | struct of_action_push_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 642 | uint16_t type == 17; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 643 | uint16_t len; |
| 644 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 645 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 646 | }; |
| 647 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 648 | struct of_action_pop_vlan : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 649 | uint16_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 650 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 651 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 652 | }; |
| 653 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 654 | struct of_action_push_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 655 | uint16_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 656 | uint16_t len; |
| 657 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 658 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 659 | }; |
| 660 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 661 | struct of_action_pop_mpls : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 662 | uint16_t type == 20; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 663 | uint16_t len; |
| 664 | uint16_t ethertype; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 665 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 666 | }; |
| 667 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 668 | struct of_action_set_queue : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 669 | uint16_t type == 21; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 670 | uint16_t len; |
| 671 | uint32_t queue_id; |
| 672 | }; |
| 673 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 674 | struct of_action_group : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 675 | uint16_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 676 | uint16_t len; |
| 677 | uint32_t group_id; |
| 678 | }; |
| 679 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 680 | struct of_action_set_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 681 | uint16_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 682 | uint16_t len; |
| 683 | uint8_t nw_ttl; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 684 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 685 | }; |
| 686 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 687 | struct of_action_dec_nw_ttl : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 688 | uint16_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 689 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 690 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 691 | }; |
| 692 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 693 | struct of_action_set_field : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 694 | uint16_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 695 | uint16_t len; |
Rich Lane | be90eae | 2013-07-22 16:44:26 -0700 | [diff] [blame] | 696 | of_oxm_t field; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 697 | }; |
| 698 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 699 | struct of_action_experimenter : of_action { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 700 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 701 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 702 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 703 | of_octets_t data; |
| 704 | }; |
| 705 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 706 | struct of_action { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 707 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 708 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 709 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 710 | }; |
| 711 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 712 | struct of_instruction { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 713 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 714 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 715 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 716 | }; |
| 717 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 718 | struct of_instruction_goto_table : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 719 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 720 | uint16_t len; |
| 721 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 722 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 723 | }; |
| 724 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 725 | struct of_instruction_write_metadata : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 726 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 727 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 728 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 729 | uint64_t metadata; |
| 730 | uint64_t metadata_mask; |
| 731 | }; |
| 732 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 733 | struct of_instruction_write_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 734 | uint16_t type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 735 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 736 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 737 | list(of_action_t) actions; |
| 738 | }; |
| 739 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 740 | struct of_instruction_apply_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 741 | uint16_t type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 742 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 743 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 744 | list(of_action_t) actions; |
| 745 | }; |
| 746 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 747 | struct of_instruction_clear_actions : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 748 | uint16_t type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 749 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 750 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 751 | }; |
| 752 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 753 | struct of_instruction_experimenter : of_instruction { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 754 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 755 | uint16_t len; |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 756 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 757 | of_octets_t data; |
| 758 | }; |
| 759 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 760 | struct of_flow_mod : of_header { |
| 761 | uint8_t version; |
| 762 | uint8_t type == 14; |
| 763 | uint16_t length; |
| 764 | uint32_t xid; |
| 765 | uint64_t cookie; |
| 766 | uint64_t cookie_mask; |
| 767 | uint8_t table_id; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 768 | of_fm_cmd_t _command == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 769 | uint16_t idle_timeout; |
| 770 | uint16_t hard_timeout; |
| 771 | uint16_t priority; |
| 772 | uint32_t buffer_id; |
| 773 | of_port_no_t out_port; |
| 774 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 775 | enum ofp_flow_mod_flags flags; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 776 | pad(2); |
| 777 | of_match_t match; |
| 778 | list(of_instruction_t) instructions; |
| 779 | }; |
| 780 | |
| 781 | struct of_flow_add : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 782 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 783 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 784 | uint16_t length; |
| 785 | uint32_t xid; |
| 786 | uint64_t cookie; |
| 787 | uint64_t cookie_mask; |
| 788 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 789 | of_fm_cmd_t _command == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 790 | uint16_t idle_timeout; |
| 791 | uint16_t hard_timeout; |
| 792 | uint16_t priority; |
| 793 | uint32_t buffer_id; |
| 794 | of_port_no_t out_port; |
| 795 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 796 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 797 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 798 | of_match_t match; |
| 799 | list(of_instruction_t) instructions; |
| 800 | }; |
| 801 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 802 | struct of_flow_modify : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 803 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 804 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 805 | uint16_t length; |
| 806 | uint32_t xid; |
| 807 | uint64_t cookie; |
| 808 | uint64_t cookie_mask; |
| 809 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 810 | of_fm_cmd_t _command == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 811 | uint16_t idle_timeout; |
| 812 | uint16_t hard_timeout; |
| 813 | uint16_t priority; |
| 814 | uint32_t buffer_id; |
| 815 | of_port_no_t out_port; |
| 816 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 817 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 818 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 819 | of_match_t match; |
| 820 | list(of_instruction_t) instructions; |
| 821 | }; |
| 822 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 823 | struct of_flow_modify_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 824 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 825 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 826 | uint16_t length; |
| 827 | uint32_t xid; |
| 828 | uint64_t cookie; |
| 829 | uint64_t cookie_mask; |
| 830 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 831 | of_fm_cmd_t _command == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 832 | uint16_t idle_timeout; |
| 833 | uint16_t hard_timeout; |
| 834 | uint16_t priority; |
| 835 | uint32_t buffer_id; |
| 836 | of_port_no_t out_port; |
| 837 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 838 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 839 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 840 | of_match_t match; |
| 841 | list(of_instruction_t) instructions; |
| 842 | }; |
| 843 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 844 | struct of_flow_delete : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 845 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 846 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 847 | uint16_t length; |
| 848 | uint32_t xid; |
| 849 | uint64_t cookie; |
| 850 | uint64_t cookie_mask; |
| 851 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 852 | of_fm_cmd_t _command == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 853 | uint16_t idle_timeout; |
| 854 | uint16_t hard_timeout; |
| 855 | uint16_t priority; |
| 856 | uint32_t buffer_id; |
| 857 | of_port_no_t out_port; |
| 858 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 859 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 860 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 861 | of_match_t match; |
| 862 | list(of_instruction_t) instructions; |
| 863 | }; |
| 864 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 865 | struct of_flow_delete_strict : of_flow_mod { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 866 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 867 | uint8_t type == 14; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 868 | uint16_t length; |
| 869 | uint32_t xid; |
| 870 | uint64_t cookie; |
| 871 | uint64_t cookie_mask; |
| 872 | uint8_t table_id; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 873 | of_fm_cmd_t _command == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 874 | uint16_t idle_timeout; |
| 875 | uint16_t hard_timeout; |
| 876 | uint16_t priority; |
| 877 | uint32_t buffer_id; |
| 878 | of_port_no_t out_port; |
| 879 | uint32_t out_group; |
Andreas Wundsam | dfeb594 | 2013-09-19 13:07:49 -0700 | [diff] [blame] | 880 | enum ofp_flow_mod_flags flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 881 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 882 | of_match_t match; |
| 883 | list(of_instruction_t) instructions; |
| 884 | }; |
| 885 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 886 | struct of_bucket { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 887 | uint16_t len; |
| 888 | uint16_t weight; |
| 889 | of_port_no_t watch_port; |
| 890 | uint32_t watch_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 891 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 892 | list(of_action_t) actions; |
| 893 | }; |
| 894 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 895 | struct of_group_mod : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 896 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 897 | uint8_t type == 15; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 898 | uint16_t length; |
| 899 | uint32_t xid; |
| 900 | uint16_t command; |
| 901 | uint8_t group_type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 902 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 903 | uint32_t group_id; |
| 904 | list(of_bucket_t) buckets; |
| 905 | }; |
| 906 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 907 | struct of_packet_out : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 908 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 909 | uint8_t type == 13; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 910 | uint16_t length; |
| 911 | uint32_t xid; |
| 912 | uint32_t buffer_id; |
| 913 | of_port_no_t in_port; |
| 914 | uint16_t actions_len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 915 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 916 | list(of_action_t) actions; |
| 917 | of_octets_t data; |
| 918 | }; |
| 919 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 920 | struct of_packet_in : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 921 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 922 | uint8_t type == 10; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 923 | uint16_t length; |
| 924 | uint32_t xid; |
| 925 | uint32_t buffer_id; |
| 926 | uint16_t total_len; |
| 927 | uint8_t reason; |
| 928 | uint8_t table_id; |
| 929 | of_match_t match; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 930 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 931 | of_octets_t data; /* FIXME: Ensure total_len gets updated */ |
| 932 | }; |
| 933 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 934 | struct of_flow_removed : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 935 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 936 | uint8_t type == 11; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 937 | uint16_t length; |
| 938 | uint32_t xid; |
| 939 | uint64_t cookie; |
| 940 | uint16_t priority; |
| 941 | uint8_t reason; |
| 942 | uint8_t table_id; |
| 943 | uint32_t duration_sec; |
| 944 | uint32_t duration_nsec; |
| 945 | uint16_t idle_timeout; |
| 946 | uint16_t hard_timeout; |
| 947 | uint64_t packet_count; |
| 948 | uint64_t byte_count; |
| 949 | of_match_t match; |
| 950 | }; |
| 951 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 952 | struct of_error_msg : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 953 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 954 | uint8_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 955 | uint16_t length; |
| 956 | uint32_t xid; |
| 957 | uint16_t err_type; |
| 958 | uint16_t code; |
| 959 | of_octets_t data; |
| 960 | }; |
| 961 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 962 | // struct of_error_experimenter_msg { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 963 | // uint8_t version; |
| 964 | // uint8_t type; |
| 965 | // uint16_t length; |
| 966 | // uint32_t xid; |
| 967 | // uint16_t err_type; |
| 968 | // uint16_t subtype; |
| 969 | // uint32_t experimenter; |
| 970 | // of_octets_t data; |
| 971 | //}; |
| 972 | |
| 973 | // STATS ENTRIES: flow, table, port, queue, group stats, group desc stats |
| 974 | // FIXME: Verify disambiguation w/ length in object and entry |
| 975 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 976 | struct of_flow_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 977 | uint16_t length; |
| 978 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 979 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 980 | uint32_t duration_sec; |
| 981 | uint32_t duration_nsec; |
| 982 | uint16_t priority; |
| 983 | uint16_t idle_timeout; |
| 984 | uint16_t hard_timeout; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 985 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 986 | uint64_t cookie; |
| 987 | uint64_t packet_count; |
| 988 | uint64_t byte_count; |
| 989 | of_match_t match; |
| 990 | list(of_instruction_t) instructions; |
| 991 | }; |
| 992 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 993 | struct of_table_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 994 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 995 | pad(7); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 996 | of_table_name_t name; |
| 997 | of_match_bmap_t match; |
| 998 | of_wc_bmap_t wildcards; |
| 999 | uint32_t write_actions; |
| 1000 | uint32_t apply_actions; |
| 1001 | uint64_t write_setfields; |
| 1002 | uint64_t apply_setfields; |
| 1003 | uint64_t metadata_match; |
| 1004 | uint64_t metadata_write; |
| 1005 | uint32_t instructions; |
| 1006 | uint32_t config; |
| 1007 | uint32_t max_entries; |
| 1008 | uint32_t active_count; |
| 1009 | uint64_t lookup_count; |
| 1010 | uint64_t matched_count; |
| 1011 | }; |
| 1012 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1013 | struct of_port_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1014 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1015 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1016 | uint64_t rx_packets; |
| 1017 | uint64_t tx_packets; |
| 1018 | uint64_t rx_bytes; |
| 1019 | uint64_t tx_bytes; |
| 1020 | uint64_t rx_dropped; |
| 1021 | uint64_t tx_dropped; |
| 1022 | uint64_t rx_errors; |
| 1023 | uint64_t tx_errors; |
| 1024 | uint64_t rx_frame_err; |
| 1025 | uint64_t rx_over_err; |
| 1026 | uint64_t rx_crc_err; |
| 1027 | uint64_t collisions; |
| 1028 | }; |
| 1029 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1030 | struct of_queue_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1031 | of_port_no_t port_no; |
| 1032 | uint32_t queue_id; |
| 1033 | uint64_t tx_bytes; |
| 1034 | uint64_t tx_packets; |
| 1035 | uint64_t tx_errors; |
| 1036 | }; |
| 1037 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1038 | struct of_bucket_counter { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1039 | uint64_t packet_count; |
| 1040 | uint64_t byte_count; |
| 1041 | }; |
| 1042 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1043 | struct of_group_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1044 | uint16_t length; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1045 | pad(2); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1046 | uint32_t group_id; |
| 1047 | uint32_t ref_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1048 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1049 | uint64_t packet_count; |
| 1050 | uint64_t byte_count; |
| 1051 | list(of_bucket_counter_t) bucket_stats; |
| 1052 | }; |
| 1053 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1054 | struct of_group_desc_stats_entry { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1055 | uint16_t length; |
| 1056 | uint8_t type; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1057 | pad(1); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1058 | uint32_t group_id; |
| 1059 | list(of_bucket_t) buckets; |
| 1060 | }; |
| 1061 | |
| 1062 | // STATS: |
| 1063 | // Desc, flow, agg, table, port, queue, group, group_desc, group_feat, experi |
| 1064 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1065 | struct of_stats_request : of_header { |
| 1066 | uint8_t version; |
| 1067 | uint8_t type == 18; |
| 1068 | uint16_t length; |
| 1069 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1070 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1071 | uint16_t flags; |
| 1072 | pad(4); |
| 1073 | }; |
| 1074 | |
| 1075 | struct of_stats_reply : of_header { |
| 1076 | uint8_t version; |
| 1077 | uint8_t type == 19; |
| 1078 | uint16_t length; |
| 1079 | uint32_t xid; |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1080 | uint16_t stats_type == ?; |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1081 | uint16_t flags; |
| 1082 | pad(4); |
| 1083 | }; |
| 1084 | |
| 1085 | struct of_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1086 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1087 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1088 | uint16_t length; |
| 1089 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1090 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1091 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1092 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1093 | }; |
| 1094 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1095 | struct of_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1096 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1097 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1098 | uint16_t length; |
| 1099 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1100 | uint16_t stats_type == 0; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1101 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1102 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1103 | of_desc_str_t mfr_desc; |
| 1104 | of_desc_str_t hw_desc; |
| 1105 | of_desc_str_t sw_desc; |
| 1106 | of_serial_num_t serial_num; |
| 1107 | of_desc_str_t dp_desc; |
| 1108 | }; |
| 1109 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1110 | struct of_flow_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1111 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1112 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1113 | uint16_t length; |
| 1114 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1115 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1116 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1117 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1118 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1119 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1120 | of_port_no_t out_port; |
| 1121 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1122 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1123 | uint64_t cookie; |
| 1124 | uint64_t cookie_mask; |
| 1125 | of_match_t match; |
| 1126 | }; |
| 1127 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1128 | struct of_flow_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1129 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1130 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1131 | uint16_t length; |
| 1132 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1133 | uint16_t stats_type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1134 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1135 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1136 | list(of_flow_stats_entry_t) entries; |
| 1137 | }; |
| 1138 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1139 | struct of_aggregate_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1140 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1141 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1142 | uint16_t length; |
| 1143 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1144 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1145 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1146 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1147 | uint8_t table_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1148 | pad(3); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1149 | of_port_no_t out_port; |
| 1150 | uint32_t out_group; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1151 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1152 | uint64_t cookie; |
| 1153 | uint64_t cookie_mask; |
| 1154 | of_match_t match; |
| 1155 | }; |
| 1156 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1157 | struct of_aggregate_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1158 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1159 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1160 | uint16_t length; |
| 1161 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1162 | uint16_t stats_type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1163 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1164 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1165 | uint64_t packet_count; |
| 1166 | uint64_t byte_count; |
| 1167 | uint32_t flow_count; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1168 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1169 | }; |
| 1170 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1171 | struct of_table_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1172 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1173 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1174 | uint16_t length; |
| 1175 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1176 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1177 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1178 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1179 | }; |
| 1180 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1181 | struct of_table_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1182 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1183 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1184 | uint16_t length; |
| 1185 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1186 | uint16_t stats_type == 3; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1187 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1188 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1189 | list(of_table_stats_entry_t) entries; |
| 1190 | }; |
| 1191 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1192 | struct of_port_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1193 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1194 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1195 | uint16_t length; |
| 1196 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1197 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1198 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1199 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1200 | of_port_no_t port_no; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1201 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1202 | }; |
| 1203 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1204 | struct of_port_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1205 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1206 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1207 | uint16_t length; |
| 1208 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1209 | uint16_t stats_type == 4; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1210 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1211 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1212 | list(of_port_stats_entry_t) entries; |
| 1213 | }; |
| 1214 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1215 | struct of_queue_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1216 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1217 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1218 | uint16_t length; |
| 1219 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1220 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1221 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1222 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1223 | of_port_no_t port_no; |
| 1224 | uint32_t queue_id; |
| 1225 | }; |
| 1226 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1227 | struct of_queue_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1228 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1229 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1230 | uint16_t length; |
| 1231 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1232 | uint16_t stats_type == 5; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1233 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1234 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1235 | list(of_queue_stats_entry_t) entries; |
| 1236 | }; |
| 1237 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1238 | struct of_group_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1239 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1240 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1241 | uint16_t length; |
| 1242 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1243 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1244 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1245 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1246 | uint32_t group_id; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1247 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1248 | }; |
| 1249 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1250 | struct of_group_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1251 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1252 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1253 | uint16_t length; |
| 1254 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1255 | uint16_t stats_type == 6; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1256 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1257 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1258 | list(of_group_stats_entry_t) entries; |
| 1259 | }; |
| 1260 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1261 | struct of_group_desc_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1262 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1263 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1264 | uint16_t length; |
| 1265 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1266 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1267 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1268 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1269 | }; |
| 1270 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1271 | struct of_group_desc_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1272 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1273 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1274 | uint16_t length; |
| 1275 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1276 | uint16_t stats_type == 7; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1277 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1278 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1279 | list(of_group_desc_stats_entry_t) entries; |
| 1280 | }; |
| 1281 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1282 | struct of_group_features_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1283 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1284 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1285 | uint16_t length; |
| 1286 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1287 | uint16_t stats_type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1288 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1289 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1290 | }; |
| 1291 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1292 | struct of_group_features_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1293 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1294 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1295 | uint16_t length; |
| 1296 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1297 | uint16_t stats_type == 8; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1298 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1299 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1300 | uint32_t types; |
| 1301 | uint32_t capabilities; |
| 1302 | uint32_t max_groups_all; |
| 1303 | uint32_t max_groups_select; |
| 1304 | uint32_t max_groups_indirect; |
| 1305 | uint32_t max_groups_ff; |
| 1306 | uint32_t actions_all; |
| 1307 | uint32_t actions_select; |
| 1308 | uint32_t actions_indirect; |
| 1309 | uint32_t actions_ff; |
| 1310 | }; |
| 1311 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1312 | struct of_experimenter_stats_request : of_stats_request { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1313 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1314 | uint8_t type == 18; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1315 | uint16_t length; |
| 1316 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1317 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1318 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1319 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1320 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1321 | uint32_t subtype; |
| 1322 | of_octets_t data; |
| 1323 | }; |
| 1324 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1325 | struct of_experimenter_stats_reply : of_stats_reply { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1326 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1327 | uint8_t type == 19; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1328 | uint16_t length; |
| 1329 | uint32_t xid; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1330 | uint16_t stats_type == 0xffff; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1331 | uint16_t flags; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1332 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1333 | uint32_t experimenter == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1334 | uint32_t subtype; |
| 1335 | of_octets_t data; |
| 1336 | }; |
| 1337 | |
| 1338 | // END OF STATS OBJECTS |
| 1339 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1340 | struct of_queue_prop { |
Andreas Wundsam | c37ba3d | 2013-08-02 17:51:51 -0700 | [diff] [blame] | 1341 | uint16_t type == ?; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1342 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1343 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1344 | }; |
| 1345 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1346 | struct of_queue_prop_min_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1347 | uint16_t type == 1; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1348 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1349 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1350 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1351 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1352 | }; |
| 1353 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1354 | struct of_queue_prop_max_rate : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1355 | uint16_t type == 2; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1356 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1357 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1358 | uint16_t rate; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1359 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1360 | }; |
| 1361 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1362 | struct of_queue_prop_experimenter : of_queue_prop { |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1363 | uint16_t type == 65535; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1364 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1365 | pad(4); |
Rich Lane | b25d07c | 2013-08-22 17:22:43 -0700 | [diff] [blame] | 1366 | uint32_t experimenter == ?; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1367 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1368 | of_octets_t data; |
| 1369 | }; |
| 1370 | |
Rich Lane | 68ae4d7 | 2013-05-09 10:55:19 -0700 | [diff] [blame] | 1371 | struct of_packet_queue { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1372 | uint32_t queue_id; |
| 1373 | of_port_no_t port; |
| 1374 | uint16_t len; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1375 | pad(6); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1376 | list(of_queue_prop_t) properties; |
| 1377 | }; |
| 1378 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1379 | struct of_queue_get_config_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1380 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1381 | uint8_t type == 22; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1382 | uint16_t length; |
| 1383 | uint32_t xid; |
| 1384 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1385 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1386 | }; |
| 1387 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1388 | struct of_queue_get_config_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1389 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1390 | uint8_t type == 23; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1391 | uint16_t length; |
| 1392 | uint32_t xid; |
| 1393 | of_port_no_t port; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1394 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1395 | list(of_packet_queue_t) queues; |
| 1396 | }; |
| 1397 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1398 | struct of_role_request : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1399 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1400 | uint8_t type == 24; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1401 | uint16_t length; |
| 1402 | uint32_t xid; |
| 1403 | uint32_t role; |
Rich Lane | e2af4ee | 2013-05-09 11:04:06 -0700 | [diff] [blame] | 1404 | pad(4); |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1405 | uint64_t generation_id; |
| 1406 | }; |
| 1407 | |
Rich Lane | e9c37db | 2013-06-21 18:30:24 -0700 | [diff] [blame] | 1408 | struct of_role_reply : of_header { |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1409 | uint8_t version; |
Rich Lane | 31b8714 | 2013-05-09 22:05:42 -0700 | [diff] [blame] | 1410 | uint8_t type == 25; |
Rich Lane | a06d0c3 | 2013-03-25 08:52:03 -0700 | [diff] [blame] | 1411 | uint16_t length; |
| 1412 | uint32_t xid; |
| 1413 | of_octets_t data; |
| 1414 | }; |