Carmelo Cascone | 5db3968 | 2017-09-07 16:36:42 +0200 | [diff] [blame^] | 1 | +---------------------------------------------------------------------+ |
| 2 | | Log file: mau.resources.log | |
| 3 | | Compiler version: 5.1.0 (fca32d1) | |
| 4 | | Created on: Thu Sep 7 13:56:53 2017 | |
| 5 | +---------------------------------------------------------------------+ |
| 6 | |
| 7 | |
| 8 | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| 9 | | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID | |
| 10 | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| 11 | | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | |
| 12 | | 1 | 1 | 16 | 1 | 0 | 1 | 3 | 3 | 3 | 2 | 0 | 1 | 0 | 4 | 0 | 2 | 1 | 1 | |
| 13 | | 2 | 2 | 0 | 9 | 0 | 2 | 4 | 4 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 | |
| 14 | | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 15 | | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 16 | | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 17 | | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 18 | | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 19 | | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 20 | | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 21 | | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 22 | | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 23 | | | | | | | | | | | | | | | | | | | | |
| 24 | | Totals | 5 | 16 | 12 | 0 | 5 | 7 | 7 | 3 | 4 | 0 | 3 | 0 | 4 | 0 | 2 | 1 | 5 | |
| 25 | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| 26 | |
| 27 | |
| 28 | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| 29 | | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID | |
| 30 | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| 31 | | 0 | 1.56% | 0.00% | 0.48% | 0.00% | 12.50% | 0.00% | 0.00% | 0.00% | 3.12% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% | |
| 32 | | 1 | 0.78% | 24.24% | 0.24% | 0.00% | 6.25% | 3.75% | 6.25% | 12.50% | 6.25% | 0.00% | 25.00% | 0.00% | 3.12% | 0.00% | 6.25% | 3.12% | 6.25% | |
| 33 | | 2 | 1.56% | 0.00% | 2.16% | 0.00% | 12.50% | 5.00% | 8.33% | 0.00% | 3.12% | 0.00% | 50.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% | |
| 34 | | 3 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | |
| 35 | | 4 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | |
| 36 | | 5 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | |
| 37 | | 6 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | |
| 38 | | 7 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | |
| 39 | | 8 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | |
| 40 | | 9 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | |
| 41 | | 10 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | |
| 42 | | 11 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | |
| 43 | | | | | | | | | | | | | | | | | | | | |
| 44 | | Average | 0.33% | 2.02% | 0.24% | 0.00% | 2.60% | 0.73% | 1.22% | 1.04% | 1.04% | 0.00% | 6.25% | 0.00% | 0.26% | 0.00% | 0.52% | 0.26% | 2.60% | |
| 45 | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| 46 | |
| 47 | |
| 48 | Allocated Resource Usage |
| 49 | -------------------------------------------------------------------------------------------------------------------- |
| 50 | | Table | Stage | Crossbar | Hash | Gateways | RAMs | TCAMs | Map | Action | VLIW | |
| 51 | | Name | Number | Bytes | Bits | | | | RAMs | Data | Slots | |
| 52 | | | | | | | | | | Bus | | |
| 53 | | | | | | | | | | Bytes | | |
| 54 | -------------------------------------------------------------------------------------------------------------------- |
| 55 | | _condition_0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | |
| 56 | | _condition_3 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | |
| 57 | | ingress_pkt__action__ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 58 | | ingress_pkt | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| 59 | | egress_pkt__action__ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 60 | | egress_pkt | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| 61 | | _condition_1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | |
| 62 | | table0__action__ | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | |
| 63 | | table0 | 1 | 16 | 0 | 0 | 1 | 3 | 1 | 0 | 3 | |
| 64 | | table0_counter | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | |
| 65 | | _condition_2 | 2 | 2 | 9 | 1 | 0 | 0 | 0 | 0 | 0 | |
| 66 | | ingress_port_count_table__action__ | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 67 | | ingress_port_count_table | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| 68 | | egress_port_count_table__action__ | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 69 | | egress_port_count_table | 2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | |
| 70 | | ingress_port_counter | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | |
| 71 | | egress_port_counter | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | |
| 72 | -------------------------------------------------------------------------------------------------------------------- |
| 73 | |