Pipeline 0 -- default
Stages Occupied: 2
Resource Usage Summary
Stage Number |
Exact Match Input xbar |
Ternary Match Input xbar |
Hash Bit |
Hash Dist Unit |
Gateway |
SRAM |
Map RAM |
TCAM |
VLIW Instr |
Meter ALU |
Stats ALU |
Stash |
Action Data Bus Bytes |
8-bit Action Slots |
16-bit Action Slots |
32-bit Action Slots |
Logical TableID |
0 |
1 |
16 |
1 |
0 |
2 |
3 |
3 |
3 |
3 |
0 |
1 |
0 |
4 |
0 |
2 |
1 |
2 |
1 |
2 |
0 |
9 |
0 |
2 |
4 |
4 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Totals |
3 |
16 |
10 |
0 |
4 |
7 |
7 |
3 |
4 |
0 |
3 |
0 |
4 |
0 |
2 |
1 |
4 |
Resource Percentage Summary
Stage Number |
Exact Match Input xbar |
Ternary Match Input xbar |
Hash Bit |
Hash Dist Unit |
Gateway |
SRAM |
Map RAM |
TCAM |
VLIW Instr |
Meter ALU |
Stats ALU |
Stash |
Action Data Bus Bytes |
8-bit Action Slots |
16-bit Action Slots |
32-bit Action Slots |
Logical TableID |
0 |
0.78% |
24.24% |
0.24% |
0.00% |
12.50% |
3.75% |
6.25% |
12.50% |
9.38% |
0.00% |
25.00% |
0.00% |
3.12% |
0.00% |
6.25% |
3.12% |
12.50% |
1 |
1.56% |
0.00% |
2.16% |
0.00% |
12.50% |
5.00% |
8.33% |
0.00% |
3.12% |
0.00% |
50.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
12.50% |
2 |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
3 |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
4 |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
5 |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
6 |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
7 |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
8 |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
9 |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
10 |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
11 |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
0.00% |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Average |
0.20% |
2.02% |
0.20% |
0.00% |
2.08% |
0.73% |
1.22% |
1.04% |
1.04% |
0.00% |
6.25% |
0.00% |
0.26% |
0.00% |
0.52% |
0.26% |
2.08% |
Phase 0 is not in use.
MAU Stage 0
MAU Stage 1
MAU Stage 2
MAU Stage 3
MAU Stage 4
MAU Stage 5
MAU Stage 6
MAU Stage 7
MAU Stage 8
MAU Stage 9
MAU Stage 10
MAU Stage 11
Created on Fri Sep 8 08:23:58 2017
Compiler version: 5.1.0 (fca32d1)