| Table Name | Stage Number | Crossbar Bytes | Hash Bits | Gateways | RAMs | TCAMs | Map RAMs | Action Data Bus Bytes | VLIW Slots |
| _condition_0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
| process_packet_out_table__action__ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| process_packet_out_table | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
| table0__action__ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 |
| table0 | 0 | 16 | 0 | 0 | 1 | 3 | 1 | 0 | 3 |
| table0_counter | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
| _condition_2 | 1 | 2 | 9 | 1 | 0 | 0 | 0 | 0 | 0 |
| ingress_port_count_table__action__ | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| ingress_port_count_table | 1 | 2 | 10 | 0 | 0 | 0 | 0 | 0 | 1 |
| egress_port_count_table__action__ | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| egress_port_count_table | 1 | 2 | 10 | 1 | 0 | 0 | 0 | 0 | 1 |
| ingress_port_counter | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
| egress_port_counter | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |