Row 255
State <POV initialization>_<Ingress intrinsic metadata>_<Phase 0> (from state <Shim start state>)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
0 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
10 |
8 |
0 |
0 |
8 |
1 |
1 |
0 |
0 |
0 |
0 |
10 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
80 |
1ff |
0 |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
81 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 254
State parse_ethernet (from state parse_pkt_in)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
e |
2 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
c |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
1ff |
0 |
84 |
85 |
3 |
0 |
0 |
0 |
0 |
42 |
1ff |
43 |
41 |
0 |
0 |
1 |
0 |
c |
5 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
0 |
1ff |
8 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
0 |
7 |
|
Row 253
State parse_ipv4 (from state parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2 |
800 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
3 |
0 |
0 |
9 |
1 |
1 |
0 |
0 |
6 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
141 |
0 |
83 |
140 |
1 |
0 |
0 |
0 |
0 |
120 |
1ff |
43 |
40 |
0 |
0 |
1 |
0 |
1 |
e |
0 |
3 |
1ff |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
2 |
0 |
100 |
10 |
9 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
d |
8 |
0 |
0 |
|
Row 252
State <leaf> (from state parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 251
State parse_tcp (from state parse_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3 |
e000 |
ff |
6 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
144 |
0 |
142 |
143 |
101 |
0 |
0 |
0 |
0 |
122 |
123 |
43 |
121 |
0 |
0 |
1 |
0 |
6 |
4 |
a |
8 |
145 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
102 |
0 |
1ff |
10 |
c |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
10 |
0 |
1 |
|
Row 250
State parse_udp (from state parse_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3 |
e000 |
ff |
11 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
1ff |
0 |
142 |
1ff |
5 |
0 |
0 |
0 |
0 |
122 |
1ff |
43 |
121 |
0 |
0 |
1 |
0 |
0 |
6 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
20 |
0 |
5 |
|
Row 249
State <leaf> (from state parse_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 248
State parse_tcp//spilled (from state parse_tcp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
4 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
124 |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3 |
0 |
0 |
|
Row 247
State parse_pkt_out (from state default_parser)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
6 |
ff40 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
2 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
2 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
1ff |
0 |
81 |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
43 |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
2 |
0 |
0 |
|
Row 246
State parse_ethernet (from state default_parser)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
6 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
e |
2 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
c |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
1ff |
0 |
84 |
85 |
3 |
0 |
0 |
0 |
0 |
42 |
1ff |
43 |
41 |
0 |
0 |
1 |
0 |
c |
5 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
0 |
1ff |
8 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
0 |
7 |
|
Row 245
State parse_ethernet (from state parse_pkt_out)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
7 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
e |
2 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
c |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
1ff |
0 |
84 |
85 |
3 |
0 |
0 |
0 |
0 |
42 |
1ff |
43 |
41 |
0 |
0 |
1 |
0 |
c |
5 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
0 |
1ff |
8 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
0 |
7 |
|
Row 244
State start (from state <POV initialization>_<Ingress intrinsic metadata>_<Phase 0>)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
8 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
9 |
0 |
0 |
c |
1 |
0 |
0 |
0 |
0 |
0 |
d |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
43 |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
40 |
0 |
0 |
|
Row 243
State parse_pkt_in (from state start)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
9 |
ffff |
ff |
0 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
2 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
2 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
1ff |
0 |
81 |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
43 |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
|
Row 242
State default_parser (from state start)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
9 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 241
Unmatchable
|
Row 240
Unmatchable
|
Row 239
Unmatchable
|
Row 238
Unmatchable
|
Row 237
Unmatchable
|
Row 236
Unmatchable
|
Row 235
Unmatchable
|
Row 234
Unmatchable
|
Row 233
Unmatchable
|
Row 232
Unmatchable
|
Row 231
Unmatchable
|
Row 230
Unmatchable
|
Row 229
Unmatchable
|
Row 228
Unmatchable
|
Row 227
Unmatchable
|
Row 226
Unmatchable
|
Row 225
Unmatchable
|
Row 224
Unmatchable
|
Row 223
Unmatchable
|
Row 222
Unmatchable
|
Row 221
Unmatchable
|
Row 220
Unmatchable
|
Row 219
Unmatchable
|
Row 218
Unmatchable
|
Row 217
Unmatchable
|
Row 216
Unmatchable
|
Row 215
Unmatchable
|
Row 214
Unmatchable
|
Row 213
Unmatchable
|
Row 212
Unmatchable
|
Row 211
Unmatchable
|
Row 210
Unmatchable
|
Row 209
Unmatchable
|
Row 208
Unmatchable
|
Row 207
Unmatchable
|
Row 206
Unmatchable
|
Row 205
Unmatchable
|
Row 204
Unmatchable
|
Row 203
Unmatchable
|
Row 202
Unmatchable
|
Row 201
Unmatchable
|
Row 200
Unmatchable
|
Row 199
Unmatchable
|
Row 198
Unmatchable
|
Row 197
Unmatchable
|
Row 196
Unmatchable
|
Row 195
Unmatchable
|
Row 194
Unmatchable
|
Row 193
Unmatchable
|
Row 192
Unmatchable
|
Row 191
Unmatchable
|
Row 190
Unmatchable
|
Row 189
Unmatchable
|
Row 188
Unmatchable
|
Row 187
Unmatchable
|
Row 186
Unmatchable
|
Row 185
Unmatchable
|
Row 184
Unmatchable
|
Row 183
Unmatchable
|
Row 182
Unmatchable
|
Row 181
Unmatchable
|
Row 180
Unmatchable
|
Row 179
Unmatchable
|
Row 178
Unmatchable
|
Row 177
Unmatchable
|
Row 176
Unmatchable
|
Row 175
Unmatchable
|
Row 174
Unmatchable
|
Row 173
Unmatchable
|
Row 172
Unmatchable
|
Row 171
Unmatchable
|
Row 170
Unmatchable
|
Row 169
Unmatchable
|
Row 168
Unmatchable
|
Row 167
Unmatchable
|
Row 166
Unmatchable
|
Row 165
Unmatchable
|
Row 164
Unmatchable
|
Row 163
Unmatchable
|
Row 162
Unmatchable
|
Row 161
Unmatchable
|
Row 160
Unmatchable
|
Row 159
Unmatchable
|
Row 158
Unmatchable
|
Row 157
Unmatchable
|
Row 156
Unmatchable
|
Row 155
Unmatchable
|
Row 154
Unmatchable
|
Row 153
Unmatchable
|
Row 152
Unmatchable
|
Row 151
Unmatchable
|
Row 150
Unmatchable
|
Row 149
Unmatchable
|
Row 148
Unmatchable
|
Row 147
Unmatchable
|
Row 146
Unmatchable
|
Row 145
Unmatchable
|
Row 144
Unmatchable
|
Row 143
Unmatchable
|
Row 142
Unmatchable
|
Row 141
Unmatchable
|
Row 140
Unmatchable
|
Row 139
Unmatchable
|
Row 138
Unmatchable
|
Row 137
Unmatchable
|
Row 136
Unmatchable
|
Row 135
Unmatchable
|
Row 134
Unmatchable
|
Row 133
Unmatchable
|
Row 132
Unmatchable
|
Row 131
Unmatchable
|
Row 130
Unmatchable
|
Row 129
Unmatchable
|
Row 128
Unmatchable
|
Row 127
Unmatchable
|
Row 126
Unmatchable
|
Row 125
Unmatchable
|
Row 124
Unmatchable
|
Row 123
Unmatchable
|
Row 122
Unmatchable
|
Row 121
Unmatchable
|
Row 120
Unmatchable
|
Row 119
Unmatchable
|
Row 118
Unmatchable
|
Row 117
Unmatchable
|
Row 116
Unmatchable
|
Row 115
Unmatchable
|
Row 114
Unmatchable
|
Row 113
Unmatchable
|
Row 112
Unmatchable
|
Row 111
Unmatchable
|
Row 110
Unmatchable
|
Row 109
Unmatchable
|
Row 108
Unmatchable
|
Row 107
Unmatchable
|
Row 106
Unmatchable
|
Row 105
Unmatchable
|
Row 104
Unmatchable
|
Row 103
Unmatchable
|
Row 102
Unmatchable
|
Row 101
Unmatchable
|
Row 100
Unmatchable
|
Row 99
Unmatchable
|
Row 98
Unmatchable
|
Row 97
Unmatchable
|
Row 96
Unmatchable
|
Row 95
Unmatchable
|
Row 94
Unmatchable
|
Row 93
Unmatchable
|
Row 92
Unmatchable
|
Row 91
Unmatchable
|
Row 90
Unmatchable
|
Row 89
Unmatchable
|
Row 88
Unmatchable
|
Row 87
Unmatchable
|
Row 86
Unmatchable
|
Row 85
Unmatchable
|
Row 84
Unmatchable
|
Row 83
Unmatchable
|
Row 82
Unmatchable
|
Row 81
Unmatchable
|
Row 80
Unmatchable
|
Row 79
Unmatchable
|
Row 78
Unmatchable
|
Row 77
Unmatchable
|
Row 76
Unmatchable
|
Row 75
Unmatchable
|
Row 74
Unmatchable
|
Row 73
Unmatchable
|
Row 72
Unmatchable
|
Row 71
Unmatchable
|
Row 70
Unmatchable
|
Row 69
Unmatchable
|
Row 68
Unmatchable
|
Row 67
Unmatchable
|
Row 66
Unmatchable
|
Row 65
Unmatchable
|
Row 64
Unmatchable
|
Row 63
Unmatchable
|
Row 62
Unmatchable
|
Row 61
Unmatchable
|
Row 60
Unmatchable
|
Row 59
Unmatchable
|
Row 58
Unmatchable
|
Row 57
Unmatchable
|
Row 56
Unmatchable
|
Row 55
Unmatchable
|
Row 54
Unmatchable
|
Row 53
Unmatchable
|
Row 52
Unmatchable
|
Row 51
Unmatchable
|
Row 50
Unmatchable
|
Row 49
Unmatchable
|
Row 48
Unmatchable
|
Row 47
Unmatchable
|
Row 46
Unmatchable
|
Row 45
Unmatchable
|
Row 44
Unmatchable
|
Row 43
Unmatchable
|
Row 42
Unmatchable
|
Row 41
Unmatchable
|
Row 40
Unmatchable
|
Row 39
Unmatchable
|
Row 38
Unmatchable
|
Row 37
Unmatchable
|
Row 36
Unmatchable
|
Row 35
Unmatchable
|
Row 34
Unmatchable
|
Row 33
Unmatchable
|
Row 32
Unmatchable
|
Row 31
Unmatchable
|
Row 30
Unmatchable
|
Row 29
Unmatchable
|
Row 28
Unmatchable
|
Row 27
Unmatchable
|
Row 26
Unmatchable
|
Row 25
Unmatchable
|
Row 24
Unmatchable
|
Row 23
Unmatchable
|
Row 22
Unmatchable
|
Row 21
Unmatchable
|
Row 20
Unmatchable
|
Row 19
Unmatchable
|
Row 18
Unmatchable
|
Row 17
Unmatchable
|
Row 16
Unmatchable
|
Row 15
Unmatchable
|
Row 14
Unmatchable
|
Row 13
Unmatchable
|
Row 12
Unmatchable
|
Row 11
Unmatchable
|
Row 10
Unmatchable
|
Row 9
Unmatchable
|
Row 8
Unmatchable
|
Row 7
Unmatchable
|
Row 6
Unmatchable
|
Row 5
Unmatchable
|
Row 4
Unmatchable
|
Row 3
Unmatchable
|
Row 2
Unmatchable
|
Row 1
Unmatchable
|
Row 0
Unmatchable
|
Matchable row occupancy: 14/256 (5.47%)
|