Support for Tofino pipeconfs in ECMP app
Change-Id: I34c16f5f349c480f53b1bfc6a1fd91ec5a328ee3
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gw.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gw.log
new file mode 100644
index 0000000..0affae5
--- /dev/null
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/mavericks/logs/mau.gw.log
@@ -0,0 +1,125 @@
++---------------------------------------------------------------------+
+| Log file: mau.gw.log |
+| Compiler version: 5.1.0 (fca32d1) |
+| Created on: Thu Sep 7 14:48:49 2017 |
++---------------------------------------------------------------------+
+
+cond _condition_0: valid packet_out_hdr
+ valid packet_out_hdr
+ ! not valid packet_out_hdr
+cond _condition_0 can be gateway (1+0)x1
+cond !_condition_0 can be gateway (1+0)x1
+_condition_0 is gateway for ingress_pkt
+cond _condition_1: not valid packet_out_hdr
+ not valid packet_out_hdr
+ ! not not valid packet_out_hdr
+cond _condition_1 can be gateway (1+0)x1
+cond !_condition_1 can be gateway (1+0)x1
+_condition_1 is gateway for table0
+cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 254
+ ig_intr_md_for_tm.ucast_egress_port < 254
+ ! ig_intr_md_for_tm.ucast_egress_port >= 254
+cond _condition_2 can be gateway (9+0)x1
+cond !_condition_2 can be gateway (9+0)x1
+_condition_2 is gateway for ingress_port_count_table
+cond _condition_3: ig_intr_md_for_tm.copy_to_cpu == 1
+ ig_intr_md_for_tm.copy_to_cpu == 1
+ ! ig_intr_md_for_tm.copy_to_cpu != 1
+cond _condition_3 can be gateway (0+1)x1
+cond !_condition_3 can be gateway (0+1)x2
+_condition_3 is gateway for egress_pkt
+fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f84d6b710d0>]) and and xor_fields is OrderedSet()
+fields = OrderedSet() and and xor_fields is OrderedSet()
+fields = OrderedSet() and and xor_fields is OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f84d6b71390>])
+fields = OrderedSet() and and xor_fields is OrderedSet()
+cond _condition_0: valid packet_out_hdr
+ valid packet_out_hdr
+ ! not valid packet_out_hdr
+cond _condition_0 can be gateway (1+0)x1
+cond !_condition_0 can be gateway (1+0)x1
+_condition_0 is gateway for ingress_pkt
+cond _condition_1: not valid packet_out_hdr
+ not valid packet_out_hdr
+ ! not not valid packet_out_hdr
+cond _condition_1 can be gateway (1+0)x1
+cond !_condition_1 can be gateway (1+0)x1
+_condition_1 is gateway for table0
+cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 254
+ ig_intr_md_for_tm.ucast_egress_port < 254
+ ! ig_intr_md_for_tm.ucast_egress_port >= 254
+cond _condition_2 can be gateway (9+0)x1
+cond !_condition_2 can be gateway (9+0)x1
+_condition_2 is gateway for ingress_port_count_table
+cond _condition_3: ig_intr_md_for_tm.copy_to_cpu == 1
+ ig_intr_md_for_tm.copy_to_cpu == 1
+ ! ig_intr_md_for_tm.copy_to_cpu != 1
+cond _condition_3 can be gateway (0+1)x1
+cond !_condition_3 can be gateway (0+1)x2
+_condition_3 is gateway for egress_pkt
+fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f84d6b710d0>]) and and xor_fields is OrderedSet()
+fields = OrderedSet() and and xor_fields is OrderedSet()
+fields = OrderedSet() and and xor_fields is OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f84d6b71390>])
+fields = OrderedSet() and and xor_fields is OrderedSet()
+cond _condition_0: valid packet_out_hdr
+ valid packet_out_hdr
+ ! not valid packet_out_hdr
+cond _condition_0 can be gateway (1+0)x1
+cond !_condition_0 can be gateway (1+0)x1
+_condition_0 is gateway for ingress_pkt
+cond _condition_1: not valid packet_out_hdr
+ not valid packet_out_hdr
+ ! not not valid packet_out_hdr
+cond _condition_1 can be gateway (1+0)x1
+cond !_condition_1 can be gateway (1+0)x1
+_condition_1 is gateway for table0
+cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 254
+ ig_intr_md_for_tm.ucast_egress_port < 254
+ ! ig_intr_md_for_tm.ucast_egress_port >= 254
+cond _condition_2 can be gateway (9+0)x1
+cond !_condition_2 can be gateway (9+0)x1
+_condition_2 is gateway for ingress_port_count_table
+cond _condition_3: ig_intr_md_for_tm.copy_to_cpu == 1
+ ig_intr_md_for_tm.copy_to_cpu == 1
+ ! ig_intr_md_for_tm.copy_to_cpu != 1
+cond _condition_3 can be gateway (0+1)x1
+cond !_condition_3 can be gateway (0+1)x2
+_condition_3 is gateway for egress_pkt
+fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f84d6b710d0>]) and and xor_fields is OrderedSet()
+fields = OrderedSet() and and xor_fields is OrderedSet()
+fields = OrderedSet() and and xor_fields is OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f84d6b71390>])
+fields = OrderedSet() and and xor_fields is OrderedSet()
+cond _always_true: True == True
+ True
+ ! False
+--> Stage Gateway Table for condition _condition_0 in stage 0
+T -> ingress_pkt(0), F -> _condition_1(16)
+building tcam for GatewayTest('valid packet_out_hdr')
+ adding line (match=200000000 mask=200000000 T)
+tcam data: [(match=200000000 mask=200000000 T)]
+final.tcam: [(match=200000000 mask=200000000 T)], miss=False
+--> Stage Gateway Table for condition _condition_3 in stage 0
+T -> egress_pkt(1), F -> None(255)
+building tcam for GatewayTest('ig_intr_md_for_tm.copy_to_cpu == 1')
+ adding line (match=100000000 mask=100000000 T)
+tcam data: [(match=100000000 mask=100000000 T)]
+final.tcam: [(match=100000000 mask=100000000 T)], miss=False
+--> Stage Gateway Table for condition _condition_1 in stage 1
+T -> table0(16), F -> _condition_2(48)
+building tcam for GatewayTest('not valid packet_out_hdr')
+ adding line (match=0 mask=100000000 T)
+tcam data: [(match=0 mask=100000000 T)]
+final.tcam: [(match=0 mask=100000000 T)], miss=False
+--> Stage Gateway Table for condition _condition_2 in stage 3
+T -> ingress_port_count_table(48), F -> None(255)
+building tcam for GatewayTest('ig_intr_md_for_tm.ucast_egress_port < 254')
+ adding line (range=[ffff ffff 3fff] match=0 mask=0 T)
+ adding line (range=[ffff 7fff ffff] match=0 mask=0 T)
+ adding line (range=[0 ffff ffff] match=0 mask=0 T)
+tcam data: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[0 ffff ffff] match=0 mask=0 T)]
+final.tcam: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[0 ffff ffff] match=0 mask=0 T)], miss=False
+--> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 3
+T -> egress_port_count_table(49), F -> egress_port_count_table(49)
+building tcam for GatewayTest('True')
+ adding line (match=0 mask=0 T)
+tcam data: [(match=0 mask=0 T)]
+final.tcam: [(match=0 mask=0 T)], miss=False